HPM SDK
HPMicro Software Development Kit
hpm_sdxc_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SDXC_H
10 #define HPM_SDXC_H
11 
12 typedef struct {
13  __RW uint32_t SDMASA; /* 0x0: */
14  __RW uint32_t BLK_ATTR; /* 0x4: */
15  __RW uint32_t CMD_ARG; /* 0x8: */
16  __RW uint32_t CMD_XFER; /* 0xC: */
17  __R uint32_t RESP[4]; /* 0x10 - 0x1C: */
18  __RW uint32_t BUF_DATA; /* 0x20: */
19  __R uint32_t PSTATE; /* 0x24: */
20  __RW uint32_t PROT_CTRL; /* 0x28: */
21  __RW uint32_t SYS_CTRL; /* 0x2C: */
22  __RW uint32_t INT_STAT; /* 0x30: */
23  __RW uint32_t INT_STAT_EN; /* 0x34: */
24  __RW uint32_t INT_SIGNAL_EN; /* 0x38: */
25  __RW uint32_t AC_HOST_CTRL; /* 0x3C: */
26  __R uint32_t CAPABILITIES1; /* 0x40: */
27  __R uint32_t CAPABILITIES2; /* 0x44: */
28  __R uint32_t CURR_CAPABILITIES1; /* 0x48: */
29  __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */
30  __W uint32_t FORCE_EVENT; /* 0x50: */
31  __R uint32_t ADMA_ERR_STAT; /* 0x54: */
32  __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */
33  __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */
34  __R uint16_t PRESET[11]; /* 0x60 - 0x74: */
35  __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */
36  __RW uint32_t ADMA_ID_ADDR; /* 0x78: */
37  __R uint8_t RESERVED2[106]; /* 0x7C - 0xE5: Reserved */
38  __R uint16_t P_EMBEDDED_CNTRL; /* 0xE6: */
39  __R uint16_t P_VENDOR_SPECIFIC_AREA; /* 0xE8: */
40  __R uint16_t P_VENDOR2_SPECIFIC_AREA; /* 0xEA: */
41  __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */
42  __R uint16_t SLOT_INTR_STATUS; /* 0xFC: */
43  __R uint8_t RESERVED4[130]; /* 0xFE - 0x17F: Reserved */
44  __R uint32_t CQVER; /* 0x180: */
45  __R uint32_t CQCAP; /* 0x184: */
46  __RW uint32_t CQCFG; /* 0x188: */
47  __RW uint32_t CQCTL; /* 0x18C: */
48  __RW uint32_t CQIS; /* 0x190: */
49  __RW uint32_t CQISE; /* 0x194: */
50  __RW uint32_t CQISGE; /* 0x198: */
51  __RW uint32_t CQIC; /* 0x19C: */
52  __RW uint32_t CQTDLBA; /* 0x1A0: */
53  __R uint8_t RESERVED5[4]; /* 0x1A4 - 0x1A7: Reserved */
54  __RW uint32_t CQTDBR; /* 0x1A8: */
55  __RW uint32_t CQTCN; /* 0x1AC: */
56  __RW uint32_t CQDQS; /* 0x1B0: */
57  __RW uint32_t CQDPT; /* 0x1B4: */
58  __RW uint32_t CQTCLR; /* 0x1B8: */
59  __R uint8_t RESERVED6[4]; /* 0x1BC - 0x1BF: Reserved */
60  __RW uint32_t CQSSC1; /* 0x1C0: */
61  __RW uint32_t CQSSC2; /* 0x1C4: */
62  __R uint32_t CQCRDCT; /* 0x1C8: */
63  __R uint8_t RESERVED7[4]; /* 0x1CC - 0x1CF: Reserved */
64  __RW uint32_t CQRMEM; /* 0x1D0: */
65  __R uint32_t CQTERRI; /* 0x1D4: */
66  __R uint32_t CQCRI; /* 0x1D8: */
67  __R uint32_t CQCRA; /* 0x1DC: */
68  __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */
69  __R uint32_t MSHC_VER_ID; /* 0x500: */
70  __R uint32_t MSHC_VER_TYPE; /* 0x504: */
71  __R uint8_t RESERVED9[36]; /* 0x508 - 0x52B: Reserved */
72  __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */
73  __R uint8_t RESERVED10[16]; /* 0x530 - 0x53F: Reserved */
74  __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */
75  __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */
76  __R uint8_t RESERVED11[10936]; /* 0x548 - 0x2FFF: Reserved */
77  __RW uint32_t MISC_CTRL0; /* 0x3000: */
78  __RW uint32_t MISC_CTRL1; /* 0x3004: */
79 } SDXC_Type;
80 
81 
82 /* Bitfield definition for register: SDMASA */
83 /*
84  * BLOCKCNT_SDMASA (RW)
85  *
86  * 32-bit Block Count (SDMA System Address)
87  * - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode.
88  * When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position.
89  * It can be accessed only if no transaction is executing. Reading this register during data transfers may
90  * return an invalid value.
91  * - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count.
92  * The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero.
93  * This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value.
94  * Following are the values for BLOCKCNT_SDMASA:
95  * - 0xFFFF_FFFF: 4G - 1 Block
96  * -
97  * - 0x0000_0002: 2 Blocks
98  * - 0x0000_0001: 1 Block
99  * - 0x0000_0000: Stop Count
100  * Note:
101  * - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode.
102  * The system address must be programmed in the ADMA System Address register.
103  * - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes.
104  * Auto CMD23 cannot be used with SDMA.
105  * - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register.
106  */
107 #define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL)
108 #define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U)
109 #define SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK)
110 #define SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT)
111 
112 /* Bitfield definition for register: BLK_ATTR */
113 /*
114  * BLOCK_CNT (RW)
115  *
116  * 16-bit Block Count
117  * - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected.
118  * - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected.
119  * Following are the values for BLOCK_CNT:
120  * - 0x0: Stop Count
121  * - 0x1: 1 Block
122  * - 0x2: 2 Blocks
123  * - .
124  * - 0xFFFF: 65535 Blocks
125  * Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes.
126  */
127 #define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL)
128 #define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U)
129 #define SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK)
130 #define SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT)
131 
132 /*
133  * SDMA_BUF_BDARY (RW)
134  *
135  * SDMA Buffer Boundary
136  * These bits specify the size of contiguous buffer in system memory.
137  * The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register.
138  * Values:
139  * - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary
140  * - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary
141  * - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary
142  * - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary
143  * - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary
144  * - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary
145  * - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary
146  * - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary
147  */
148 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U)
149 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U)
150 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK)
151 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT)
152 
153 /*
154  * XFER_BLOCK_SIZE (RW)
155  *
156  * Transfer Block Size
157  * These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing.
158  * Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE:
159  * - 0x1: 1 byte
160  * - 0x2: 2 bytes
161  * - 0x3: 3 bytes
162  * - .
163  * - 0x1FF: 511 byte
164  * - 0x200: 512 byt es
165  * - .
166  * - 0x800: 2048 bytes
167  * Note: This register must be programmed with a non-zero value for data transfer.
168  */
169 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU)
170 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U)
171 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK)
172 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT)
173 
174 /* Bitfield definition for register: CMD_ARG */
175 /*
176  * ARGUMNET (RW)
177  *
178  * Command Argument
179  * These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format.
180  */
181 #define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL)
182 #define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U)
183 #define SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK)
184 #define SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT)
185 
186 /* Bitfield definition for register: CMD_XFER */
187 /*
188  * CMD_INDEX (RW)
189  *
190  * Command Index
191  * These bits are set to the command number that is specified in bits 45-40 of the Command Format.
192  */
193 #define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL)
194 #define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U)
195 #define SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK)
196 #define SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT)
197 
198 /*
199  * CMD_TYPE (RW)
200  *
201  * Command Type
202  * These bits indicate the command type.
203  * Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3.
204  * Values:
205  * 0x3 (ABORT_CMD): Abort
206  * 0x2 (RESUME_CMD): Resume
207  * 0x1 (SUSPEND_CMD): Suspend
208  * 0x0 (NORMAL_CMD): Normal
209  */
210 #define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL)
211 #define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U)
212 #define SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK)
213 #define SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT)
214 
215 /*
216  * DATA_PRESENT_SEL (RW)
217  *
218  * Data Present Select
219  * This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances:
220  * Command using the CMD line
221  * Command with no data transfer but using busy signal on the DAT[0] line
222  * Resume Command
223  * Values:
224  * 0x0 (NO_DATA): No Data Present
225  * 0x1 (DATA): Data Present
226  */
227 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL)
228 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U)
229 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK)
230 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT)
231 
232 /*
233  * CMD_IDX_CHK_ENABLE (RW)
234  *
235  * Command Index Check Enable
236  * This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index.
237  * If the value is not the same, it is reported as a Command Index error.
238  * Note:
239  * Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response.
240  * For the tuning command, this bit must always be set to enable the index check.
241  * Values:
242  * 0x0 (DISABLED): Disable
243  * 0x1 (ENABLED): Enable
244  */
245 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL)
246 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U)
247 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK)
248 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT)
249 
250 /*
251  * CMD_CRC_CHK_ENABLE (RW)
252  *
253  * Command CRC Check Enable
254  * This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error.
255  * Note:
256  * CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response.
257  * For the tuning command, this bit must always be set to 1 to enable the CRC check.
258  * Values:
259  * 0x0 (DISABLED): Disable
260  * 0x1 (ENABLED): Enable
261  */
262 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL)
263 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U)
264 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK)
265 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT)
266 
267 /*
268  * SUB_CMD_FLAG (RW)
269  *
270  * Sub Command Flag
271  * This bit distinguishes between a main command and a sub command.
272  * Values:
273  * 0x0 (MAIN): Main Command
274  * 0x1 (SUB): Sub Command
275  */
276 #define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL)
277 #define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U)
278 #define SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK)
279 #define SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT)
280 
281 /*
282  * RESP_TYPE_SELECT (RW)
283  *
284  * Response Type Select
285  * This bit indicates the type of response expected from the card.
286  * Values:
287  * 0x0 (NO_RESP): No Response
288  * 0x1 (RESP_LEN_136): Response Length 136
289  * 0x2 (RESP_LEN_48): Response Length 48
290  * 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response
291  */
292 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL)
293 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U)
294 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK)
295 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT)
296 
297 /*
298  * RESP_INT_DISABLE (RW)
299  *
300  * Response Interrupt Disable
301  * The Host Controller supports response check function to avoid overhead of response error check by the Host driver.
302  * Response types of only R1 and R5 can be checked by the Controller.
303  * If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register.
304  * If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1.
305  * The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable.
306  * Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting.
307  * Values:
308  * - 0x0 (ENABLED): Response Interrupt is enabled
309  * - 0x1 (DISABLED): Response Interrupt is disabled
310  */
311 #define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U)
312 #define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U)
313 #define SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK)
314 #define SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT)
315 
316 /*
317  * RESP_ERR_CHK_ENABLE (RW)
318  *
319  * Response Error Check Enable
320  * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller.
321  * If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register.
322  * Note:
323  * - Response error check must not be enabled for any response type other than R1 and R5.
324  * - Response check must not be enabled for the tuning command.
325  * Values:
326  * - 0x0 (DISABLED): Response Error Check is disabled
327  * - 0x1 (ENABLED): Response Error Check is enabled
328  */
329 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U)
330 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U)
331 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)
332 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT)
333 
334 /*
335  * RESP_TYPE (RW)
336  *
337  * Response Type R1/R5
338  * This bit selects either R1 or R5 as a response type when the Response Error Check is selected.
339  * Error statuses checked in R1:
340  * OUT_OF_RANGE
341  * ADDRESS_ERROR
342  * BLOCK_LEN_ERROR
343  * WP_VIOLATION
344  * CARD_IS_LOCKED
345  * COM_CRC_ERROR
346  * CARD_ECC_FAILED
347  * CC_ERROR
348  * ERROR
349  * Response Flags checked in R5:
350  * COM_CRC_ERROR
351  * ERROR
352  * FUNCTION_NUMBER
353  * OUT_OF_RANGE
354  * Values:
355  * 0x0 (RESP_R1): R1 (Memory)
356  * 0x1 (RESP_R5): R5 (SDIO)
357  */
358 #define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U)
359 #define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U)
360 #define SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK)
361 #define SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT)
362 
363 /*
364  * MULTI_BLK_SEL (RW)
365  *
366  * Multi/Single Block Select
367  * This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register.
368  * Values:
369  * 0x0 (SINGLE): Single Block
370  * 0x1 (MULTI): Multiple Block
371  */
372 #define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U)
373 #define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U)
374 #define SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK)
375 #define SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT)
376 
377 /*
378  * DATA_XFER_DIR (RW)
379  *
380  * Data Transfer Direction Select
381  * This bit defines the direction of DAT line data transfers.
382  * This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands.
383  * Values:
384  * 0x1 (READ): Read (Card to Host)
385  * 0x0 (WRITE): Write (Host to Card)
386  */
387 #define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U)
388 #define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U)
389 #define SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK)
390 #define SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT)
391 
392 /*
393  * AUTO_CMD_ENABLE (RW)
394  *
395  * Auto Command Enable
396  * This field determines use of Auto Command functions.
397  * Note: In SDIO, this field must be set as 00b (Auto Command Disabled).
398  * Values:
399  * 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled
400  * 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable
401  * 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable
402  * 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel
403  */
404 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU)
405 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U)
406 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK)
407 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT)
408 
409 /*
410  * BLOCK_COUNT_ENABLE (RW)
411  *
412  * Block Count Enable
413  * This bit is used to enable the Block Count register, which is relevant for multiple block transfers.
414  * If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
415  * The Host Driver must set this bit to 0 when ADMA is used.
416  * Values:
417  * 0x1 (ENABLED): Enable
418  * 0x0 (DISABLED): Disable
419  */
420 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U)
421 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U)
422 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK)
423 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT)
424 
425 /*
426  * DMA_ENABLE (RW)
427  *
428  * DMA Enable
429  * This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register.
430  * You can select one of the DMA modes by using DMA Select in the Host Control 1 register.
431  * Values:
432  * 0x1 (ENABLED): DMA Data transfer
433  * 0x0 (DISABLED): No data transfer or Non-DMA data transfer
434  */
435 #define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U)
436 #define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U)
437 #define SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK)
438 #define SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT)
439 
440 /* Bitfield definition for register array: RESP */
441 /*
442  * RESP01 (RO)
443  *
444  * Command Response
445  * These bits reflect 39-8 bits of SD/eMMC Response Field.
446  * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register.
447  */
448 #define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL)
449 #define SDXC_RESP_RESP01_SHIFT (0U)
450 #define SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT)
451 
452 /* Bitfield definition for register: BUF_DATA */
453 /*
454  * BUF_DATA (RW)
455  *
456  * Buffer Data
457  * These bits enable access to the Host Controller packet buffer.
458  */
459 #define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL)
460 #define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U)
461 #define SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK)
462 #define SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT)
463 
464 /* Bitfield definition for register: PSTATE */
465 /*
466  * SUB_CMD_STAT (RO)
467  *
468  * Sub Command Status
469  * This bit is used to distinguish between a main command and a sub command status.
470  * Values:
471  * 0x0 (FALSE): Main Command Status
472  * 0x1 (TRUE): Sub Command Status
473  */
474 #define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL)
475 #define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U)
476 #define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT)
477 
478 /*
479  * CMD_ISSUE_ERR (RO)
480  *
481  * Command Not Issued by Error
482  * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error.
483  * Values:
484  * 0x0 (FALSE): No error for issuing a command
485  * 0x1 (TRUE): Command cannot be issued
486  */
487 #define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL)
488 #define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U)
489 #define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT)
490 
491 /*
492  * CMD_LINE_LVL (RO)
493  *
494  * Command-Line Signal Level
495  * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal.
496  */
497 #define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL)
498 #define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U)
499 #define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT)
500 
501 /*
502  * DAT_3_0 (RO)
503  *
504  * DAT[3:0] Line Signal Level
505  * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal.
506  */
507 #define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL)
508 #define SDXC_PSTATE_DAT_3_0_SHIFT (20U)
509 #define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT)
510 
511 /*
512  * WR_PROTECT_SW_LVL (RO)
513  *
514  * Write Protect Switch Pin Level
515  * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal.
516  * Values:
517  * 0x0 (FALSE): Write protected
518  * 0x1 (TRUE): Write enabled
519  */
520 #define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL)
521 #define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U)
522 #define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT)
523 
524 /*
525  * CARD_DETECT_PIN_LEVEL (RO)
526  *
527  * Card Detect Pin Level
528  * This bit reflects the inverse synchronized value of the card_detect_n signal.
529  * Values:
530  * 0x0 (FALSE): No card present
531  * 0x1 (TRUE): Card Present
532  */
533 #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL)
534 #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U)
535 #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT)
536 
537 /*
538  * CARD_STABLE (RO)
539  *
540  * Card Stable
541  * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0.
542  * Values:
543  * 0x0 (FALSE): Reset or Debouncing
544  * 0x1 (TRUE): No Card or Inserted
545  */
546 #define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL)
547 #define SDXC_PSTATE_CARD_STABLE_SHIFT (17U)
548 #define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT)
549 
550 /*
551  * CARD_INSERTED (RO)
552  *
553  * Card Inserted
554  * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize.
555  * Values:
556  * 0x0 (FALSE): Reset, Debouncing, or No card
557  * 0x1 (TRUE): Card Inserted
558  */
559 #define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL)
560 #define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U)
561 #define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT)
562 
563 /*
564  * BUF_RD_ENABLE (RO)
565  *
566  * Buffer Read Enable
567  * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer.
568  * Values:
569  * 0x0 (DISABLED): Read disable
570  * 0x1 (ENABLED): Read enable
571  */
572 #define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U)
573 #define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U)
574 #define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT)
575 
576 /*
577  * BUF_WR_ENABLE (RO)
578  *
579  * Buffer Write Enable
580  * This bit is used for non-DMA transfers. This bit is set if space is available for writing data.
581  * Values:
582  * 0x0 (DISABLED): Write disable
583  * 0x1 (ENABLED): Write enable
584  */
585 #define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U)
586 #define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U)
587 #define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT)
588 
589 /*
590  * RD_XFER_ACTIVE (RO)
591  *
592  * Read Transfer Active
593  * This bit indicates whether a read transfer is active for SD/eMMC mode.
594  * Values:
595  * 0x0 (INACTIVE): No valid data
596  * 0x1 (ACTIVE): Transferring data
597  */
598 #define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U)
599 #define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U)
600 #define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT)
601 
602 /*
603  * WR_XFER_ACTIVE (RO)
604  *
605  * Write Transfer Active
606  * This status indicates whether a write transfer is active for SD/eMMC mode.
607  * Values:
608  * 0x0 (INACTIVE): No valid data
609  * 0x1 (ACTIVE): Transferring data
610  */
611 #define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U)
612 #define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U)
613 #define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT)
614 
615 /*
616  * DAT_7_4 (RO)
617  *
618  * DAT[7:4] Line Signal Level
619  * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal.
620  */
621 #define SDXC_PSTATE_DAT_7_4_MASK (0xF0U)
622 #define SDXC_PSTATE_DAT_7_4_SHIFT (4U)
623 #define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT)
624 
625 /*
626  * RE_TUNE_REQ (RO)
627  *
628  * Re-Tuning Request
629  * SDXC does not generate retuning request. The software must maintain the Retuning timer.
630  */
631 #define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U)
632 #define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U)
633 #define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT)
634 
635 /*
636  * DAT_LINE_ACTIVE (RO)
637  *
638  * DAT Line Active (
639  * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use.
640  * In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus.
641  * In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus.
642  * For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus.
643  * Values:
644  * 0x0 (INACTIVE): DAT Line Inactive
645  * 0x1 (ACTIVE): DAT Line Active
646  */
647 #define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U)
648 #define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U)
649 #define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT)
650 
651 /*
652  * DAT_INHIBIT (RO)
653  *
654  * Command Inhibit (DAT)
655  * This bit is generated if either DAT line active or Read transfer active is set to 1.
656  * If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands.
657  * Values:
658  * 0x0 (READY): Can issue command which used DAT line
659  * 0x1 (NOT_READY): Cannot issue command which used DAT line
660  */
661 #define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U)
662 #define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U)
663 #define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT)
664 
665 /*
666  * CMD_INHIBIT (RO)
667  *
668  * Command Inhibit (CMD)
669  * This bit indicates the following :
670  * If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line.
671  * This bit is set when the command register is written. This bit is cleared when the command response is received.
672  * This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command.
673  * Values:
674  * 0x0 (READY): Host Controller is ready to issue a command
675  * 0x1 (NOT_READY): Host Controller is not ready to issue a command
676  */
677 #define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U)
678 #define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U)
679 #define SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT)
680 
681 /* Bitfield definition for register: PROT_CTRL */
682 /*
683  * CARD_REMOVAL (RW)
684  *
685  * Wakeup Event Enable on SD Card Removal
686  * This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register.
687  * For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit.
688  * Values:
689  * 0x0 (DISABLED): Disable
690  * 0x1 (ENABLED): Enable
691  */
692 #define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL)
693 #define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U)
694 #define SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK)
695 #define SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT)
696 
697 /*
698  * CARD_INSERT (RW)
699  *
700  * Wakeup Event Enable on SD Card Insertion
701  * This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register.
702  * FN_WUS (Wake Up Support) in CIS does not affect this bit.
703  * Values:
704  * 0x0 (DISABLED): Disable
705  * 0x1 (ENABLED): Enable
706  */
707 #define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL)
708 #define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U)
709 #define SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK)
710 #define SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT)
711 
712 /*
713  * CARD_INT (RW)
714  *
715  * Wakeup Event Enable on Card Interrupt
716  * This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register.
717  * This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
718  * Values:
719  * 0x0 (DISABLED): Disable
720  * 0x1 (ENABLED): Enable
721  */
722 #define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL)
723 #define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U)
724 #define SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK)
725 #define SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT)
726 
727 /*
728  * INT_AT_BGAP (RW)
729  *
730  * Interrupt At Block Gap
731  * This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle.
732  * Setting to 1 enables interrupt detection at the block gap for a multiple block transfer.
733  * Values:
734  * 0x0 (DISABLE): Disabled
735  * 0x1 (ENABLE): Enabled
736  */
737 #define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL)
738 #define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U)
739 #define SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK)
740 #define SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT)
741 
742 /*
743  * RD_WAIT_CTRL (RW)
744  *
745  * Read Wait Control
746  * This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait.
747  * Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled.
748  * Values:
749  * 0x0 (DISABLE): Disable Read Wait Control
750  * 0x1 (ENABLE): Enable Read Wait Control
751  */
752 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL)
753 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U)
754 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK)
755 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT)
756 
757 /*
758  * CONTINUE_REQ (RW)
759  *
760  * Continue Request
761  * This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request.
762  * The Host Controller automatically clears this bit when the transaction restarts.
763  * If stop at block gap request is set to 1, any write to this bit is ignored.
764  * Values:
765  * 0x0 (NO_AFFECT): No Affect
766  * 0x1 (RESTART): Restart
767  */
768 #define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL)
769 #define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U)
770 #define SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK)
771 #define SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT)
772 
773 /*
774  * STOP_BG_REQ (RW)
775  *
776  * Stop At Block Gap Request
777  * This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers.
778  * Values:
779  * 0x0 (XFER): Transfer
780  * 0x1 (STOP): Stop
781  */
782 #define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL)
783 #define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U)
784 #define SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK)
785 #define SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT)
786 
787 /*
788  * SD_BUS_VOL_VDD1 (RW)
789  *
790  * SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD
791  * These bits enable the Host Driver to select the voltage level for an SD/eMMC card.
792  * Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register.
793  * If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage.
794  * The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry.
795  * SD Bus Voltage Select options:
796  * 0x7 : 3.3V(Typical)
797  * 0x6 : 3.0V(Typical)
798  * 0x5 : 1.8V(Typical) for Embedded
799  * 0x4 : 0x0 - Reserved
800  * eMMC Bus Voltage Select options:
801  * 0x7 : 3.3V(Typical)
802  * 0x6 : 1.8V(Typical)
803  * 0x5 : 1.2V(Typical)
804  * 0x4 : 0x0 - Reserved
805  * Values:
806  * 0x7 (V_3_3): 3.3V (Typ.)
807  * 0x6 (V_3_0): 3.0V (Typ.)
808  * 0x5 (V_1_8): 1.8V (Typ.) for Embedded
809  * 0x4 (RSVD4): Reserved
810  * 0x3 (RSVD3): Reserved
811  * 0x2 (RSVD2): Reserved
812  * 0x1 (RSVD1): Reserved
813  * 0x0 (RSVD0): Reserved
814  */
815 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U)
816 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U)
817 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK)
818 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT)
819 
820 /*
821  * SD_BUS_PWR_VDD1 (RW)
822  *
823  * SD Bus Power for VDD1
824  * This bit enables VDD1 power of the card.
825  * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card.
826  * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared.
827  * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register.
828  * Values:
829  * 0x0 (OFF): Power off
830  * 0x1 (ON): Power on
831  */
832 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U)
833 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U)
834 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK)
835 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT)
836 
837 /*
838  * EXT_DAT_XFER (RW)
839  *
840  * Extended Data Transfer Width
841  * This bit controls 8-bit bus width mode of embedded device.
842  * Values:
843  * 0x1 (EIGHT_BIT): 8-bit Bus Width
844  * 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width
845  */
846 #define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U)
847 #define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U)
848 #define SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK)
849 #define SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT)
850 
851 /*
852  * DMA_SEL (RW)
853  *
854  * DMA Select
855  * This field is used to select the DMA type.
856  * When Host Version 4 Enable is 1 in Host Control 2 register:
857  * 0x0 : SDMA is selected
858  * 0x1 : Reserved
859  * 0x2 : ADMA2 is selected
860  * 0x3 : ADMA2 or ADMA3 is selected
861  * When Host Version 4 Enable is 0 in Host Control 2 register:
862  * 0x0 : SDMA is selected
863  * 0x1 : Reserved
864  * 0x2 : 32-bit Address ADMA2 is selected
865  * 0x3 : 64-bit Address ADMA2 is selected
866  * Values:
867  * 0x0 (SDMA): SDMA is selected
868  * 0x1 (RSVD_BIT): Reserved
869  * 0x2 (ADMA2): ADMA2 is selected
870  * 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected
871  */
872 #define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U)
873 #define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U)
874 #define SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK)
875 #define SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT)
876 
877 /*
878  * HIGH_SPEED_EN (RW)
879  *
880  * High Speed Enable
881  * this bit is used to determine the selection of preset value for High Speed mode.
882  * Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register.
883  * Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit.
884  * Values:
885  * 0x1 (HIGH_SPEED): High Speed mode
886  * 0x0 (NORMAL_SPEED): Normal Speed mode
887  */
888 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U)
889 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U)
890 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK)
891 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT)
892 
893 /*
894  * DAT_XFER_WIDTH (RW)
895  *
896  * Data Transfer Width
897  * For SD/eMMC mode,this bit selects the data transfer width of the Host Controller.
898  * The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant.
899  * Values:
900  * 0x1 (FOUR_BIT): 4-bit mode
901  * 0x0 (ONE_BIT): 1-bit mode
902  */
903 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U)
904 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U)
905 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK)
906 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT)
907 
908 /* Bitfield definition for register: SYS_CTRL */
909 /*
910  * SW_RST_DAT (RW)
911  *
912  * Software Reset For DAT line
913  * This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset.
914  * The following registers and bits are cleared by this bit:
915  * Buffer Data Port register
916  * -Buffer is cleared and initialized.
917  * Present state register
918  * -Buffer Read Enable
919  * -Buffer Write Enable
920  * -Read Transfer Active
921  * -Write Transfer Active
922  * -DAT Line Active
923  * -Command Inhibit (DAT)
924  * Block Gap Control register
925  * -Continue Request
926  * -Stop At Block Gap Request
927  * Normal Interrupt status register
928  * -Buffer Read Ready
929  * -Buffer Write Ready
930  * -DMA Interrupt
931  * -Block Gap Event
932  * -Transfer Complete
933  * In UHS-II mode, this bit shall be set to 0
934  * Values:
935  * 0x0 (FALSE): Work
936  * 0x1 (TRUE): Reset
937  */
938 #define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL)
939 #define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U)
940 #define SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK)
941 #define SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT)
942 
943 /*
944  * SW_RST_CMD (RW)
945  *
946  * Software Reset For CMD line
947  * This bit resets only a part of the command circuit to be able to issue a command.
948  * It bit is also used to initialize a UHS-II command circuit.
949  * This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit.
950  * Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors.
951  * The following registers and bits are cleared by this bit:
952  * Present State register : Command Inhibit (CMD) bit
953  * Normal Interrupt Status register : Command Complete bit
954  * Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit
955  * Values:
956  * 0x0 (FALSE): Work
957  * 0x1 (TRUE): Reset
958  */
959 #define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL)
960 #define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U)
961 #define SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK)
962 #define SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT)
963 
964 /*
965  * SW_RST_ALL (RW)
966  *
967  * Software Reset For All
968  * This reset affects the entire Host Controller except for the card detection circuit.
969  * During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller.
970  * All registers are reset except the capabilities register.
971  * If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card.
972  * Values:
973  * 0x0 (FALSE): Work
974  * 0x1 (TRUE): Reset
975  */
976 #define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL)
977 #define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U)
978 #define SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK)
979 #define SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT)
980 
981 /*
982  * TOUT_CNT (RW)
983  *
984  * Data Timeout Counter Value.
985  * This value determines the interval by which DAT line timeouts are detected.
986  * The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value.
987  * When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register).
988  * The values for these bits are:
989  * 0xF : Reserved
990  * 0xE : TMCLK x 2^27
991  * .........
992  * 0x1 : TMCLK x 2^14
993  * 0x0 : TMCLK x 2^13
994  * Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit.
995  */
996 #define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL)
997 #define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U)
998 #define SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK)
999 #define SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT)
1000 
1001 /*
1002  * FREQ_SEL (RW)
1003  *
1004  * SDCLK/RCLK Frequency Select
1005  * These bits are used to select the frequency of the SDCLK signal.
1006  * These bits depend on setting of Preset Value Enable in the Host Control 2 register.
1007  * If Preset Value Enable = 0, these bits are set by the Host Driver.
1008  * If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register.
1009  * The value is reflected on the lower 8-bit of the card_clk_freq_selsignal.
1010  * 10-bit Divided Clock Mode:
1011  * 0x3FF : 1/2046 Divided clock
1012  * ..........
1013  * N : 1/2N Divided Clock
1014  * ..........
1015  * 0x002 : 1/4 Divided Clock
1016  * 0x001 : 1/2 Divided Clock
1017  * 0x000 : Base clock (10MHz - 255 MHz)
1018  * Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency:
1019  * 0x3FF : Base clock * M /1024
1020  * ..........
1021  * N-1 : Base clock * M /N
1022  * ..........
1023  * 0x002 : Base clock * M /3
1024  * 0x001 : Base clock * M /2
1025  * 0x000 : Base clock * M
1026  */
1027 #define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U)
1028 #define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U)
1029 #define SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK)
1030 #define SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT)
1031 
1032 /*
1033  * UPPER_FREQ_SEL (RW)
1034  *
1035  * These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control.
1036  * The value is reflected on the upper 2 bits of the card_clk_freq_sel signal.
1037  */
1038 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U)
1039 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U)
1040 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK)
1041 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT)
1042 
1043 /*
1044  * CLK_GEN_SELECT (RW)
1045  *
1046  * Clock Generator Select
1047  * This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select.
1048  * If Preset Value Enable = 0, this bit is set by the Host Driver.
1049  * If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers.
1050  * The value is reflected on the card_clk_gen_sel signal.
1051  * Values:
1052  * 0x0 (FALSE): Divided Clock Mode
1053  * 0x1 (TRUE): Programmable Clock Mode
1054  */
1055 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U)
1056 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U)
1057 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK)
1058 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT)
1059 
1060 /*
1061  * PLL_ENABLE (RW)
1062  *
1063  * PLL Enable
1064  * This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1).
1065  * When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal.
1066  * Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' .
1067  * Values:
1068  * 0x0 (FALSE): PLL is in low power mode
1069  * 0x1 (TRUE): PLL is enabled
1070  */
1071 #define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U)
1072 #define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U)
1073 #define SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK)
1074 #define SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT)
1075 
1076 /*
1077  * SD_CLK_EN (RW)
1078  *
1079  * SD/eMMC Clock Enable
1080  * This bit stops the SDCLK or RCLK when set to 0.
1081  * The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0.
1082  * The value is reflected on the clk2card_on pin.
1083  * Values:
1084  * 0x0 (FALSE): Disable providing SDCLK/RCLK
1085  * 0x1 (TRUE): Enable providing SDCLK/RCLK
1086  */
1087 #define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U)
1088 #define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U)
1089 #define SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK)
1090 #define SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT)
1091 
1092 /*
1093  * INTERNAL_CLK_STABLE (RW)
1094  *
1095  * Internal Clock Stable
1096  * This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set.
1097  * This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1,
1098  * and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1.
1099  * Values:
1100  * 0x0 (FALSE): Not Ready
1101  * 0x1 (TRUE): Ready
1102  */
1103 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U)
1104 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U)
1105 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)
1106 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT)
1107 
1108 /*
1109  * INTERNAL_CLK_EN (RW)
1110  *
1111  * Internal Clock Enable
1112  * This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt.
1113  * The Host Controller must stop its internal clock to enter a very low power state.
1114  * However, registers can still be read and written to. The value is reflected on the intclk_en signal.
1115  * Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' .
1116  * Values:
1117  * 0x0 (FALSE): Stop
1118  * 0x1 (TRUE): Oscillate
1119  */
1120 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U)
1121 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U)
1122 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK)
1123 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT)
1124 
1125 /* Bitfield definition for register: INT_STAT */
1126 /*
1127  * BOOT_ACK_ERR (R/W1C)
1128  *
1129  * Boot Acknowledgment Error
1130  * This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode.
1131  * In SD/UHS-II mode, this bit is irrelevant.
1132  */
1133 #define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL)
1134 #define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U)
1135 #define SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK)
1136 #define SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT)
1137 
1138 /*
1139  * RESP_ERR (R/W1C)
1140  *
1141  * Response Error
1142  * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution.
1143  * If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode.
1144  * Values:
1145  * 0x0 (FALSE): No error
1146  * 0x1 (TRUE): Error
1147  */
1148 #define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL)
1149 #define SDXC_INT_STAT_RESP_ERR_SHIFT (27U)
1150 #define SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK)
1151 #define SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT)
1152 
1153 /*
1154  * TUNING_ERR (R/W1C)
1155  *
1156  * Tuning Error
1157  * This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure
1158  * (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register).
1159  * By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning.
1160  * To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure.
1161  * The Tuning Error is higher priority than the other error interrupts generated during data transfer.
1162  * By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error.
1163  * This is applicable in SD/eMMC mode.
1164  * Values:
1165  * 0x0 (FALSE): No error
1166  * 0x1 (TRUE): Error
1167  */
1168 #define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL)
1169 #define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U)
1170 #define SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK)
1171 #define SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT)
1172 
1173 /*
1174  * ADMA_ERR (R/W1C)
1175  *
1176  * ADMA Error
1177  * This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons:
1178  * Error response received from System bus (Master I/F)
1179  * ADMA3,ADMA2 Descriptors invalid
1180  * CQE Task or Transfer descriptors invalid
1181  * When the error occurs, the state of the ADMA is saved in the ADMA Error Status register.
1182  * In eMMC CQE mode:
1183  * The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state.
1184  * ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state.
1185  * The Host Driver may find that Valid bit is not set at the error descriptor.
1186  * Values:
1187  * 0x0 (FALSE): No error
1188  * 0x1 (TRUE): Error
1189  */
1190 #define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL)
1191 #define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U)
1192 #define SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK)
1193 #define SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT)
1194 
1195 /*
1196  * AUTO_CMD_ERR (R/W1C)
1197  *
1198  * Auto CMD Error
1199  * This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode.
1200  * This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1.
1201  * D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit.
1202  * Values:
1203  * 0x0 (FALSE): No error
1204  * 0x1 (TRUE): Error
1205  */
1206 #define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL)
1207 #define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U)
1208 #define SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK)
1209 #define SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT)
1210 
1211 /*
1212  * CUR_LMT_ERR (R/W1C)
1213  *
1214  * Current Limit Error
1215  * By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus.
1216  * If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status.
1217  * A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure.
1218  * A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred.
1219  * The Host Controller may require some sampling time to detect the current limit.
1220  * SDXC Host Controller does not support this function, this bit is always set to 0.
1221  * Values:
1222  * 0x0 (FALSE): No error
1223  * 0x1 (TRUE): Power Fail
1224  */
1225 #define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL)
1226 #define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U)
1227 #define SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK)
1228 #define SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT)
1229 
1230 /*
1231  * DATA_END_BIT_ERR (R/W1C)
1232  *
1233  * Data End Bit Error
1234  * This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status.
1235  * Values:
1236  * 0x0 (FALSE): No error
1237  * 0x1 (TRUE): Error
1238  */
1239 #define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL)
1240 #define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U)
1241 #define SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK)
1242 #define SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT)
1243 
1244 /*
1245  * DATA_CRC_ERR (R/W1C)
1246  *
1247  * Data CRC Error
1248  * This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line,
1249  * when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout.
1250  * Values:
1251  * 0x0 (FALSE): No error
1252  * 0x1 (TRUE): Error
1253  */
1254 #define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL)
1255 #define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U)
1256 #define SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK)
1257 #define SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT)
1258 
1259 /*
1260  * DATA_TOUT_ERR (R/W1C)
1261  *
1262  * Data Timeout Error
1263  * This bit is set in SD/eMMC mode when detecting one of the following timeout conditions:
1264  * Busy timeout for R1b, R5b type
1265  * Busy timeout after Write CRC status
1266  * Write CRC Status timeout
1267  * Read Data timeout
1268  * Values:
1269  * 0x0 (FALSE): No error
1270  * 0x1 (TRUE): Time out
1271  */
1272 #define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL)
1273 #define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U)
1274 #define SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK)
1275 #define SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT)
1276 
1277 /*
1278  * CMD_IDX_ERR (R/W1C)
1279  *
1280  * Command Index Error
1281  * This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode.
1282  * Values:
1283  * 0x0 (FALSE): No error
1284  * 0x1 (TRUE): Error
1285  */
1286 #define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL)
1287 #define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U)
1288 #define SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK)
1289 #define SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT)
1290 
1291 /*
1292  * CMD_END_BIT_ERR (R/W1C)
1293  *
1294  * Command End Bit Error
1295  * This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode.
1296  * Values:
1297  * 0x0 (FALSE): No error
1298  * 0x1 (TRUE): End Bit error generated
1299  */
1300 #define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL)
1301 #define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U)
1302 #define SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK)
1303 #define SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT)
1304 
1305 /*
1306  * CMD_CRC_ERR (R/W1C)
1307  *
1308  * Command CRC Error
1309  * Command CRC Error is generated in SD/eMMC mode for following two cases.
1310  * If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response.
1311  * The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued.
1312  * If the Host Controller drives the CMD line to 1 level,
1313  * but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1.
1314  * The Command Timeout Error is also set to 1 to distinguish a CMD line conflict.
1315  * Values:
1316  * 0x0 (FALSE): No error
1317  * 0x1 (TRUE): CRC error generated
1318  */
1319 #define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL)
1320 #define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U)
1321 #define SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK)
1322 #define SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT)
1323 
1324 /*
1325  * CMD_TOUT_ERR (R/W1C)
1326  *
1327  * Command Timeout Error
1328  * In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command.
1329  * If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles.
1330  * Values:
1331  * 0x0 (FALSE): No error
1332  * 0x1 (TRUE): Time out
1333  */
1334 #define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL)
1335 #define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U)
1336 #define SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK)
1337 #define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT)
1338 
1339 /*
1340  * ERR_INTERRUPT (RO)
1341  *
1342  * Error Interrupt
1343  * If any of the bits in the Error Interrupt Status register are set, then this bit is set.
1344  * Values:
1345  * 0x0 (FALSE): No Error
1346  * 0x1 (TRUE): Error
1347  */
1348 #define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U)
1349 #define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U)
1350 #define SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT)
1351 
1352 /*
1353  * CQE_EVENT (R/W1C)
1354  *
1355  * Command Queuing Event
1356  * This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details.
1357  * Values:
1358  * 0x0 (FALSE): No Event
1359  * 0x1 (TRUE): Command Queuing Event is detected
1360  */
1361 #define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U)
1362 #define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U)
1363 #define SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK)
1364 #define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT)
1365 
1366 /*
1367  * FX_EVENT (RO)
1368  *
1369  * FX Event
1370  * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function.
1371  * Values:
1372  * 0x0 (FALSE): No Event
1373  * 0x1 (TRUE): FX Event is detected
1374  */
1375 #define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U)
1376 #define SDXC_INT_STAT_FX_EVENT_SHIFT (13U)
1377 #define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT)
1378 
1379 /*
1380  * RE_TUNE_EVENT (RO)
1381  *
1382  * Re-tuning Event
1383  * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported.
1384  */
1385 #define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U)
1386 #define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U)
1387 #define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT)
1388 
1389 /*
1390  * CARD_INTERRUPT (RO)
1391  *
1392  * Card Interrupt
1393  * This bit reflects the synchronized value of:
1394  * DAT[1] Interrupt Input for SD Mode
1395  * DAT[2] Interrupt Input for UHS-II Mode
1396  * Values:
1397  * 0x0 (FALSE): No Card Interrupt
1398  * 0x1 (TRUE): Generate Card Interrupt
1399  */
1400 #define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U)
1401 #define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U)
1402 #define SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT)
1403 
1404 /*
1405  * CARD_REMOVAL (R/W1C)
1406  *
1407  * Card Removal
1408  * This bit is set if the Card Inserted in the Present State register changes from 1 to 0.
1409  * Values:
1410  * 0x0 (FALSE): Card state stable or Debouncing
1411  * 0x1 (TRUE): Card Removed
1412  */
1413 #define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U)
1414 #define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U)
1415 #define SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK)
1416 #define SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT)
1417 
1418 /*
1419  * CARD_INSERTION (R/W1C)
1420  *
1421  * Card Insertion
1422  * This bit is set if the Card Inserted in the Present State register changes from 0 to 1.
1423  * Values:
1424  * 0x0 (FALSE): Card state stable or Debouncing
1425  * 0x1 (TRUE): Card Inserted
1426  */
1427 #define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U)
1428 #define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U)
1429 #define SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK)
1430 #define SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT)
1431 
1432 /*
1433  * BUF_RD_READY (R/W1C)
1434  *
1435  * Buffer Read Ready
1436  * This bit is set if the Buffer Read Enable changes from 0 to 1.
1437  * Values:
1438  * 0x0 (FALSE): Not ready to read buffer
1439  * 0x1 (TRUE): Ready to read buffer
1440  */
1441 #define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U)
1442 #define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U)
1443 #define SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK)
1444 #define SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT)
1445 
1446 /*
1447  * BUF_WR_READY (R/W1C)
1448  *
1449  * Buffer Write Ready
1450  * This bit is set if the Buffer Write Enable changes from 0 to 1.
1451  * Values:
1452  * 0x0 (FALSE): Not ready to write buffer
1453  * 0x1 (TRUE): Ready to write buffer
1454  */
1455 #define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U)
1456 #define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U)
1457 #define SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK)
1458 #define SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT)
1459 
1460 /*
1461  * DMA_INTERRUPT (R/W1C)
1462  *
1463  * DMA Interrupt
1464  * This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer.
1465  * In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt.
1466  * This interrupt is not generated after a Transfer Complete.
1467  * Values:
1468  * 0x0 (FALSE): No DMA Interrupt
1469  * 0x1 (TRUE): DMA Interrupt is generated
1470  */
1471 #define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U)
1472 #define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U)
1473 #define SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK)
1474 #define SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT)
1475 
1476 /*
1477  * BGAP_EVENT (R/W1C)
1478  *
1479  * Block Gap Event
1480  * This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request.
1481  * Values:
1482  * 0x0 (FALSE): No Block Gap Event
1483  * 0x1 (TRUE): Transaction stopped at block gap
1484  */
1485 #define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U)
1486 #define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U)
1487 #define SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK)
1488 #define SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT)
1489 
1490 /*
1491  * XFER_COMPLETE (R/W1C)
1492  *
1493  * Transfer Complete
1494  * This bit is set when a read/write transfer and a command with status busy is completed.
1495  * Values:
1496  * 0x0 (FALSE): Not complete
1497  * 0x1 (TRUE): Command execution is completed
1498  */
1499 #define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U)
1500 #define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U)
1501 #define SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK)
1502 #define SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT)
1503 
1504 /*
1505  * CMD_COMPLETE (R/W1C)
1506  *
1507  * Command Complete
1508  * In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23.
1509  * This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1.
1510  * Values:
1511  * 0x0 (FALSE): No command complete
1512  * 0x1 (TRUE): Command Complete
1513  */
1514 #define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U)
1515 #define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U)
1516 #define SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK)
1517 #define SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT)
1518 
1519 /* Bitfield definition for register: INT_STAT_EN */
1520 /*
1521  * BOOT_ACK_ERR_STAT_EN (RW)
1522  *
1523  * Boot Acknowledgment Error (eMMC Mode only)
1524  * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT).
1525  * Values:
1526  * 0x0 (FALSE): Masked
1527  * 0x1 (TRUE): Enabled
1528  */
1529 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL)
1530 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U)
1531 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK)
1532 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT)
1533 
1534 /*
1535  * RESP_ERR_STAT_EN (RW)
1536  *
1537  * Response Error Status Enable (SD Mode only)
1538  * Values:
1539  * 0x0 (FALSE): Masked
1540  * 0x1 (TRUE): Enabled
1541  */
1542 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL)
1543 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U)
1544 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK)
1545 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT)
1546 
1547 /*
1548  * TUNING_ERR_STAT_EN (RW)
1549  *
1550  * Tuning Error Status Enable (UHS-I Mode only)
1551  * Values:
1552  * 0x0 (FALSE): Masked
1553  * 0x1 (TRUE): Enabled
1554  */
1555 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL)
1556 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U)
1557 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK)
1558 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT)
1559 
1560 /*
1561  * ADMA_ERR_STAT_EN (RW)
1562  *
1563  * ADMA Error Status Enable
1564  * Values:
1565  * 0x0 (FALSE): Masked
1566  * 0x1 (TRUE): Enabled
1567  */
1568 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL)
1569 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U)
1570 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK)
1571 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT)
1572 
1573 /*
1574  * AUTO_CMD_ERR_STAT_EN (RW)
1575  *
1576  * Auto CMD Error Status Enable (SD/eMMC Mode only).
1577  * Values:
1578  * 0x0 (FALSE): Masked
1579  * 0x1 (TRUE): Enabled
1580  */
1581 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL)
1582 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U)
1583 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK)
1584 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT)
1585 
1586 /*
1587  * CUR_LMT_ERR_STAT_EN (RW)
1588  *
1589  * Current Limit Error Status Enable
1590  * Values:
1591  * 0x0 (FALSE): Masked
1592  * 0x1 (TRUE): Enabled
1593  */
1594 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL)
1595 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U)
1596 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK)
1597 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT)
1598 
1599 /*
1600  * DATA_END_BIT_ERR_STAT_EN (RW)
1601  *
1602  * Data End Bit Error Status Enable (SD/eMMC Mode only).
1603  * Values:
1604  * 0x0 (FALSE): Masked
1605  * 0x1 (TRUE): Enabled
1606  */
1607 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL)
1608 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U)
1609 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK)
1610 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT)
1611 
1612 /*
1613  * DATA_CRC_ERR_STAT_EN (RW)
1614  *
1615  * Data CRC Error Status Enable (SD/eMMC Mode only)
1616  * Values:
1617  * 0x0 (FALSE): Masked
1618  * 0x1 (TRUE): Enabled
1619  */
1620 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL)
1621 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U)
1622 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK)
1623 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT)
1624 
1625 /*
1626  * DATA_TOUT_ERR_STAT_EN (RW)
1627  *
1628  * Data Timeout Error Status Enable (SD/eMMC Mode only)
1629  * Values:
1630  * 0x0 (FALSE): Masked
1631  * 0x1 (TRUE): Enabled
1632  */
1633 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL)
1634 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U)
1635 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK)
1636 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT)
1637 
1638 /*
1639  * CMD_IDX_ERR_STAT_EN (RW)
1640  *
1641  * Command Index Error Status Enable (SD/eMMC Mode only)
1642  * Values:
1643  * 0x0 (FALSE): Masked
1644  * 0x1 (TRUE): Enabled
1645  */
1646 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL)
1647 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U)
1648 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK)
1649 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT)
1650 
1651 /*
1652  * CMD_END_BIT_ERR_STAT_EN (RW)
1653  *
1654  * Command End Bit Error Status Enable (SD/eMMC Mode only)
1655  * Values:
1656  * 0x0 (FALSE): Masked
1657  * 0x1 (TRUE): Enabled
1658  */
1659 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL)
1660 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U)
1661 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK)
1662 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT)
1663 
1664 /*
1665  * CMD_CRC_ERR_STAT_EN (RW)
1666  *
1667  * Command CRC Error Status Enable (SD/eMMC Mode only)
1668  * Values:
1669  * 0x0 (FALSE): Masked
1670  * 0x1 (TRUE): Enabled
1671  */
1672 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL)
1673 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U)
1674 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK)
1675 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT)
1676 
1677 /*
1678  * CMD_TOUT_ERR_STAT_EN (RW)
1679  *
1680  * Command Timeout Error Status Enable (SD/eMMC Mode only).
1681  * Values:
1682  * 0x0 (FALSE): Masked
1683  * 0x1 (TRUE): Enabled
1684  */
1685 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL)
1686 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U)
1687 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK)
1688 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT)
1689 
1690 /*
1691  * CQE_EVENT_STAT_EN (RW)
1692  *
1693  * CQE Event Status Enable
1694  * Values:
1695  * 0x0 (FALSE): Masked
1696  * 0x1 (TRUE): Enabled
1697  */
1698 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U)
1699 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U)
1700 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK)
1701 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT)
1702 
1703 /*
1704  * FX_EVENT_STAT_EN (RW)
1705  *
1706  * FX Event Status Enable
1707  * This bit is added from Version 4.10.
1708  * Values:
1709  * 0x0 (FALSE): Masked
1710  * 0x1 (TRUE): Enabled
1711  */
1712 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U)
1713 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U)
1714 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK)
1715 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT)
1716 
1717 /*
1718  * RE_TUNE_EVENT_STAT_EN (RW)
1719  *
1720  * Re-Tuning Event (UHS-I only) Status Enable
1721  * Values:
1722  * 0x0 (FALSE): Masked
1723  * 0x1 (TRUE): Enabled
1724  */
1725 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U)
1726 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U)
1727 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK)
1728 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT)
1729 
1730 /*
1731  * CARD_INTERRUPT_STAT_EN (RW)
1732  *
1733  * Card Interrupt Status Enable
1734  * If this bit is set to 0, the Host Controller clears the interrupt request to the System.
1735  * The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1.
1736  * The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts.
1737  * By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating).
1738  * Values:
1739  * 0x0 (FALSE): Masked
1740  * 0x1 (TRUE): Enabled
1741  */
1742 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U)
1743 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U)
1744 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK)
1745 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT)
1746 
1747 /*
1748  * CARD_REMOVAL_STAT_EN (RW)
1749  *
1750  * Card Removal Status Enable
1751  * Values:
1752  * 0x0 (FALSE): Masked
1753  * 0x1 (TRUE): Enabled
1754  */
1755 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U)
1756 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U)
1757 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK)
1758 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT)
1759 
1760 /*
1761  * CARD_INSERTION_STAT_EN (RW)
1762  *
1763  * Card Insertion Status Enable
1764  * Values:
1765  * 0x0 (FALSE): Masked
1766  * 0x1 (TRUE): Enabled
1767  */
1768 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U)
1769 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U)
1770 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK)
1771 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT)
1772 
1773 /*
1774  * BUF_RD_READY_STAT_EN (RW)
1775  *
1776  * Buffer Read Ready Status Enable
1777  * Values:
1778  * 0x0 (FALSE): Masked
1779  * 0x1 (TRUE): Enabled
1780  */
1781 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U)
1782 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U)
1783 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK)
1784 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT)
1785 
1786 /*
1787  * BUF_WR_READY_STAT_EN (RW)
1788  *
1789  * Buffer Write Ready Status Enable
1790  * Values:
1791  * 0x0 (FALSE): Masked
1792  * 0x1 (TRUE): Enabled
1793  */
1794 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U)
1795 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U)
1796 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK)
1797 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT)
1798 
1799 /*
1800  * DMA_INTERRUPT_STAT_EN (RW)
1801  *
1802  * DMA Interrupt Status Enable
1803  * Values:
1804  * 0x0 (FALSE): Masked
1805  * 0x1 (TRUE): Enabled
1806  */
1807 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U)
1808 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U)
1809 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK)
1810 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT)
1811 
1812 /*
1813  * BGAP_EVENT_STAT_EN (RW)
1814  *
1815  * Block Gap Event Status Enable
1816  * Values:
1817  * 0x0 (FALSE): Masked
1818  * 0x1 (TRUE): Enabled
1819  */
1820 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U)
1821 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U)
1822 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK)
1823 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT)
1824 
1825 /*
1826  * XFER_COMPLETE_STAT_EN (RW)
1827  *
1828  * Transfer Complete Status Enable
1829  * Values:
1830  * 0x0 (FALSE): Masked
1831  * 0x1 (TRUE): Enabled
1832  */
1833 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U)
1834 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U)
1835 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK)
1836 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT)
1837 
1838 /*
1839  * CMD_COMPLETE_STAT_EN (RW)
1840  *
1841  * Command Complete Status Enable
1842  * Values:
1843  * 0x0 (FALSE): Masked
1844  * 0x1 (TRUE): Enabled
1845  */
1846 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U)
1847 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U)
1848 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK)
1849 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT)
1850 
1851 /* Bitfield definition for register: INT_SIGNAL_EN */
1852 /*
1853  * BOOT_ACK_ERR_SIGNAL_EN (RW)
1854  *
1855  * Boot Acknowledgment Error (eMMC Mode only).
1856  * Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set.
1857  * Values:
1858  * 0x0 (FALSE): Masked
1859  * 0x1 (TRUE): Enabled
1860  */
1861 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL)
1862 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U)
1863 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK)
1864 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT)
1865 
1866 /*
1867  * RESP_ERR_SIGNAL_EN (RW)
1868  *
1869  * Response Error Signal Enable (SD Mode only)
1870  * Values:
1871  * 0x0 (FALSE): Masked
1872  * 0x1 (TRUE): Enabled
1873  */
1874 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL)
1875 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U)
1876 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK)
1877 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT)
1878 
1879 /*
1880  * TUNING_ERR_SIGNAL_EN (RW)
1881  *
1882  * Tuning Error Signal Enable (UHS-I Mode only)
1883  * Values:
1884  * 0x0 (FALSE): Masked
1885  * 0x1 (TRUE): Enabled
1886  */
1887 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL)
1888 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U)
1889 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK)
1890 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT)
1891 
1892 /*
1893  * ADMA_ERR_SIGNAL_EN (RW)
1894  *
1895  * ADMA Error Signal Enable
1896  * Values:
1897  * 0x0 (FALSE): Masked
1898  * 0x1 (TRUE): Enabled
1899  */
1900 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL)
1901 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U)
1902 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK)
1903 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT)
1904 
1905 /*
1906  * AUTO_CMD_ERR_SIGNAL_EN (RW)
1907  *
1908  * Auto CMD Error Signal Enable (SD/eMMC Mode only)
1909  * Values:
1910  * 0x0 (FALSE): Masked
1911  * 0x1 (TRUE): Enabled
1912  */
1913 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL)
1914 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U)
1915 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK)
1916 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT)
1917 
1918 /*
1919  * CUR_LMT_ERR_SIGNAL_EN (RW)
1920  *
1921  * Current Limit Error Signal Enable
1922  * Values:
1923  * 0x0 (FALSE): Masked
1924  * 0x1 (TRUE): Enabled
1925  */
1926 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL)
1927 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U)
1928 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK)
1929 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT)
1930 
1931 /*
1932  * DATA_END_BIT_ERR_SIGNAL_EN (RW)
1933  *
1934  * Data End Bit Error Signal Enable (SD/eMMC Mode only)
1935  * Values:
1936  * 0x0 (FALSE): Masked
1937  * 0x1 (TRUE): Enabled
1938  */
1939 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL)
1940 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U)
1941 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK)
1942 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT)
1943 
1944 /*
1945  * DATA_CRC_ERR_SIGNAL_EN (RW)
1946  *
1947  * Data CRC Error Signal Enable (SD/eMMC Mode only)
1948  * Values:
1949  * 0x0 (FALSE): Masked
1950  * 0x1 (TRUE): Enabled
1951  */
1952 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL)
1953 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U)
1954 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK)
1955 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT)
1956 
1957 /*
1958  * DATA_TOUT_ERR_SIGNAL_EN (RW)
1959  *
1960  * Data Timeout Error Signal Enable (SD/eMMC Mode only)
1961  * Values:
1962  * 0x0 (FALSE): Masked
1963  * 0x1 (TRUE): Enabled
1964  */
1965 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL)
1966 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U)
1967 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK)
1968 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT)
1969 
1970 /*
1971  * CMD_IDX_ERR_SIGNAL_EN (RW)
1972  *
1973  * Command Index Error Signal Enable (SD/eMMC Mode only)
1974  * Values:
1975  * 0x0 (FALSE): No error
1976  * 0x1 (TRUE): Error
1977  */
1978 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL)
1979 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U)
1980 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK)
1981 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT)
1982 
1983 /*
1984  * CMD_END_BIT_ERR_SIGNAL_EN (RW)
1985  *
1986  * Command End Bit Error Signal Enable (SD/eMMC Mode only)
1987  * Values:
1988  * 0x0 (FALSE): Masked
1989  * 0x1 (TRUE): Enabled
1990  */
1991 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL)
1992 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U)
1993 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK)
1994 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT)
1995 
1996 /*
1997  * CMD_CRC_ERR_SIGNAL_EN (RW)
1998  *
1999  * Command CRC Error Signal Enable (SD/eMMC Mode only)
2000  * Values:
2001  * 0x0 (FALSE): Masked
2002  * 0x1 (TRUE): Enabled
2003  */
2004 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL)
2005 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U)
2006 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK)
2007 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT)
2008 
2009 /*
2010  * CMD_TOUT_ERR_SIGNAL_EN (RW)
2011  *
2012  * Command Timeout Error Signal Enable (SD/eMMC Mode only)
2013  * Values:
2014  * 0x0 (FALSE): Masked
2015  * 0x1 (TRUE): Enabled
2016  */
2017 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL)
2018 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U)
2019 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK)
2020 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT)
2021 
2022 /*
2023  * CQE_EVENT_SIGNAL_EN (RW)
2024  *
2025  * Command Queuing Engine Event Signal Enable
2026  * Values:
2027  * 0x0 (FALSE): Masked
2028  * 0x1 (TRUE): Enabled
2029  */
2030 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U)
2031 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U)
2032 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK)
2033 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT)
2034 
2035 /*
2036  * FX_EVENT_SIGNAL_EN (RW)
2037  *
2038  * FX Event Signal Enable
2039  * Values:
2040  * 0x0 (FALSE): Masked
2041  * 0x1 (TRUE): Enabled
2042  */
2043 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U)
2044 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U)
2045 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK)
2046 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT)
2047 
2048 /*
2049  * RE_TUNE_EVENT_SIGNAL_EN (RW)
2050  *
2051  * Re-Tuning Event (UHS-I only) Signal Enable.
2052  * Values:
2053  * 0x0 (FALSE): Masked
2054  * 0x1 (TRUE): Enabled
2055  */
2056 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U)
2057 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U)
2058 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK)
2059 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT)
2060 
2061 /*
2062  * CARD_INTERRUPT_SIGNAL_EN (RW)
2063  *
2064  * Card Interrupt Signal Enable
2065  * Values:
2066  * 0x0 (FALSE): Masked
2067  * 0x1 (TRUE): Enabled
2068  */
2069 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U)
2070 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U)
2071 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK)
2072 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT)
2073 
2074 /*
2075  * CARD_REMOVAL_SIGNAL_EN (RW)
2076  *
2077  * Card Removal Signal Enable
2078  * Values:
2079  * 0x0 (FALSE): Masked
2080  * 0x1 (TRUE): Enabled
2081  */
2082 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U)
2083 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U)
2084 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK)
2085 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT)
2086 
2087 /*
2088  * CARD_INSERTION_SIGNAL_EN (RW)
2089  *
2090  * Card Insertion Signal Enable
2091  * Values:
2092  * 0x0 (FALSE): Masked
2093  * 0x1 (TRUE): Enabled
2094  */
2095 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U)
2096 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U)
2097 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK)
2098 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT)
2099 
2100 /*
2101  * BUF_RD_READY_SIGNAL_EN (RW)
2102  *
2103  * Buffer Read Ready Signal Enable
2104  * Values:
2105  * 0x0 (FALSE): Masked
2106  * 0x1 (TRUE): Enabled
2107  */
2108 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U)
2109 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U)
2110 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK)
2111 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT)
2112 
2113 /*
2114  * BUF_WR_READY_SIGNAL_EN (RW)
2115  *
2116  * Buffer Write Ready Signal Enable
2117  * Values:
2118  * 0x0 (FALSE): Masked
2119  * 0x1 (TRUE): Enabled
2120  */
2121 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U)
2122 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U)
2123 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK)
2124 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT)
2125 
2126 /*
2127  * DMA_INTERRUPT_SIGNAL_EN (RW)
2128  *
2129  * DMA Interrupt Signal Enable
2130  * Values:
2131  * 0x0 (FALSE): Masked
2132  * 0x1 (TRUE): Enabled
2133  */
2134 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U)
2135 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U)
2136 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK)
2137 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT)
2138 
2139 /*
2140  * BGAP_EVENT_SIGNAL_EN (RW)
2141  *
2142  * Block Gap Event Signal Enable
2143  * Values:
2144  * 0x0 (FALSE): Masked
2145  * 0x1 (TRUE): Enabled
2146  */
2147 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U)
2148 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U)
2149 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK)
2150 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT)
2151 
2152 /*
2153  * XFER_COMPLETE_SIGNAL_EN (RW)
2154  *
2155  * Transfer Complete Signal Enable
2156  * Values:
2157  * 0x0 (FALSE): Masked
2158  * 0x1 (TRUE): Enabled
2159  */
2160 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U)
2161 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U)
2162 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK)
2163 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT)
2164 
2165 /*
2166  * CMD_COMPLETE_SIGNAL_EN (RW)
2167  *
2168  * Command Complete Signal Enable
2169  * Values:
2170  * 0x0 (FALSE): Masked
2171  * 0x1 (TRUE): Enabled
2172  */
2173 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U)
2174 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U)
2175 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK)
2176 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT)
2177 
2178 /* Bitfield definition for register: AC_HOST_CTRL */
2179 /*
2180  * PRESET_VAL_ENABLE (RW)
2181  *
2182  * Preset Value Enable
2183  * This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers.
2184  * When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller.
2185  * These values are selected from set of Preset Value registers based on selected speed mode.
2186  * Values:
2187  * 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver
2188  * 0x1 (TRUE): Automatic Selection by Preset Value are Enabled
2189  */
2190 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL)
2191 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U)
2192 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK)
2193 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT)
2194 
2195 /*
2196  * ASYNC_INT_ENABLE (RW)
2197  *
2198  * Asynchronous Interrupt Enable
2199  * This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register.
2200  * Values:
2201  * 0x0 (FALSE): Disabled
2202  * 0x1 (TRUE): Enabled
2203  */
2204 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL)
2205 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U)
2206 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK)
2207 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT)
2208 
2209 /*
2210  * HOST_VER4_ENABLE (RW)
2211  *
2212  * Host Version 4 Enable
2213  * This bit selects either Version 3.00 compatible mode or Version 4 mode.
2214  * Functions of following fields are modified for Host Version 4 mode:
2215  * SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h)
2216  * ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register
2217  * 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1
2218  * Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register
2219  * 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register
2220  * Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers,
2221  * UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0).
2222  * Values:
2223  * 0x0 (FALSE): Version 3.00 compatible mode
2224  * 0x1 (TRUE): Version 4 mode
2225  */
2226 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL)
2227 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U)
2228 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK)
2229 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT)
2230 
2231 /*
2232  * CMD23_ENABLE (RW)
2233  *
2234  * CMD23 Enable
2235  * If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer.
2236  * Values:
2237  * 0x0 (FALSE): Auto CMD23 is disabled
2238  * 0x1 (TRUE): Auto CMD23 is enabled
2239  */
2240 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL)
2241 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U)
2242 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK)
2243 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT)
2244 
2245 /*
2246  * ADMA2_LEN_MODE (RW)
2247  *
2248  * ADMA2 Length Mode
2249  * This bit selects ADMA2 Length mode to be either 16-bit or 26-bit.
2250  * Values:
2251  * 0x0 (FALSE): 16-bit Data Length Mode
2252  * 0x1 (TRUE): 26-bit Data Length Mode
2253  */
2254 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL)
2255 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U)
2256 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK)
2257 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT)
2258 
2259 /*
2260  * SAMPLE_CLK_SEL (RW)
2261  *
2262  * Sampling Clock Select
2263  * This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT.
2264  * This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared).
2265  * Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed.
2266  * The value is reflected on the sample_cclk_sel pin.
2267  * Values:
2268  * 0x0 (FALSE): Fixed clock is used to sample data
2269  * 0x1 (TRUE): Tuned clock is used to sample data
2270  */
2271 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL)
2272 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U)
2273 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK)
2274 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT)
2275 
2276 /*
2277  * EXEC_TUNING (RW)
2278  *
2279  * Execute Tuning
2280  * This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed.
2281  * Values:
2282  * 0x0 (FALSE): Not Tuned or Tuning completed
2283  * 0x1 (TRUE): Execute Tuning
2284  */
2285 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL)
2286 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U)
2287 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)
2288 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT)
2289 
2290 /*
2291  * SIGNALING_EN (RW)
2292  *
2293  * 1.8V Signaling Enable
2294  * This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes.
2295  * Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V.
2296  * Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin.
2297  * Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50).
2298  * Values:
2299  * 0x0 (V_3_3): 3.3V Signalling
2300  * 0x1 (V_1_8): 1.8V Signalling
2301  */
2302 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL)
2303 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U)
2304 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK)
2305 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT)
2306 
2307 /*
2308  * UHS_MODE_SEL (RW)
2309  *
2310  * UHS Mode/eMMC Speed Mode Select
2311  * These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode.
2312  * UHS Mode (SD/UHS-II mode only):
2313  * 0x0 (SDR12): SDR12/Legacy
2314  * 0x1 (SDR25): SDR25/High Speed SDR
2315  * 0x2 (SDR50): SDR50
2316  * 0x3 (SDR104): SDR104/HS200
2317  * 0x4 (DDR50): DDR50/High Speed DDR
2318  * 0x5 (RSVD5): Reserved
2319  * 0x6 (RSVD6): Reserved
2320  * 0x7 (UHS2): UHS-II/HS400
2321  * eMMC Speed Mode (eMMC mode only):
2322  * 0x0: Legacy
2323  * 0x1: High Speed SDR
2324  * 0x2: Reserved
2325  * 0x3: HS200
2326  * 0x4: High Speed DDR
2327  * 0x5: Reserved
2328  * 0x6: Reserved
2329  * 0x7: HS400
2330  */
2331 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL)
2332 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U)
2333 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK)
2334 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT)
2335 
2336 /*
2337  * CMD_NOT_ISSUED_AUTO_CMD12 (RO)
2338  *
2339  * Command Not Issued By Auto CMD12 Error
2340  * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register.
2341  * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
2342  * Values:
2343  * 0x1 (TRUE): Not Issued
2344  * 0x0 (FALSE): No Error
2345  */
2346 #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)
2347 #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)
2348 #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)
2349 
2350 /*
2351  * AUTO_CMD_RESP_ERR (RO)
2352  *
2353  * Auto CMD Response Error
2354  * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13.
2355  * This status is ignored if any bit between D00 to D04 is set to 1.
2356  * Values:
2357  * 0x1 (TRUE): Error
2358  * 0x0 (FALSE): No Error
2359  */
2360 #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U)
2361 #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U)
2362 #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT)
2363 
2364 /*
2365  * AUTO_CMD_IDX_ERR (RO)
2366  *
2367  * Auto CMD Index Error
2368  * This bit is set if the command index error occurs in response to a command.
2369  * Values:
2370  * 0x1 (TRUE): Error
2371  * 0x0 (FALSE): No Error
2372  */
2373 #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U)
2374 #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U)
2375 #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT)
2376 
2377 /*
2378  * AUTO_CMD_EBIT_ERR (RO)
2379  *
2380  * Auto CMD End Bit Error
2381  * This bit is set when detecting that the end bit of command response is 0.
2382  * Values:
2383  * 0x1 (TRUE): End Bit Error Generated
2384  * 0x0 (FALSE): No Error
2385  */
2386 #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U)
2387 #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U)
2388 #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT)
2389 
2390 /*
2391  * AUTO_CMD_CRC_ERR (RO)
2392  *
2393  * Auto CMD CRC Error
2394  * This bit is set when detecting a CRC error in the command response.
2395  * Values:
2396  * 0x1 (TRUE): CRC Error Generated
2397  * 0x0 (FALSE): No Error
2398  */
2399 #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U)
2400 #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U)
2401 #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT)
2402 
2403 /*
2404  * AUTO_CMD_TOUT_ERR (RO)
2405  *
2406  * Auto CMD Timeout Error
2407  * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command.
2408  * If this bit is set to 1, error status bits (D04-D01) are meaningless.
2409  * Values:
2410  * 0x1 (TRUE): Time out
2411  * 0x0 (FALSE): No Error
2412  */
2413 #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U)
2414 #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U)
2415 #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT)
2416 
2417 /*
2418  * AUTO_CMD12_NOT_EXEC (RO)
2419  *
2420  * Auto CMD12 Not Executed
2421  * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12.
2422  * Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error.
2423  * If this bit is set to 1, error status bits (D04-D01) is meaningless.
2424  * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
2425  * Values:
2426  * 0x1 (TRUE): Not Executed
2427  * 0x0 (FALSE): Executed
2428  */
2429 #define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U)
2430 #define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U)
2431 #define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT)
2432 
2433 /* Bitfield definition for register: CAPABILITIES1 */
2434 /*
2435  * SLOT_TYPE_R (RO)
2436  *
2437  * Slot Type
2438  * These bits indicate usage of a slot by a specific Host System.
2439  * Values:
2440  * 0x0 (REMOVABLE_SLOT): Removable Card Slot
2441  * 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device
2442  * 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode)
2443  * 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices
2444  */
2445 #define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL)
2446 #define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U)
2447 #define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT)
2448 
2449 /*
2450  * ASYNC_INT_SUPPORT (RO)
2451  *
2452  * Asynchronous Interrupt Support (SD Mode only)
2453  * Values:
2454  * 0x0 (FALSE): Asynchronous Interrupt Not Supported
2455  * 0x1 (TRUE): Asynchronous Interrupt Supported
2456  */
2457 #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL)
2458 #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U)
2459 #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT)
2460 
2461 /*
2462  * VOLT_18 (RO)
2463  *
2464  * Voltage Support for 1.8V
2465  * Values:
2466  * 0x0 (FALSE): 1.8V Not Supported
2467  * 0x1 (TRUE): 1.8V Supported
2468  */
2469 #define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL)
2470 #define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U)
2471 #define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT)
2472 
2473 /*
2474  * VOLT_30 (RO)
2475  *
2476  * Voltage Support for SD 3.0V or Embedded 1.2V
2477  * Values:
2478  * 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported
2479  * 0x1 (TRUE): SD 3.0V or Embedded Supported
2480  */
2481 #define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL)
2482 #define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U)
2483 #define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT)
2484 
2485 /*
2486  * VOLT_33 (RO)
2487  *
2488  * Voltage Support for 3.3V
2489  * Values:
2490  * 0x0 (FALSE): 3.3V Not Supported
2491  * 0x1 (TRUE): 3.3V Supported
2492  */
2493 #define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL)
2494 #define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U)
2495 #define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT)
2496 
2497 /*
2498  * SUS_RES_SUPPORT (RO)
2499  *
2500  * Suspense/Resume Support
2501  * This bit indicates whether the Host Controller supports Suspend/Resume functionality.
2502  * If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported.
2503  * Values:
2504  * 0x0 (FALSE): Not Supported
2505  * 0x1 (TRUE): Supported
2506  */
2507 #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL)
2508 #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U)
2509 #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT)
2510 
2511 /*
2512  * SDMA_SUPPORT (RO)
2513  *
2514  * SDMA Support
2515  * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly.
2516  * Values:
2517  * 0x0 (FALSE): SDMA not Supported
2518  * 0x1 (TRUE): SDMA Supported
2519  */
2520 #define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL)
2521 #define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U)
2522 #define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT)
2523 
2524 /*
2525  * HIGH_SPEED_SUPPORT (RO)
2526  *
2527  * High Speed Support
2528  * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz.
2529  * Values:
2530  * 0x0 (FALSE): High Speed not Supported
2531  * 0x1 (TRUE): High Speed Supported
2532  */
2533 #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL)
2534 #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U)
2535 #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT)
2536 
2537 /*
2538  * ADMA2_SUPPORT (RO)
2539  *
2540  * ADMA2 Support
2541  * This bit indicates whether the Host Controller is capable of using ADMA2.
2542  * Values:
2543  * 0x0 (FALSE): ADMA2 not Supported
2544  * 0x1 (TRUE): ADMA2 Supported
2545  */
2546 #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL)
2547 #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U)
2548 #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT)
2549 
2550 /*
2551  * EMBEDDED_8_BIT (RO)
2552  *
2553  * 8-bit Support for Embedded Device
2554  * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b.
2555  * Values:
2556  * 0x0 (FALSE): 8-bit Bus Width not Supported
2557  * 0x1 (TRUE): 8-bit Bus Width Supported
2558  */
2559 #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL)
2560 #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U)
2561 #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT)
2562 
2563 /*
2564  * MAX_BLK_LEN (RO)
2565  *
2566  * Maximum Block Length
2567  * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller.
2568  * The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit
2569  * Values:
2570  * 0x0 (ZERO): 512 Byte
2571  * 0x1 (ONE): 1024 Byte
2572  * 0x2 (TWO): 2048 Byte
2573  * 0x3 (THREE): Reserved
2574  */
2575 #define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL)
2576 #define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U)
2577 #define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT)
2578 
2579 /*
2580  * BASE_CLK_FREQ (RO)
2581  *
2582  * Base Clock Frequency for SD clock
2583  * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version.
2584  * 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00.
2585  * The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz.
2586  * -0x00 : Get information through another method
2587  * -0x01 : 1 MHz
2588  * -0x02 : 2 MHz
2589  * -.............
2590  * -0x3F : 63 MHz
2591  * -0x40-0xFF : Not Supported
2592  * 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz.
2593  * -0x00 : Get information through another method
2594  * -0x01 : 1 MHz
2595  * -0x02 : 2 MHz
2596  * -............
2597  * -0xFF : 255 MHz
2598  * If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency.
2599  * If these bits are all 0, the Host system has to get information using a different method.
2600  */
2601 #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U)
2602 #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U)
2603 #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT)
2604 
2605 /*
2606  * TOUT_CLK_UNIT (RO)
2607  *
2608  * Timeout Clock Unit
2609  * This bit shows the unit of base clock frequency used to detect Data TImeout Error.
2610  * Values:
2611  * 0x0 (KHZ): KHz
2612  * 0x1 (MHZ): MHz
2613  */
2614 #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U)
2615 #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U)
2616 #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT)
2617 
2618 /*
2619  * TOUT_CLK_FREQ (RO)
2620  *
2621  * Timeout Clock Frequency
2622  * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz.
2623  * 0x00 : Get information through another method
2624  * 0x01 : 1KHz / 1MHz
2625  * 0x02 : 2KHz / 2MHz
2626  * 0x03 : 3KHz / 3MHz
2627  * ...........
2628  * 0x3F : 63KHz / 63MHz
2629  */
2630 #define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU)
2631 #define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U)
2632 #define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT)
2633 
2634 /* Bitfield definition for register: CAPABILITIES2 */
2635 /*
2636  * VDD2_18V_SUPPORT (RO)
2637  *
2638  * 1.8V VDD2 Support
2639  * This bit indicates support of VDD2 for the Host System.
2640  * 0x0 (FALSE): 1.8V VDD2 is not Supported
2641  * 0x1 (TRUE): 1.8V VDD2 is Supported
2642  */
2643 #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL)
2644 #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U)
2645 #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT)
2646 
2647 /*
2648  * ADMA3_SUPPORT (RO)
2649  *
2650  * ADMA3 Support
2651  * This bit indicates whether the Host Controller is capable of using ADMA3.
2652  * Values:
2653  * 0x0 (FALSE): ADMA3 not Supported
2654  * 0x1 (TRUE): ADMA3 Supported
2655  */
2656 #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL)
2657 #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U)
2658 #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT)
2659 
2660 /*
2661  * CLK_MUL (RO)
2662  *
2663  * Clock Multiplier
2664  * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator.
2665  * 0x0: Clock Multiplier is not Supported
2666  * 0x1: Clock Multiplier M = 2
2667  * 0x2: Clock Multiplier M = 3
2668  * .........
2669  * 0xFF: Clock Multiplier M = 256
2670  */
2671 #define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL)
2672 #define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U)
2673 #define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT)
2674 
2675 /*
2676  * RE_TUNING_MODES (RO)
2677  *
2678  * Re-Tuning Modes (UHS-I only)
2679  * These bits select the re-tuning method and limit the maximum data length.
2680  * Values:
2681  * 0x0 (MODE1): Timer
2682  * 0x1 (MODE2): Timer and Re-Tuning Request (Not supported)
2683  * 0x2 (MODE3): Auto Re-Tuning (for transfer)
2684  * 0x3 (RSVD_MODE): Reserved
2685  */
2686 #define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U)
2687 #define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U)
2688 #define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT)
2689 
2690 /*
2691  * USE_TUNING_SDR50 (RO)
2692  *
2693  * Use Tuning for SDR50 (UHS-I only)
2694  * Values:
2695  * 0x0 (ZERO): SDR50 does not require tuning
2696  * 0x1 (ONE): SDR50 requires tuning
2697  */
2698 #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U)
2699 #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U)
2700 #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT)
2701 
2702 /*
2703  * RETUNE_CNT (RO)
2704  *
2705  * Timer Count for Re-Tuning (UHS-I only)
2706  * 0x0: Re-Tuning Timer disabled
2707  * 0x1: 1 seconds
2708  * 0x2: 2 seconds
2709  * 0x3: 4 seconds
2710  * ........
2711  * 0xB: 1024 seconds
2712  * 0xC: Reserved
2713  * 0xD: Reserved
2714  * 0xE: Reserved
2715  * 0xF: Get information from other source
2716  */
2717 #define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U)
2718 #define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U)
2719 #define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT)
2720 
2721 /*
2722  * DRV_TYPED (RO)
2723  *
2724  * Driver Type D Support (UHS-I only)
2725  * This bit indicates support of Driver Type D for 1.8 Signaling.
2726  * Values:
2727  * 0x0 (FALSE): Driver Type D is not supported
2728  * 0x1 (TRUE): Driver Type D is supported
2729  */
2730 #define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U)
2731 #define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U)
2732 #define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT)
2733 
2734 /*
2735  * DRV_TYPEC (RO)
2736  *
2737  * Driver Type C Support (UHS-I only)
2738  * This bit indicates support of Driver Type C for 1.8 Signaling.
2739  * Values:
2740  * 0x0 (FALSE): Driver Type C is not supported
2741  * 0x1 (TRUE): Driver Type C is supported
2742  */
2743 #define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U)
2744 #define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U)
2745 #define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT)
2746 
2747 /*
2748  * DRV_TYPEA (RO)
2749  *
2750  * Driver Type A Support (UHS-I only)
2751  * This bit indicates support of Driver Type A for 1.8 Signaling.
2752  * Values:
2753  * 0x0 (FALSE): Driver Type A is not supported
2754  * 0x1 (TRUE): Driver Type A is supported
2755  */
2756 #define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U)
2757 #define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U)
2758 #define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT)
2759 
2760 /*
2761  * UHS2_SUPPORT (RO)
2762  *
2763  * UHS-II Support (UHS-II only)
2764  * This bit indicates whether Host Controller supports UHS-II.
2765  * Values:
2766  * 0x0 (FALSE): UHS-II is not supported
2767  * 0x1 (TRUE): UHS-II is supported
2768  */
2769 #define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U)
2770 #define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U)
2771 #define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT)
2772 
2773 /*
2774  * DDR50_SUPPORT (RO)
2775  *
2776  * DDR50 Support (UHS-I only)
2777  * Values:
2778  * 0x0 (FALSE): DDR50 is not supported
2779  * 0x1 (TRUE): DDR50 is supported
2780  */
2781 #define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U)
2782 #define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U)
2783 #define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT)
2784 
2785 /*
2786  * SDR104_SUPPORT (RO)
2787  *
2788  * SDR104 Support (UHS-I only)
2789  * This bit mentions that SDR104 requires tuning.
2790  * Values:
2791  * 0x0 (FALSE): SDR104 is not supported
2792  * 0x1 (TRUE): SDR104 is supported
2793  */
2794 #define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U)
2795 #define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U)
2796 #define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT)
2797 
2798 /*
2799  * SDR50_SUPPORT (RO)
2800  *
2801  * SDR50 Support (UHS-I only)
2802  * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not.
2803  * Values:
2804  * 0x0 (FALSE): SDR50 is not supported
2805  * 0x1 (TRUE): SDR50 is supported
2806  */
2807 #define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U)
2808 #define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U)
2809 #define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT)
2810 
2811 /* Bitfield definition for register: CURR_CAPABILITIES1 */
2812 /*
2813  * MAX_CUR_18V (RO)
2814  *
2815  * Maximum Current for 1.8V
2816  * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card.
2817  * 0: Get information through another method
2818  * 1: 4mA
2819  * 2: 8mA
2820  * 3: 13mA
2821  * .......
2822  * 255: 1020mA
2823  */
2824 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL)
2825 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U)
2826 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT)
2827 
2828 /*
2829  * MAX_CUR_30V (RO)
2830  *
2831  * Maximum Current for 3.0V
2832  * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card.
2833  * 0: Get information through another method
2834  * 1: 4mA
2835  * 2: 8mA
2836  * 3: 13mA
2837  * .......
2838  * 255: 1020mA
2839  */
2840 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U)
2841 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U)
2842 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT)
2843 
2844 /*
2845  * MAX_CUR_33V (RO)
2846  *
2847  * Maximum Current for 3.3V
2848  * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card.
2849  * 0: Get information through another method
2850  * 1: 4mA
2851  * 2: 8mA
2852  * 3: 13mA
2853  * .......
2854  * 255: 1020mA
2855  */
2856 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU)
2857 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U)
2858 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT)
2859 
2860 /* Bitfield definition for register: CURR_CAPABILITIES2 */
2861 /*
2862  * MAX_CUR_VDD2_18V (RO)
2863  *
2864  * Maximum Current for 1.8V VDD2
2865  * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card.
2866  * 0: Get information through another method
2867  * 1: 4mA
2868  * 2: 8mA
2869  * 3: 13mA
2870  * .......
2871  * 255: 1020mA
2872  */
2873 #define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU)
2874 #define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U)
2875 #define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT)
2876 
2877 /* Bitfield definition for register: FORCE_EVENT */
2878 /*
2879  * FORCE_BOOT_ACK_ERR (WO)
2880  *
2881  * Force Event for Boot Ack error
2882  * Values:
2883  * 0x0 (FALSE): Not Affected
2884  * 0x1 (TRUE): Boot ack Error Status is set
2885  */
2886 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL)
2887 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U)
2888 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK)
2889 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT)
2890 
2891 /*
2892  * FORCE_RESP_ERR (WO)
2893  *
2894  * Force Event for Response Error (SD Mode only)
2895  * Values:
2896  * 0x0 (FALSE): Not Affected
2897  * 0x1 (TRUE): Response Error Status is set
2898  */
2899 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL)
2900 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U)
2901 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK)
2902 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT)
2903 
2904 /*
2905  * FORCE_TUNING_ERR (WO)
2906  *
2907  * Force Event for Tuning Error (UHS-I Mode only)
2908  * Values:
2909  * 0x0 (FALSE): Not Affected
2910  * 0x1 (TRUE): Tuning Error Status is set
2911  */
2912 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL)
2913 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U)
2914 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK)
2915 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT)
2916 
2917 /*
2918  * FORCE_ADMA_ERR (WO)
2919  *
2920  * Force Event for ADMA Error
2921  * Values:
2922  * 0x0 (FALSE): Not Affected
2923  * 0x1 (TRUE): ADMA Error Status is set
2924  */
2925 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL)
2926 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U)
2927 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK)
2928 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT)
2929 
2930 /*
2931  * FORCE_AUTO_CMD_ERR (WO)
2932  *
2933  * Force Event for Auto CMD Error (SD/eMMC Mode only)
2934  * Values:
2935  * 0x0 (FALSE): Not Affected
2936  * 0x1 (TRUE): Auto CMD Error Status is set
2937  */
2938 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL)
2939 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U)
2940 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK)
2941 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT)
2942 
2943 /*
2944  * FORCE_CUR_LMT_ERR (WO)
2945  *
2946  * Force Event for Current Limit Error
2947  * Values:
2948  * 0x0 (FALSE): Not Affected
2949  * 0x1 (TRUE): Current Limit Error Status is set
2950  */
2951 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL)
2952 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U)
2953 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK)
2954 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT)
2955 
2956 /*
2957  * FORCE_DATA_END_BIT_ERR (WO)
2958  *
2959  * Force Event for Data End Bit Error (SD/eMMC Mode only)
2960  * Values:
2961  * 0x0 (FALSE): Not Affected
2962  * 0x1 (TRUE): Data End Bit Error Status is set
2963  */
2964 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL)
2965 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U)
2966 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK)
2967 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT)
2968 
2969 /*
2970  * FORCE_DATA_CRC_ERR (WO)
2971  *
2972  * Force Event for Data CRC Error (SD/eMMC Mode only)
2973  * Values:
2974  * 0x0 (FALSE): Not Affected
2975  * 0x1 (TRUE): Data CRC Error Status is set
2976  */
2977 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL)
2978 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U)
2979 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK)
2980 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT)
2981 
2982 /*
2983  * FORCE_DATA_TOUT_ERR (WO)
2984  *
2985  * Force Event for Data Timeout Error (SD/eMMC Mode only)
2986  * Values:
2987  * 0x0 (FALSE): Not Affected
2988  * 0x1 (TRUE): Data Timeout Error Status is set
2989  */
2990 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL)
2991 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U)
2992 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK)
2993 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT)
2994 
2995 /*
2996  * FORCE_CMD_IDX_ERR (WO)
2997  *
2998  * Force Event for Command Index Error (SD/eMMC Mode only)
2999  * Values:
3000  * 0x0 (FALSE): Not Affected
3001  * 0x1 (TRUE): Command Index Error Status is set
3002  */
3003 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL)
3004 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U)
3005 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK)
3006 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT)
3007 
3008 /*
3009  * FORCE_CMD_END_BIT_ERR (WO)
3010  *
3011  * Force Event for Command End Bit Error (SD/eMMC Mode only)
3012  * Values:
3013  * 0x0 (FALSE): Not Affected
3014  * 0x1 (TRUE): Command End Bit Error Status is set
3015  */
3016 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL)
3017 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U)
3018 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK)
3019 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT)
3020 
3021 /*
3022  * FORCE_CMD_CRC_ERR (WO)
3023  *
3024  * Force Event for Command CRC Error (SD/eMMC Mode only)
3025  * Values:
3026  * 0x0 (FALSE): Not Affected
3027  * 0x1 (TRUE): Command CRC Error Status is set
3028  */
3029 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL)
3030 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U)
3031 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK)
3032 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT)
3033 
3034 /*
3035  * FORCE_CMD_TOUT_ERR (WO)
3036  *
3037  * Force Event for Command Timeout Error (SD/eMMC Mode only)
3038  * Values:
3039  * 0x0 (FALSE): Not Affected
3040  * 0x1 (TRUE): Command Timeout Error Status is set
3041  */
3042 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL)
3043 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U)
3044 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK)
3045 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT)
3046 
3047 /*
3048  * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (WO)
3049  *
3050  * Force Event for Command Not Issued By Auto CMD12 Error
3051  * Values:
3052  * 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set
3053  * 0x0 (FALSE): Not Affected
3054  */
3055 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)
3056 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)
3057 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK)
3058 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)
3059 
3060 /*
3061  * FORCE_AUTO_CMD_RESP_ERR (WO)
3062  *
3063  * Force Event for Auto CMD Response Error
3064  * Values:
3065  * 0x1 (TRUE): Auto CMD Response Error Status is set
3066  * 0x0 (FALSE): Not Affected
3067  */
3068 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U)
3069 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U)
3070 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK)
3071 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT)
3072 
3073 /*
3074  * FORCE_AUTO_CMD_IDX_ERR (WO)
3075  *
3076  * Force Event for Auto CMD Index Error
3077  * Values:
3078  * 0x1 (TRUE): Auto CMD Index Error Status is set
3079  * 0x0 (FALSE): Not Affected
3080  */
3081 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U)
3082 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U)
3083 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK)
3084 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT)
3085 
3086 /*
3087  * FORCE_AUTO_CMD_EBIT_ERR (WO)
3088  *
3089  * Force Event for Auto CMD End Bit Error
3090  * Values:
3091  * 0x1 (TRUE): Auto CMD End Bit Error Status is set
3092  * 0x0 (FALSE): Not Affected
3093  */
3094 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U)
3095 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U)
3096 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK)
3097 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT)
3098 
3099 /*
3100  * FORCE_AUTO_CMD_CRC_ERR (WO)
3101  *
3102  * Force Event for Auto CMD CRC Error
3103  * Values:
3104  * 0x1 (TRUE): Auto CMD CRC Error Status is set
3105  * 0x0 (FALSE): Not Affected
3106  */
3107 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U)
3108 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U)
3109 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK)
3110 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT)
3111 
3112 /*
3113  * FORCE_AUTO_CMD_TOUT_ERR (WO)
3114  *
3115  * Force Event for Auto CMD Timeout Error
3116  * Values:
3117  * 0x1 (TRUE): Auto CMD Timeout Error Status is set
3118  * 0x0 (FALSE): Not Affected
3119  */
3120 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U)
3121 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U)
3122 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK)
3123 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT)
3124 
3125 /*
3126  * FORCE_AUTO_CMD12_NOT_EXEC (WO)
3127  *
3128  * Force Event for Auto CMD12 Not Executed
3129  * Values:
3130  * 0x1 (TRUE): Auto CMD12 Not Executed Status is set
3131  * 0x0 (FALSE): Not Affected
3132  */
3133 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U)
3134 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U)
3135 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK)
3136 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT)
3137 
3138 /* Bitfield definition for register: ADMA_ERR_STAT */
3139 /*
3140  * ADMA_LEN_ERR (RO)
3141  *
3142  * ADMA Length Mismatch Error States
3143  * This error occurs in the following instances:
3144  * While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length
3145  * When the total data length cannot be divided by the block length
3146  * Values:
3147  * 0x0 (NO_ERR): No Error
3148  * 0x1 (ERROR): Error
3149  */
3150 #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U)
3151 #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U)
3152 #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT)
3153 
3154 /*
3155  * ADMA_ERR_STATES (RO)
3156  *
3157  * ADMA Error States
3158  * These bits indicate the state of ADMA when an error occurs during ADMA data transfer.
3159  * Values:
3160  * 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor
3161  * 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor
3162  * 0x2 (UNUSED): Never set this state
3163  * 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor
3164  */
3165 #define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U)
3166 #define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U)
3167 #define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT)
3168 
3169 /* Bitfield definition for register: ADMA_SYS_ADDR */
3170 /*
3171  * ADMA_SA (RW)
3172  *
3173  * ADMA System Address
3174  * These bits indicate the lower 32 bits of the ADMA system address.
3175  * SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location
3176  * ADMA2: This register stores the byte address of the executing command of the descriptor table
3177  * ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched.
3178  */
3179 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL)
3180 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U)
3181 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK)
3182 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT)
3183 
3184 /* Bitfield definition for register array: PRESET */
3185 /*
3186  * CLK_GEN_SEL_VAL (RO)
3187  *
3188  * Clock Generator Select Value
3189  * This bit is effective when the Host Controller supports a programmable clock generator.
3190  * Values:
3191  * 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator
3192  * 0x1 (PROG): Programmable Clock Generator
3193  */
3194 #define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U)
3195 #define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U)
3196 #define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT)
3197 
3198 /*
3199  * FREQ_SEL_VAL (RO)
3200  *
3201  * SDCLK/RCLK Frequency Select Value
3202  * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System.
3203  */
3204 #define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU)
3205 #define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U)
3206 #define SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT)
3207 
3208 /* Bitfield definition for register: ADMA_ID_ADDR */
3209 /*
3210  * ADMA_ID_ADDR (RW)
3211  *
3212  * ADMA Integrated Descriptor Address
3213  * These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address.
3214  * The start address of Integrated Descriptor is set to these register bits.
3215  * The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address.
3216  */
3217 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL)
3218 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U)
3219 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK)
3220 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT)
3221 
3222 /* Bitfield definition for register: P_EMBEDDED_CNTRL */
3223 /*
3224  * REG_OFFSET_ADDR (RO)
3225  *
3226  * Offset Address of Embedded Control register.
3227  */
3228 #define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU)
3229 #define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U)
3230 #define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT)
3231 
3232 /* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */
3233 /*
3234  * REG_OFFSET_ADDR (RO)
3235  *
3236  * Base offset Address for Vendor-Specific registers.
3237  */
3238 #define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU)
3239 #define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)
3240 #define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)
3241 
3242 /* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */
3243 /*
3244  * REG_OFFSET_ADDR (RO)
3245  *
3246  * Base offset Address for Command Queuing registers.
3247  */
3248 #define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU)
3249 #define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)
3250 #define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)
3251 
3252 /* Bitfield definition for register: SLOT_INTR_STATUS */
3253 /*
3254  * INTR_SLOT (RO)
3255  *
3256  * Interrupt signal for each Slot
3257  * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot.
3258  * A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits.
3259  * By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h.
3260  * Bit 00: Slot 1
3261  * Bit 01: Slot 2
3262  * Bit 02: Slot 3
3263  * ..........
3264  * ..........
3265  * Bit 07: Slot 8
3266  * Note: MSHC Host Controller support single card slot. This register shall always return 0.
3267  */
3268 #define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU)
3269 #define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U)
3270 #define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT)
3271 
3272 /* Bitfield definition for register: CQVER */
3273 /*
3274  * EMMC_VER_MAHOR (RO)
3275  *
3276  * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format.
3277  */
3278 #define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U)
3279 #define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U)
3280 #define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT)
3281 
3282 /*
3283  * EMMC_VER_MINOR (RO)
3284  *
3285  * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format.
3286  */
3287 #define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U)
3288 #define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U)
3289 #define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT)
3290 
3291 /*
3292  * EMMC_VER_SUFFIX (RO)
3293  *
3294  * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format.
3295  */
3296 #define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU)
3297 #define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U)
3298 #define SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT)
3299 
3300 /* Bitfield definition for register: CQCAP */
3301 /*
3302  * CRYPTO_SUPPORT (RO)
3303  *
3304  * Crypto Support
3305  * This bit indicates whether the Host Controller supports cryptographic operations.
3306  * Values:
3307  * 0x0 (FALSE): Crypto not Supported
3308  * 0x1 (TRUE): Crypto Supported
3309  */
3310 #define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL)
3311 #define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U)
3312 #define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT)
3313 
3314 /*
3315  * ITCFMUL (RO)
3316  *
3317  * Internal Timer Clock Frequency Multiplier (ITCFMUL)
3318  * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS
3319  * polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved.
3320  * Values:
3321  * 0x0 (CLK_1KHz): 1KHz clock
3322  * 0x1 (CLK_10KHz): 10KHz clock
3323  * 0x2 (CLK_100KHz): 100KHz clock
3324  * 0x3 (CLK_1MHz): 1MHz clock
3325  * 0x4 (CLK_10MHz): 10MHz clock
3326  */
3327 #define SDXC_CQCAP_ITCFMUL_MASK (0xF000U)
3328 #define SDXC_CQCAP_ITCFMUL_SHIFT (12U)
3329 #define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT)
3330 
3331 /*
3332  * ITCFVAL (RO)
3333  *
3334  * Internal Timer Clock Frequency Value (ITCFVAL)
3335  * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL.
3336  */
3337 #define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU)
3338 #define SDXC_CQCAP_ITCFVAL_SHIFT (0U)
3339 #define SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT)
3340 
3341 /* Bitfield definition for register: CQCFG */
3342 /*
3343  * DCMD_EN (RW)
3344  *
3345  * This bit indicates to the hardware whether the Task
3346  * Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor.
3347  * Values:
3348  * 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor
3349  * 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor
3350  */
3351 #define SDXC_CQCFG_DCMD_EN_MASK (0x1000U)
3352 #define SDXC_CQCFG_DCMD_EN_SHIFT (12U)
3353 #define SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK)
3354 #define SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT)
3355 
3356 /*
3357  * TASK_DESC_SIZE (RW)
3358  *
3359  * Bit Value Description
3360  * This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled).
3361  * Values:
3362  * 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits
3363  * 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit
3364  */
3365 #define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U)
3366 #define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U)
3367 #define SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK)
3368 #define SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT)
3369 
3370 /*
3371  * CQ_EN (RW)
3372  *
3373  */
3374 #define SDXC_CQCFG_CQ_EN_MASK (0x1U)
3375 #define SDXC_CQCFG_CQ_EN_SHIFT (0U)
3376 #define SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK)
3377 #define SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT)
3378 
3379 /* Bitfield definition for register: CQCTL */
3380 /*
3381  * CLR_ALL_TASKS (RW)
3382  *
3383  * Clear all tasks
3384  * This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue.
3385  * Values:
3386  * 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller
3387  * 0x0 (NO_EFFECT): Programming 0 has no effect
3388  */
3389 #define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U)
3390 #define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U)
3391 #define SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK)
3392 #define SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT)
3393 
3394 /*
3395  * HALT (RW)
3396  *
3397  * Halt request and resume
3398  * Values:
3399  * 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus.
3400  * For example, issuing a Discard Task command (CMDQ_TASK_MGMT).
3401  * When the software writes 1, CQE completes the ongoing task (if any in progress).
3402  * After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1.
3403  * The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus.
3404  * 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity
3405  */
3406 #define SDXC_CQCTL_HALT_MASK (0x1U)
3407 #define SDXC_CQCTL_HALT_SHIFT (0U)
3408 #define SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK)
3409 #define SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT)
3410 
3411 /* Bitfield definition for register: CQIS */
3412 /*
3413  * TCL (RW)
3414  *
3415  * Task cleared interrupt
3416  * This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE.
3417  * The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL).
3418  * A value of 1 clears this status bit.
3419  * Values:
3420  * 0x1 (SET): TCL Interrupt is set
3421  * 0x0 (NOTSET): TCL Interrupt is not set
3422  */
3423 #define SDXC_CQIS_TCL_MASK (0x8U)
3424 #define SDXC_CQIS_TCL_SHIFT (3U)
3425 #define SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK)
3426 #define SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT)
3427 
3428 /*
3429  * RED (RW)
3430  *
3431  * Response error detected interrupt
3432  * This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status
3433  * field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked.
3434  * A value of 1 clears this status bit.
3435  * Values:
3436  * 0x1 (SET): RED Interrupt is set
3437  * 0x0 (NOTSET): RED Interrupt is not set
3438  */
3439 #define SDXC_CQIS_RED_MASK (0x4U)
3440 #define SDXC_CQIS_RED_SHIFT (2U)
3441 #define SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK)
3442 #define SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT)
3443 
3444 /*
3445  * TCC (RW)
3446  *
3447  * Task complete interrupt
3448  * This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met:
3449  * A task is completed and the INT bit is set in its Task Descriptor
3450  * Interrupt caused by Interrupt Coalescing logic due to timeout
3451  * Interrupt Coalescing logic reached the configured threshold
3452  * A value of 1 clears this status bit
3453  */
3454 #define SDXC_CQIS_TCC_MASK (0x2U)
3455 #define SDXC_CQIS_TCC_SHIFT (1U)
3456 #define SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK)
3457 #define SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT)
3458 
3459 /*
3460  * HAC (RW)
3461  *
3462  * Halt complete interrupt
3463  * This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state.
3464  * A value of 1 clears this status bit.
3465  * Values:
3466  * 0x1 (SET): HAC Interrupt is set
3467  * 0x0 (NOTSET): HAC Interrupt is not set
3468  */
3469 #define SDXC_CQIS_HAC_MASK (0x1U)
3470 #define SDXC_CQIS_HAC_SHIFT (0U)
3471 #define SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK)
3472 #define SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT)
3473 
3474 /* Bitfield definition for register: CQISE */
3475 /*
3476  * TCL_STE (RW)
3477  *
3478  * Task cleared interrupt status enable
3479  * Values:
3480  * 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active
3481  * 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled
3482  */
3483 #define SDXC_CQISE_TCL_STE_MASK (0x8U)
3484 #define SDXC_CQISE_TCL_STE_SHIFT (3U)
3485 #define SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK)
3486 #define SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT)
3487 
3488 /*
3489  * RED_STE (RW)
3490  *
3491  * Response error detected interrupt status enable
3492  * Values:
3493  * 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active
3494  * 0x0 (INT_STS_DISABLE): CQIS.RED is disabled
3495  */
3496 #define SDXC_CQISE_RED_STE_MASK (0x4U)
3497 #define SDXC_CQISE_RED_STE_SHIFT (2U)
3498 #define SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK)
3499 #define SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT)
3500 
3501 /*
3502  * TCC_STE (RW)
3503  *
3504  * Task complete interrupt status enable
3505  * Values:
3506  * 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active
3507  * 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled
3508  */
3509 #define SDXC_CQISE_TCC_STE_MASK (0x2U)
3510 #define SDXC_CQISE_TCC_STE_SHIFT (1U)
3511 #define SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK)
3512 #define SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT)
3513 
3514 /*
3515  * HAC_STE (RW)
3516  *
3517  * Halt complete interrupt status enable
3518  * Values:
3519  * 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active
3520  * 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled
3521  */
3522 #define SDXC_CQISE_HAC_STE_MASK (0x1U)
3523 #define SDXC_CQISE_HAC_STE_SHIFT (0U)
3524 #define SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK)
3525 #define SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT)
3526 
3527 /* Bitfield definition for register: CQISGE */
3528 /*
3529  * TCL_SGE (RW)
3530  *
3531  * Task cleared interrupt signal enable
3532  * Values:
3533  * 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active
3534  * 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled
3535  */
3536 #define SDXC_CQISGE_TCL_SGE_MASK (0x8U)
3537 #define SDXC_CQISGE_TCL_SGE_SHIFT (3U)
3538 #define SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK)
3539 #define SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT)
3540 
3541 /*
3542  * RED_SGE (RW)
3543  *
3544  * Response error detected interrupt signal enable
3545  * Values:
3546  * 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active
3547  * 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled
3548  */
3549 #define SDXC_CQISGE_RED_SGE_MASK (0x4U)
3550 #define SDXC_CQISGE_RED_SGE_SHIFT (2U)
3551 #define SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK)
3552 #define SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT)
3553 
3554 /*
3555  * TCC_SGE (RW)
3556  *
3557  * Task complete interrupt signal enable
3558  * Values:
3559  * 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active
3560  * 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled
3561  */
3562 #define SDXC_CQISGE_TCC_SGE_MASK (0x2U)
3563 #define SDXC_CQISGE_TCC_SGE_SHIFT (1U)
3564 #define SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK)
3565 #define SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT)
3566 
3567 /*
3568  * HAC_SGE (RW)
3569  *
3570  * Halt complete interrupt signal enable
3571  * Values:
3572  * 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active
3573  * 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled
3574  */
3575 #define SDXC_CQISGE_HAC_SGE_MASK (0x1U)
3576 #define SDXC_CQISGE_HAC_SGE_SHIFT (0U)
3577 #define SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK)
3578 #define SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT)
3579 
3580 /* Bitfield definition for register: CQIC */
3581 /*
3582  * INTC_EN (RW)
3583  *
3584  * Interrupt Coalescing Enable Bit
3585  * Values:
3586  * 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated
3587  * 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default)
3588  */
3589 #define SDXC_CQIC_INTC_EN_MASK (0x80000000UL)
3590 #define SDXC_CQIC_INTC_EN_SHIFT (31U)
3591 #define SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK)
3592 #define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT)
3593 
3594 /*
3595  * INTC_STAT (RO)
3596  *
3597  * Interrupt Coalescing Status Bit
3598  * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt
3599  * coalescing (that is, this is set if and only if INTC counter > 0).
3600  * Values:
3601  * 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0)
3602  * 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0)
3603  */
3604 #define SDXC_CQIC_INTC_STAT_MASK (0x100000UL)
3605 #define SDXC_CQIC_INTC_STAT_SHIFT (20U)
3606 #define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT)
3607 
3608 /*
3609  * INTC_RST (WO)
3610  *
3611  * Counter and Timer Reset
3612  * When host driver writes 1, the interrupt coalescing timer and counter are reset.
3613  * Values:
3614  * 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset
3615  * 0x0 (NO_EFFECT): No Effect
3616  */
3617 #define SDXC_CQIC_INTC_RST_MASK (0x10000UL)
3618 #define SDXC_CQIC_INTC_RST_SHIFT (16U)
3619 #define SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK)
3620 #define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT)
3621 
3622 /*
3623  * INTC_TH_WEN (WO)
3624  *
3625  * Interrupt Coalescing Counter Threshold Write Enable
3626  * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle.
3627  * Values:
3628  * 0x1 (WEN_SET): Sets INTC_TH_WEN
3629  * 0x0 (WEN_CLR): Clears INTC_TH_WEN
3630  */
3631 #define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U)
3632 #define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U)
3633 #define SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK)
3634 #define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT)
3635 
3636 /*
3637  * INTC_TH (WO)
3638  *
3639  * Interrupt Coalescing Counter Threshold filed
3640  * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt.
3641  * Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE.
3642  * The counter is reset by software during the interrupt service routine.
3643  * The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt.
3644  * 0x0: Interrupt coalescing feature disabled
3645  * 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes
3646  * 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes
3647  * ........
3648  * 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes
3649  * To write to this field, the INTC_TH_WEN bit must be set during the same write operation.
3650  */
3651 #define SDXC_CQIC_INTC_TH_MASK (0x1F00U)
3652 #define SDXC_CQIC_INTC_TH_SHIFT (8U)
3653 #define SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK)
3654 #define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT)
3655 
3656 /*
3657  * TOUT_VAL_WEN (WO)
3658  *
3659  * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle.
3660  * Values:
3661  * 0x1 (WEN_SET): Sets TOUT_VAL_WEN
3662  * 0x0 (WEN_CLR): clears TOUT_VAL_WEN
3663  */
3664 #define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U)
3665 #define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U)
3666 #define SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK)
3667 #define SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT)
3668 
3669 /*
3670  * TOUT_VAL (RW)
3671  *
3672  * Interrupt Coalescing Timeout Value
3673  * Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt.
3674  * Timer Operation: The timer is reset by software during the interrupt service routine.
3675  * It starts running when the first data transfer task with INT=0 is completed, after the timer was reset.
3676  * When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops.
3677  * The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register.
3678  * 0x0: Timer is disabled. Timeout-based interrupt is not generated
3679  * 0x1: Timeout on 01x1024 cycles of timer clock frequency
3680  * 0x2: Timeout on 02x1024 cycles of timer clock frequency
3681  * ........
3682  * 0x7f: Timeout on 127x1024 cycles of timer clock frequency
3683  * In order to write to this field, the TOUT_VAL_WEN bit must
3684  * be set at the same write operation.
3685  */
3686 #define SDXC_CQIC_TOUT_VAL_MASK (0x7FU)
3687 #define SDXC_CQIC_TOUT_VAL_SHIFT (0U)
3688 #define SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK)
3689 #define SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT)
3690 
3691 /* Bitfield definition for register: CQTDLBA */
3692 /*
3693  * TDLBA (RW)
3694  *
3695  * This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory.
3696  * The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver.
3697  * This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE
3698  */
3699 #define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL)
3700 #define SDXC_CQTDLBA_TDLBA_SHIFT (0U)
3701 #define SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK)
3702 #define SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT)
3703 
3704 /* Bitfield definition for register: CQTDBR */
3705 /*
3706  * DBR (RW)
3707  *
3708  * The software configures TDLBA and TDLBAU, and enable
3709  * CQE in CQCFG before using this register.
3710  * Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL.
3711  * Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit.
3712  * CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions.
3713  * CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to
3714  * the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument.
3715  * The corresponding bit is cleared to 0 by CQE in one of the following events:
3716  * A task execution is completed (with success or error).
3717  * The task is cleared using CQTCLR register.
3718  * All tasks are cleared using CQCTL register.
3719  * CQE is disabled using CQCFG register.
3720  * Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction.
3721  * In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index.
3722  * If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order.
3723  */
3724 #define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL)
3725 #define SDXC_CQTDBR_DBR_SHIFT (0U)
3726 #define SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK)
3727 #define SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT)
3728 
3729 /* Bitfield definition for register: CQTCN */
3730 /*
3731  * TCN (RW)
3732  *
3733  * Task Completion Notification
3734  * Each of the 32 bits are bit mapped to the 32 tasks.
3735  * Bit-N(1): Task-N has completed execution (with success or errors)
3736  * Bit-N(0): Task-N has not completed, could be pending or not submitted.
3737  * On task completion, software may read this register to know tasks that have completed. After reading this register,
3738  * software may clear the relevant bit fields by writing 1 to the corresponding bits.
3739  */
3740 #define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL)
3741 #define SDXC_CQTCN_TCN_SHIFT (0U)
3742 #define SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK)
3743 #define SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT)
3744 
3745 /* Bitfield definition for register: CQDQS */
3746 /*
3747  * DQS (RW)
3748  *
3749  * Device Queue Status
3750  * Each of the 32 bits are bit mapped to the 32 tasks.
3751  * Bit-N(1): Device has marked task N as ready for execution
3752  * Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted.
3753  * Host controller updates this register with response of the Device Queue Status command.
3754  */
3755 #define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL)
3756 #define SDXC_CQDQS_DQS_SHIFT (0U)
3757 #define SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK)
3758 #define SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT)
3759 
3760 /* Bitfield definition for register: CQDPT */
3761 /*
3762  * DPT (RW)
3763  *
3764  * Device-Pending Tasks
3765  * Each of the 32 bits are bit mapped to the 32 tasks.
3766  * Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution
3767  * Bit-N(0): Task-N is not yet queued.
3768  * Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed.
3769  * The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution.
3770  * Software reads this register in the task-discard procedure to determine if the task is queued in the device
3771  */
3772 #define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL)
3773 #define SDXC_CQDPT_DPT_SHIFT (0U)
3774 #define SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK)
3775 #define SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT)
3776 
3777 /* Bitfield definition for register: CQTCLR */
3778 /*
3779  * TCLR (RW)
3780  *
3781  * Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued.
3782  * This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.
3783  * When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task.
3784  * CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete.
3785  * Software must poll on the CQTCLR until it is leared to verify that a clear operation was done.
3786  */
3787 #define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL)
3788 #define SDXC_CQTCLR_TCLR_SHIFT (0U)
3789 #define SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK)
3790 #define SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT)
3791 
3792 /* Bitfield definition for register: CQSSC1 */
3793 /*
3794  * SQSCMD_BLK_CNT (RW)
3795  *
3796  * This field indicates when SQS CMD is sent while data transfer is in progress.
3797  * A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction.
3798  * 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle.
3799  * 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction.
3800  * 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending.
3801  * 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending.
3802  * ........
3803  * 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending.
3804  * Should be programmed only when CQCFG.CQ_EN is 0
3805  */
3806 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL)
3807 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U)
3808 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK)
3809 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT)
3810 
3811 /*
3812  * SQSCMD_IDLE_TMR (RW)
3813  *
3814  * This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling.
3815  * Periodic polling is used when tasks are pending in the device, but no data transfer is in progress.
3816  * When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS.
3817  * Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register.
3818  * The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods).
3819  * For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns).
3820  * If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us.
3821  * Should be programmed only when CQCFG.CQ_EN is '0'
3822  */
3823 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU)
3824 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U)
3825 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK)
3826 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT)
3827 
3828 /* Bitfield definition for register: CQSSC2 */
3829 /*
3830  * SQSCMD_RCA (RW)
3831  *
3832  * This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument.
3833  * CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command.
3834  */
3835 #define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU)
3836 #define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U)
3837 #define SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK)
3838 #define SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT)
3839 
3840 /* Bitfield definition for register: CQCRDCT */
3841 /*
3842  * DCMD_RESP (RO)
3843  *
3844  * This register contains the response of the command generated by the last direct command (DCMD) task that was sent.
3845  * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller.
3846  */
3847 #define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL)
3848 #define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U)
3849 #define SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT)
3850 
3851 /* Bitfield definition for register: CQRMEM */
3852 /*
3853  * RESP_ERR_MASK (RW)
3854  *
3855  * The bits of this field are bit mapped to the device response.
3856  * This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses.
3857  * 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated.
3858  * 0: When a R1/R1b response is received, bit i in the device status is ignored.
3859  * The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status.
3860  * Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic.
3861  */
3862 #define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL)
3863 #define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U)
3864 #define SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK)
3865 #define SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT)
3866 
3867 /* Bitfield definition for register: CQTERRI */
3868 /*
3869  * TRANS_ERR_TASKID (RO)
3870  *
3871  * This field captures the ID of the task that was executed and whose data transfer has errors.
3872  */
3873 #define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL)
3874 #define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U)
3875 #define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT)
3876 
3877 /*
3878  * TRANS_ERR_CMD_INDX (RO)
3879  *
3880  * This field captures the index of the command that was executed and whose data transfer has errors.
3881  */
3882 #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL)
3883 #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U)
3884 #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT)
3885 
3886 /*
3887  * RESP_ERR_FIELDS_VALID (RO)
3888  *
3889  * This bit is updated when an error is detected while a command transaction was in progress.
3890  * Values:
3891  * 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields
3892  * 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX
3893  */
3894 #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U)
3895 #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U)
3896 #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT)
3897 
3898 /*
3899  * RESP_ERR_TASKID (RO)
3900  *
3901  * This field captures the ID of the task which was executed on the command line when the error occurred.
3902  */
3903 #define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U)
3904 #define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U)
3905 #define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT)
3906 
3907 /*
3908  * RESP_ERR_CMD_INDX (RO)
3909  *
3910  * This field captures the index of the command that was executed on the command line when the error occurred
3911  */
3912 #define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU)
3913 #define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U)
3914 #define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT)
3915 
3916 /* Bitfield definition for register: CQCRI */
3917 /*
3918  * CMD_RESP_INDX (RO)
3919  *
3920  * Last Command Response index
3921  * This field stores the index of the last received command response. Controller updates the value every time a command response is received
3922  */
3923 #define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU)
3924 #define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U)
3925 #define SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT)
3926 
3927 /* Bitfield definition for register: CQCRA */
3928 /*
3929  * CMD_RESP_ARG (RO)
3930  *
3931  * Last Command Response argument
3932  * This field stores the argument of the last received command response. Controller updates the value every time a command response is received.
3933  */
3934 #define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL)
3935 #define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U)
3936 #define SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT)
3937 
3938 /* Bitfield definition for register: MSHC_VER_ID */
3939 /*
3940  * VER_ID (RO)
3941  *
3942  */
3943 #define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL)
3944 #define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U)
3945 #define SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT)
3946 
3947 /* Bitfield definition for register: MSHC_VER_TYPE */
3948 /*
3949  * VER_TYPE (RO)
3950  *
3951  */
3952 #define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL)
3953 #define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U)
3954 #define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT)
3955 
3956 /* Bitfield definition for register: EMMC_BOOT_CTRL */
3957 /*
3958  * BOOT_TOUT_CNT (RW)
3959  *
3960  * Boot Ack Timeout Counter Value.
3961  * This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation.
3962  * 0xF : Reserved
3963  * 0xE : TMCLK x 2^27
3964  * ............
3965  * 0x1 : TMCLK x 2^14
3966  * 0x0 : TMCLK x 2^13
3967  */
3968 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL)
3969 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U)
3970 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK)
3971 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT)
3972 
3973 /*
3974  * BOOT_ACK_ENABLE (RW)
3975  *
3976  * Boot Acknowledge Enable
3977  * When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode.
3978  * Values:
3979  * 0x1 (TRUE): Boot Ack enable
3980  * 0x0 (FALSE): Boot Ack disable
3981  */
3982 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL)
3983 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U)
3984 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK)
3985 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT)
3986 
3987 /*
3988  * VALIDATE_BOOT (WO)
3989  *
3990  * Validate Mandatory Boot Enable bit
3991  * This bit is used to validate the MAN_BOOT_EN bit.
3992  * Values:
3993  * 0x1 (TRUE): Validate Mandatory boot enable bit
3994  * 0x0 (FALSE): Ignore Mandatory boot Enable bit
3995  */
3996 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL)
3997 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U)
3998 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK)
3999 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT)
4000 
4001 /*
4002  * MAN_BOOT_EN (RW)
4003  *
4004  * Mandatory Boot Enable
4005  * This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit.
4006  * Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated.
4007  * Values:
4008  * 0x1 (MAN_BOOT_EN): Mandatory boot enable
4009  * 0x0 (MAN_BOOT_DIS): Mandatory boot disable
4010  */
4011 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL)
4012 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U)
4013 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK)
4014 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT)
4015 
4016 /*
4017  * CQE_PREFETCH_DISABLE (RW)
4018  *
4019  * Enable or Disable CQE's PREFETCH feature
4020  * This field allows Software to disable CQE's data prefetch feature when set to 1.
4021  * Values:
4022  * 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers
4023  * 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled
4024  */
4025 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U)
4026 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U)
4027 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK)
4028 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT)
4029 
4030 /*
4031  * CQE_ALGO_SEL (RW)
4032  *
4033  * Scheduler algorithm selected for execution
4034  * This bit selects the Algorithm used for selecting one of the many ready tasks for execution.
4035  * Values:
4036  * 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks
4037  * 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings
4038  */
4039 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U)
4040 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U)
4041 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK)
4042 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT)
4043 
4044 /*
4045  * ENH_STROBE_ENABLE (RW)
4046  *
4047  * Enhanced Strobe Enable
4048  * This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode.
4049  * Values:
4050  * 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode
4051  * 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode
4052  */
4053 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U)
4054 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U)
4055 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK)
4056 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT)
4057 
4058 /*
4059  * EMMC_RST_N_OE (RW)
4060  *
4061  * Output Enable control for EMMC Device Reset signal PAD
4062  * control.
4063  * This field drived sd_rst_n_oe output of SDXC
4064  * Values:
4065  * 0x1 (ENABLE): sd_rst_n_oe is 1
4066  * 0x0 (DISABLE): sd_rst_n_oe is 0
4067  */
4068 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U)
4069 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U)
4070 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK)
4071 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT)
4072 
4073 /*
4074  * EMMC_RST_N (RW)
4075  *
4076  * EMMC Device Reset signal control.
4077  * This register field controls the sd_rst_n output of SDXC
4078  * Values:
4079  * 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted
4080  * 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low)
4081  */
4082 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U)
4083 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U)
4084 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK)
4085 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT)
4086 
4087 /*
4088  * DISABLE_DATA_CRC_CHK (RW)
4089  *
4090  * Disable Data CRC Check
4091  * This bit controls masking of CRC16 error for Card Write in eMMC mode.
4092  * This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block,
4093  * which may generate CRC error. This CRC error can be masked using this bit during bus testing.
4094  * Values:
4095  * 0x1 (DISABLE): DATA CRC check is disabled
4096  * 0x0 (ENABLE): DATA CRC check is enabled
4097  */
4098 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U)
4099 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U)
4100 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK)
4101 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT)
4102 
4103 /*
4104  * CARD_IS_EMMC (RW)
4105  *
4106  * eMMC Card present
4107  * This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC.
4108  * Values:
4109  * 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card
4110  * 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card
4111  */
4112 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U)
4113 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U)
4114 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK)
4115 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT)
4116 
4117 /* Bitfield definition for register: AUTO_TUNING_CTRL */
4118 /*
4119  * SWIN_TH_VAL (RW)
4120  *
4121  * Sampling window threshold value setting
4122  * The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps
4123  * can use values from 0x0 to 0x1F.
4124  * This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0'
4125  * 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window.
4126  * 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window.
4127  * 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window.
4128  * ........
4129  * 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window.
4130  */
4131 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL)
4132 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U)
4133 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK)
4134 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT)
4135 
4136 /*
4137  * POST_CHANGE_DLY (RW)
4138  *
4139  * Time taken for phase switching and stable clock output.
4140  * Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel.
4141  * Values:
4142  * 0x0 (LATENCY_LT_1): Less than 1-cycle latency
4143  * 0x1 (LATENCY_LT_2): Less than 2-cycle latency
4144  * 0x2 (LATENCY_LT_3): Less than 3-cycle latency
4145  * 0x3 (LATENCY_LT_4): Less than 4-cycle latency
4146  */
4147 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL)
4148 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U)
4149 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK)
4150 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT)
4151 
4152 /*
4153  * PRE_CHANGE_DLY (RW)
4154  *
4155  * Maximum Latency specification between cclk_tx and cclk_rx.
4156  * Values:
4157  * 0x0 (LATENCY_LT_1): Less than 1-cycle latency
4158  * 0x1 (LATENCY_LT_2): Less than 2-cycle latency
4159  * 0x2 (LATENCY_LT_3): Less than 3-cycle latency
4160  * 0x3 (LATENCY_LT_4): Less than 4-cycle latency
4161  */
4162 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL)
4163 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U)
4164 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK)
4165 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT)
4166 
4167 /*
4168  * TUNE_CLK_STOP_EN (RW)
4169  *
4170  * Clock stopping control for Tuning and auto-tuning circuit.
4171  * When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel.
4172  * This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching.
4173  * Set this bit to 0 if the PHY or delayline can guarantee glitch free switching.
4174  * Values:
4175  * 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change
4176  * 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching
4177  */
4178 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL)
4179 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U)
4180 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK)
4181 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT)
4182 
4183 /*
4184  * WIN_EDGE_SEL (RW)
4185  *
4186  * This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine.
4187  * 0x0: User selection disabled. Tuning calculated edges are used.
4188  * 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages.
4189  * 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess
4190  * ...
4191  * 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages.
4192  */
4193 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U)
4194 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U)
4195 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK)
4196 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT)
4197 
4198 /*
4199  * SW_TUNE_EN (RW)
4200  *
4201  * This fields enables software-managed tuning flow.
4202  * Values:
4203  * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable.
4204  * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled
4205  */
4206 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U)
4207 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U)
4208 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK)
4209 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT)
4210 
4211 /*
4212  * RPT_TUNE_ERR (RW)
4213  *
4214  * Framing errors are not generated when executing tuning.
4215  * This debug bit allows users to report these errors.
4216  * Values:
4217  * 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors
4218  * 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported.
4219  */
4220 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U)
4221 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U)
4222 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK)
4223 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT)
4224 
4225 /*
4226  * SWIN_TH_EN (RW)
4227  *
4228  * Sampling window Threshold enable
4229  * Selects the tuning mode
4230  * Field should be programmed only when SAMPLE_CLK_SEL is '0'
4231  * Values:
4232  * 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold
4233  * set by SWIN_TH_VAL field
4234  * 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window
4235  */
4236 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U)
4237 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U)
4238 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK)
4239 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT)
4240 
4241 /*
4242  * CI_SEL (RW)
4243  *
4244  * Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output.
4245  * Values:
4246  * 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval
4247  * 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer
4248  */
4249 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U)
4250 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U)
4251 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK)
4252 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT)
4253 
4254 /*
4255  * AT_EN (RW)
4256  *
4257  * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support.
4258  * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning.
4259  * This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0.
4260  * Values:
4261  * 0x1 (AT_ENABLE): AutoTuning is enabled
4262  * 0x0 (AT_DISABLE): AutoTuning is disabled
4263  */
4264 #define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U)
4265 #define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U)
4266 #define SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK)
4267 #define SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT)
4268 
4269 /* Bitfield definition for register: AUTO_TUNING_STAT */
4270 /*
4271  * L_EDGE_PH_CODE (RO)
4272  *
4273  * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window.
4274  */
4275 #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL)
4276 #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U)
4277 #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT)
4278 
4279 /*
4280  * R_EDGE_PH_CODE (RO)
4281  *
4282  * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window.
4283  */
4284 #define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U)
4285 #define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U)
4286 #define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT)
4287 
4288 /*
4289  * CENTER_PH_CODE (RW)
4290  *
4291  * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel
4292  */
4293 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU)
4294 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U)
4295 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK)
4296 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT)
4297 
4298 /* Bitfield definition for register: MISC_CTRL0 */
4299 /*
4300  * CARDCLK_INV_EN (RW)
4301  *
4302  * set to invert card_clk, for slow speed card to meet 5ns setup timing.
4303  * May cause glitch on clock, should be set before enable clk(in core cfg)
4304  */
4305 #define SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL)
4306 #define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U)
4307 #define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK)
4308 #define SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) >> SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT)
4309 
4310 /*
4311  * PAD_CLK_SEL_B (RW)
4312  *
4313  * set to use internal clock directly, may have timing issue;
4314  * clr to use clock loopback from pad.
4315  */
4316 #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL)
4317 #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U)
4318 #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK)
4319 #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT)
4320 
4321 /*
4322  * FREQ_SEL_SW_EN (RW)
4323  *
4324  * set to use FREQ_SEL_SW as card clock divider;
4325  * clear to use core logic as clock divider.
4326  */
4327 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U)
4328 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U)
4329 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK)
4330 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT)
4331 
4332 /*
4333  * TMCLK_EN (RW)
4334  *
4335  * set to force enable tmclk;
4336  * clear to use core signal intclk_en to control it
4337  */
4338 #define SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U)
4339 #define SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U)
4340 #define SDXC_MISC_CTRL0_TMCLK_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) & SDXC_MISC_CTRL0_TMCLK_EN_MASK)
4341 #define SDXC_MISC_CTRL0_TMCLK_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) >> SDXC_MISC_CTRL0_TMCLK_EN_SHIFT)
4342 
4343 /*
4344  * FREQ_SEL_SW (RW)
4345  *
4346  * software card clock divider, it will be used only when FREQ_SEL_SW_EN is set
4347  */
4348 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU)
4349 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U)
4350 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK)
4351 #define SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT)
4352 
4353 /* Bitfield definition for register: MISC_CTRL1 */
4354 /*
4355  * CARD_ACTIVE (RW)
4356  *
4357  * SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL).
4358  * When counter finished, this bit will be cleared by hardware.
4359  * Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time)
4360  */
4361 #define SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL)
4362 #define SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U)
4363 #define SDXC_MISC_CTRL1_CARD_ACTIVE_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)
4364 #define SDXC_MISC_CTRL1_CARD_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT)
4365 
4366 /*
4367  * CARD_ACTIVE_PERIOD_SEL (RW)
4368  *
4369  * card clock delay config.
4370  * 00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle
4371  */
4372 #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL)
4373 #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U)
4374 #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK)
4375 #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT)
4376 
4377 /*
4378  * CARDCLK_DLYSEL (RW)
4379  *
4380  * for card clock DLL, default 0
4381  */
4382 #define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK (0x3F00000UL)
4383 #define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT (20U)
4384 #define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK)
4385 #define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) >> SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT)
4386 
4387 /*
4388  * STROBE_DLYSEL (RW)
4389  *
4390  * for strobe DLL, default 7taps(1ns)
4391  */
4392 #define SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK (0x3F000UL)
4393 #define SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT (12U)
4394 #define SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK)
4395 #define SDXC_MISC_CTRL1_STROBE_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) >> SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT)
4396 
4397 
4398 
4399 /* RESP register group index macro definition */
4400 #define SDXC_RESP_RESP01 (0UL)
4401 #define SDXC_RESP_RESP23 (1UL)
4402 #define SDXC_RESP_RESP45 (2UL)
4403 #define SDXC_RESP_RESP67 (3UL)
4404 
4405 /* PRESET register group index macro definition */
4406 #define SDXC_PRESET_INIT (0UL)
4407 #define SDXC_PRESET_DS (1UL)
4408 #define SDXC_PRESET_HS (2UL)
4409 #define SDXC_PRESET_SDR12 (3UL)
4410 #define SDXC_PRESET_SDR25 (4UL)
4411 #define SDXC_PRESET_SDR50 (5UL)
4412 #define SDXC_PRESET_SDR104 (6UL)
4413 #define SDXC_PRESET_DDR50 (7UL)
4414 #define SDXC_PRESET_UHS2 (10UL)
4415 
4416 
4417 #endif /* HPM_SDXC_H */
SDXC_Type
Definition: hpm_sdxc_regs.h:12