Data Structures
struct	SDXC_Type

Macros
#define	SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL)

#define	SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U)

#define	SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK)

#define	SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT)

#define	SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL)

#define	SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U)

#define	SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK)

#define	SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT)

#define	SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U)

#define	SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U)

#define	SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK)

#define	SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT)

#define	SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU)

#define	SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U)

#define	SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK)

#define	SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT)

#define	SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL)

#define	SDXC_CMD_ARG_ARGUMNET_SHIFT (0U)

#define	SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK)

#define	SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT)

#define	SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL)

#define	SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U)

#define	SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK)

#define	SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT)

#define	SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL)

#define	SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U)

#define	SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK)

#define	SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT)

#define	SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL)

#define	SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U)

#define	SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK)

#define	SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT)

#define	SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL)

#define	SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U)

#define	SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK)

#define	SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT)

#define	SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL)

#define	SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U)

#define	SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK)

#define	SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT)

#define	SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL)

#define	SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U)

#define	SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK)

#define	SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT)

#define	SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL)

#define	SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U)

#define	SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK)

#define	SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT)

#define	SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U)

#define	SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U)

#define	SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK)

#define	SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT)

#define	SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U)

#define	SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U)

#define	SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)

#define	SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT)

#define	SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U)

#define	SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U)

#define	SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK)

#define	SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT)

#define	SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U)

#define	SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U)

#define	SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK)

#define	SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT)

#define	SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U)

#define	SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U)

#define	SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK)

#define	SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT)

#define	SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU)

#define	SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U)

#define	SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK)

#define	SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT)

#define	SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U)

#define	SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U)

#define	SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK)

#define	SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT)

#define	SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U)

#define	SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U)

#define	SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK)

#define	SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT)

#define	SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL)

#define	SDXC_RESP_RESP01_SHIFT (0U)

#define	SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT)

#define	SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL)

#define	SDXC_BUF_DATA_BUF_DATA_SHIFT (0U)

#define	SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK)

#define	SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT)

#define	SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL)

#define	SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U)

#define	SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT)

#define	SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL)

#define	SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U)

#define	SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT)

#define	SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL)

#define	SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U)

#define	SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT)

#define	SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL)

#define	SDXC_PSTATE_DAT_3_0_SHIFT (20U)

#define	SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT)

#define	SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL)

#define	SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U)

#define	SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT)

#define	SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL)

#define	SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U)

#define	SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT)

#define	SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL)

#define	SDXC_PSTATE_CARD_STABLE_SHIFT (17U)

#define	SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT)

#define	SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL)

#define	SDXC_PSTATE_CARD_INSERTED_SHIFT (16U)

#define	SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT)

#define	SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U)

#define	SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U)

#define	SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT)

#define	SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U)

#define	SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U)

#define	SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT)

#define	SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U)

#define	SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U)

#define	SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT)

#define	SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U)

#define	SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U)

#define	SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT)

#define	SDXC_PSTATE_DAT_7_4_MASK (0xF0U)

#define	SDXC_PSTATE_DAT_7_4_SHIFT (4U)

#define	SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT)

#define	SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U)

#define	SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U)

#define	SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT)

#define	SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U)

#define	SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U)

#define	SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT)

#define	SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U)

#define	SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U)

#define	SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT)

#define	SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U)

#define	SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U)

#define	SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT)

#define	SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL)

#define	SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U)

#define	SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK)

#define	SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT)

#define	SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL)

#define	SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U)

#define	SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK)

#define	SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT)

#define	SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL)

#define	SDXC_PROT_CTRL_CARD_INT_SHIFT (24U)

#define	SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK)

#define	SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT)

#define	SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL)

#define	SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U)

#define	SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK)

#define	SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT)

#define	SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL)

#define	SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U)

#define	SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK)

#define	SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT)

#define	SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL)

#define	SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U)

#define	SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK)

#define	SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT)

#define	SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL)

#define	SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U)

#define	SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK)

#define	SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT)

#define	SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U)

#define	SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U)

#define	SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK)

#define	SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT)

#define	SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U)

#define	SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U)

#define	SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK)

#define	SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT)

#define	SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U)

#define	SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U)

#define	SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK)

#define	SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT)

#define	SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U)

#define	SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U)

#define	SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK)

#define	SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT)

#define	SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U)

#define	SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U)

#define	SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK)

#define	SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT)

#define	SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U)

#define	SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U)

#define	SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK)

#define	SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT)

#define	SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL)

#define	SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U)

#define	SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK)

#define	SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT)

#define	SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL)

#define	SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U)

#define	SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK)

#define	SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT)

#define	SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL)

#define	SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U)

#define	SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK)

#define	SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT)

#define	SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL)

#define	SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U)

#define	SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK)

#define	SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT)

#define	SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U)

#define	SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U)

#define	SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK)

#define	SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT)

#define	SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U)

#define	SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U)

#define	SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK)

#define	SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT)

#define	SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U)

#define	SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U)

#define	SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK)

#define	SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT)

#define	SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U)

#define	SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U)

#define	SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK)

#define	SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT)

#define	SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U)

#define	SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U)

#define	SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK)

#define	SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK)

#define	SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT)

#define	SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL)

#define	SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U)

#define	SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK)

#define	SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT)

#define	SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL)

#define	SDXC_INT_STAT_RESP_ERR_SHIFT (27U)

#define	SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK)

#define	SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT)

#define	SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL)

#define	SDXC_INT_STAT_TUNING_ERR_SHIFT (26U)

#define	SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK)

#define	SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT)

#define	SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL)

#define	SDXC_INT_STAT_ADMA_ERR_SHIFT (25U)

#define	SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK)

#define	SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT)

#define	SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL)

#define	SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U)

#define	SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK)

#define	SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT)

#define	SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL)

#define	SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U)

#define	SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK)

#define	SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT)

#define	SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL)

#define	SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U)

#define	SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK)

#define	SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT)

#define	SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL)

#define	SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U)

#define	SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK)

#define	SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT)

#define	SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL)

#define	SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U)

#define	SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK)

#define	SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT)

#define	SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL)

#define	SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U)

#define	SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK)

#define	SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT)

#define	SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL)

#define	SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U)

#define	SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK)

#define	SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT)

#define	SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL)

#define	SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U)

#define	SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK)

#define	SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT)

#define	SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL)

#define	SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U)

#define	SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK)

#define	SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT)

#define	SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U)

#define	SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U)

#define	SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT)

#define	SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U)

#define	SDXC_INT_STAT_CQE_EVENT_SHIFT (14U)

#define	SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK)

#define	SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT)

#define	SDXC_INT_STAT_FX_EVENT_MASK (0x2000U)

#define	SDXC_INT_STAT_FX_EVENT_SHIFT (13U)

#define	SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT)

#define	SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U)

#define	SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U)

#define	SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT)

#define	SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U)

#define	SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U)

#define	SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT)

#define	SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U)

#define	SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U)

#define	SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK)

#define	SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT)

#define	SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U)

#define	SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U)

#define	SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK)

#define	SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT)

#define	SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U)

#define	SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U)

#define	SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK)

#define	SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT)

#define	SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U)

#define	SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U)

#define	SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK)

#define	SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT)

#define	SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U)

#define	SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U)

#define	SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK)

#define	SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT)

#define	SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U)

#define	SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U)

#define	SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK)

#define	SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT)

#define	SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U)

#define	SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U)

#define	SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK)

#define	SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT)

#define	SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U)

#define	SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U)

#define	SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK)

#define	SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT)

#define	SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL)

#define	SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U)

#define	SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL)

#define	SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U)

#define	SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL)

#define	SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U)

#define	SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL)

#define	SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U)

#define	SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL)

#define	SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U)

#define	SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL)

#define	SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U)

#define	SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL)

#define	SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U)

#define	SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL)

#define	SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U)

#define	SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL)

#define	SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U)

#define	SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL)

#define	SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U)

#define	SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL)

#define	SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U)

#define	SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL)

#define	SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U)

#define	SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL)

#define	SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U)

#define	SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U)

#define	SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U)

#define	SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U)

#define	SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U)

#define	SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U)

#define	SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U)

#define	SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U)

#define	SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U)

#define	SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U)

#define	SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U)

#define	SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U)

#define	SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U)

#define	SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U)

#define	SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U)

#define	SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U)

#define	SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U)

#define	SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U)

#define	SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U)

#define	SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U)

#define	SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U)

#define	SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U)

#define	SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U)

#define	SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT)

#define	SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U)

#define	SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U)

#define	SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK)

#define	SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL)

#define	SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U)

#define	SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL)

#define	SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U)

#define	SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL)

#define	SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U)

#define	SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL)

#define	SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U)

#define	SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL)

#define	SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U)

#define	SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL)

#define	SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U)

#define	SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL)

#define	SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U)

#define	SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL)

#define	SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U)

#define	SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL)

#define	SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U)

#define	SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL)

#define	SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U)

#define	SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL)

#define	SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U)

#define	SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL)

#define	SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U)

#define	SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL)

#define	SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U)

#define	SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U)

#define	SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U)

#define	SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U)

#define	SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U)

#define	SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U)

#define	SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U)

#define	SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U)

#define	SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U)

#define	SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U)

#define	SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U)

#define	SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U)

#define	SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U)

#define	SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U)

#define	SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U)

#define	SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U)

#define	SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U)

#define	SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U)

#define	SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U)

#define	SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U)

#define	SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U)

#define	SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U)

#define	SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U)

#define	SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT)

#define	SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U)

#define	SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U)

#define	SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK)

#define	SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT)

#define	SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL)

#define	SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U)

#define	SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK)

#define	SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT)

#define	SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL)

#define	SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U)

#define	SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK)

#define	SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT)

#define	SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL)

#define	SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U)

#define	SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK)

#define	SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT)

#define	SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL)

#define	SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U)

#define	SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK)

#define	SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT)

#define	SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL)

#define	SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U)

#define	SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK)

#define	SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT)

#define	SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL)

#define	SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U)

#define	SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK)

#define	SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT)

#define	SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL)

#define	SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U)

#define	SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)

#define	SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT)

#define	SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL)

#define	SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U)

#define	SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK)

#define	SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT)

#define	SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL)

#define	SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U)

#define	SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK)

#define	SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT)

#define	SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)

#define	SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)

#define	SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U)

#define	SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT)

#define	SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL)

#define	SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U)

#define	SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT)

#define	SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL)

#define	SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U)

#define	SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL)

#define	SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U)

#define	SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT)

#define	SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL)

#define	SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U)

#define	SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT)

#define	SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL)

#define	SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U)

#define	SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT)

#define	SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL)

#define	SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U)

#define	SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL)

#define	SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U)

#define	SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL)

#define	SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U)

#define	SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL)

#define	SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U)

#define	SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL)

#define	SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U)

#define	SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT)

#define	SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL)

#define	SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U)

#define	SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT)

#define	SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U)

#define	SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U)

#define	SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT)

#define	SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U)

#define	SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U)

#define	SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT)

#define	SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU)

#define	SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U)

#define	SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT)

#define	SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL)

#define	SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U)

#define	SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL)

#define	SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U)

#define	SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL)

#define	SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U)

#define	SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT)

#define	SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U)

#define	SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U)

#define	SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT)

#define	SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U)

#define	SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U)

#define	SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT)

#define	SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U)

#define	SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U)

#define	SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT)

#define	SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U)

#define	SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U)

#define	SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT)

#define	SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U)

#define	SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U)

#define	SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT)

#define	SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U)

#define	SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U)

#define	SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT)

#define	SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U)

#define	SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U)

#define	SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U)

#define	SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U)

#define	SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U)

#define	SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U)

#define	SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT)

#define	SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U)

#define	SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U)

#define	SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U)

#define	SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT)

#define	SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU)

#define	SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U)

#define	SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL)

#define	SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U)

#define	SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL)

#define	SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U)

#define	SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL)

#define	SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U)

#define	SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL)

#define	SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U)

#define	SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL)

#define	SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U)

#define	SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL)

#define	SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U)

#define	SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL)

#define	SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U)

#define	SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL)

#define	SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U)

#define	SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL)

#define	SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U)

#define	SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL)

#define	SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U)

#define	SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL)

#define	SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U)

#define	SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL)

#define	SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U)

#define	SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)

#define	SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)

#define	SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK)

#define	SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK)

#define	SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT)

#define	SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U)

#define	SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U)

#define	SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT)

#define	SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U)

#define	SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U)

#define	SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT)

#define	SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL)

#define	SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U)

#define	SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK)

#define	SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT)

#define	SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U)

#define	SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U)

#define	SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT)

#define	SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU)

#define	SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U)

#define	SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT)

#define	SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL)

#define	SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U)

#define	SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK)

#define	SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT)

#define	SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU)

#define	SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U)

#define	SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT)

#define	SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU)

#define	SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)

#define	SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)

#define	SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU)

#define	SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)

#define	SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)

#define	SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU)

#define	SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U)

#define	SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT)

#define	SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U)

#define	SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U)

#define	SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT)

#define	SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U)

#define	SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U)

#define	SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT)

#define	SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU)

#define	SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U)

#define	SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT)

#define	SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL)

#define	SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U)

#define	SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT)

#define	SDXC_CQCAP_ITCFMUL_MASK (0xF000U)

#define	SDXC_CQCAP_ITCFMUL_SHIFT (12U)

#define	SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT)

#define	SDXC_CQCAP_ITCFVAL_MASK (0x3FFU)

#define	SDXC_CQCAP_ITCFVAL_SHIFT (0U)

#define	SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT)

#define	SDXC_CQCFG_DCMD_EN_MASK (0x1000U)

#define	SDXC_CQCFG_DCMD_EN_SHIFT (12U)

#define	SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK)

#define	SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT)

#define	SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U)

#define	SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U)

#define	SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK)

#define	SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT)

#define	SDXC_CQCFG_CQ_EN_MASK (0x1U)

#define	SDXC_CQCFG_CQ_EN_SHIFT (0U)

#define	SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK)

#define	SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT)

#define	SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U)

#define	SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U)

#define	SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK)

#define	SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT)

#define	SDXC_CQCTL_HALT_MASK (0x1U)

#define	SDXC_CQCTL_HALT_SHIFT (0U)

#define	SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK)

#define	SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT)

#define	SDXC_CQIS_TCL_MASK (0x8U)

#define	SDXC_CQIS_TCL_SHIFT (3U)

#define	SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK)

#define	SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT)

#define	SDXC_CQIS_RED_MASK (0x4U)

#define	SDXC_CQIS_RED_SHIFT (2U)

#define	SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK)

#define	SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT)

#define	SDXC_CQIS_TCC_MASK (0x2U)

#define	SDXC_CQIS_TCC_SHIFT (1U)

#define	SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK)

#define	SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT)

#define	SDXC_CQIS_HAC_MASK (0x1U)

#define	SDXC_CQIS_HAC_SHIFT (0U)

#define	SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK)

#define	SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT)

#define	SDXC_CQISE_TCL_STE_MASK (0x8U)

#define	SDXC_CQISE_TCL_STE_SHIFT (3U)

#define	SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK)

#define	SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT)

#define	SDXC_CQISE_RED_STE_MASK (0x4U)

#define	SDXC_CQISE_RED_STE_SHIFT (2U)

#define	SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK)

#define	SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT)

#define	SDXC_CQISE_TCC_STE_MASK (0x2U)

#define	SDXC_CQISE_TCC_STE_SHIFT (1U)

#define	SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK)

#define	SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT)

#define	SDXC_CQISE_HAC_STE_MASK (0x1U)

#define	SDXC_CQISE_HAC_STE_SHIFT (0U)

#define	SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK)

#define	SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT)

#define	SDXC_CQISGE_TCL_SGE_MASK (0x8U)

#define	SDXC_CQISGE_TCL_SGE_SHIFT (3U)

#define	SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK)

#define	SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT)

#define	SDXC_CQISGE_RED_SGE_MASK (0x4U)

#define	SDXC_CQISGE_RED_SGE_SHIFT (2U)

#define	SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK)

#define	SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT)

#define	SDXC_CQISGE_TCC_SGE_MASK (0x2U)

#define	SDXC_CQISGE_TCC_SGE_SHIFT (1U)

#define	SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK)

#define	SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT)

#define	SDXC_CQISGE_HAC_SGE_MASK (0x1U)

#define	SDXC_CQISGE_HAC_SGE_SHIFT (0U)

#define	SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK)

#define	SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT)

#define	SDXC_CQIC_INTC_EN_MASK (0x80000000UL)

#define	SDXC_CQIC_INTC_EN_SHIFT (31U)

#define	SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK)

#define	SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT)

#define	SDXC_CQIC_INTC_STAT_MASK (0x100000UL)

#define	SDXC_CQIC_INTC_STAT_SHIFT (20U)

#define	SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT)

#define	SDXC_CQIC_INTC_RST_MASK (0x10000UL)

#define	SDXC_CQIC_INTC_RST_SHIFT (16U)

#define	SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK)

#define	SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT)

#define	SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U)

#define	SDXC_CQIC_INTC_TH_WEN_SHIFT (15U)

#define	SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK)

#define	SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT)

#define	SDXC_CQIC_INTC_TH_MASK (0x1F00U)

#define	SDXC_CQIC_INTC_TH_SHIFT (8U)

#define	SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK)

#define	SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT)

#define	SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U)

#define	SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U)

#define	SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK)

#define	SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT)

#define	SDXC_CQIC_TOUT_VAL_MASK (0x7FU)

#define	SDXC_CQIC_TOUT_VAL_SHIFT (0U)

#define	SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK)

#define	SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT)

#define	SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL)

#define	SDXC_CQTDLBA_TDLBA_SHIFT (0U)

#define	SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK)

#define	SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT)

#define	SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL)

#define	SDXC_CQTDBR_DBR_SHIFT (0U)

#define	SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK)

#define	SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT)

#define	SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL)

#define	SDXC_CQTCN_TCN_SHIFT (0U)

#define	SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK)

#define	SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT)

#define	SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL)

#define	SDXC_CQDQS_DQS_SHIFT (0U)

#define	SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK)

#define	SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT)

#define	SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL)

#define	SDXC_CQDPT_DPT_SHIFT (0U)

#define	SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK)

#define	SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT)

#define	SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL)

#define	SDXC_CQTCLR_TCLR_SHIFT (0U)

#define	SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK)

#define	SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT)

#define	SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL)

#define	SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U)

#define	SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK)

#define	SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT)

#define	SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU)

#define	SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U)

#define	SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK)

#define	SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT)

#define	SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU)

#define	SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U)

#define	SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK)

#define	SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT)

#define	SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL)

#define	SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U)

#define	SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT)

#define	SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL)

#define	SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U)

#define	SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK)

#define	SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT)

#define	SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL)

#define	SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U)

#define	SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT)

#define	SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL)

#define	SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U)

#define	SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT)

#define	SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U)

#define	SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U)

#define	SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT)

#define	SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U)

#define	SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U)

#define	SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT)

#define	SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU)

#define	SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U)

#define	SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT)

#define	SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU)

#define	SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U)

#define	SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT)

#define	SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL)

#define	SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U)

#define	SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT)

#define	SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL)

#define	SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U)

#define	SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT)

#define	SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL)

#define	SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U)

#define	SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK)

#define	SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL)

#define	SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U)

#define	SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK)

#define	SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL)

#define	SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U)

#define	SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK)

#define	SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U)

#define	SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U)

#define	SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK)

#define	SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U)

#define	SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U)

#define	SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK)

#define	SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U)

#define	SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U)

#define	SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK)

#define	SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK)

#define	SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U)

#define	SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U)

#define	SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK)

#define	SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT)

#define	SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U)

#define	SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U)

#define	SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK)

#define	SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL)

#define	SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U)

#define	SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK)

#define	SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL)

#define	SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U)

#define	SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK)

#define	SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL)

#define	SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U)

#define	SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK)

#define	SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U)

#define	SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U)

#define	SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK)

#define	SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U)

#define	SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U)

#define	SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK)

#define	SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U)

#define	SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U)

#define	SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK)

#define	SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK)

#define	SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U)

#define	SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U)

#define	SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK)

#define	SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT)

#define	SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U)

#define	SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U)

#define	SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK)

#define	SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT)

#define	SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL)

#define	SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U)

#define	SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT)

#define	SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U)

#define	SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U)

#define	SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT)

#define	SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU)

#define	SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U)

#define	SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK)

#define	SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT)

#define	SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL)

#define	SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U)

#define	SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK)

#define	SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) >> SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT)

#define	SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL)

#define	SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U)

#define	SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK)

#define	SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT)

#define	SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U)

#define	SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U)

#define	SDXC_MISC_CTRL0_TMCLK_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) & SDXC_MISC_CTRL0_TMCLK_EN_MASK)

#define	SDXC_MISC_CTRL0_TMCLK_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) >> SDXC_MISC_CTRL0_TMCLK_EN_SHIFT)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK)

#define	SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK)

#define	SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT)

#define	SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK (0x3F00000UL)

#define	SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT (20U)

#define	SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK)

#define	SDXC_MISC_CTRL1_CARDCLK_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) >> SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT)

#define	SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK (0x3F000UL)

#define	SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT (12U)

#define	SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK)

#define	SDXC_MISC_CTRL1_STROBE_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) >> SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT)

#define	SDXC_RESP_RESP01 (0UL)

#define	SDXC_RESP_RESP23 (1UL)

#define	SDXC_RESP_RESP45 (2UL)

#define	SDXC_RESP_RESP67 (3UL)

#define	SDXC_PRESET_INIT (0UL)

#define	SDXC_PRESET_DS (1UL)

#define	SDXC_PRESET_HS (2UL)

#define	SDXC_PRESET_SDR12 (3UL)

#define	SDXC_PRESET_SDR25 (4UL)

#define	SDXC_PRESET_SDR50 (5UL)

#define	SDXC_PRESET_SDR104 (6UL)

#define	SDXC_PRESET_DDR50 (7UL)

#define	SDXC_PRESET_UHS2 (10UL)

Macro Definition Documentation

◆ SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET

#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT)

◆ SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK

#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL)

◆ SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET

#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK)

◆ SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT

#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U)

◆ SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET

#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT)

◆ SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK

#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL)

◆ SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET

#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK)

◆ SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT

#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET

#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK

#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT

#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET

#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK

#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT

#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET

#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK

#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT

#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET

#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK

#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT

#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET

#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK

#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT

#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET

#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK

#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U)

◆ SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT

#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U)

◆ SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET

#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT)

◆ SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK

#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL)

◆ SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET

#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK)

◆ SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT

#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U)

◆ SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET

#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)

◆ SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK

#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)

◆ SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT

#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)

◆ SDXC_AC_HOST_CTRL_EXEC_TUNING_GET

#define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT)

◆ SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK

#define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL)

◆ SDXC_AC_HOST_CTRL_EXEC_TUNING_SET

#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)

◆ SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT

#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U)

◆ SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET

#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT)

◆ SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK

#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL)

◆ SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET

#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK)

◆ SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT

#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U)

◆ SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET

#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT)

◆ SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK

#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL)

◆ SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET

#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK)

◆ SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT

#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U)

◆ SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET

#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT)

◆ SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK

#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL)

◆ SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET

#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK)

◆ SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT

#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U)

◆ SDXC_AC_HOST_CTRL_SIGNALING_EN_GET

#define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT)

◆ SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK

#define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL)

◆ SDXC_AC_HOST_CTRL_SIGNALING_EN_SET

#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK)

◆ SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT

#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U)

◆ SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET

#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET ( x ) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT)

◆ SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK

#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL)

◆ SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET

#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET ( x ) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK)

◆ SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT

#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U)

◆ SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET

#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET ( x ) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT)

◆ SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK

#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U)

◆ SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT

#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U)

◆ SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET

#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET ( x ) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT)

◆ SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK

#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U)

◆ SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT

#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U)

◆ SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET

#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET ( x ) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT)

◆ SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK

#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL)

◆ SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET

#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET ( x ) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK)

◆ SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT

#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U)

◆ SDXC_ADMA_SYS_ADDR_ADMA_SA_GET

#define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET ( x ) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT)

◆ SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK

#define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL)

◆ SDXC_ADMA_SYS_ADDR_ADMA_SA_SET

#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET ( x ) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK)

◆ SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT

#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U)

◆ SDXC_AUTO_TUNING_CTRL_AT_EN_GET

#define SDXC_AUTO_TUNING_CTRL_AT_EN_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_AT_EN_MASK

#define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U)

◆ SDXC_AUTO_TUNING_CTRL_AT_EN_SET

#define SDXC_AUTO_TUNING_CTRL_AT_EN_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK)

◆ SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT

#define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U)

◆ SDXC_AUTO_TUNING_CTRL_CI_SEL_GET

#define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK

#define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U)

◆ SDXC_AUTO_TUNING_CTRL_CI_SEL_SET

#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK)

◆ SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT

#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U)

◆ SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET

#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK

#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL)

◆ SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET

#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK)

◆ SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT

#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U)

◆ SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET

#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK

#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL)

◆ SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET

#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK)

◆ SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT

#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U)

◆ SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET

#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK

#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U)

◆ SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET

#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK)

◆ SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT

#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U)

◆ SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET

#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK

#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U)

◆ SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET

#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK)

◆ SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT

#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK)

◆ SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT

#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U)

◆ SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET

#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK

#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL)

◆ SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET

#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK)

◆ SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT

#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U)

◆ SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET

#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT)

◆ SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK

#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U)

◆ SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET

#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK)

◆ SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT

#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U)

◆ SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET

#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT)

◆ SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK

#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU)

◆ SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET

#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET ( x ) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK)

◆ SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT

#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U)

◆ SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET

#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT)

◆ SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK

#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL)

◆ SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT

#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U)

◆ SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET

#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET ( x ) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT)

◆ SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK

#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U)

◆ SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT

#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U)

◆ SDXC_BLK_ATTR_BLOCK_CNT_GET

#define SDXC_BLK_ATTR_BLOCK_CNT_GET ( x ) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT)

◆ SDXC_BLK_ATTR_BLOCK_CNT_MASK

#define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL)

◆ SDXC_BLK_ATTR_BLOCK_CNT_SET

#define SDXC_BLK_ATTR_BLOCK_CNT_SET ( x ) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK)

◆ SDXC_BLK_ATTR_BLOCK_CNT_SHIFT

#define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U)

◆ SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET

#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET ( x ) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT)

◆ SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK

#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U)

◆ SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET

#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET ( x ) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK)

◆ SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT

#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U)

◆ SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET

#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET ( x ) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT)

◆ SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK

#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU)

◆ SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET

#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET ( x ) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK)

◆ SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT

#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U)

◆ SDXC_BUF_DATA_BUF_DATA_GET

#define SDXC_BUF_DATA_BUF_DATA_GET ( x ) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT)

◆ SDXC_BUF_DATA_BUF_DATA_MASK

#define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL)

◆ SDXC_BUF_DATA_BUF_DATA_SET

#define SDXC_BUF_DATA_BUF_DATA_SET ( x ) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK)

◆ SDXC_BUF_DATA_BUF_DATA_SHIFT

#define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U)

◆ SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET

#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK

#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL)

◆ SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT

#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U)

◆ SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET

#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK

#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL)

◆ SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT

#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U)

◆ SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET

#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT)

◆ SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK

#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U)

◆ SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT

#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U)

◆ SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET

#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT)

◆ SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK

#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL)

◆ SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT

#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U)

◆ SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET

#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK

#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL)

◆ SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT

#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U)

◆ SDXC_CAPABILITIES1_MAX_BLK_LEN_GET

#define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT)

◆ SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK

#define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL)

◆ SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT

#define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U)

◆ SDXC_CAPABILITIES1_SDMA_SUPPORT_GET

#define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK

#define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL)

◆ SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT

#define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U)

◆ SDXC_CAPABILITIES1_SLOT_TYPE_R_GET

#define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT)

◆ SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK

#define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL)

◆ SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT

#define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U)

◆ SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET

#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK

#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL)

◆ SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT

#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U)

◆ SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET

#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT)

◆ SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK

#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU)

◆ SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT

#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U)

◆ SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET

#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT)

◆ SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK

#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U)

◆ SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT

#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U)

◆ SDXC_CAPABILITIES1_VOLT_18_GET

#define SDXC_CAPABILITIES1_VOLT_18_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT)

◆ SDXC_CAPABILITIES1_VOLT_18_MASK

#define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL)

◆ SDXC_CAPABILITIES1_VOLT_18_SHIFT

#define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U)

◆ SDXC_CAPABILITIES1_VOLT_30_GET

#define SDXC_CAPABILITIES1_VOLT_30_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT)

◆ SDXC_CAPABILITIES1_VOLT_30_MASK

#define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL)

◆ SDXC_CAPABILITIES1_VOLT_30_SHIFT

#define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U)

◆ SDXC_CAPABILITIES1_VOLT_33_GET

#define SDXC_CAPABILITIES1_VOLT_33_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT)

◆ SDXC_CAPABILITIES1_VOLT_33_MASK

#define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL)

◆ SDXC_CAPABILITIES1_VOLT_33_SHIFT

#define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U)

◆ SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET

#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK

#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL)

◆ SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT

#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U)

◆ SDXC_CAPABILITIES2_CLK_MUL_GET

#define SDXC_CAPABILITIES2_CLK_MUL_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT)

◆ SDXC_CAPABILITIES2_CLK_MUL_MASK

#define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL)

◆ SDXC_CAPABILITIES2_CLK_MUL_SHIFT

#define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U)

◆ SDXC_CAPABILITIES2_DDR50_SUPPORT_GET

#define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK

#define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U)

◆ SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT

#define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U)

◆ SDXC_CAPABILITIES2_DRV_TYPEA_GET

#define SDXC_CAPABILITIES2_DRV_TYPEA_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT)

◆ SDXC_CAPABILITIES2_DRV_TYPEA_MASK

#define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U)

◆ SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT

#define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U)

◆ SDXC_CAPABILITIES2_DRV_TYPEC_GET

#define SDXC_CAPABILITIES2_DRV_TYPEC_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT)

◆ SDXC_CAPABILITIES2_DRV_TYPEC_MASK

#define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U)

◆ SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT

#define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U)

◆ SDXC_CAPABILITIES2_DRV_TYPED_GET

#define SDXC_CAPABILITIES2_DRV_TYPED_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT)

◆ SDXC_CAPABILITIES2_DRV_TYPED_MASK

#define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U)

◆ SDXC_CAPABILITIES2_DRV_TYPED_SHIFT

#define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U)

◆ SDXC_CAPABILITIES2_RE_TUNING_MODES_GET

#define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT)

◆ SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK

#define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U)

◆ SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT

#define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U)

◆ SDXC_CAPABILITIES2_RETUNE_CNT_GET

#define SDXC_CAPABILITIES2_RETUNE_CNT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT)

◆ SDXC_CAPABILITIES2_RETUNE_CNT_MASK

#define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U)

◆ SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT

#define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U)

◆ SDXC_CAPABILITIES2_SDR104_SUPPORT_GET

#define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK

#define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U)

◆ SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT

#define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U)

◆ SDXC_CAPABILITIES2_SDR50_SUPPORT_GET

#define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK

#define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U)

◆ SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT

#define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U)

◆ SDXC_CAPABILITIES2_UHS2_SUPPORT_GET

#define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK

#define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U)

◆ SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT

#define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U)

◆ SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET

#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT)

◆ SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK

#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U)

◆ SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT

#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U)

◆ SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET

#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT)

◆ SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK

#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL)

◆ SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT

#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U)

◆ SDXC_CMD_ARG_ARGUMNET_GET

#define SDXC_CMD_ARG_ARGUMNET_GET ( x ) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT)

◆ SDXC_CMD_ARG_ARGUMNET_MASK

#define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL)

◆ SDXC_CMD_ARG_ARGUMNET_SET

#define SDXC_CMD_ARG_ARGUMNET_SET ( x ) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK)

◆ SDXC_CMD_ARG_ARGUMNET_SHIFT

#define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U)

◆ SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET

#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT)

◆ SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK

#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU)

◆ SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET

#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK)

◆ SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT

#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U)

◆ SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET

#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT)

◆ SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK

#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U)

◆ SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET

#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK)

◆ SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT

#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U)

◆ SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET

#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT)

◆ SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK

#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL)

◆ SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET

#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK)

◆ SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT

#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U)

◆ SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET

#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT)

◆ SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK

#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL)

◆ SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET

#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK)

◆ SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT

#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U)

◆ SDXC_CMD_XFER_CMD_INDEX_GET

#define SDXC_CMD_XFER_CMD_INDEX_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT)

◆ SDXC_CMD_XFER_CMD_INDEX_MASK

#define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL)

◆ SDXC_CMD_XFER_CMD_INDEX_SET

#define SDXC_CMD_XFER_CMD_INDEX_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK)

◆ SDXC_CMD_XFER_CMD_INDEX_SHIFT

#define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U)

◆ SDXC_CMD_XFER_CMD_TYPE_GET

#define SDXC_CMD_XFER_CMD_TYPE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT)

◆ SDXC_CMD_XFER_CMD_TYPE_MASK

#define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL)

◆ SDXC_CMD_XFER_CMD_TYPE_SET

#define SDXC_CMD_XFER_CMD_TYPE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK)

◆ SDXC_CMD_XFER_CMD_TYPE_SHIFT

#define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U)

◆ SDXC_CMD_XFER_DATA_PRESENT_SEL_GET

#define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT)

◆ SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK

#define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL)

◆ SDXC_CMD_XFER_DATA_PRESENT_SEL_SET

#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK)

◆ SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT

#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U)

◆ SDXC_CMD_XFER_DATA_XFER_DIR_GET

#define SDXC_CMD_XFER_DATA_XFER_DIR_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT)

◆ SDXC_CMD_XFER_DATA_XFER_DIR_MASK

#define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U)

◆ SDXC_CMD_XFER_DATA_XFER_DIR_SET

#define SDXC_CMD_XFER_DATA_XFER_DIR_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK)

◆ SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT

#define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U)

◆ SDXC_CMD_XFER_DMA_ENABLE_GET

#define SDXC_CMD_XFER_DMA_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT)

◆ SDXC_CMD_XFER_DMA_ENABLE_MASK

#define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U)

◆ SDXC_CMD_XFER_DMA_ENABLE_SET

#define SDXC_CMD_XFER_DMA_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK)

◆ SDXC_CMD_XFER_DMA_ENABLE_SHIFT

#define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U)

◆ SDXC_CMD_XFER_MULTI_BLK_SEL_GET

#define SDXC_CMD_XFER_MULTI_BLK_SEL_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT)

◆ SDXC_CMD_XFER_MULTI_BLK_SEL_MASK

#define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U)

◆ SDXC_CMD_XFER_MULTI_BLK_SEL_SET

#define SDXC_CMD_XFER_MULTI_BLK_SEL_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK)

◆ SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT

#define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U)

◆ SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET

#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT)

◆ SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK

#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U)

◆ SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET

#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)

◆ SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT

#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U)

◆ SDXC_CMD_XFER_RESP_INT_DISABLE_GET

#define SDXC_CMD_XFER_RESP_INT_DISABLE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT)

◆ SDXC_CMD_XFER_RESP_INT_DISABLE_MASK

#define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U)

◆ SDXC_CMD_XFER_RESP_INT_DISABLE_SET

#define SDXC_CMD_XFER_RESP_INT_DISABLE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK)

◆ SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT

#define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U)

◆ SDXC_CMD_XFER_RESP_TYPE_GET

#define SDXC_CMD_XFER_RESP_TYPE_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT)

◆ SDXC_CMD_XFER_RESP_TYPE_MASK

#define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U)

◆ SDXC_CMD_XFER_RESP_TYPE_SELECT_GET

#define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT)

◆ SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK

#define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL)

◆ SDXC_CMD_XFER_RESP_TYPE_SELECT_SET

#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK)

◆ SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT

#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U)

◆ SDXC_CMD_XFER_RESP_TYPE_SET

#define SDXC_CMD_XFER_RESP_TYPE_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK)

◆ SDXC_CMD_XFER_RESP_TYPE_SHIFT

#define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U)

◆ SDXC_CMD_XFER_SUB_CMD_FLAG_GET

#define SDXC_CMD_XFER_SUB_CMD_FLAG_GET ( x ) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT)

◆ SDXC_CMD_XFER_SUB_CMD_FLAG_MASK

#define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL)

◆ SDXC_CMD_XFER_SUB_CMD_FLAG_SET

#define SDXC_CMD_XFER_SUB_CMD_FLAG_SET ( x ) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK)

◆ SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT

#define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U)

◆ SDXC_CQCAP_CRYPTO_SUPPORT_GET

#define SDXC_CQCAP_CRYPTO_SUPPORT_GET ( x ) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT)

◆ SDXC_CQCAP_CRYPTO_SUPPORT_MASK

#define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL)

◆ SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT

#define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U)

◆ SDXC_CQCAP_ITCFMUL_GET

#define SDXC_CQCAP_ITCFMUL_GET ( x ) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT)

◆ SDXC_CQCAP_ITCFMUL_MASK

#define SDXC_CQCAP_ITCFMUL_MASK (0xF000U)

◆ SDXC_CQCAP_ITCFMUL_SHIFT

#define SDXC_CQCAP_ITCFMUL_SHIFT (12U)

◆ SDXC_CQCAP_ITCFVAL_GET

#define SDXC_CQCAP_ITCFVAL_GET ( x ) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT)

◆ SDXC_CQCAP_ITCFVAL_MASK

#define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU)

◆ SDXC_CQCAP_ITCFVAL_SHIFT

#define SDXC_CQCAP_ITCFVAL_SHIFT (0U)

◆ SDXC_CQCFG_CQ_EN_GET

#define SDXC_CQCFG_CQ_EN_GET ( x ) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT)

◆ SDXC_CQCFG_CQ_EN_MASK

#define SDXC_CQCFG_CQ_EN_MASK (0x1U)

◆ SDXC_CQCFG_CQ_EN_SET

#define SDXC_CQCFG_CQ_EN_SET ( x ) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK)

◆ SDXC_CQCFG_CQ_EN_SHIFT

#define SDXC_CQCFG_CQ_EN_SHIFT (0U)

◆ SDXC_CQCFG_DCMD_EN_GET

#define SDXC_CQCFG_DCMD_EN_GET ( x ) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT)

◆ SDXC_CQCFG_DCMD_EN_MASK

#define SDXC_CQCFG_DCMD_EN_MASK (0x1000U)

◆ SDXC_CQCFG_DCMD_EN_SET

#define SDXC_CQCFG_DCMD_EN_SET ( x ) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK)

◆ SDXC_CQCFG_DCMD_EN_SHIFT

#define SDXC_CQCFG_DCMD_EN_SHIFT (12U)

◆ SDXC_CQCFG_TASK_DESC_SIZE_GET

#define SDXC_CQCFG_TASK_DESC_SIZE_GET ( x ) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT)

◆ SDXC_CQCFG_TASK_DESC_SIZE_MASK

#define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U)

◆ SDXC_CQCFG_TASK_DESC_SIZE_SET

#define SDXC_CQCFG_TASK_DESC_SIZE_SET ( x ) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK)

◆ SDXC_CQCFG_TASK_DESC_SIZE_SHIFT

#define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U)

◆ SDXC_CQCRA_CMD_RESP_ARG_GET

#define SDXC_CQCRA_CMD_RESP_ARG_GET ( x ) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT)

◆ SDXC_CQCRA_CMD_RESP_ARG_MASK

#define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL)

◆ SDXC_CQCRA_CMD_RESP_ARG_SHIFT

#define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U)

◆ SDXC_CQCRDCT_DCMD_RESP_GET

#define SDXC_CQCRDCT_DCMD_RESP_GET ( x ) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT)

◆ SDXC_CQCRDCT_DCMD_RESP_MASK

#define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL)

◆ SDXC_CQCRDCT_DCMD_RESP_SHIFT

#define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U)

◆ SDXC_CQCRI_CMD_RESP_INDX_GET

#define SDXC_CQCRI_CMD_RESP_INDX_GET ( x ) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT)

◆ SDXC_CQCRI_CMD_RESP_INDX_MASK

#define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU)

◆ SDXC_CQCRI_CMD_RESP_INDX_SHIFT

#define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U)

◆ SDXC_CQCTL_CLR_ALL_TASKS_GET

#define SDXC_CQCTL_CLR_ALL_TASKS_GET ( x ) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT)

◆ SDXC_CQCTL_CLR_ALL_TASKS_MASK

#define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U)

◆ SDXC_CQCTL_CLR_ALL_TASKS_SET

#define SDXC_CQCTL_CLR_ALL_TASKS_SET ( x ) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK)

◆ SDXC_CQCTL_CLR_ALL_TASKS_SHIFT

#define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U)

◆ SDXC_CQCTL_HALT_GET

#define SDXC_CQCTL_HALT_GET ( x ) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT)

◆ SDXC_CQCTL_HALT_MASK

#define SDXC_CQCTL_HALT_MASK (0x1U)

◆ SDXC_CQCTL_HALT_SET

#define SDXC_CQCTL_HALT_SET ( x ) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK)

◆ SDXC_CQCTL_HALT_SHIFT

#define SDXC_CQCTL_HALT_SHIFT (0U)

◆ SDXC_CQDPT_DPT_GET

#define SDXC_CQDPT_DPT_GET ( x ) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT)

◆ SDXC_CQDPT_DPT_MASK

#define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL)

◆ SDXC_CQDPT_DPT_SET

#define SDXC_CQDPT_DPT_SET ( x ) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK)

◆ SDXC_CQDPT_DPT_SHIFT

#define SDXC_CQDPT_DPT_SHIFT (0U)

◆ SDXC_CQDQS_DQS_GET

#define SDXC_CQDQS_DQS_GET ( x ) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT)

◆ SDXC_CQDQS_DQS_MASK

#define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL)

◆ SDXC_CQDQS_DQS_SET

#define SDXC_CQDQS_DQS_SET ( x ) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK)

◆ SDXC_CQDQS_DQS_SHIFT

#define SDXC_CQDQS_DQS_SHIFT (0U)

◆ SDXC_CQIC_INTC_EN_GET

#define SDXC_CQIC_INTC_EN_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT)

◆ SDXC_CQIC_INTC_EN_MASK

#define SDXC_CQIC_INTC_EN_MASK (0x80000000UL)

◆ SDXC_CQIC_INTC_EN_SET

#define SDXC_CQIC_INTC_EN_SET ( x ) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK)

◆ SDXC_CQIC_INTC_EN_SHIFT

#define SDXC_CQIC_INTC_EN_SHIFT (31U)

◆ SDXC_CQIC_INTC_RST_GET

#define SDXC_CQIC_INTC_RST_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT)

◆ SDXC_CQIC_INTC_RST_MASK

#define SDXC_CQIC_INTC_RST_MASK (0x10000UL)

◆ SDXC_CQIC_INTC_RST_SET

#define SDXC_CQIC_INTC_RST_SET ( x ) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK)

◆ SDXC_CQIC_INTC_RST_SHIFT

#define SDXC_CQIC_INTC_RST_SHIFT (16U)

◆ SDXC_CQIC_INTC_STAT_GET

#define SDXC_CQIC_INTC_STAT_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT)

◆ SDXC_CQIC_INTC_STAT_MASK

#define SDXC_CQIC_INTC_STAT_MASK (0x100000UL)

◆ SDXC_CQIC_INTC_STAT_SHIFT

#define SDXC_CQIC_INTC_STAT_SHIFT (20U)

◆ SDXC_CQIC_INTC_TH_GET

#define SDXC_CQIC_INTC_TH_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT)

◆ SDXC_CQIC_INTC_TH_MASK

#define SDXC_CQIC_INTC_TH_MASK (0x1F00U)

◆ SDXC_CQIC_INTC_TH_SET

#define SDXC_CQIC_INTC_TH_SET ( x ) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK)

◆ SDXC_CQIC_INTC_TH_SHIFT

#define SDXC_CQIC_INTC_TH_SHIFT (8U)

◆ SDXC_CQIC_INTC_TH_WEN_GET

#define SDXC_CQIC_INTC_TH_WEN_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT)

◆ SDXC_CQIC_INTC_TH_WEN_MASK

#define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U)

◆ SDXC_CQIC_INTC_TH_WEN_SET

#define SDXC_CQIC_INTC_TH_WEN_SET ( x ) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK)

◆ SDXC_CQIC_INTC_TH_WEN_SHIFT

#define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U)

◆ SDXC_CQIC_TOUT_VAL_GET

#define SDXC_CQIC_TOUT_VAL_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT)

◆ SDXC_CQIC_TOUT_VAL_MASK

#define SDXC_CQIC_TOUT_VAL_MASK (0x7FU)

◆ SDXC_CQIC_TOUT_VAL_SET

#define SDXC_CQIC_TOUT_VAL_SET ( x ) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK)

◆ SDXC_CQIC_TOUT_VAL_SHIFT

#define SDXC_CQIC_TOUT_VAL_SHIFT (0U)

◆ SDXC_CQIC_TOUT_VAL_WEN_GET

#define SDXC_CQIC_TOUT_VAL_WEN_GET ( x ) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT)

◆ SDXC_CQIC_TOUT_VAL_WEN_MASK

#define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U)

◆ SDXC_CQIC_TOUT_VAL_WEN_SET

#define SDXC_CQIC_TOUT_VAL_WEN_SET ( x ) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK)

◆ SDXC_CQIC_TOUT_VAL_WEN_SHIFT

#define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U)

◆ SDXC_CQIS_HAC_GET

#define SDXC_CQIS_HAC_GET ( x ) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT)

◆ SDXC_CQIS_HAC_MASK

#define SDXC_CQIS_HAC_MASK (0x1U)

◆ SDXC_CQIS_HAC_SET

#define SDXC_CQIS_HAC_SET ( x ) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK)

◆ SDXC_CQIS_HAC_SHIFT

#define SDXC_CQIS_HAC_SHIFT (0U)

◆ SDXC_CQIS_RED_GET

#define SDXC_CQIS_RED_GET ( x ) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT)

◆ SDXC_CQIS_RED_MASK

#define SDXC_CQIS_RED_MASK (0x4U)

◆ SDXC_CQIS_RED_SET

#define SDXC_CQIS_RED_SET ( x ) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK)

◆ SDXC_CQIS_RED_SHIFT

#define SDXC_CQIS_RED_SHIFT (2U)

◆ SDXC_CQIS_TCC_GET

#define SDXC_CQIS_TCC_GET ( x ) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT)

◆ SDXC_CQIS_TCC_MASK

#define SDXC_CQIS_TCC_MASK (0x2U)

◆ SDXC_CQIS_TCC_SET

#define SDXC_CQIS_TCC_SET ( x ) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK)

◆ SDXC_CQIS_TCC_SHIFT

#define SDXC_CQIS_TCC_SHIFT (1U)

◆ SDXC_CQIS_TCL_GET

#define SDXC_CQIS_TCL_GET ( x ) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT)

◆ SDXC_CQIS_TCL_MASK

#define SDXC_CQIS_TCL_MASK (0x8U)

◆ SDXC_CQIS_TCL_SET

#define SDXC_CQIS_TCL_SET ( x ) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK)

◆ SDXC_CQIS_TCL_SHIFT

#define SDXC_CQIS_TCL_SHIFT (3U)

◆ SDXC_CQISE_HAC_STE_GET

#define SDXC_CQISE_HAC_STE_GET ( x ) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT)

◆ SDXC_CQISE_HAC_STE_MASK

#define SDXC_CQISE_HAC_STE_MASK (0x1U)

◆ SDXC_CQISE_HAC_STE_SET

#define SDXC_CQISE_HAC_STE_SET ( x ) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK)

◆ SDXC_CQISE_HAC_STE_SHIFT

#define SDXC_CQISE_HAC_STE_SHIFT (0U)

◆ SDXC_CQISE_RED_STE_GET

#define SDXC_CQISE_RED_STE_GET ( x ) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT)

◆ SDXC_CQISE_RED_STE_MASK

#define SDXC_CQISE_RED_STE_MASK (0x4U)

◆ SDXC_CQISE_RED_STE_SET

#define SDXC_CQISE_RED_STE_SET ( x ) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK)

◆ SDXC_CQISE_RED_STE_SHIFT

#define SDXC_CQISE_RED_STE_SHIFT (2U)

◆ SDXC_CQISE_TCC_STE_GET

#define SDXC_CQISE_TCC_STE_GET ( x ) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT)

◆ SDXC_CQISE_TCC_STE_MASK

#define SDXC_CQISE_TCC_STE_MASK (0x2U)

◆ SDXC_CQISE_TCC_STE_SET

#define SDXC_CQISE_TCC_STE_SET ( x ) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK)

◆ SDXC_CQISE_TCC_STE_SHIFT

#define SDXC_CQISE_TCC_STE_SHIFT (1U)

◆ SDXC_CQISE_TCL_STE_GET

#define SDXC_CQISE_TCL_STE_GET ( x ) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT)

◆ SDXC_CQISE_TCL_STE_MASK

#define SDXC_CQISE_TCL_STE_MASK (0x8U)

◆ SDXC_CQISE_TCL_STE_SET

#define SDXC_CQISE_TCL_STE_SET ( x ) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK)

◆ SDXC_CQISE_TCL_STE_SHIFT

#define SDXC_CQISE_TCL_STE_SHIFT (3U)

◆ SDXC_CQISGE_HAC_SGE_GET

#define SDXC_CQISGE_HAC_SGE_GET ( x ) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT)

◆ SDXC_CQISGE_HAC_SGE_MASK

#define SDXC_CQISGE_HAC_SGE_MASK (0x1U)

◆ SDXC_CQISGE_HAC_SGE_SET

#define SDXC_CQISGE_HAC_SGE_SET ( x ) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK)

◆ SDXC_CQISGE_HAC_SGE_SHIFT

#define SDXC_CQISGE_HAC_SGE_SHIFT (0U)

◆ SDXC_CQISGE_RED_SGE_GET

#define SDXC_CQISGE_RED_SGE_GET ( x ) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT)

◆ SDXC_CQISGE_RED_SGE_MASK

#define SDXC_CQISGE_RED_SGE_MASK (0x4U)

◆ SDXC_CQISGE_RED_SGE_SET

#define SDXC_CQISGE_RED_SGE_SET ( x ) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK)

◆ SDXC_CQISGE_RED_SGE_SHIFT

#define SDXC_CQISGE_RED_SGE_SHIFT (2U)

◆ SDXC_CQISGE_TCC_SGE_GET

#define SDXC_CQISGE_TCC_SGE_GET ( x ) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT)

◆ SDXC_CQISGE_TCC_SGE_MASK

#define SDXC_CQISGE_TCC_SGE_MASK (0x2U)

◆ SDXC_CQISGE_TCC_SGE_SET

#define SDXC_CQISGE_TCC_SGE_SET ( x ) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK)

◆ SDXC_CQISGE_TCC_SGE_SHIFT

#define SDXC_CQISGE_TCC_SGE_SHIFT (1U)

◆ SDXC_CQISGE_TCL_SGE_GET

#define SDXC_CQISGE_TCL_SGE_GET ( x ) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT)

◆ SDXC_CQISGE_TCL_SGE_MASK

#define SDXC_CQISGE_TCL_SGE_MASK (0x8U)

◆ SDXC_CQISGE_TCL_SGE_SET

#define SDXC_CQISGE_TCL_SGE_SET ( x ) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK)

◆ SDXC_CQISGE_TCL_SGE_SHIFT

#define SDXC_CQISGE_TCL_SGE_SHIFT (3U)

◆ SDXC_CQRMEM_RESP_ERR_MASK_GET

#define SDXC_CQRMEM_RESP_ERR_MASK_GET ( x ) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT)

◆ SDXC_CQRMEM_RESP_ERR_MASK_MASK

#define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL)

◆ SDXC_CQRMEM_RESP_ERR_MASK_SET

#define SDXC_CQRMEM_RESP_ERR_MASK_SET ( x ) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK)

◆ SDXC_CQRMEM_RESP_ERR_MASK_SHIFT

#define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U)

◆ SDXC_CQSSC1_SQSCMD_BLK_CNT_GET

#define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET ( x ) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT)

◆ SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK

#define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL)

◆ SDXC_CQSSC1_SQSCMD_BLK_CNT_SET

#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET ( x ) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK)

◆ SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT

#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U)

◆ SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET

#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET ( x ) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT)

◆ SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK

#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU)

◆ SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET

#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET ( x ) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK)

◆ SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT

#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U)

◆ SDXC_CQSSC2_SQSCMD_RCA_GET

#define SDXC_CQSSC2_SQSCMD_RCA_GET ( x ) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT)

◆ SDXC_CQSSC2_SQSCMD_RCA_MASK

#define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU)

◆ SDXC_CQSSC2_SQSCMD_RCA_SET

#define SDXC_CQSSC2_SQSCMD_RCA_SET ( x ) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK)

◆ SDXC_CQSSC2_SQSCMD_RCA_SHIFT

#define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U)

◆ SDXC_CQTCLR_TCLR_GET

#define SDXC_CQTCLR_TCLR_GET ( x ) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT)

◆ SDXC_CQTCLR_TCLR_MASK

#define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL)

◆ SDXC_CQTCLR_TCLR_SET

#define SDXC_CQTCLR_TCLR_SET ( x ) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK)

◆ SDXC_CQTCLR_TCLR_SHIFT

#define SDXC_CQTCLR_TCLR_SHIFT (0U)

◆ SDXC_CQTCN_TCN_GET

#define SDXC_CQTCN_TCN_GET ( x ) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT)

◆ SDXC_CQTCN_TCN_MASK

#define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL)

◆ SDXC_CQTCN_TCN_SET

#define SDXC_CQTCN_TCN_SET ( x ) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK)

◆ SDXC_CQTCN_TCN_SHIFT

#define SDXC_CQTCN_TCN_SHIFT (0U)

◆ SDXC_CQTDBR_DBR_GET

#define SDXC_CQTDBR_DBR_GET ( x ) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT)

◆ SDXC_CQTDBR_DBR_MASK

#define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL)

◆ SDXC_CQTDBR_DBR_SET

#define SDXC_CQTDBR_DBR_SET ( x ) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK)

◆ SDXC_CQTDBR_DBR_SHIFT

#define SDXC_CQTDBR_DBR_SHIFT (0U)

◆ SDXC_CQTDLBA_TDLBA_GET

#define SDXC_CQTDLBA_TDLBA_GET ( x ) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT)

◆ SDXC_CQTDLBA_TDLBA_MASK

#define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL)

◆ SDXC_CQTDLBA_TDLBA_SET

#define SDXC_CQTDLBA_TDLBA_SET ( x ) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK)

◆ SDXC_CQTDLBA_TDLBA_SHIFT

#define SDXC_CQTDLBA_TDLBA_SHIFT (0U)

◆ SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET

#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET ( x ) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT)

◆ SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK

#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU)

◆ SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT

#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U)

◆ SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET

#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET ( x ) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT)

◆ SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK

#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U)

◆ SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT

#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U)

◆ SDXC_CQTERRI_RESP_ERR_TASKID_GET

#define SDXC_CQTERRI_RESP_ERR_TASKID_GET ( x ) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT)

◆ SDXC_CQTERRI_RESP_ERR_TASKID_MASK

#define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U)

◆ SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT

#define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U)

◆ SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET

#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET ( x ) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT)

◆ SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK

#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL)

◆ SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT

#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U)

◆ SDXC_CQTERRI_TRANS_ERR_TASKID_GET

#define SDXC_CQTERRI_TRANS_ERR_TASKID_GET ( x ) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT)

◆ SDXC_CQTERRI_TRANS_ERR_TASKID_MASK

#define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL)

◆ SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT

#define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U)

◆ SDXC_CQVER_EMMC_VER_MAHOR_GET

#define SDXC_CQVER_EMMC_VER_MAHOR_GET ( x ) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT)

◆ SDXC_CQVER_EMMC_VER_MAHOR_MASK

#define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U)

◆ SDXC_CQVER_EMMC_VER_MAHOR_SHIFT

#define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U)

◆ SDXC_CQVER_EMMC_VER_MINOR_GET

#define SDXC_CQVER_EMMC_VER_MINOR_GET ( x ) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT)

◆ SDXC_CQVER_EMMC_VER_MINOR_MASK

#define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U)

◆ SDXC_CQVER_EMMC_VER_MINOR_SHIFT

#define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U)

◆ SDXC_CQVER_EMMC_VER_SUFFIX_GET

#define SDXC_CQVER_EMMC_VER_SUFFIX_GET ( x ) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT)

◆ SDXC_CQVER_EMMC_VER_SUFFIX_MASK

#define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU)

◆ SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT

#define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET ( x ) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET ( x ) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET ( x ) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU)

◆ SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT

#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U)

◆ SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET

#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET ( x ) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT)

◆ SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK

#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU)

◆ SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT

#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET

#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK

#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET

#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT

#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET

#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK

#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET

#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK)

◆ SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT

#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U)

◆ SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET

#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK

#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U)

◆ SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET

#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK)

◆ SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT

#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U)

◆ SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET

#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK

#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U)

◆ SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET

#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK)

◆ SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT

#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U)

◆ SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET

#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK

#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U)

◆ SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET

#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK)

◆ SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT

#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U)

◆ SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET

#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK

#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U)

◆ SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET

#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK)

◆ SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT

#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK)

◆ SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT

#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U)

◆ SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET

#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK

#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U)

◆ SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET

#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK)

◆ SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT

#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U)

◆ SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET

#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK

#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL)

◆ SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET

#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK)

◆ SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT

#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U)

◆ SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET

#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET ( x ) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT)

◆ SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK

#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL)

◆ SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET

#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET ( x ) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK)

◆ SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT

#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U)

◆ SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL)

◆ SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U)

◆ SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL)

◆ SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U)

◆ SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL)

◆ SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U)

◆ SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL)

◆ SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U)

◆ SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL)

◆ SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U)

◆ SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET

#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK

#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)

◆ SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET

#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK)

◆ SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT

#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)

◆ SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL)

◆ SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U)

◆ SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL)

◆ SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U)

◆ SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL)

◆ SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U)

◆ SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL)

◆ SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U)

◆ SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL)

◆ SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U)

◆ SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL)

◆ SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U)

◆ SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET

#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET ( x ) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT)

◆ SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK

#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL)

◆ SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET

#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET ( x ) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK)

◆ SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT

#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U)

◆ SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL)

◆ SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U)

◆ SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL)

◆ SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U)

◆ SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U)

◆ SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U)

◆ SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL)

◆ SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U)

◆ SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U)

◆ SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U)

◆ SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U)

◆ SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U)

◆ SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U)

◆ SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U)

◆ SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U)

◆ SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U)

◆ SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U)

◆ SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U)

◆ SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U)

◆ SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U)

◆ SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL)

◆ SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U)

◆ SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL)

◆ SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U)

◆ SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL)

◆ SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U)

◆ SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL)

◆ SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U)

◆ SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U)

◆ SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U)

◆ SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL)

◆ SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U)

◆ SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL)

◆ SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U)

◆ SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL)

◆ SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U)

◆ SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL)

◆ SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U)

◆ SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U)

◆ SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U)

◆ SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U)

◆ SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U)

◆ SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U)

◆ SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U)

◆ SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL)

◆ SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U)

◆ SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL)

◆ SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U)

◆ SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET

#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT)

◆ SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK

#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U)

◆ SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET

#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK)

◆ SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT

#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U)

◆ SDXC_INT_STAT_ADMA_ERR_GET

#define SDXC_INT_STAT_ADMA_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT)

◆ SDXC_INT_STAT_ADMA_ERR_MASK

#define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL)

◆ SDXC_INT_STAT_ADMA_ERR_SET

#define SDXC_INT_STAT_ADMA_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK)

◆ SDXC_INT_STAT_ADMA_ERR_SHIFT

#define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U)

◆ SDXC_INT_STAT_AUTO_CMD_ERR_GET

#define SDXC_INT_STAT_AUTO_CMD_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT)

◆ SDXC_INT_STAT_AUTO_CMD_ERR_MASK

#define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL)

◆ SDXC_INT_STAT_AUTO_CMD_ERR_SET

#define SDXC_INT_STAT_AUTO_CMD_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK)

◆ SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT

#define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U)

◆ SDXC_INT_STAT_BGAP_EVENT_GET

#define SDXC_INT_STAT_BGAP_EVENT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT)

◆ SDXC_INT_STAT_BGAP_EVENT_MASK

#define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U)

◆ SDXC_INT_STAT_BGAP_EVENT_SET

#define SDXC_INT_STAT_BGAP_EVENT_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK)

◆ SDXC_INT_STAT_BGAP_EVENT_SHIFT

#define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U)

◆ SDXC_INT_STAT_BOOT_ACK_ERR_GET

#define SDXC_INT_STAT_BOOT_ACK_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT)

◆ SDXC_INT_STAT_BOOT_ACK_ERR_MASK

#define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL)

◆ SDXC_INT_STAT_BOOT_ACK_ERR_SET

#define SDXC_INT_STAT_BOOT_ACK_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK)

◆ SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT

#define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U)

◆ SDXC_INT_STAT_BUF_RD_READY_GET

#define SDXC_INT_STAT_BUF_RD_READY_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT)

◆ SDXC_INT_STAT_BUF_RD_READY_MASK

#define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U)

◆ SDXC_INT_STAT_BUF_RD_READY_SET

#define SDXC_INT_STAT_BUF_RD_READY_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK)

◆ SDXC_INT_STAT_BUF_RD_READY_SHIFT

#define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U)

◆ SDXC_INT_STAT_BUF_WR_READY_GET

#define SDXC_INT_STAT_BUF_WR_READY_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT)

◆ SDXC_INT_STAT_BUF_WR_READY_MASK

#define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U)

◆ SDXC_INT_STAT_BUF_WR_READY_SET

#define SDXC_INT_STAT_BUF_WR_READY_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK)

◆ SDXC_INT_STAT_BUF_WR_READY_SHIFT

#define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U)

◆ SDXC_INT_STAT_CARD_INSERTION_GET

#define SDXC_INT_STAT_CARD_INSERTION_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT)

◆ SDXC_INT_STAT_CARD_INSERTION_MASK

#define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U)

◆ SDXC_INT_STAT_CARD_INSERTION_SET

#define SDXC_INT_STAT_CARD_INSERTION_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK)

◆ SDXC_INT_STAT_CARD_INSERTION_SHIFT

#define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U)

◆ SDXC_INT_STAT_CARD_INTERRUPT_GET

#define SDXC_INT_STAT_CARD_INTERRUPT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT)

◆ SDXC_INT_STAT_CARD_INTERRUPT_MASK

#define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U)

◆ SDXC_INT_STAT_CARD_INTERRUPT_SHIFT

#define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U)

◆ SDXC_INT_STAT_CARD_REMOVAL_GET

#define SDXC_INT_STAT_CARD_REMOVAL_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT)

◆ SDXC_INT_STAT_CARD_REMOVAL_MASK

#define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U)

◆ SDXC_INT_STAT_CARD_REMOVAL_SET

#define SDXC_INT_STAT_CARD_REMOVAL_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK)

◆ SDXC_INT_STAT_CARD_REMOVAL_SHIFT

#define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U)

◆ SDXC_INT_STAT_CMD_COMPLETE_GET

#define SDXC_INT_STAT_CMD_COMPLETE_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT)

◆ SDXC_INT_STAT_CMD_COMPLETE_MASK

#define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U)

◆ SDXC_INT_STAT_CMD_COMPLETE_SET

#define SDXC_INT_STAT_CMD_COMPLETE_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK)

◆ SDXC_INT_STAT_CMD_COMPLETE_SHIFT

#define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U)

◆ SDXC_INT_STAT_CMD_CRC_ERR_GET

#define SDXC_INT_STAT_CMD_CRC_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT)

◆ SDXC_INT_STAT_CMD_CRC_ERR_MASK

#define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL)

◆ SDXC_INT_STAT_CMD_CRC_ERR_SET

#define SDXC_INT_STAT_CMD_CRC_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK)

◆ SDXC_INT_STAT_CMD_CRC_ERR_SHIFT

#define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U)

◆ SDXC_INT_STAT_CMD_END_BIT_ERR_GET

#define SDXC_INT_STAT_CMD_END_BIT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT)

◆ SDXC_INT_STAT_CMD_END_BIT_ERR_MASK

#define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL)

◆ SDXC_INT_STAT_CMD_END_BIT_ERR_SET

#define SDXC_INT_STAT_CMD_END_BIT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK)

◆ SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT

#define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U)

◆ SDXC_INT_STAT_CMD_IDX_ERR_GET

#define SDXC_INT_STAT_CMD_IDX_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT)

◆ SDXC_INT_STAT_CMD_IDX_ERR_MASK

#define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL)

◆ SDXC_INT_STAT_CMD_IDX_ERR_SET

#define SDXC_INT_STAT_CMD_IDX_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK)

◆ SDXC_INT_STAT_CMD_IDX_ERR_SHIFT

#define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U)

◆ SDXC_INT_STAT_CMD_TOUT_ERR_GET

#define SDXC_INT_STAT_CMD_TOUT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT)

◆ SDXC_INT_STAT_CMD_TOUT_ERR_MASK

#define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL)

◆ SDXC_INT_STAT_CMD_TOUT_ERR_SET

#define SDXC_INT_STAT_CMD_TOUT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK)

◆ SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT

#define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U)

◆ SDXC_INT_STAT_CQE_EVENT_GET

#define SDXC_INT_STAT_CQE_EVENT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT)

◆ SDXC_INT_STAT_CQE_EVENT_MASK

#define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U)

◆ SDXC_INT_STAT_CQE_EVENT_SET

#define SDXC_INT_STAT_CQE_EVENT_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK)

◆ SDXC_INT_STAT_CQE_EVENT_SHIFT

#define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U)

◆ SDXC_INT_STAT_CUR_LMT_ERR_GET

#define SDXC_INT_STAT_CUR_LMT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT)

◆ SDXC_INT_STAT_CUR_LMT_ERR_MASK

#define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL)

◆ SDXC_INT_STAT_CUR_LMT_ERR_SET

#define SDXC_INT_STAT_CUR_LMT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK)

◆ SDXC_INT_STAT_CUR_LMT_ERR_SHIFT

#define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U)

◆ SDXC_INT_STAT_DATA_CRC_ERR_GET

#define SDXC_INT_STAT_DATA_CRC_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT)

◆ SDXC_INT_STAT_DATA_CRC_ERR_MASK

#define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL)

◆ SDXC_INT_STAT_DATA_CRC_ERR_SET

#define SDXC_INT_STAT_DATA_CRC_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK)

◆ SDXC_INT_STAT_DATA_CRC_ERR_SHIFT

#define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U)

◆ SDXC_INT_STAT_DATA_END_BIT_ERR_GET

#define SDXC_INT_STAT_DATA_END_BIT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT)

◆ SDXC_INT_STAT_DATA_END_BIT_ERR_MASK

#define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL)

◆ SDXC_INT_STAT_DATA_END_BIT_ERR_SET

#define SDXC_INT_STAT_DATA_END_BIT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK)

◆ SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT

#define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U)

◆ SDXC_INT_STAT_DATA_TOUT_ERR_GET

#define SDXC_INT_STAT_DATA_TOUT_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT)

◆ SDXC_INT_STAT_DATA_TOUT_ERR_MASK

#define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL)

◆ SDXC_INT_STAT_DATA_TOUT_ERR_SET

#define SDXC_INT_STAT_DATA_TOUT_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK)

◆ SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT

#define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U)

◆ SDXC_INT_STAT_DMA_INTERRUPT_GET

#define SDXC_INT_STAT_DMA_INTERRUPT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT)

◆ SDXC_INT_STAT_DMA_INTERRUPT_MASK

#define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U)

◆ SDXC_INT_STAT_DMA_INTERRUPT_SET

#define SDXC_INT_STAT_DMA_INTERRUPT_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK)

◆ SDXC_INT_STAT_DMA_INTERRUPT_SHIFT

#define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U)

◆ SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL)

◆ SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U)

◆ SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL)

◆ SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U)

◆ SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET

#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK

#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U)

◆ SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET

#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U)

◆ SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL)

◆ SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U)

◆ SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET

#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK

#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U)

◆ SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET

#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U)

◆ SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET

#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK

#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U)

◆ SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET

#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U)

◆ SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET

#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U)

◆ SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET

#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U)

◆ SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET

#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U)

◆ SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET

#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U)

◆ SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET

#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U)

◆ SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET

#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U)

◆ SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET

#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U)

◆ SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET

#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U)

◆ SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL)

◆ SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U)

◆ SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL)

◆ SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U)

◆ SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL)

◆ SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U)

◆ SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL)

◆ SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U)

◆ SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET

#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U)

◆ SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET

#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U)

◆ SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL)

◆ SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U)

◆ SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL)

◆ SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U)

◆ SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL)

◆ SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U)

◆ SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL)

◆ SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U)

◆ SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET

#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK

#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U)

◆ SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET

#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U)

◆ SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET

#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK

#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U)

◆ SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET

#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U)

◆ SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET

#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK

#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U)

◆ SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET

#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U)

◆ SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL)

◆ SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U)

◆ SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET

#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK

#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL)

◆ SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET

#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U)

◆ SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET

#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT)

◆ SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK

#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U)

◆ SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET

#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK)

◆ SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT

#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U)

◆ SDXC_INT_STAT_ERR_INTERRUPT_GET

#define SDXC_INT_STAT_ERR_INTERRUPT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT)

◆ SDXC_INT_STAT_ERR_INTERRUPT_MASK

#define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U)

◆ SDXC_INT_STAT_ERR_INTERRUPT_SHIFT

#define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U)

◆ SDXC_INT_STAT_FX_EVENT_GET

#define SDXC_INT_STAT_FX_EVENT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT)

◆ SDXC_INT_STAT_FX_EVENT_MASK

#define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U)

◆ SDXC_INT_STAT_FX_EVENT_SHIFT

#define SDXC_INT_STAT_FX_EVENT_SHIFT (13U)

◆ SDXC_INT_STAT_RE_TUNE_EVENT_GET

#define SDXC_INT_STAT_RE_TUNE_EVENT_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT)

◆ SDXC_INT_STAT_RE_TUNE_EVENT_MASK

#define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U)

◆ SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT

#define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U)

◆ SDXC_INT_STAT_RESP_ERR_GET

#define SDXC_INT_STAT_RESP_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT)

◆ SDXC_INT_STAT_RESP_ERR_MASK

#define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL)

◆ SDXC_INT_STAT_RESP_ERR_SET

#define SDXC_INT_STAT_RESP_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK)

◆ SDXC_INT_STAT_RESP_ERR_SHIFT

#define SDXC_INT_STAT_RESP_ERR_SHIFT (27U)

◆ SDXC_INT_STAT_TUNING_ERR_GET

#define SDXC_INT_STAT_TUNING_ERR_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT)

◆ SDXC_INT_STAT_TUNING_ERR_MASK

#define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL)

◆ SDXC_INT_STAT_TUNING_ERR_SET

#define SDXC_INT_STAT_TUNING_ERR_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK)

◆ SDXC_INT_STAT_TUNING_ERR_SHIFT

#define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U)

◆ SDXC_INT_STAT_XFER_COMPLETE_GET

#define SDXC_INT_STAT_XFER_COMPLETE_GET ( x ) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT)

◆ SDXC_INT_STAT_XFER_COMPLETE_MASK

#define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U)

◆ SDXC_INT_STAT_XFER_COMPLETE_SET

#define SDXC_INT_STAT_XFER_COMPLETE_SET ( x ) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK)

◆ SDXC_INT_STAT_XFER_COMPLETE_SHIFT

#define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U)

◆ SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET

#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) >> SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT)

◆ SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK

#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL)

◆ SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET

#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK)

◆ SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT

#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_GET

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_SET

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK)

◆ SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT

#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U)

◆ SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET

#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT)

◆ SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK

#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL)

◆ SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET

#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK)

◆ SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT

#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U)

◆ SDXC_MISC_CTRL0_TMCLK_EN_GET

#define SDXC_MISC_CTRL0_TMCLK_EN_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) >> SDXC_MISC_CTRL0_TMCLK_EN_SHIFT)

◆ SDXC_MISC_CTRL0_TMCLK_EN_MASK

#define SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U)

◆ SDXC_MISC_CTRL0_TMCLK_EN_SET

#define SDXC_MISC_CTRL0_TMCLK_EN_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) & SDXC_MISC_CTRL0_TMCLK_EN_MASK)

◆ SDXC_MISC_CTRL0_TMCLK_EN_SHIFT

#define SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_GET

#define SDXC_MISC_CTRL1_CARD_ACTIVE_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_MASK

#define SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET

#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK

#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET

#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT

#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_SET

#define SDXC_MISC_CTRL1_CARD_ACTIVE_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)

◆ SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT

#define SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U)

◆ SDXC_MISC_CTRL1_CARDCLK_DLYSEL_GET

#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) >> SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT)

◆ SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK

#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK (0x3F00000UL)

◆ SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET

#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK)

◆ SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT

#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT (20U)

◆ SDXC_MISC_CTRL1_STROBE_DLYSEL_GET

#define SDXC_MISC_CTRL1_STROBE_DLYSEL_GET ( x ) (((uint32_t)(x) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) >> SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT)

◆ SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK

#define SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK (0x3F000UL)

◆ SDXC_MISC_CTRL1_STROBE_DLYSEL_SET

#define SDXC_MISC_CTRL1_STROBE_DLYSEL_SET ( x ) (((uint32_t)(x) << SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK)

◆ SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT

#define SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT (12U)

◆ SDXC_MSHC_VER_ID_VER_ID_GET

#define SDXC_MSHC_VER_ID_VER_ID_GET ( x ) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT)

◆ SDXC_MSHC_VER_ID_VER_ID_MASK

#define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL)

◆ SDXC_MSHC_VER_ID_VER_ID_SHIFT

#define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U)

◆ SDXC_MSHC_VER_TYPE_VER_TYPE_GET

#define SDXC_MSHC_VER_TYPE_VER_TYPE_GET ( x ) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT)

◆ SDXC_MSHC_VER_TYPE_VER_TYPE_MASK

#define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL)

◆ SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT

#define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U)

◆ SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET

#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET ( x ) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT)

◆ SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK

#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU)

◆ SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT

#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U)

◆ SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET

#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET ( x ) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)

◆ SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK

#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU)

◆ SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT

#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)

◆ SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET

#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET ( x ) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)

◆ SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK

#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU)

◆ SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT

#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)

◆ SDXC_PRESET_CLK_GEN_SEL_VAL_GET

#define SDXC_PRESET_CLK_GEN_SEL_VAL_GET ( x ) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT)

◆ SDXC_PRESET_CLK_GEN_SEL_VAL_MASK

#define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U)

◆ SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT

#define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U)

◆ SDXC_PRESET_DDR50

#define SDXC_PRESET_DDR50 (7UL)

◆ SDXC_PRESET_DS

#define SDXC_PRESET_DS (1UL)

◆ SDXC_PRESET_FREQ_SEL_VAL_GET

#define SDXC_PRESET_FREQ_SEL_VAL_GET ( x ) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT)

◆ SDXC_PRESET_FREQ_SEL_VAL_MASK

#define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU)

◆ SDXC_PRESET_FREQ_SEL_VAL_SHIFT

#define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U)

◆ SDXC_PRESET_HS

#define SDXC_PRESET_HS (2UL)

◆ SDXC_PRESET_INIT

#define SDXC_PRESET_INIT (0UL)

◆ SDXC_PRESET_SDR104

#define SDXC_PRESET_SDR104 (6UL)

◆ SDXC_PRESET_SDR12

#define SDXC_PRESET_SDR12 (3UL)

◆ SDXC_PRESET_SDR25

#define SDXC_PRESET_SDR25 (4UL)

◆ SDXC_PRESET_SDR50

#define SDXC_PRESET_SDR50 (5UL)

◆ SDXC_PRESET_UHS2

#define SDXC_PRESET_UHS2 (10UL)

◆ SDXC_PROT_CTRL_CARD_INSERT_GET

#define SDXC_PROT_CTRL_CARD_INSERT_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT)

◆ SDXC_PROT_CTRL_CARD_INSERT_MASK

#define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL)

◆ SDXC_PROT_CTRL_CARD_INSERT_SET

#define SDXC_PROT_CTRL_CARD_INSERT_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK)

◆ SDXC_PROT_CTRL_CARD_INSERT_SHIFT

#define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U)

◆ SDXC_PROT_CTRL_CARD_INT_GET

#define SDXC_PROT_CTRL_CARD_INT_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT)

◆ SDXC_PROT_CTRL_CARD_INT_MASK

#define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL)

◆ SDXC_PROT_CTRL_CARD_INT_SET

#define SDXC_PROT_CTRL_CARD_INT_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK)

◆ SDXC_PROT_CTRL_CARD_INT_SHIFT

#define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U)

◆ SDXC_PROT_CTRL_CARD_REMOVAL_GET

#define SDXC_PROT_CTRL_CARD_REMOVAL_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT)

◆ SDXC_PROT_CTRL_CARD_REMOVAL_MASK

#define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL)

◆ SDXC_PROT_CTRL_CARD_REMOVAL_SET

#define SDXC_PROT_CTRL_CARD_REMOVAL_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK)

◆ SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT

#define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U)

◆ SDXC_PROT_CTRL_CONTINUE_REQ_GET

#define SDXC_PROT_CTRL_CONTINUE_REQ_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT)

◆ SDXC_PROT_CTRL_CONTINUE_REQ_MASK

#define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL)

◆ SDXC_PROT_CTRL_CONTINUE_REQ_SET

#define SDXC_PROT_CTRL_CONTINUE_REQ_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK)

◆ SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT

#define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U)

◆ SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET

#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT)

◆ SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK

#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U)

◆ SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET

#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK)

◆ SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT

#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U)

◆ SDXC_PROT_CTRL_DMA_SEL_GET

#define SDXC_PROT_CTRL_DMA_SEL_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT)

◆ SDXC_PROT_CTRL_DMA_SEL_MASK

#define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U)

◆ SDXC_PROT_CTRL_DMA_SEL_SET

#define SDXC_PROT_CTRL_DMA_SEL_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK)

◆ SDXC_PROT_CTRL_DMA_SEL_SHIFT

#define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U)

◆ SDXC_PROT_CTRL_EXT_DAT_XFER_GET

#define SDXC_PROT_CTRL_EXT_DAT_XFER_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT)

◆ SDXC_PROT_CTRL_EXT_DAT_XFER_MASK

#define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U)

◆ SDXC_PROT_CTRL_EXT_DAT_XFER_SET

#define SDXC_PROT_CTRL_EXT_DAT_XFER_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK)

◆ SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT

#define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U)

◆ SDXC_PROT_CTRL_HIGH_SPEED_EN_GET

#define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT)

◆ SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK

#define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U)

◆ SDXC_PROT_CTRL_HIGH_SPEED_EN_SET

#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK)

◆ SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT

#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U)

◆ SDXC_PROT_CTRL_INT_AT_BGAP_GET

#define SDXC_PROT_CTRL_INT_AT_BGAP_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT)

◆ SDXC_PROT_CTRL_INT_AT_BGAP_MASK

#define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL)

◆ SDXC_PROT_CTRL_INT_AT_BGAP_SET

#define SDXC_PROT_CTRL_INT_AT_BGAP_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK)

◆ SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT

#define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U)

◆ SDXC_PROT_CTRL_RD_WAIT_CTRL_GET

#define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT)

◆ SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK

#define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL)

◆ SDXC_PROT_CTRL_RD_WAIT_CTRL_SET

#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK)

◆ SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT

#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U)

◆ SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET

#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT)

◆ SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK

#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U)

◆ SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET

#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK)

◆ SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT

#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U)

◆ SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET

#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT)

◆ SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK

#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U)

◆ SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET

#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK)

◆ SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT

#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U)

◆ SDXC_PROT_CTRL_STOP_BG_REQ_GET

#define SDXC_PROT_CTRL_STOP_BG_REQ_GET ( x ) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT)

◆ SDXC_PROT_CTRL_STOP_BG_REQ_MASK

#define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL)

◆ SDXC_PROT_CTRL_STOP_BG_REQ_SET

#define SDXC_PROT_CTRL_STOP_BG_REQ_SET ( x ) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK)

◆ SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT

#define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U)

◆ SDXC_PSTATE_BUF_RD_ENABLE_GET

#define SDXC_PSTATE_BUF_RD_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT)

◆ SDXC_PSTATE_BUF_RD_ENABLE_MASK

#define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U)

◆ SDXC_PSTATE_BUF_RD_ENABLE_SHIFT

#define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U)

◆ SDXC_PSTATE_BUF_WR_ENABLE_GET

#define SDXC_PSTATE_BUF_WR_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT)

◆ SDXC_PSTATE_BUF_WR_ENABLE_MASK

#define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U)

◆ SDXC_PSTATE_BUF_WR_ENABLE_SHIFT

#define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U)

◆ SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET

#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT)

◆ SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK

#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL)

◆ SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT

#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U)

◆ SDXC_PSTATE_CARD_INSERTED_GET

#define SDXC_PSTATE_CARD_INSERTED_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT)

◆ SDXC_PSTATE_CARD_INSERTED_MASK

#define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL)

◆ SDXC_PSTATE_CARD_INSERTED_SHIFT

#define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U)

◆ SDXC_PSTATE_CARD_STABLE_GET

#define SDXC_PSTATE_CARD_STABLE_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT)

◆ SDXC_PSTATE_CARD_STABLE_MASK

#define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL)

◆ SDXC_PSTATE_CARD_STABLE_SHIFT

#define SDXC_PSTATE_CARD_STABLE_SHIFT (17U)

◆ SDXC_PSTATE_CMD_INHIBIT_GET

#define SDXC_PSTATE_CMD_INHIBIT_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT)

◆ SDXC_PSTATE_CMD_INHIBIT_MASK

#define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U)

◆ SDXC_PSTATE_CMD_INHIBIT_SHIFT

#define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U)

◆ SDXC_PSTATE_CMD_ISSUE_ERR_GET

#define SDXC_PSTATE_CMD_ISSUE_ERR_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT)

◆ SDXC_PSTATE_CMD_ISSUE_ERR_MASK

#define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL)

◆ SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT

#define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U)

◆ SDXC_PSTATE_CMD_LINE_LVL_GET

#define SDXC_PSTATE_CMD_LINE_LVL_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT)

◆ SDXC_PSTATE_CMD_LINE_LVL_MASK

#define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL)

◆ SDXC_PSTATE_CMD_LINE_LVL_SHIFT

#define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U)

◆ SDXC_PSTATE_DAT_3_0_GET

#define SDXC_PSTATE_DAT_3_0_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT)

◆ SDXC_PSTATE_DAT_3_0_MASK

#define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL)

◆ SDXC_PSTATE_DAT_3_0_SHIFT

#define SDXC_PSTATE_DAT_3_0_SHIFT (20U)

◆ SDXC_PSTATE_DAT_7_4_GET

#define SDXC_PSTATE_DAT_7_4_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT)

◆ SDXC_PSTATE_DAT_7_4_MASK

#define SDXC_PSTATE_DAT_7_4_MASK (0xF0U)

◆ SDXC_PSTATE_DAT_7_4_SHIFT

#define SDXC_PSTATE_DAT_7_4_SHIFT (4U)

◆ SDXC_PSTATE_DAT_INHIBIT_GET

#define SDXC_PSTATE_DAT_INHIBIT_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT)

◆ SDXC_PSTATE_DAT_INHIBIT_MASK

#define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U)

◆ SDXC_PSTATE_DAT_INHIBIT_SHIFT

#define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U)

◆ SDXC_PSTATE_DAT_LINE_ACTIVE_GET

#define SDXC_PSTATE_DAT_LINE_ACTIVE_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT)

◆ SDXC_PSTATE_DAT_LINE_ACTIVE_MASK

#define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U)

◆ SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT

#define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U)

◆ SDXC_PSTATE_RD_XFER_ACTIVE_GET

#define SDXC_PSTATE_RD_XFER_ACTIVE_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT)

◆ SDXC_PSTATE_RD_XFER_ACTIVE_MASK

#define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U)

◆ SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT

#define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U)

◆ SDXC_PSTATE_RE_TUNE_REQ_GET

#define SDXC_PSTATE_RE_TUNE_REQ_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT)

◆ SDXC_PSTATE_RE_TUNE_REQ_MASK

#define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U)

◆ SDXC_PSTATE_RE_TUNE_REQ_SHIFT

#define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U)

◆ SDXC_PSTATE_SUB_CMD_STAT_GET

#define SDXC_PSTATE_SUB_CMD_STAT_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT)

◆ SDXC_PSTATE_SUB_CMD_STAT_MASK

#define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL)

◆ SDXC_PSTATE_SUB_CMD_STAT_SHIFT

#define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U)

◆ SDXC_PSTATE_WR_PROTECT_SW_LVL_GET

#define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT)

◆ SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK

#define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL)

◆ SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT

#define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U)

◆ SDXC_PSTATE_WR_XFER_ACTIVE_GET

#define SDXC_PSTATE_WR_XFER_ACTIVE_GET ( x ) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT)

◆ SDXC_PSTATE_WR_XFER_ACTIVE_MASK

#define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U)

◆ SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT

#define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U)

◆ SDXC_RESP_RESP01

#define SDXC_RESP_RESP01 (0UL)

◆ SDXC_RESP_RESP01_GET

#define SDXC_RESP_RESP01_GET ( x ) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT)

◆ SDXC_RESP_RESP01_MASK

#define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL)

◆ SDXC_RESP_RESP01_SHIFT

#define SDXC_RESP_RESP01_SHIFT (0U)

◆ SDXC_RESP_RESP23

#define SDXC_RESP_RESP23 (1UL)

◆ SDXC_RESP_RESP45

#define SDXC_RESP_RESP45 (2UL)

◆ SDXC_RESP_RESP67

#define SDXC_RESP_RESP67 (3UL)

◆ SDXC_SDMASA_BLOCKCNT_SDMASA_GET

#define SDXC_SDMASA_BLOCKCNT_SDMASA_GET ( x ) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT)

◆ SDXC_SDMASA_BLOCKCNT_SDMASA_MASK

#define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL)

◆ SDXC_SDMASA_BLOCKCNT_SDMASA_SET

#define SDXC_SDMASA_BLOCKCNT_SDMASA_SET ( x ) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK)

◆ SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT

#define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U)

◆ SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET

#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET ( x ) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT)

◆ SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK

#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU)

◆ SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT

#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U)

◆ SDXC_SYS_CTRL_CLK_GEN_SELECT_GET

#define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT)

◆ SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK

#define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U)

◆ SDXC_SYS_CTRL_CLK_GEN_SELECT_SET

#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK)

◆ SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT

#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U)

◆ SDXC_SYS_CTRL_FREQ_SEL_GET

#define SDXC_SYS_CTRL_FREQ_SEL_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT)

◆ SDXC_SYS_CTRL_FREQ_SEL_MASK

#define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U)

◆ SDXC_SYS_CTRL_FREQ_SEL_SET

#define SDXC_SYS_CTRL_FREQ_SEL_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK)

◆ SDXC_SYS_CTRL_FREQ_SEL_SHIFT

#define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET

#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK

#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET

#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT

#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET

#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK

#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET

#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)

◆ SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT

#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U)

◆ SDXC_SYS_CTRL_PLL_ENABLE_GET

#define SDXC_SYS_CTRL_PLL_ENABLE_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT)

◆ SDXC_SYS_CTRL_PLL_ENABLE_MASK

#define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U)

◆ SDXC_SYS_CTRL_PLL_ENABLE_SET

#define SDXC_SYS_CTRL_PLL_ENABLE_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK)

◆ SDXC_SYS_CTRL_PLL_ENABLE_SHIFT

#define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U)

◆ SDXC_SYS_CTRL_SD_CLK_EN_GET

#define SDXC_SYS_CTRL_SD_CLK_EN_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT)

◆ SDXC_SYS_CTRL_SD_CLK_EN_MASK

#define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U)

◆ SDXC_SYS_CTRL_SD_CLK_EN_SET

#define SDXC_SYS_CTRL_SD_CLK_EN_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK)

◆ SDXC_SYS_CTRL_SD_CLK_EN_SHIFT

#define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U)

◆ SDXC_SYS_CTRL_SW_RST_ALL_GET

#define SDXC_SYS_CTRL_SW_RST_ALL_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT)

◆ SDXC_SYS_CTRL_SW_RST_ALL_MASK

#define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL)

◆ SDXC_SYS_CTRL_SW_RST_ALL_SET

#define SDXC_SYS_CTRL_SW_RST_ALL_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK)

◆ SDXC_SYS_CTRL_SW_RST_ALL_SHIFT

#define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U)

◆ SDXC_SYS_CTRL_SW_RST_CMD_GET

#define SDXC_SYS_CTRL_SW_RST_CMD_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT)

◆ SDXC_SYS_CTRL_SW_RST_CMD_MASK

#define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL)

◆ SDXC_SYS_CTRL_SW_RST_CMD_SET

#define SDXC_SYS_CTRL_SW_RST_CMD_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK)

◆ SDXC_SYS_CTRL_SW_RST_CMD_SHIFT

#define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U)

◆ SDXC_SYS_CTRL_SW_RST_DAT_GET

#define SDXC_SYS_CTRL_SW_RST_DAT_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT)

◆ SDXC_SYS_CTRL_SW_RST_DAT_MASK

#define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL)

◆ SDXC_SYS_CTRL_SW_RST_DAT_SET

#define SDXC_SYS_CTRL_SW_RST_DAT_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK)

◆ SDXC_SYS_CTRL_SW_RST_DAT_SHIFT

#define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U)

◆ SDXC_SYS_CTRL_TOUT_CNT_GET

#define SDXC_SYS_CTRL_TOUT_CNT_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT)

◆ SDXC_SYS_CTRL_TOUT_CNT_MASK

#define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL)

◆ SDXC_SYS_CTRL_TOUT_CNT_SET

#define SDXC_SYS_CTRL_TOUT_CNT_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK)

◆ SDXC_SYS_CTRL_TOUT_CNT_SHIFT

#define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U)

◆ SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET

#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET ( x ) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT)

◆ SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK

#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U)

◆ SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET

#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET ( x ) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK)

◆ SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT

#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U)

Data Structures

Macros