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| #define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA03_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA05_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA07_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PA07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PA08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA08_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA08_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA08_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA09_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA09_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA09_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA09_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA09_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA10_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA10_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PA10_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA10_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA10_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA10_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA11_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA11_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PA11_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA11_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PA11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA11_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA11_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA11_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA11_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA12_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PA12_FUNC_CTL_ESC0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA12_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA12_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PA12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA12_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA12_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA12_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA13_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PA13_FUNC_CTL_ESC0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA13_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA13_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PA13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA13_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA13_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA14_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA14_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PA14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA14_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA14_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA14_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA15_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA15_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PA15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA15_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA15_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA16_FUNC_CTL_ESC0_P0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA16_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA16_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA16_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA16_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA17_FUNC_CTL_ESC0_P0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA17_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA17_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA17_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA17_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA18_FUNC_CTL_ESC0_P0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA18_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA18_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA18_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA18_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA19_FUNC_CTL_ESC0_P0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA19_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA19_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA19_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA19_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA20_FUNC_CTL_ESC0_P0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA20_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA20_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA20_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA20_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA21_FUNC_CTL_ESC0_P0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA21_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA21_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA21_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA21_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA21_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA22_FUNC_CTL_ESC0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA22_FUNC_CTL_ETH0_TXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA22_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA22_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA22_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA22_FUNC_CTL_TSW0_P2_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA23_FUNC_CTL_ESC0_P0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA23_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA23_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA23_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PA23_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA23_FUNC_CTL_TSW0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA24_FUNC_CTL_ESC0_P0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA24_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA24_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA24_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA24_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA25_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PA25_FUNC_CTL_ESC0_P0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA25_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA25_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA25_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA25_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA26_FUNC_CTL_ESC0_P0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA26_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA26_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA26_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA26_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA27_FUNC_CTL_ESC0_P0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA27_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA27_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA27_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA28_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PA28_FUNC_CTL_ESC0_P0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA28_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA28_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA29_FUNC_CTL_ESC0_P0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PA29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA29_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA29_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PA30_FUNC_CTL_ESC0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA30_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA30_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA30_FUNC_CTL_TSW0_P1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PA31_FUNC_CTL_ESC0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PA31_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PA31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PA31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PA31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PA31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PA31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PA31_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PA31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PA31_FUNC_CTL_TSW0_P1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB00_FUNC_CTL_ESC0_P0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB00_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB00_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB00_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB00_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB00_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB01_FUNC_CTL_ESC0_P0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB01_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB01_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB01_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB01_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB01_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB01_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB02_FUNC_CTL_ESC0_P0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB02_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB02_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB02_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB02_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB02_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB02_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB02_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB03_FUNC_CTL_ESC0_P0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB03_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB03_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB03_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB03_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB03_FUNC_CTL_SPI4_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB03_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB04_FUNC_CTL_ESC0_P0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB04_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB04_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB04_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB04_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB04_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB04_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB05_FUNC_CTL_ESC0_P0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB05_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB05_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB05_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB05_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB05_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB05_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB06_FUNC_CTL_ESC0_P0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB06_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB06_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB06_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB06_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB06_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB07_FUNC_CTL_ESC0_P0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB07_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB07_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB07_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB07_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB07_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB08_FUNC_CTL_ESC0_P0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB08_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB08_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB08_FUNC_CTL_SPI4_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB08_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB09_FUNC_CTL_ESC0_P0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB09_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB09_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB09_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB09_FUNC_CTL_SPI4_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB09_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB10_FUNC_CTL_ESC0_P0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB10_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB10_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB10_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB10_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB11_FUNC_CTL_ESC0_P0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB11_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB11_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PB11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB11_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB11_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB12_FUNC_CTL_ESC0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB12_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB12_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB12_FUNC_CTL_TSW0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB13_FUNC_CTL_ESC0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB13_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB13_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB13_FUNC_CTL_TSW0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB14_FUNC_CTL_ESC0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB14_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB14_FUNC_CTL_SPI4_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB14_FUNC_CTL_TSW0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB15_FUNC_CTL_ESC0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB15_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB15_FUNC_CTL_SPI4_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB15_FUNC_CTL_TSW0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB16_FUNC_CTL_ESC0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB16_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB16_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB16_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB16_FUNC_CTL_TSW0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB17_FUNC_CTL_ESC0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB17_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB17_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB17_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB17_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB17_FUNC_CTL_TSW0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB18_FUNC_CTL_ESC0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB18_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB18_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB18_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB18_FUNC_CTL_TSW0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB19_FUNC_CTL_ESC0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB19_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB19_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB19_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB19_FUNC_CTL_SPI7_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB19_FUNC_CTL_TSW0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB20_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB20_FUNC_CTL_ESC0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB20_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB20_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB20_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB20_FUNC_CTL_SPI6_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB20_FUNC_CTL_TSW0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB21_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB21_FUNC_CTL_ESC0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB21_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB21_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB21_FUNC_CTL_SPI6_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB21_FUNC_CTL_TSW0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB22_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB22_FUNC_CTL_ESC0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB22_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB22_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB22_FUNC_CTL_SPI6_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB22_FUNC_CTL_TSW0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB23_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PB23_FUNC_CTL_ESC0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB23_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB23_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PB23_FUNC_CTL_SPI6_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB23_FUNC_CTL_TSW0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PB23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB24_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB24_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PB24_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB24_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB24_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB24_FUNC_CTL_SPI7_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB24_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PB24_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB25_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB25_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PB25_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB25_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB25_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB25_FUNC_CTL_SPI7_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB25_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PB25_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB26_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB26_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PB26_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB26_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB26_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB26_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PB26_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB26_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB26_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB27_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB27_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB27_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB27_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PB27_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB27_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB28_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB28_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB28_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB28_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB28_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB28_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB29_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PB29_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PB29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB29_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB29_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB29_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB29_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PB29_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB29_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PB29_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB30_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB30_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB30_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB30_FUNC_CTL_SPI7_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB30_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB30_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PB31_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PB31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PB31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PB31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PB31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PB31_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PB31_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PB31_FUNC_CTL_SPI7_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PB31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PB31_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PB31_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PB31_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC00_FUNC_CTL_ESC0_GPI_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC00_FUNC_CTL_ESC0_GPI_63 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC00_FUNC_CTL_ESC0_GPO_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC00_FUNC_CTL_FEMC_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC00_FUNC_CTL_PPI0_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC00_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC01_FUNC_CTL_ESC0_GPI_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC01_FUNC_CTL_ESC0_GPI_62 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC01_FUNC_CTL_ESC0_GPO_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC01_FUNC_CTL_FEMC_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC01_FUNC_CTL_PPI0_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC01_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC02_FUNC_CTL_ESC0_GPI_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC02_FUNC_CTL_ESC0_GPI_61 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC02_FUNC_CTL_ESC0_GPO_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC02_FUNC_CTL_FEMC_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC02_FUNC_CTL_PPI0_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC02_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC02_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC03_FUNC_CTL_ESC0_GPI_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC03_FUNC_CTL_ESC0_GPI_60 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC03_FUNC_CTL_ESC0_GPO_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC03_FUNC_CTL_FEMC_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC03_FUNC_CTL_PPI0_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC03_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC03_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC04_FUNC_CTL_ESC0_GPI_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC04_FUNC_CTL_ESC0_GPI_59 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC04_FUNC_CTL_ESC0_GPO_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC04_FUNC_CTL_FEMC_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC04_FUNC_CTL_PPI0_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC04_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC04_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC05_FUNC_CTL_ESC0_GPI_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC05_FUNC_CTL_ESC0_GPI_58 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC05_FUNC_CTL_ESC0_GPO_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC05_FUNC_CTL_FEMC_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC05_FUNC_CTL_PPI0_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC05_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC05_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC06_FUNC_CTL_ESC0_GPI_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC06_FUNC_CTL_ESC0_GPI_57 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC06_FUNC_CTL_ESC0_GPO_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC06_FUNC_CTL_FEMC_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC06_FUNC_CTL_PPI0_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC06_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC07_FUNC_CTL_ESC0_GPI_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC07_FUNC_CTL_ESC0_GPI_56 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC07_FUNC_CTL_ESC0_GPO_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC07_FUNC_CTL_FEMC_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC07_FUNC_CTL_PPI0_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC08_FUNC_CTL_ESC0_GPI_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC08_FUNC_CTL_ESC0_GPI_55 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC08_FUNC_CTL_ESC0_GPO_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC08_FUNC_CTL_FEMC_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC08_FUNC_CTL_PPI0_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC08_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC08_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC09_FUNC_CTL_ESC0_GPI_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC09_FUNC_CTL_ESC0_GPI_54 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC09_FUNC_CTL_ESC0_GPO_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC09_FUNC_CTL_FEMC_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC09_FUNC_CTL_PPI0_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC09_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC09_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC09_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC10_FUNC_CTL_ESC0_GPI_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC10_FUNC_CTL_ESC0_GPI_53 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC10_FUNC_CTL_ESC0_GPO_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC10_FUNC_CTL_FEMC_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC10_FUNC_CTL_PPI0_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC10_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC10_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC10_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC11_FUNC_CTL_ESC0_GPI_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC11_FUNC_CTL_ESC0_GPI_52 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC11_FUNC_CTL_ESC0_GPO_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC11_FUNC_CTL_FEMC_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC11_FUNC_CTL_PPI0_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC11_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC11_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC11_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC12_FUNC_CTL_ESC0_GPI_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC12_FUNC_CTL_ESC0_GPI_51 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC12_FUNC_CTL_ESC0_GPO_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC12_FUNC_CTL_FEMC_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC12_FUNC_CTL_PPI0_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC12_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC12_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC12_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC13_FUNC_CTL_ESC0_GPI_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC13_FUNC_CTL_ESC0_GPI_50 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC13_FUNC_CTL_ESC0_GPO_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC13_FUNC_CTL_FEMC_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC13_FUNC_CTL_PPI0_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC13_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC13_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC13_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC13_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC13_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC14_FUNC_CTL_ESC0_GPI_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC14_FUNC_CTL_ESC0_GPI_49 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC14_FUNC_CTL_ESC0_GPO_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC14_FUNC_CTL_FEMC_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC14_FUNC_CTL_PPI0_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC14_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC14_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC14_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC14_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC15_FUNC_CTL_ESC0_GPI_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC15_FUNC_CTL_ESC0_GPI_48 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC15_FUNC_CTL_ESC0_GPO_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC15_FUNC_CTL_FEMC_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC15_FUNC_CTL_PPI0_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC15_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC15_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC15_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC15_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC16_FUNC_CTL_ESC0_GPI_47 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC16_FUNC_CTL_ESC0_GPO_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC16_FUNC_CTL_FEMC_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC16_FUNC_CTL_PPI0_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC16_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC16_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PC17_FUNC_CTL_ESC0_GPI_46 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC17_FUNC_CTL_ESC0_GPO_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC17_FUNC_CTL_FEMC_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC17_FUNC_CTL_PPI0_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC17_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PC17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC18_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC18_FUNC_CTL_ESC0_GPI_45 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC18_FUNC_CTL_ESC0_GPO_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC18_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC18_FUNC_CTL_PPI0_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC19_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC19_FUNC_CTL_ESC0_GPI_44 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC19_FUNC_CTL_ESC0_GPO_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC19_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC19_FUNC_CTL_PPI0_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC19_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC20_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC20_FUNC_CTL_ESC0_GPI_43 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC20_FUNC_CTL_ESC0_GPO_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC20_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC20_FUNC_CTL_PPI0_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC20_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC21_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC21_FUNC_CTL_ESC0_GPI_42 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC21_FUNC_CTL_ESC0_GPO_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC21_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC21_FUNC_CTL_PPI0_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC21_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC21_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC21_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC22_FUNC_CTL_ESC0_GPI_41 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC22_FUNC_CTL_ESC0_GPO_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC22_FUNC_CTL_FEMC_SRDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC22_FUNC_CTL_PPI0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC22_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC22_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC22_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC23_FUNC_CTL_ESC0_GPI_40 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC23_FUNC_CTL_ESC0_GPO_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC23_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC23_FUNC_CTL_PPI0_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC23_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC23_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC23_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC24_FUNC_CTL_ESC0_GPI_39 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC24_FUNC_CTL_ESC0_GPO_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC24_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC24_FUNC_CTL_PPI0_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC24_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC25_FUNC_CTL_ESC0_GPI_38 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC25_FUNC_CTL_ESC0_GPO_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC25_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC25_FUNC_CTL_PPI0_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC25_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC26_FUNC_CTL_ESC0_GPI_37 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC26_FUNC_CTL_ESC0_GPO_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC26_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC26_FUNC_CTL_PPI0_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC26_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC27_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC27_FUNC_CTL_ESC0_GPI_36 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC27_FUNC_CTL_ESC0_GPO_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC27_FUNC_CTL_FEMC_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC27_FUNC_CTL_PPI0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC27_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC28_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC28_FUNC_CTL_ESC0_GPI_35 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC28_FUNC_CTL_ESC0_GPO_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC28_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC28_FUNC_CTL_PPI0_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC28_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC29_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC29_FUNC_CTL_ESC0_GPI_34 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC29_FUNC_CTL_ESC0_GPO_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC29_FUNC_CTL_FEMC_SCLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PC29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC29_FUNC_CTL_PPI0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC29_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PC29_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PC30_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC30_FUNC_CTL_ESC0_GPI_33 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC30_FUNC_CTL_ESC0_GPO_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC30_FUNC_CTL_FEMC_SCS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC30_FUNC_CTL_PPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC30_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PC30_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PC31_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PC31_FUNC_CTL_ESC0_GPI_32 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PC31_FUNC_CTL_ESC0_GPO_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PC31_FUNC_CTL_FEMC_SCS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PC31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PC31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PC31_FUNC_CTL_PPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PC31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PC31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PC31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PC31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PC31_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PC31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PC31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD00_FUNC_CTL_ESC0_GPI_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD00_FUNC_CTL_ESC0_GPO_32 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD00_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD00_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD00_FUNC_CTL_PPI0_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD01_FUNC_CTL_ESC0_GPI_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD01_FUNC_CTL_ESC0_GPO_33 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD01_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD01_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD01_FUNC_CTL_PPI0_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD02_FUNC_CTL_ESC0_GPI_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD02_FUNC_CTL_ESC0_GPO_34 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD02_FUNC_CTL_ESC0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD02_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD02_FUNC_CTL_PPI0_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD03_FUNC_CTL_ESC0_GPI_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD03_FUNC_CTL_ESC0_GPO_35 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD03_FUNC_CTL_ESC0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD03_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD03_FUNC_CTL_PPI0_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD03_FUNC_CTL_SPI5_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD04_FUNC_CTL_ESC0_GPI_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD04_FUNC_CTL_ESC0_GPO_36 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD04_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD04_FUNC_CTL_PPI0_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD04_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD05_FUNC_CTL_ESC0_GPI_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD05_FUNC_CTL_ESC0_GPO_37 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD05_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD05_FUNC_CTL_PPI0_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD05_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD06_FUNC_CTL_ESC0_GPI_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD06_FUNC_CTL_ESC0_GPO_38 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD06_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD06_FUNC_CTL_PPI0_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD06_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD07_FUNC_CTL_ESC0_GPI_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD07_FUNC_CTL_ESC0_GPO_39 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD07_FUNC_CTL_FEMC_SCLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD07_FUNC_CTL_PPI0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD07_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD08_FUNC_CTL_ESC0_GPI_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD08_FUNC_CTL_ESC0_GPO_40 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD08_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD08_FUNC_CTL_PPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD08_FUNC_CTL_SPI5_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD09_FUNC_CTL_ESC0_GPI_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD09_FUNC_CTL_ESC0_GPO_41 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD09_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD09_FUNC_CTL_SPI5_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD10_FUNC_CTL_ESC0_GPI_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD10_FUNC_CTL_ESC0_GPO_42 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD10_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD10_FUNC_CTL_PPI0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD10_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD11_FUNC_CTL_ESC0_GPI_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD11_FUNC_CTL_ESC0_GPO_43 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD11_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD11_FUNC_CTL_PPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD11_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD12_FUNC_CTL_ESC0_GPI_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD12_FUNC_CTL_ESC0_GPO_44 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD12_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD12_FUNC_CTL_PPI0_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD12_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD12_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD13_FUNC_CTL_ESC0_GPI_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD13_FUNC_CTL_ESC0_GPO_45 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD13_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD13_FUNC_CTL_PPI0_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD13_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD13_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD13_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD14_FUNC_CTL_ESC0_GPI_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD14_FUNC_CTL_ESC0_GPO_46 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD14_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD14_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD14_FUNC_CTL_PPI0_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD14_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD14_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD14_FUNC_CTL_SPI5_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD14_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PD14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD15_FUNC_CTL_ESC0_GPI_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD15_FUNC_CTL_ESC0_GPO_47 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD15_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD15_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD15_FUNC_CTL_PPI0_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD15_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD15_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD15_FUNC_CTL_SPI5_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD15_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PD15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD16_FUNC_CTL_ESC0_GPI_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD16_FUNC_CTL_ESC0_GPO_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD16_FUNC_CTL_ESC0_GPO_48 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD16_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD16_FUNC_CTL_PPI0_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD16_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PD16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD17_FUNC_CTL_ESC0_GPI_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD17_FUNC_CTL_ESC0_GPO_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD17_FUNC_CTL_ESC0_GPO_49 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD17_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD17_FUNC_CTL_PPI0_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PD17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD18_FUNC_CTL_ESC0_GPI_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD18_FUNC_CTL_ESC0_GPO_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD18_FUNC_CTL_ESC0_GPO_50 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD18_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD18_FUNC_CTL_PPI0_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD19_FUNC_CTL_ESC0_GPI_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD19_FUNC_CTL_ESC0_GPO_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD19_FUNC_CTL_ESC0_GPO_51 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD19_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD19_FUNC_CTL_PPI0_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD19_FUNC_CTL_SPI6_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD20_FUNC_CTL_ESC0_GPI_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD20_FUNC_CTL_ESC0_GPO_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD20_FUNC_CTL_ESC0_GPO_52 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD20_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD20_FUNC_CTL_PPI0_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD20_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD20_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD21_FUNC_CTL_ESC0_GPI_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD21_FUNC_CTL_ESC0_GPO_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD21_FUNC_CTL_ESC0_GPO_53 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD21_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD21_FUNC_CTL_PPI0_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD21_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD21_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD21_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD22_FUNC_CTL_ESC0_GPI_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD22_FUNC_CTL_ESC0_GPO_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD22_FUNC_CTL_ESC0_GPO_54 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD22_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD22_FUNC_CTL_PPI0_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD22_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD22_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD22_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD23_FUNC_CTL_ESC0_GPI_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD23_FUNC_CTL_ESC0_GPO_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD23_FUNC_CTL_ESC0_GPO_55 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD23_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD23_FUNC_CTL_PPI0_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD23_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD23_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD23_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD24_FUNC_CTL_ESC0_GPI_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD24_FUNC_CTL_ESC0_GPO_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD24_FUNC_CTL_ESC0_GPO_56 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD24_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD24_FUNC_CTL_PPI0_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD24_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD24_FUNC_CTL_SPI6_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD24_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD25_FUNC_CTL_ESC0_GPI_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD25_FUNC_CTL_ESC0_GPO_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD25_FUNC_CTL_ESC0_GPO_57 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD25_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD25_FUNC_CTL_PPI0_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD25_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD25_FUNC_CTL_SPI6_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD25_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD26_FUNC_CTL_ESC0_GPI_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD26_FUNC_CTL_ESC0_GPO_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD26_FUNC_CTL_ESC0_GPO_58 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD26_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD26_FUNC_CTL_PPI0_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD26_FUNC_CTL_SPI6_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD26_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD26_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD27_FUNC_CTL_ESC0_GPI_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD27_FUNC_CTL_ESC0_GPO_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD27_FUNC_CTL_ESC0_GPO_59 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD27_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD27_FUNC_CTL_PPI0_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD27_FUNC_CTL_SPI6_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD27_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD28_FUNC_CTL_ESC0_GPI_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD28_FUNC_CTL_ESC0_GPO_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD28_FUNC_CTL_ESC0_GPO_60 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD28_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD28_FUNC_CTL_PPI0_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD28_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD28_FUNC_CTL_SPI6_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD28_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD29_FUNC_CTL_ESC0_GPI_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD29_FUNC_CTL_ESC0_GPO_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD29_FUNC_CTL_ESC0_GPO_61 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD29_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PD29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD29_FUNC_CTL_PPI0_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD29_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD29_FUNC_CTL_SPI6_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD29_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD29_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PD30_FUNC_CTL_ESC0_GPI_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD30_FUNC_CTL_ESC0_GPO_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD30_FUNC_CTL_ESC0_GPO_62 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD30_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD30_FUNC_CTL_PPI0_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD30_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD30_FUNC_CTL_SPI6_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD30_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PD31_FUNC_CTL_ESC0_GPI_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PD31_FUNC_CTL_ESC0_GPO_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PD31_FUNC_CTL_ESC0_GPO_63 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PD31_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PD31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PD31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PD31_FUNC_CTL_PPI0_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PD31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PD31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PD31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PD31_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PD31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PD31_FUNC_CTL_SPI6_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PD31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PD31_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE00_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE00_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PE00_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE00_FUNC_CTL_PPI0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PE00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE00_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE00_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE00_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE00_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE00_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PE00_FUNC_CTL_TSW0_P1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PE01_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PE01_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE01_FUNC_CTL_PPI0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PE01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE01_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE01_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE01_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE01_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE01_FUNC_CTL_TSW0_P1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE02_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PE02_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE02_FUNC_CTL_PPI0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PE02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE02_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE02_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE02_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE03_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE03_FUNC_CTL_PPI0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) |
| #define IOC_PE03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE03_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE03_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE03_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE03_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE03_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PE03_FUNC_CTL_TSW0_P2_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE03_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PE04_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PE04_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE04_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PE04_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE04_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE04_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE04_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PE04_FUNC_CTL_TSW0_P2_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE05_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PE05_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE05_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE05_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE05_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PE05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE06_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PE06_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE06_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE06_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE06_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE06_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PE06_FUNC_CTL_TSW0_P3_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE06_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PE07_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE07_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PE07_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE07_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE07_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PE07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE07_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PE07_FUNC_CTL_TSW0_P3_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE08_FUNC_CTL_ESC0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE08_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE08_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE08_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE09_FUNC_CTL_ESC0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE09_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE09_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE09_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE10_FUNC_CTL_ESC0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE10_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE10_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE11_FUNC_CTL_ESC0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE11_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE11_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE11_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE12_FUNC_CTL_ESC0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE12_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE12_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE13_FUNC_CTL_ESC0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE13_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE14_FUNC_CTL_ESC0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE14_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE14_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE15_FUNC_CTL_ESC0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE15_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE15_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE16_FUNC_CTL_ESC0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE16_FUNC_CTL_GPIO_E_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE16_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE16_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE16_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE16_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE17_FUNC_CTL_ESC0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE17_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE17_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE17_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE17_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE18_FUNC_CTL_ESC0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE18_FUNC_CTL_GPIO_E_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE18_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE18_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE18_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE19_FUNC_CTL_ESC0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE19_FUNC_CTL_GPIO_E_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE19_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE19_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE19_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE19_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE20_FUNC_CTL_ESC0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE20_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE20_FUNC_CTL_GPIO_E_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE20_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE20_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE20_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE20_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE20_FUNC_CTL_TSW0_P3_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE21_FUNC_CTL_ESC0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE21_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE21_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE21_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE21_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE21_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE21_FUNC_CTL_TSW0_P3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE22_FUNC_CTL_ESC0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE22_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE22_FUNC_CTL_GPIO_E_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE22_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE22_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE22_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE22_FUNC_CTL_TSW0_P3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE23_FUNC_CTL_ESC0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE23_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE23_FUNC_CTL_GPIO_E_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE23_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE23_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE23_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE23_FUNC_CTL_TSW0_P3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE24_FUNC_CTL_ESC0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE24_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE24_FUNC_CTL_GPIO_E_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE24_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE24_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE24_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE24_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE24_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE24_FUNC_CTL_TSW0_P3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE25_FUNC_CTL_ESC0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE25_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE25_FUNC_CTL_GPIO_E_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE25_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE25_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE25_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE25_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE25_FUNC_CTL_TSW0_P3_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE26_FUNC_CTL_ESC0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE26_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE26_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE26_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE26_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE26_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE26_FUNC_CTL_TSW0_P3_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE27_FUNC_CTL_ESC0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE27_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE27_FUNC_CTL_GPIO_E_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE27_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE27_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE27_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE27_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE27_FUNC_CTL_TSW0_P3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE28_FUNC_CTL_ESC0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE28_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE28_FUNC_CTL_GPIO_E_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE28_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE28_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE28_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE28_FUNC_CTL_TSW0_P3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE29_FUNC_CTL_ESC0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE29_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE29_FUNC_CTL_GPIO_E_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PE29_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE29_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE29_FUNC_CTL_TSW0_P3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PE30_FUNC_CTL_ESC0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE30_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE30_FUNC_CTL_GPIO_E_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE30_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE30_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE30_FUNC_CTL_TSW0_P3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PE31_FUNC_CTL_ESC0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PE31_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PE31_FUNC_CTL_GPIO_E_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PE31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PE31_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) |
| #define IOC_PE31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PE31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PE31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PE31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PE31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PE31_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PE31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PE31_FUNC_CTL_TSW0_P3_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PE31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF00_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PF00_FUNC_CTL_ESC0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF00_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF00_FUNC_CTL_GPIO_F_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF00_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF00_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF00_FUNC_CTL_TSW0_P3_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF01_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PF01_FUNC_CTL_ESC0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF01_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF01_FUNC_CTL_GPIO_F_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF01_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF01_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF01_FUNC_CTL_TSW0_P3_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF02_FUNC_CTL_ESC0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF02_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF02_FUNC_CTL_GPIO_F_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF02_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF02_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF02_FUNC_CTL_TSW0_P3_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF03_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PF03_FUNC_CTL_ESC0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF03_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF03_FUNC_CTL_GPIO_F_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF03_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF03_FUNC_CTL_SPI4_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF03_FUNC_CTL_TSW0_P3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF04_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PF04_FUNC_CTL_ESC0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF04_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF04_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF04_FUNC_CTL_TSW0_P3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF05_FUNC_CTL_ESC0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF05_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF05_FUNC_CTL_GPIO_F_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF05_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF05_FUNC_CTL_TSW0_P3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF06_FUNC_CTL_ESC0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF06_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF06_FUNC_CTL_GPIO_F_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF06_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF06_FUNC_CTL_TSW0_P3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF07_FUNC_CTL_ESC0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF07_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF07_FUNC_CTL_GPIO_F_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF07_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF07_FUNC_CTL_TSW0_P3_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF08_FUNC_CTL_ESC0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF08_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF08_FUNC_CTL_GPIO_F_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF08_FUNC_CTL_SPI4_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF08_FUNC_CTL_TSW0_P3_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF09_FUNC_CTL_ESC0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF09_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF09_FUNC_CTL_GPIO_F_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF09_FUNC_CTL_SPI4_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF09_FUNC_CTL_TSW0_P3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF10_FUNC_CTL_ESC0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF10_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF10_FUNC_CTL_GPIO_F_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF10_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF10_FUNC_CTL_TSW0_P3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF11_FUNC_CTL_ESC0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF11_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF11_FUNC_CTL_GPIO_F_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF11_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF11_FUNC_CTL_TSW0_P3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF12_FUNC_CTL_ESC0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF12_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF12_FUNC_CTL_GPIO_F_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF12_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF12_FUNC_CTL_TSW0_P3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF13_FUNC_CTL_ESC0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF13_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF13_FUNC_CTL_GPIO_F_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF13_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF13_FUNC_CTL_TSW0_P3_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF14_FUNC_CTL_ESC0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF14_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF14_FUNC_CTL_GPIO_F_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF14_FUNC_CTL_SPI4_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF14_FUNC_CTL_TSW0_P3_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF15_FUNC_CTL_ESC0_P2_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PF15_FUNC_CTL_ETH0_TXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PF15_FUNC_CTL_GPIO_F_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) |
| #define IOC_PF15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) |
| #define IOC_PF15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) |
| #define IOC_PF15_FUNC_CTL_SPI4_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF15_FUNC_CTL_TSW0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PF15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF16_FUNC_CTL_GPIO_F_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF16_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF17_FUNC_CTL_GPIO_F_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF17_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF18_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PF18_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PF18_FUNC_CTL_GPIO_F_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF18_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF18_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PF18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF18_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PF19_FUNC_CTL_GPIO_F_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF19_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF19_FUNC_CTL_SPI7_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF19_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PF19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF19_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PF20_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PF20_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PF20_FUNC_CTL_GPIO_F_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF20_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF20_FUNC_CTL_SPI6_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF20_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PF20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF20_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PF21_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PF21_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PF21_FUNC_CTL_GPIO_F_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF21_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF21_FUNC_CTL_SPI6_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF21_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PF21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF21_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PF22_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) |
| #define IOC_PF22_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) |
| #define IOC_PF22_FUNC_CTL_GPIO_F_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF22_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF22_FUNC_CTL_SPI6_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF22_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PF22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF22_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PF23_FUNC_CTL_GPIO_F_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF23_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF23_FUNC_CTL_SPI6_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF23_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PF24_FUNC_CTL_GPIO_F_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF24_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF24_FUNC_CTL_SPI7_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF24_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF25_FUNC_CTL_GPIO_F_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF25_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF25_FUNC_CTL_SPI7_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF25_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF26_FUNC_CTL_GPIO_F_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF26_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF26_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF26_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) |
| #define IOC_PF26_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF26_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF27_FUNC_CTL_GPIO_F_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF27_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF27_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF27_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF28_FUNC_CTL_GPIO_F_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF28_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF28_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF28_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF29_FUNC_CTL_GPIO_F_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PF29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF29_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF29_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF29_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF29_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PF30_FUNC_CTL_GPIO_F_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF30_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF30_FUNC_CTL_SPI7_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF30_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PF31_FUNC_CTL_GPIO_F_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PF31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PF31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PF31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) |
| #define IOC_PF31_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) |
| #define IOC_PF31_FUNC_CTL_SPI7_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PF31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) |
| #define IOC_PF31_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV00_FUNC_CTL_ESC0_P0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV00_FUNC_CTL_GPIO_V_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV00_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV01_FUNC_CTL_ESC0_P0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV01_FUNC_CTL_GPIO_V_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV01_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV02_FUNC_CTL_ESC0_P0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV02_FUNC_CTL_GPIO_V_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV02_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV03_FUNC_CTL_ESC0_P0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV03_FUNC_CTL_GPIO_V_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV03_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV03_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV04_FUNC_CTL_ESC0_P0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV04_FUNC_CTL_GPIO_V_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV04_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV04_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV05_FUNC_CTL_ESC0_P0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV05_FUNC_CTL_GPIO_V_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV05_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV05_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV06_FUNC_CTL_ESC0_P0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV06_FUNC_CTL_GPIO_V_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV06_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV07_FUNC_CTL_ESC0_P0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV07_FUNC_CTL_GPIO_V_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV07_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV08_FUNC_CTL_ESC0_P0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV08_FUNC_CTL_GPIO_V_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV08_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV08_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV09_FUNC_CTL_ESC0_P0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV09_FUNC_CTL_GPIO_V_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV09_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV09_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV10_FUNC_CTL_ESC0_P0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV10_FUNC_CTL_GPIO_V_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV10_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV10_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV11_FUNC_CTL_ESC0_P0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV11_FUNC_CTL_GPIO_V_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV11_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV11_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV12_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV12_FUNC_CTL_GPIO_V_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV12_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV12_FUNC_CTL_TSW0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PV12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV13_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV13_FUNC_CTL_GPIO_V_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PV13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV13_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PV14_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV14_FUNC_CTL_GPIO_V_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV14_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PV15_FUNC_CTL_ESC0_P0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PV15_FUNC_CTL_GPIO_V_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PV15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PV15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PV15_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PV15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW00_FUNC_CTL_ESC0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW00_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW00_FUNC_CTL_GPIO_W_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW00_FUNC_CTL_TSW0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW01_FUNC_CTL_ESC0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW01_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW01_FUNC_CTL_GPIO_W_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW01_FUNC_CTL_TSW0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW02_FUNC_CTL_ESC0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW02_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW02_FUNC_CTL_GPIO_W_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW02_FUNC_CTL_TSW0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW03_FUNC_CTL_ESC0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW03_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW03_FUNC_CTL_GPIO_W_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW03_FUNC_CTL_SPI5_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW03_FUNC_CTL_TSW0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW04_FUNC_CTL_ESC0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW04_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW04_FUNC_CTL_GPIO_W_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW04_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW04_FUNC_CTL_TSW0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW05_FUNC_CTL_ESC0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW05_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW05_FUNC_CTL_GPIO_W_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW05_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW05_FUNC_CTL_TSW0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW06_FUNC_CTL_ESC0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW06_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW06_FUNC_CTL_GPIO_W_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW06_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW06_FUNC_CTL_TSW0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW07_FUNC_CTL_ESC0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW07_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW07_FUNC_CTL_GPIO_W_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW07_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW07_FUNC_CTL_TSW0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW08_FUNC_CTL_ESC0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW08_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW08_FUNC_CTL_GPIO_W_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW08_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PW08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW08_FUNC_CTL_SPI5_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW08_FUNC_CTL_TSW0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW09_FUNC_CTL_ESC0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW09_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW09_FUNC_CTL_GPIO_W_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW09_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PW09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW09_FUNC_CTL_SPI5_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW09_FUNC_CTL_TSW0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW10_FUNC_CTL_ESC0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW10_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW10_FUNC_CTL_GPIO_W_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW10_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW10_FUNC_CTL_TSW0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW11_FUNC_CTL_ESC0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW11_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW11_FUNC_CTL_GPIO_W_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW11_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW11_FUNC_CTL_TSW0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW12_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW12_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW12_FUNC_CTL_GPIO_W_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW12_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PW12_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW12_FUNC_CTL_TSW0_P2_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW13_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW13_FUNC_CTL_ETH0_TXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW13_FUNC_CTL_GPIO_W_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW13_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PW13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW13_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW14_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW14_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW14_FUNC_CTL_GPIO_W_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW14_FUNC_CTL_SPI5_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW15_FUNC_CTL_ESC0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW15_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW15_FUNC_CTL_GPIO_W_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW15_FUNC_CTL_SPI5_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW16_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW16_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW16_FUNC_CTL_GPIO_W_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW16_FUNC_CTL_TSW0_P1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW17_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW17_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) |
| #define IOC_PW17_FUNC_CTL_GPIO_W_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW17_FUNC_CTL_TSW0_P1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW18_FUNC_CTL_ESC0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW18_FUNC_CTL_GPIO_W_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW18_FUNC_CTL_TSW0_P2_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW19_FUNC_CTL_ESC0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW19_FUNC_CTL_GPIO_W_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW19_FUNC_CTL_SPI6_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW19_FUNC_CTL_TSW0_P2_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) |
| #define IOC_PW19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW20_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW20_FUNC_CTL_GPIO_W_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW20_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PW20_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW21_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW21_FUNC_CTL_GPIO_W_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PW21_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) |
| #define IOC_PW21_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PW22_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) |
| #define IOC_PW22_FUNC_CTL_GPIO_W_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW22_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PW23_FUNC_CTL_GPIO_W_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PW23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PW23_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PW23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX00_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX01_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX02_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PX02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PX02_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX03_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PX03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PX03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PX03_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PX04_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PX04_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PX05_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PX05_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX06_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PX06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX06_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PX07_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) |
| #define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PX07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PX07_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PX07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PX07_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) |
| #define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PY02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PY02_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PY03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PY03_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PY04_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PY04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PY05_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PY05_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PY06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PY06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PY07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PY07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PY07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) |
| #define IOC_PY07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PZ00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PZ01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PZ02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PZ02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PZ02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PZ03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PZ03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PZ04_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PZ04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) |
| #define IOC_PZ05_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PZ05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PZ05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) |
| #define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PZ06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PZ06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |
| #define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) |
| #define IOC_PZ07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) |
| #define IOC_PZ07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) |
| #define IOC_PZ07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) |
| #define IOC_PZ07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) |