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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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Go to the source code of this file.
Data Structures | |
| struct | QEIV2_Type |
| #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) |
| #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK (0xFFFFU) |
| #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) |
| #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT (0U) |
| #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) |
| #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK (0xFFFF0000UL) |
| #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) |
| #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT (16U) |
| #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) |
| #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U) |
| #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) |
| #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U) |
| #define QEIV2_ADCX_CFG0_X_ADCSEL_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) |
| #define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U) |
| #define QEIV2_ADCX_CFG0_X_ADCSEL_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) |
| #define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U) |
| #define QEIV2_ADCX_CFG0_X_CHAN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT) |
| #define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU) |
| #define QEIV2_ADCX_CFG0_X_CHAN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK) |
| #define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U) |
| #define QEIV2_ADCX_CFG1_X_PARAM0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) |
| #define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU) |
| #define QEIV2_ADCX_CFG1_X_PARAM0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) |
| #define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U) |
| #define QEIV2_ADCX_CFG1_X_PARAM1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) |
| #define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL) |
| #define QEIV2_ADCX_CFG1_X_PARAM1_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) |
| #define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U) |
| #define QEIV2_ADCX_CFG2_X_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) |
| #define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL) |
| #define QEIV2_ADCX_CFG2_X_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) |
| #define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U) |
| #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) |
| #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U) |
| #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) |
| #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U) |
| #define QEIV2_ADCY_CFG0_Y_ADCSEL_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) |
| #define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U) |
| #define QEIV2_ADCY_CFG0_Y_ADCSEL_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) |
| #define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U) |
| #define QEIV2_ADCY_CFG0_Y_CHAN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) |
| #define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU) |
| #define QEIV2_ADCY_CFG0_Y_CHAN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) |
| #define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U) |
| #define QEIV2_ADCY_CFG1_Y_PARAM0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) |
| #define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU) |
| #define QEIV2_ADCY_CFG1_Y_PARAM0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) |
| #define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U) |
| #define QEIV2_ADCY_CFG1_Y_PARAM1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) |
| #define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL) |
| #define QEIV2_ADCY_CFG1_Y_PARAM1_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) |
| #define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U) |
| #define QEIV2_ADCY_CFG2_Y_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) |
| #define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL) |
| #define QEIV2_ADCY_CFG2_Y_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) |
| #define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U) |
| #define QEIV2_ANGLE_ANGLE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT) |
| #define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL) |
| #define QEIV2_ANGLE_ANGLE_SHIFT (0U) |
| #define QEIV2_CAL_CFG_XY_DELAY_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT) |
| #define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL) |
| #define QEIV2_CAL_CFG_XY_DELAY_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK) |
| #define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U) |
| #define QEIV2_COUNT_CURRENT (0UL) |
| #define QEIV2_COUNT_PH_ASTAT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT) |
| #define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL) |
| #define QEIV2_COUNT_PH_ASTAT_SHIFT (26U) |
| #define QEIV2_COUNT_PH_BSTAT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT) |
| #define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL) |
| #define QEIV2_COUNT_PH_BSTAT_SHIFT (25U) |
| #define QEIV2_COUNT_PH_DIR_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT) |
| #define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL) |
| #define QEIV2_COUNT_PH_DIR_SHIFT (30U) |
| #define QEIV2_COUNT_PH_PHCNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT) |
| #define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) |
| #define QEIV2_COUNT_PH_PHCNT_SHIFT (0U) |
| #define QEIV2_COUNT_READ (1UL) |
| #define QEIV2_COUNT_SNAP0 (2UL) |
| #define QEIV2_COUNT_SNAP1 (3UL) |
| #define QEIV2_COUNT_SPD_ASTAT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT) |
| #define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL) |
| #define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U) |
| #define QEIV2_COUNT_SPD_BSTAT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT) |
| #define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL) |
| #define QEIV2_COUNT_SPD_BSTAT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK) |
| #define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U) |
| #define QEIV2_COUNT_SPD_DIR_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT) |
| #define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL) |
| #define QEIV2_COUNT_SPD_DIR_SHIFT (31U) |
| #define QEIV2_COUNT_SPD_SPDCNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT) |
| #define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) |
| #define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U) |
| #define QEIV2_COUNT_TMR_TMRCNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT) |
| #define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U) |
| #define QEIV2_COUNT_Z_ZCNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT) |
| #define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_COUNT_Z_ZCNT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK) |
| #define QEIV2_COUNT_Z_ZCNT_SHIFT (0U) |
| #define QEIV2_CR_ENCTYP_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT) |
| #define QEIV2_CR_ENCTYP_MASK (0x7U) |
| #define QEIV2_CR_ENCTYP_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK) |
| #define QEIV2_CR_ENCTYP_SHIFT (0U) |
| #define QEIV2_CR_FAULTPOS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT) |
| #define QEIV2_CR_FAULTPOS_MASK (0x40U) |
| #define QEIV2_CR_FAULTPOS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK) |
| #define QEIV2_CR_FAULTPOS_SHIFT (6U) |
| #define QEIV2_CR_H2FDIR0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT) |
| #define QEIV2_CR_H2FDIR0_MASK (0x80000UL) |
| #define QEIV2_CR_H2FDIR0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK) |
| #define QEIV2_CR_H2FDIR0_SHIFT (19U) |
| #define QEIV2_CR_H2FDIR1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT) |
| #define QEIV2_CR_H2FDIR1_MASK (0x40000UL) |
| #define QEIV2_CR_H2FDIR1_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK) |
| #define QEIV2_CR_H2FDIR1_SHIFT (18U) |
| #define QEIV2_CR_H2RDIR0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT) |
| #define QEIV2_CR_H2RDIR0_MASK (0x20000UL) |
| #define QEIV2_CR_H2RDIR0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK) |
| #define QEIV2_CR_H2RDIR0_SHIFT (17U) |
| #define QEIV2_CR_H2RDIR1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT) |
| #define QEIV2_CR_H2RDIR1_MASK (0x10000UL) |
| #define QEIV2_CR_H2RDIR1_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK) |
| #define QEIV2_CR_H2RDIR1_SHIFT (16U) |
| #define QEIV2_CR_HFDIR0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT) |
| #define QEIV2_CR_HFDIR0_MASK (0x800U) |
| #define QEIV2_CR_HFDIR0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK) |
| #define QEIV2_CR_HFDIR0_SHIFT (11U) |
| #define QEIV2_CR_HFDIR1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT) |
| #define QEIV2_CR_HFDIR1_MASK (0x400U) |
| #define QEIV2_CR_HFDIR1_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK) |
| #define QEIV2_CR_HFDIR1_SHIFT (10U) |
| #define QEIV2_CR_HRDIR0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT) |
| #define QEIV2_CR_HRDIR0_MASK (0x200U) |
| #define QEIV2_CR_HRDIR0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK) |
| #define QEIV2_CR_HRDIR0_SHIFT (9U) |
| #define QEIV2_CR_HRDIR1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT) |
| #define QEIV2_CR_HRDIR1_MASK (0x100U) |
| #define QEIV2_CR_HRDIR1_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK) |
| #define QEIV2_CR_HRDIR1_SHIFT (8U) |
| #define QEIV2_CR_PAUSEPH_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT) |
| #define QEIV2_CR_PAUSEPH_MASK (0x2000U) |
| #define QEIV2_CR_PAUSEPH_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK) |
| #define QEIV2_CR_PAUSEPH_SHIFT (13U) |
| #define QEIV2_CR_PAUSEPOS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT) |
| #define QEIV2_CR_PAUSEPOS_MASK (0x8000U) |
| #define QEIV2_CR_PAUSEPOS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK) |
| #define QEIV2_CR_PAUSEPOS_SHIFT (15U) |
| #define QEIV2_CR_PAUSESPD_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT) |
| #define QEIV2_CR_PAUSESPD_MASK (0x4000U) |
| #define QEIV2_CR_PAUSESPD_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK) |
| #define QEIV2_CR_PAUSESPD_SHIFT (14U) |
| #define QEIV2_CR_PAUSEZ_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT) |
| #define QEIV2_CR_PAUSEZ_MASK (0x1000U) |
| #define QEIV2_CR_PAUSEZ_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK) |
| #define QEIV2_CR_PAUSEZ_SHIFT (12U) |
| #define QEIV2_CR_PHCALIZ_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT) |
| #define QEIV2_CR_PHCALIZ_MASK (0x200000UL) |
| #define QEIV2_CR_PHCALIZ_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK) |
| #define QEIV2_CR_PHCALIZ_SHIFT (21U) |
| #define QEIV2_CR_RD_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT) |
| #define QEIV2_CR_RD_SEL_MASK (0x8U) |
| #define QEIV2_CR_RD_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK) |
| #define QEIV2_CR_RD_SEL_SHIFT (3U) |
| #define QEIV2_CR_READ_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT) |
| #define QEIV2_CR_READ_MASK (0x80000000UL) |
| #define QEIV2_CR_READ_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK) |
| #define QEIV2_CR_READ_SHIFT (31U) |
| #define QEIV2_CR_RSTCNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT) |
| #define QEIV2_CR_RSTCNT_MASK (0x10U) |
| #define QEIV2_CR_RSTCNT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK) |
| #define QEIV2_CR_RSTCNT_SHIFT (4U) |
| #define QEIV2_CR_SNAPEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT) |
| #define QEIV2_CR_SNAPEN_MASK (0x20U) |
| #define QEIV2_CR_SNAPEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK) |
| #define QEIV2_CR_SNAPEN_SHIFT (5U) |
| #define QEIV2_CR_Z_ONLY_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT) |
| #define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL) |
| #define QEIV2_CR_Z_ONLY_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK) |
| #define QEIV2_CR_Z_ONLY_EN_SHIFT (20U) |
| #define QEIV2_CR_ZCNTCFG_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT) |
| #define QEIV2_CR_ZCNTCFG_MASK (0x400000UL) |
| #define QEIV2_CR_ZCNTCFG_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK) |
| #define QEIV2_CR_ZCNTCFG_SHIFT (22U) |
| #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT) |
| #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U) |
| #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) |
| #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) |
| #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U) |
| #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT) |
| #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U) |
| #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT) |
| #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U) |
| #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT) |
| #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U) |
| #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT) |
| #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U) |
| #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) |
| #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) |
| #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U) |
| #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT) |
| #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U) |
| #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT) |
| #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U) |
| #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT) |
| #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U) |
| #define QEIV2_DMAEN_CYCLE0FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT) |
| #define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL) |
| #define QEIV2_DMAEN_CYCLE0FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK) |
| #define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U) |
| #define QEIV2_DMAEN_CYCLE1FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT) |
| #define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL) |
| #define QEIV2_DMAEN_CYCLE1FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK) |
| #define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U) |
| #define QEIV2_DMAEN_DIRCHGFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT) |
| #define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL) |
| #define QEIV2_DMAEN_DIRCHGFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK) |
| #define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U) |
| #define QEIV2_DMAEN_FAULTFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT) |
| #define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL) |
| #define QEIV2_DMAEN_FAULTFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK) |
| #define QEIV2_DMAEN_FAULTFEN_SHIFT (18U) |
| #define QEIV2_DMAEN_HOME2FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT) |
| #define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL) |
| #define QEIV2_DMAEN_HOME2FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK) |
| #define QEIV2_DMAEN_HOME2FEN_SHIFT (19U) |
| #define QEIV2_DMAEN_HOMEFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT) |
| #define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL) |
| #define QEIV2_DMAEN_HOMEFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK) |
| #define QEIV2_DMAEN_HOMEFEN_SHIFT (30U) |
| #define QEIV2_DMAEN_POS2CMPFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT) |
| #define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL) |
| #define QEIV2_DMAEN_POS2CMPFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK) |
| #define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U) |
| #define QEIV2_DMAEN_POSCMPFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT) |
| #define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL) |
| #define QEIV2_DMAEN_POSCMPFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK) |
| #define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U) |
| #define QEIV2_DMAEN_PULSE0FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT) |
| #define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL) |
| #define QEIV2_DMAEN_PULSE0FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK) |
| #define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U) |
| #define QEIV2_DMAEN_PULSE1FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT) |
| #define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL) |
| #define QEIV2_DMAEN_PULSE1FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK) |
| #define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U) |
| #define QEIV2_DMAEN_WDGFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT) |
| #define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL) |
| #define QEIV2_DMAEN_WDGFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK) |
| #define QEIV2_DMAEN_WDGFEN_SHIFT (31U) |
| #define QEIV2_DMAEN_WIDTHTMFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT) |
| #define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL) |
| #define QEIV2_DMAEN_WIDTHTMFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK) |
| #define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U) |
| #define QEIV2_DMAEN_ZMISSFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT) |
| #define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL) |
| #define QEIV2_DMAEN_ZMISSFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK) |
| #define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U) |
| #define QEIV2_DMAEN_ZPHFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT) |
| #define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL) |
| #define QEIV2_DMAEN_ZPHFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK) |
| #define QEIV2_DMAEN_ZPHFEN_SHIFT (28U) |
| #define QEIV2_FILT_CFG_FILT_CFG_A (0UL) |
| #define QEIV2_FILT_CFG_FILT_CFG_B (1UL) |
| #define QEIV2_FILT_CFG_FILT_CFG_F (5UL) |
| #define QEIV2_FILT_CFG_FILT_CFG_H (3UL) |
| #define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL) |
| #define QEIV2_FILT_CFG_FILT_CFG_Z (2UL) |
| #define QEIV2_FILT_CFG_FILTLEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT) |
| #define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU) |
| #define QEIV2_FILT_CFG_FILTLEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK) |
| #define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U) |
| #define QEIV2_FILT_CFG_MODE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT) |
| #define QEIV2_FILT_CFG_MODE_MASK (0xE000U) |
| #define QEIV2_FILT_CFG_MODE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK) |
| #define QEIV2_FILT_CFG_MODE_SHIFT (13U) |
| #define QEIV2_FILT_CFG_OUTINV_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT) |
| #define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL) |
| #define QEIV2_FILT_CFG_OUTINV_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK) |
| #define QEIV2_FILT_CFG_OUTINV_SHIFT (16U) |
| #define QEIV2_FILT_CFG_SYNCEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT) |
| #define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U) |
| #define QEIV2_FILT_CFG_SYNCEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK) |
| #define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U) |
| #define QEIV2_IRQEN_CYCLE0E_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT) |
| #define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL) |
| #define QEIV2_IRQEN_CYCLE0E_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK) |
| #define QEIV2_IRQEN_CYCLE0E_SHIFT (23U) |
| #define QEIV2_IRQEN_CYCLE1E_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT) |
| #define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL) |
| #define QEIV2_IRQEN_CYCLE1E_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK) |
| #define QEIV2_IRQEN_CYCLE1E_SHIFT (22U) |
| #define QEIV2_IRQEN_DIRCHGE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT) |
| #define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL) |
| #define QEIV2_IRQEN_DIRCHGE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK) |
| #define QEIV2_IRQEN_DIRCHGE_SHIFT (24U) |
| #define QEIV2_IRQEN_FAULTE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT) |
| #define QEIV2_IRQEN_FAULTE_MASK (0x40000UL) |
| #define QEIV2_IRQEN_FAULTE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK) |
| #define QEIV2_IRQEN_FAULTE_SHIFT (18U) |
| #define QEIV2_IRQEN_HOME2E_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT) |
| #define QEIV2_IRQEN_HOME2E_MASK (0x80000UL) |
| #define QEIV2_IRQEN_HOME2E_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK) |
| #define QEIV2_IRQEN_HOME2E_SHIFT (19U) |
| #define QEIV2_IRQEN_HOMEIE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT) |
| #define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL) |
| #define QEIV2_IRQEN_HOMEIE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK) |
| #define QEIV2_IRQEN_HOMEIE_SHIFT (30U) |
| #define QEIV2_IRQEN_POS2CMPE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT) |
| #define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL) |
| #define QEIV2_IRQEN_POS2CMPE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK) |
| #define QEIV2_IRQEN_POS2CMPE_SHIFT (25U) |
| #define QEIV2_IRQEN_POSCMPIE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT) |
| #define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL) |
| #define QEIV2_IRQEN_POSCMPIE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK) |
| #define QEIV2_IRQEN_POSCMPIE_SHIFT (29U) |
| #define QEIV2_IRQEN_PULSE0E_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT) |
| #define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL) |
| #define QEIV2_IRQEN_PULSE0E_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK) |
| #define QEIV2_IRQEN_PULSE0E_SHIFT (21U) |
| #define QEIV2_IRQEN_PULSE1E_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT) |
| #define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL) |
| #define QEIV2_IRQEN_PULSE1E_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK) |
| #define QEIV2_IRQEN_PULSE1E_SHIFT (20U) |
| #define QEIV2_IRQEN_WDGIE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT) |
| #define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL) |
| #define QEIV2_IRQEN_WDGIE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK) |
| #define QEIV2_IRQEN_WDGIE_SHIFT (31U) |
| #define QEIV2_IRQEN_WIDTHTME_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT) |
| #define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL) |
| #define QEIV2_IRQEN_WIDTHTME_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK) |
| #define QEIV2_IRQEN_WIDTHTME_SHIFT (26U) |
| #define QEIV2_IRQEN_ZMISSE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT) |
| #define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL) |
| #define QEIV2_IRQEN_ZMISSE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK) |
| #define QEIV2_IRQEN_ZMISSE_SHIFT (27U) |
| #define QEIV2_IRQEN_ZPHIE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT) |
| #define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL) |
| #define QEIV2_IRQEN_ZPHIE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK) |
| #define QEIV2_IRQEN_ZPHIE_SHIFT (28U) |
| #define QEIV2_MATCH_CFG_DIRCMP2_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT) |
| #define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U) |
| #define QEIV2_MATCH_CFG_DIRCMP2_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK) |
| #define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U) |
| #define QEIV2_MATCH_CFG_DIRCMP2DIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) |
| #define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U) |
| #define QEIV2_MATCH_CFG_DIRCMP2DIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) |
| #define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U) |
| #define QEIV2_MATCH_CFG_DIRCMP_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT) |
| #define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL) |
| #define QEIV2_MATCH_CFG_DIRCMP_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK) |
| #define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U) |
| #define QEIV2_MATCH_CFG_DIRCMPDIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) |
| #define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL) |
| #define QEIV2_MATCH_CFG_DIRCMPDIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) |
| #define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) |
| #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) |
| #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U) |
| #define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) |
| #define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL) |
| #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) |
| #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U) |
| #define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) |
| #define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL) |
| #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) |
| #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U) |
| #define QEIV2_MATCH_CFG_SPDCMP2DIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) |
| #define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U) |
| #define QEIV2_MATCH_CFG_SPDCMP2DIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) |
| #define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U) |
| #define QEIV2_MATCH_CFG_SPDCMPDIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) |
| #define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL) |
| #define QEIV2_MATCH_CFG_SPDCMPDIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) |
| #define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U) |
| #define QEIV2_MATCH_CFG_ZCMP2DIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) |
| #define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U) |
| #define QEIV2_MATCH_CFG_ZCMP2DIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) |
| #define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U) |
| #define QEIV2_MATCH_CFG_ZCMPDIS_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) |
| #define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL) |
| #define QEIV2_MATCH_CFG_ZCMPDIS_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) |
| #define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U) |
| #define QEIV2_PHASE_CNT_PHASE_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) |
| #define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PHASE_CNT_PHASE_CNT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) |
| #define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U) |
| #define QEIV2_PHASE_PARAM_PHASE_PARAM_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) |
| #define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PHASE_PARAM_PHASE_PARAM_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) |
| #define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U) |
| #define QEIV2_PHASE_UPDATE_DEC_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT) |
| #define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL) |
| #define QEIV2_PHASE_UPDATE_DEC_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK) |
| #define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U) |
| #define QEIV2_PHASE_UPDATE_INC_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT) |
| #define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL) |
| #define QEIV2_PHASE_UPDATE_INC_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK) |
| #define QEIV2_PHASE_UPDATE_INC_SHIFT (31U) |
| #define QEIV2_PHASE_UPDATE_VALUE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT) |
| #define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL) |
| #define QEIV2_PHASE_UPDATE_VALUE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK) |
| #define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U) |
| #define QEIV2_PHCFG_PHMAX_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT) |
| #define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PHCFG_PHMAX_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK) |
| #define QEIV2_PHCFG_PHMAX_SHIFT (0U) |
| #define QEIV2_PHCMP2_PHCMP2_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT) |
| #define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PHCMP2_PHCMP2_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK) |
| #define QEIV2_PHCMP2_PHCMP2_SHIFT (0U) |
| #define QEIV2_PHCMP_PHCMP_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT) |
| #define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PHCMP_PHCMP_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK) |
| #define QEIV2_PHCMP_PHCMP_SHIFT (0U) |
| #define QEIV2_PHIDX_PHIDX_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT) |
| #define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PHIDX_PHIDX_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK) |
| #define QEIV2_PHIDX_PHIDX_SHIFT (0U) |
| #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) |
| #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL) |
| #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) |
| #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U) |
| #define QEIV2_POS_TIMEOUT_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT) |
| #define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL) |
| #define QEIV2_POS_TIMEOUT_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK) |
| #define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U) |
| #define QEIV2_POS_TIMEOUT_TIMEOUT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) |
| #define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL) |
| #define QEIV2_POS_TIMEOUT_TIMEOUT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) |
| #define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U) |
| #define QEIV2_POSITION_POSITION_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT) |
| #define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL) |
| #define QEIV2_POSITION_POSITION_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK) |
| #define QEIV2_POSITION_POSITION_SHIFT (0U) |
| #define QEIV2_POSITION_UPDATE_DEC_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT) |
| #define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL) |
| #define QEIV2_POSITION_UPDATE_DEC_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK) |
| #define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U) |
| #define QEIV2_POSITION_UPDATE_INC_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT) |
| #define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL) |
| #define QEIV2_POSITION_UPDATE_INC_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK) |
| #define QEIV2_POSITION_UPDATE_INC_SHIFT (31U) |
| #define QEIV2_POSITION_UPDATE_VALUE_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT) |
| #define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL) |
| #define QEIV2_POSITION_UPDATE_VALUE_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK) |
| #define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U) |
| #define QEIV2_PULSE0_CNT_PULSE0_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT) |
| #define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U) |
| #define QEIV2_PULSE0_NUM_PULSE0_NUM_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) |
| #define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0_NUM_PULSE0_NUM_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) |
| #define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U) |
| #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT) |
| #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U) |
| #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT) |
| #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U) |
| #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT) |
| #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U) |
| #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT) |
| #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U) |
| #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT) |
| #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U) |
| #define QEIV2_PULSE1_CNT_PULSE1_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT) |
| #define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U) |
| #define QEIV2_PULSE1_NUM_PULSE1_NUM_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) |
| #define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1_NUM_PULSE1_NUM_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) |
| #define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U) |
| #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT) |
| #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U) |
| #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT) |
| #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U) |
| #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT) |
| #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U) |
| #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT) |
| #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U) |
| #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT) |
| #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL) |
| #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U) |
| #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) |
| #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK (0x20000UL) |
| #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) |
| #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT (17U) |
| #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) |
| #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK (0x10000UL) |
| #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) |
| #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT (16U) |
| #define QEIV2_QEI_CFG_NEGEDGE_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) |
| #define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U) |
| #define QEIV2_QEI_CFG_NEGEDGE_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) |
| #define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U) |
| #define QEIV2_QEI_CFG_POSIDGE_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) |
| #define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U) |
| #define QEIV2_QEI_CFG_POSIDGE_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) |
| #define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U) |
| #define QEIV2_QEI_CFG_PULSE0_ONESHOT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) |
| #define QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK (0x80000UL) |
| #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) |
| #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT (19U) |
| #define QEIV2_QEI_CFG_PULSE1_ONESHOT_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) |
| #define QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK (0x40000UL) |
| #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) |
| #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT (18U) |
| #define QEIV2_QEI_CFG_SIGA_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT) |
| #define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U) |
| #define QEIV2_QEI_CFG_SIGA_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK) |
| #define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U) |
| #define QEIV2_QEI_CFG_SIGB_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT) |
| #define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U) |
| #define QEIV2_QEI_CFG_SIGB_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK) |
| #define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U) |
| #define QEIV2_QEI_CFG_SIGZ_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT) |
| #define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U) |
| #define QEIV2_QEI_CFG_SIGZ_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK) |
| #define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U) |
| #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) |
| #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U) |
| #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) |
| #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U) |
| #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) |
| #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK (0x20000000UL) |
| #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) |
| #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT (29U) |
| #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) |
| #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK (0x10000000UL) |
| #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) |
| #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT (28U) |
| #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) |
| #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK (0x80000000UL) |
| #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) |
| #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT (31U) |
| #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) |
| #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK (0x40000000UL) |
| #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) |
| #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT (30U) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK (0x200U) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT (9U) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK (0x100U) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) |
| #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT (8U) |
| #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) |
| #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK (0x800U) |
| #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) |
| #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT (11U) |
| #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) |
| #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK (0x400U) |
| #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) |
| #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT (10U) |
| #define QEIV2_QEI_CFG_UVW_POS_OPT0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) |
| #define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U) |
| #define QEIV2_QEI_CFG_UVW_POS_OPT0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) |
| #define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U) |
| #define QEIV2_READEN_CYCLE0FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT) |
| #define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL) |
| #define QEIV2_READEN_CYCLE0FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK) |
| #define QEIV2_READEN_CYCLE0FEN_SHIFT (23U) |
| #define QEIV2_READEN_CYCLE1FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT) |
| #define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL) |
| #define QEIV2_READEN_CYCLE1FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK) |
| #define QEIV2_READEN_CYCLE1FEN_SHIFT (22U) |
| #define QEIV2_READEN_DIRCHGFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT) |
| #define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL) |
| #define QEIV2_READEN_DIRCHGFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK) |
| #define QEIV2_READEN_DIRCHGFEN_SHIFT (24U) |
| #define QEIV2_READEN_FAULTFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT) |
| #define QEIV2_READEN_FAULTFEN_MASK (0x40000UL) |
| #define QEIV2_READEN_FAULTFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK) |
| #define QEIV2_READEN_FAULTFEN_SHIFT (18U) |
| #define QEIV2_READEN_HOME2FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT) |
| #define QEIV2_READEN_HOME2FEN_MASK (0x80000UL) |
| #define QEIV2_READEN_HOME2FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK) |
| #define QEIV2_READEN_HOME2FEN_SHIFT (19U) |
| #define QEIV2_READEN_HOMEFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT) |
| #define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL) |
| #define QEIV2_READEN_HOMEFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK) |
| #define QEIV2_READEN_HOMEFEN_SHIFT (30U) |
| #define QEIV2_READEN_POS2CMPFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT) |
| #define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL) |
| #define QEIV2_READEN_POS2CMPFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK) |
| #define QEIV2_READEN_POS2CMPFEN_SHIFT (25U) |
| #define QEIV2_READEN_POSCMPFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT) |
| #define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL) |
| #define QEIV2_READEN_POSCMPFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK) |
| #define QEIV2_READEN_POSCMPFEN_SHIFT (29U) |
| #define QEIV2_READEN_PULSE0FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT) |
| #define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL) |
| #define QEIV2_READEN_PULSE0FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK) |
| #define QEIV2_READEN_PULSE0FEN_SHIFT (21U) |
| #define QEIV2_READEN_PULSE1FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT) |
| #define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL) |
| #define QEIV2_READEN_PULSE1FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK) |
| #define QEIV2_READEN_PULSE1FEN_SHIFT (20U) |
| #define QEIV2_READEN_WDGFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT) |
| #define QEIV2_READEN_WDGFEN_MASK (0x80000000UL) |
| #define QEIV2_READEN_WDGFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK) |
| #define QEIV2_READEN_WDGFEN_SHIFT (31U) |
| #define QEIV2_READEN_WIDTHTMFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT) |
| #define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL) |
| #define QEIV2_READEN_WIDTHTMFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK) |
| #define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U) |
| #define QEIV2_READEN_ZMISSFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT) |
| #define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL) |
| #define QEIV2_READEN_ZMISSFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK) |
| #define QEIV2_READEN_ZMISSFEN_SHIFT (27U) |
| #define QEIV2_READEN_ZPHFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT) |
| #define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL) |
| #define QEIV2_READEN_ZPHFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK) |
| #define QEIV2_READEN_ZPHFEN_SHIFT (28U) |
| #define QEIV2_SPDCMP2_SPDCMP2_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT) |
| #define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL) |
| #define QEIV2_SPDCMP2_SPDCMP2_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK) |
| #define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U) |
| #define QEIV2_SPDCMP_SPDCMP_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT) |
| #define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) |
| #define QEIV2_SPDCMP_SPDCMP_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK) |
| #define QEIV2_SPDCMP_SPDCMP_SHIFT (0U) |
| #define QEIV2_SR_CYCLE0F_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT) |
| #define QEIV2_SR_CYCLE0F_MASK (0x800000UL) |
| #define QEIV2_SR_CYCLE0F_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK) |
| #define QEIV2_SR_CYCLE0F_SHIFT (23U) |
| #define QEIV2_SR_CYCLE1F_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT) |
| #define QEIV2_SR_CYCLE1F_MASK (0x400000UL) |
| #define QEIV2_SR_CYCLE1F_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK) |
| #define QEIV2_SR_CYCLE1F_SHIFT (22U) |
| #define QEIV2_SR_DIRCHGF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT) |
| #define QEIV2_SR_DIRCHGF_MASK (0x1000000UL) |
| #define QEIV2_SR_DIRCHGF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK) |
| #define QEIV2_SR_DIRCHGF_SHIFT (24U) |
| #define QEIV2_SR_FAULTF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT) |
| #define QEIV2_SR_FAULTF_MASK (0x40000UL) |
| #define QEIV2_SR_FAULTF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK) |
| #define QEIV2_SR_FAULTF_SHIFT (18U) |
| #define QEIV2_SR_HOME2F_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT) |
| #define QEIV2_SR_HOME2F_MASK (0x80000UL) |
| #define QEIV2_SR_HOME2F_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK) |
| #define QEIV2_SR_HOME2F_SHIFT (19U) |
| #define QEIV2_SR_HOMEF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT) |
| #define QEIV2_SR_HOMEF_MASK (0x40000000UL) |
| #define QEIV2_SR_HOMEF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK) |
| #define QEIV2_SR_HOMEF_SHIFT (30U) |
| #define QEIV2_SR_POS2CMPF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT) |
| #define QEIV2_SR_POS2CMPF_MASK (0x2000000UL) |
| #define QEIV2_SR_POS2CMPF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK) |
| #define QEIV2_SR_POS2CMPF_SHIFT (25U) |
| #define QEIV2_SR_POSCMPF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT) |
| #define QEIV2_SR_POSCMPF_MASK (0x20000000UL) |
| #define QEIV2_SR_POSCMPF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK) |
| #define QEIV2_SR_POSCMPF_SHIFT (29U) |
| #define QEIV2_SR_PULSE0F_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT) |
| #define QEIV2_SR_PULSE0F_MASK (0x200000UL) |
| #define QEIV2_SR_PULSE0F_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK) |
| #define QEIV2_SR_PULSE0F_SHIFT (21U) |
| #define QEIV2_SR_PULSE1F_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT) |
| #define QEIV2_SR_PULSE1F_MASK (0x100000UL) |
| #define QEIV2_SR_PULSE1F_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK) |
| #define QEIV2_SR_PULSE1F_SHIFT (20U) |
| #define QEIV2_SR_WDGF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT) |
| #define QEIV2_SR_WDGF_MASK (0x80000000UL) |
| #define QEIV2_SR_WDGF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK) |
| #define QEIV2_SR_WDGF_SHIFT (31U) |
| #define QEIV2_SR_WIDTHTMF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT) |
| #define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL) |
| #define QEIV2_SR_WIDTHTMF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK) |
| #define QEIV2_SR_WIDTHTMF_SHIFT (26U) |
| #define QEIV2_SR_ZMISSF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT) |
| #define QEIV2_SR_ZMISSF_MASK (0x8000000UL) |
| #define QEIV2_SR_ZMISSF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK) |
| #define QEIV2_SR_ZMISSF_SHIFT (27U) |
| #define QEIV2_SR_ZPHF_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT) |
| #define QEIV2_SR_ZPHF_MASK (0x10000000UL) |
| #define QEIV2_SR_ZPHF_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK) |
| #define QEIV2_SR_ZPHF_SHIFT (28U) |
| #define QEIV2_TIMESTAMP_TIMESTAMP_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TIMESTAMP_TIMESTAMP_MASK) >> QEIV2_TIMESTAMP_TIMESTAMP_SHIFT) |
| #define QEIV2_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) |
| #define QEIV2_TIMESTAMP_TIMESTAMP_SHIFT (0U) |
| #define QEIV2_TRGOEN_CYCLE0FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT) |
| #define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL) |
| #define QEIV2_TRGOEN_CYCLE0FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK) |
| #define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U) |
| #define QEIV2_TRGOEN_CYCLE1FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT) |
| #define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL) |
| #define QEIV2_TRGOEN_CYCLE1FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK) |
| #define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U) |
| #define QEIV2_TRGOEN_DIRCHGFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT) |
| #define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL) |
| #define QEIV2_TRGOEN_DIRCHGFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK) |
| #define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U) |
| #define QEIV2_TRGOEN_FAULTFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT) |
| #define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL) |
| #define QEIV2_TRGOEN_FAULTFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK) |
| #define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U) |
| #define QEIV2_TRGOEN_HOME2FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT) |
| #define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL) |
| #define QEIV2_TRGOEN_HOME2FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK) |
| #define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U) |
| #define QEIV2_TRGOEN_HOMEFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT) |
| #define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL) |
| #define QEIV2_TRGOEN_HOMEFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK) |
| #define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U) |
| #define QEIV2_TRGOEN_POS2CMPFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT) |
| #define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL) |
| #define QEIV2_TRGOEN_POS2CMPFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK) |
| #define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U) |
| #define QEIV2_TRGOEN_POSCMPFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT) |
| #define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL) |
| #define QEIV2_TRGOEN_POSCMPFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK) |
| #define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U) |
| #define QEIV2_TRGOEN_PULSE0FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT) |
| #define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL) |
| #define QEIV2_TRGOEN_PULSE0FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK) |
| #define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U) |
| #define QEIV2_TRGOEN_PULSE1FEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT) |
| #define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL) |
| #define QEIV2_TRGOEN_PULSE1FEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK) |
| #define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U) |
| #define QEIV2_TRGOEN_WDGFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT) |
| #define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL) |
| #define QEIV2_TRGOEN_WDGFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK) |
| #define QEIV2_TRGOEN_WDGFEN_SHIFT (31U) |
| #define QEIV2_TRGOEN_WIDTHTMFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) |
| #define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL) |
| #define QEIV2_TRGOEN_WIDTHTMFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) |
| #define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U) |
| #define QEIV2_TRGOEN_ZMISSFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT) |
| #define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL) |
| #define QEIV2_TRGOEN_ZMISSFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK) |
| #define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U) |
| #define QEIV2_TRGOEN_ZPHFEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT) |
| #define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL) |
| #define QEIV2_TRGOEN_ZPHFEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK) |
| #define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U) |
| #define QEIV2_UVW_POS_CFG_POS_EN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT) |
| #define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U) |
| #define QEIV2_UVW_POS_CFG_POS_EN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK) |
| #define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U) |
| #define QEIV2_UVW_POS_CFG_U_POS_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) |
| #define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U) |
| #define QEIV2_UVW_POS_CFG_U_POS_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) |
| #define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U) |
| #define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL) |
| #define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL) |
| #define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL) |
| #define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL) |
| #define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL) |
| #define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL) |
| #define QEIV2_UVW_POS_CFG_V_POS_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) |
| #define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU) |
| #define QEIV2_UVW_POS_CFG_V_POS_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) |
| #define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U) |
| #define QEIV2_UVW_POS_CFG_W_POS_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) |
| #define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U) |
| #define QEIV2_UVW_POS_CFG_W_POS_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) |
| #define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U) |
| #define QEIV2_UVW_POS_UVW_POS0 (0UL) |
| #define QEIV2_UVW_POS_UVW_POS0_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT) |
| #define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL) |
| #define QEIV2_UVW_POS_UVW_POS0_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK) |
| #define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U) |
| #define QEIV2_UVW_POS_UVW_POS1 (1UL) |
| #define QEIV2_UVW_POS_UVW_POS2 (2UL) |
| #define QEIV2_UVW_POS_UVW_POS3 (3UL) |
| #define QEIV2_UVW_POS_UVW_POS4 (4UL) |
| #define QEIV2_UVW_POS_UVW_POS5 (5UL) |
| #define QEIV2_WDGCFG_WDGEN_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT) |
| #define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL) |
| #define QEIV2_WDGCFG_WDGEN_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK) |
| #define QEIV2_WDGCFG_WDGEN_SHIFT (31U) |
| #define QEIV2_WDGCFG_WDGTO_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT) |
| #define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL) |
| #define QEIV2_WDGCFG_WDGTO_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK) |
| #define QEIV2_WDGCFG_WDGTO_SHIFT (0U) |
| #define QEIV2_WDGCFG_WDOG_CFG_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT) |
| #define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL) |
| #define QEIV2_WDGCFG_WDOG_CFG_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK) |
| #define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U) |
| #define QEIV2_ZCMP2_ZCMP2_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT) |
| #define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL) |
| #define QEIV2_ZCMP2_ZCMP2_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK) |
| #define QEIV2_ZCMP2_ZCMP2_SHIFT (0U) |
| #define QEIV2_ZCMP_ZCMP_GET | ( | x | ) | (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT) |
| #define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) |
| #define QEIV2_ZCMP_ZCMP_SET | ( | x | ) | (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK) |
| #define QEIV2_ZCMP_ZCMP_SHIFT (0U) |
1.9.1