HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_sdm_regs.h File Reference

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Data Structures

struct  SDM_Type
 

Macros

#define SDM_CTRL_SFTRST_MASK   (0x80000000UL)
 
#define SDM_CTRL_SFTRST_SHIFT   (31U)
 
#define SDM_CTRL_SFTRST_SET(x)   (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK)
 
#define SDM_CTRL_SFTRST_GET(x)   (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT)
 
#define SDM_CTRL_CHMD_MASK   (0x3FFC000UL)
 
#define SDM_CTRL_CHMD_SHIFT   (14U)
 
#define SDM_CTRL_CHMD_SET(x)   (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK)
 
#define SDM_CTRL_CHMD_GET(x)   (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT)
 
#define SDM_CTRL_SYNC_MCLK_MASK   (0x3C00U)
 
#define SDM_CTRL_SYNC_MCLK_SHIFT   (10U)
 
#define SDM_CTRL_SYNC_MCLK_SET(x)   (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK)
 
#define SDM_CTRL_SYNC_MCLK_GET(x)   (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT)
 
#define SDM_CTRL_SYNC_MDAT_MASK   (0x3C0U)
 
#define SDM_CTRL_SYNC_MDAT_SHIFT   (6U)
 
#define SDM_CTRL_SYNC_MDAT_SET(x)   (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK)
 
#define SDM_CTRL_SYNC_MDAT_GET(x)   (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT)
 
#define SDM_CTRL_CH_EN_MASK   (0x3CU)
 
#define SDM_CTRL_CH_EN_SHIFT   (2U)
 
#define SDM_CTRL_CH_EN_SET(x)   (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK)
 
#define SDM_CTRL_CH_EN_GET(x)   (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT)
 
#define SDM_CTRL_IE_MASK   (0x2U)
 
#define SDM_CTRL_IE_SHIFT   (1U)
 
#define SDM_CTRL_IE_SET(x)   (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK)
 
#define SDM_CTRL_IE_GET(x)   (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT)
 
#define SDM_INT_EN_CH3DRY_MASK   (0x80U)
 
#define SDM_INT_EN_CH3DRY_SHIFT   (7U)
 
#define SDM_INT_EN_CH3DRY_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK)
 
#define SDM_INT_EN_CH3DRY_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT)
 
#define SDM_INT_EN_CH2DRY_MASK   (0x40U)
 
#define SDM_INT_EN_CH2DRY_SHIFT   (6U)
 
#define SDM_INT_EN_CH2DRY_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK)
 
#define SDM_INT_EN_CH2DRY_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT)
 
#define SDM_INT_EN_CH1DRY_MASK   (0x20U)
 
#define SDM_INT_EN_CH1DRY_SHIFT   (5U)
 
#define SDM_INT_EN_CH1DRY_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK)
 
#define SDM_INT_EN_CH1DRY_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT)
 
#define SDM_INT_EN_CH0DRY_MASK   (0x10U)
 
#define SDM_INT_EN_CH0DRY_SHIFT   (4U)
 
#define SDM_INT_EN_CH0DRY_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK)
 
#define SDM_INT_EN_CH0DRY_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT)
 
#define SDM_INT_EN_CH3ERR_MASK   (0x8U)
 
#define SDM_INT_EN_CH3ERR_SHIFT   (3U)
 
#define SDM_INT_EN_CH3ERR_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK)
 
#define SDM_INT_EN_CH3ERR_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT)
 
#define SDM_INT_EN_CH2ERR_MASK   (0x4U)
 
#define SDM_INT_EN_CH2ERR_SHIFT   (2U)
 
#define SDM_INT_EN_CH2ERR_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK)
 
#define SDM_INT_EN_CH2ERR_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT)
 
#define SDM_INT_EN_CH1ERR_MASK   (0x2U)
 
#define SDM_INT_EN_CH1ERR_SHIFT   (1U)
 
#define SDM_INT_EN_CH1ERR_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK)
 
#define SDM_INT_EN_CH1ERR_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT)
 
#define SDM_INT_EN_CH0ERR_MASK   (0x1U)
 
#define SDM_INT_EN_CH0ERR_SHIFT   (0U)
 
#define SDM_INT_EN_CH0ERR_SET(x)   (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK)
 
#define SDM_INT_EN_CH0ERR_GET(x)   (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT)
 
#define SDM_STATUS_CH3DRY_MASK   (0x80U)
 
#define SDM_STATUS_CH3DRY_SHIFT   (7U)
 
#define SDM_STATUS_CH3DRY_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT)
 
#define SDM_STATUS_CH2DRY_MASK   (0x40U)
 
#define SDM_STATUS_CH2DRY_SHIFT   (6U)
 
#define SDM_STATUS_CH2DRY_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT)
 
#define SDM_STATUS_CH1DRY_MASK   (0x20U)
 
#define SDM_STATUS_CH1DRY_SHIFT   (5U)
 
#define SDM_STATUS_CH1DRY_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT)
 
#define SDM_STATUS_CH0DRY_MASK   (0x10U)
 
#define SDM_STATUS_CH0DRY_SHIFT   (4U)
 
#define SDM_STATUS_CH0DRY_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT)
 
#define SDM_STATUS_CH3ERR_MASK   (0x8U)
 
#define SDM_STATUS_CH3ERR_SHIFT   (3U)
 
#define SDM_STATUS_CH3ERR_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT)
 
#define SDM_STATUS_CH2ERR_MASK   (0x4U)
 
#define SDM_STATUS_CH2ERR_SHIFT   (2U)
 
#define SDM_STATUS_CH2ERR_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT)
 
#define SDM_STATUS_CH1ERR_MASK   (0x2U)
 
#define SDM_STATUS_CH1ERR_SHIFT   (1U)
 
#define SDM_STATUS_CH1ERR_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT)
 
#define SDM_STATUS_CH0ERR_MASK   (0x1U)
 
#define SDM_STATUS_CH0ERR_SHIFT   (0U)
 
#define SDM_STATUS_CH0ERR_GET(x)   (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT)
 
#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK   (0xFF0000UL)
 
#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT   (16U)
 
#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SET(x)   (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK)
 
#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_GET(x)   (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK) >> SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT)
 
#define SDM_CH_SDFIFOCTRL_THRSH_MASK   (0x1F0U)
 
#define SDM_CH_SDFIFOCTRL_THRSH_SHIFT   (4U)
 
#define SDM_CH_SDFIFOCTRL_THRSH_SET(x)   (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK)
 
#define SDM_CH_SDFIFOCTRL_THRSH_GET(x)   (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT)
 
#define SDM_CH_SDCTRLP_MANCH_THR_MASK   (0xFE000000UL)
 
#define SDM_CH_SDCTRLP_MANCH_THR_SHIFT   (25U)
 
#define SDM_CH_SDCTRLP_MANCH_THR_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK)
 
#define SDM_CH_SDCTRLP_MANCH_THR_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT)
 
#define SDM_CH_SDCTRLP_WDOG_THR_MASK   (0x1FE0000UL)
 
#define SDM_CH_SDCTRLP_WDOG_THR_SHIFT   (17U)
 
#define SDM_CH_SDCTRLP_WDOG_THR_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK)
 
#define SDM_CH_SDCTRLP_WDOG_THR_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT)
 
#define SDM_CH_SDCTRLP_DFFOVIE_MASK   (0x8000U)
 
#define SDM_CH_SDCTRLP_DFFOVIE_SHIFT   (15U)
 
#define SDM_CH_SDCTRLP_DFFOVIE_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK)
 
#define SDM_CH_SDCTRLP_DFFOVIE_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT)
 
#define SDM_CH_SDCTRLP_DSATIE_MASK   (0x4000U)
 
#define SDM_CH_SDCTRLP_DSATIE_SHIFT   (14U)
 
#define SDM_CH_SDCTRLP_DSATIE_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK)
 
#define SDM_CH_SDCTRLP_DSATIE_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT)
 
#define SDM_CH_SDCTRLP_DRIE_MASK   (0x2000U)
 
#define SDM_CH_SDCTRLP_DRIE_SHIFT   (13U)
 
#define SDM_CH_SDCTRLP_DRIE_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK)
 
#define SDM_CH_SDCTRLP_DRIE_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT)
 
#define SDM_CH_SDCTRLP_SYNCSEL_MASK   (0x1F80U)
 
#define SDM_CH_SDCTRLP_SYNCSEL_SHIFT   (7U)
 
#define SDM_CH_SDCTRLP_SYNCSEL_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK)
 
#define SDM_CH_SDCTRLP_SYNCSEL_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT)
 
#define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK   (0x40U)
 
#define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT   (6U)
 
#define SDM_CH_SDCTRLP_FFSYNCCLREN_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK)
 
#define SDM_CH_SDCTRLP_FFSYNCCLREN_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT)
 
#define SDM_CH_SDCTRLP_WTSYNACLR_MASK   (0x20U)
 
#define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT   (5U)
 
#define SDM_CH_SDCTRLP_WTSYNACLR_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK)
 
#define SDM_CH_SDCTRLP_WTSYNACLR_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT)
 
#define SDM_CH_SDCTRLP_WTSYNMCLR_MASK   (0x10U)
 
#define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT   (4U)
 
#define SDM_CH_SDCTRLP_WTSYNMCLR_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK)
 
#define SDM_CH_SDCTRLP_WTSYNMCLR_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT)
 
#define SDM_CH_SDCTRLP_WTSYNCEN_MASK   (0x8U)
 
#define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT   (3U)
 
#define SDM_CH_SDCTRLP_WTSYNCEN_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK)
 
#define SDM_CH_SDCTRLP_WTSYNCEN_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT)
 
#define SDM_CH_SDCTRLP_D32_MASK   (0x4U)
 
#define SDM_CH_SDCTRLP_D32_SHIFT   (2U)
 
#define SDM_CH_SDCTRLP_D32_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK)
 
#define SDM_CH_SDCTRLP_D32_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT)
 
#define SDM_CH_SDCTRLP_DR_OPT_MASK   (0x2U)
 
#define SDM_CH_SDCTRLP_DR_OPT_SHIFT   (1U)
 
#define SDM_CH_SDCTRLP_DR_OPT_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK)
 
#define SDM_CH_SDCTRLP_DR_OPT_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT)
 
#define SDM_CH_SDCTRLP_EN_MASK   (0x1U)
 
#define SDM_CH_SDCTRLP_EN_SHIFT   (0U)
 
#define SDM_CH_SDCTRLP_EN_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK)
 
#define SDM_CH_SDCTRLP_EN_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT)
 
#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK   (0x80000000UL)
 
#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT   (31U)
 
#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK)
 
#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT)
 
#define SDM_CH_SDCTRLE_CIC_GATE_POL_MASK   (0x40000000UL)
 
#define SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT   (30U)
 
#define SDM_CH_SDCTRLE_CIC_GATE_POL_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK)
 
#define SDM_CH_SDCTRLE_CIC_GATE_POL_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT)
 
#define SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK   (0x3C000000UL)
 
#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT   (26U)
 
#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK)
 
#define SDM_CH_SDCTRLE_CIC_GATE_SEL_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT)
 
#define SDM_CH_SDCTRLE_CIC_GATE_EN_MASK   (0x2000000UL)
 
#define SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT   (25U)
 
#define SDM_CH_SDCTRLE_CIC_GATE_EN_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK)
 
#define SDM_CH_SDCTRLE_CIC_GATE_EN_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT)
 
#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK   (0x400000UL)
 
#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT   (22U)
 
#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK)
 
#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK) >> SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT)
 
#define SDM_CH_SDCTRLE_DFIFO_S_T_MASK   (0x200000UL)
 
#define SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT   (21U)
 
#define SDM_CH_SDCTRLE_DFIFO_S_T_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK)
 
#define SDM_CH_SDCTRLE_DFIFO_S_T_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK) >> SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT)
 
#define SDM_CH_SDCTRLE_DATA_S_T_MASK   (0x100000UL)
 
#define SDM_CH_SDCTRLE_DATA_S_T_SHIFT   (20U)
 
#define SDM_CH_SDCTRLE_DATA_S_T_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_DATA_S_T_SHIFT) & SDM_CH_SDCTRLE_DATA_S_T_MASK)
 
#define SDM_CH_SDCTRLE_DATA_S_T_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_DATA_S_T_MASK) >> SDM_CH_SDCTRLE_DATA_S_T_SHIFT)
 
#define SDM_CH_SDCTRLE_SGD_ORDR_MASK   (0x60000UL)
 
#define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT   (17U)
 
#define SDM_CH_SDCTRLE_SGD_ORDR_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK)
 
#define SDM_CH_SDCTRLE_SGD_ORDR_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT)
 
#define SDM_CH_SDCTRLE_PWMSYNC_MASK   (0x10000UL)
 
#define SDM_CH_SDCTRLE_PWMSYNC_SHIFT   (16U)
 
#define SDM_CH_SDCTRLE_PWMSYNC_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK)
 
#define SDM_CH_SDCTRLE_PWMSYNC_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT)
 
#define SDM_CH_SDCTRLE_CIC_SCL_MASK   (0x7800U)
 
#define SDM_CH_SDCTRLE_CIC_SCL_SHIFT   (11U)
 
#define SDM_CH_SDCTRLE_CIC_SCL_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK)
 
#define SDM_CH_SDCTRLE_CIC_SCL_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT)
 
#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK   (0x7F8U)
 
#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT   (3U)
 
#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK)
 
#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT)
 
#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK   (0x7U)
 
#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT   (0U)
 
#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x)   (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK)
 
#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x)   (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT)
 
#define SDM_CH_SDST_PERIOD_MCLK_MASK   (0x7F800000UL)
 
#define SDM_CH_SDST_PERIOD_MCLK_SHIFT   (23U)
 
#define SDM_CH_SDST_PERIOD_MCLK_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT)
 
#define SDM_CH_SDST_SDATA_D0_T1_MASK   (0x2000U)
 
#define SDM_CH_SDST_SDATA_D0_T1_SHIFT   (13U)
 
#define SDM_CH_SDST_SDATA_D0_T1_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_SDATA_D0_T1_MASK) >> SDM_CH_SDST_SDATA_D0_T1_SHIFT)
 
#define SDM_CH_SDST_SDFIFO_D0_T1_MASK   (0x1000U)
 
#define SDM_CH_SDST_SDFIFO_D0_T1_SHIFT   (12U)
 
#define SDM_CH_SDST_SDFIFO_D0_T1_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_SDFIFO_D0_T1_MASK) >> SDM_CH_SDST_SDFIFO_D0_T1_SHIFT)
 
#define SDM_CH_SDST_FIFO_DR_MASK   (0x200U)
 
#define SDM_CH_SDST_FIFO_DR_SHIFT   (9U)
 
#define SDM_CH_SDST_FIFO_DR_SET(x)   (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK)
 
#define SDM_CH_SDST_FIFO_DR_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT)
 
#define SDM_CH_SDST_DOV_ERR_MASK   (0x80U)
 
#define SDM_CH_SDST_DOV_ERR_SHIFT   (7U)
 
#define SDM_CH_SDST_DOV_ERR_SET(x)   (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK)
 
#define SDM_CH_SDST_DOV_ERR_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT)
 
#define SDM_CH_SDST_DSAT_ERR_MASK   (0x40U)
 
#define SDM_CH_SDST_DSAT_ERR_SHIFT   (6U)
 
#define SDM_CH_SDST_DSAT_ERR_SET(x)   (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK)
 
#define SDM_CH_SDST_DSAT_ERR_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT)
 
#define SDM_CH_SDST_WTSYNFLG_MASK   (0x20U)
 
#define SDM_CH_SDST_WTSYNFLG_SHIFT   (5U)
 
#define SDM_CH_SDST_WTSYNFLG_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT)
 
#define SDM_CH_SDST_FILL_MASK   (0x1FU)
 
#define SDM_CH_SDST_FILL_SHIFT   (0U)
 
#define SDM_CH_SDST_FILL_GET(x)   (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT)
 
#define SDM_CH_SDATA_VAL_MASK   (0xFFFFFFFFUL)
 
#define SDM_CH_SDATA_VAL_SHIFT   (0U)
 
#define SDM_CH_SDATA_VAL_GET(x)   (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT)
 
#define SDM_CH_SDFIFO_VAL_MASK   (0xFFFFFFFFUL)
 
#define SDM_CH_SDFIFO_VAL_SHIFT   (0U)
 
#define SDM_CH_SDFIFO_VAL_GET(x)   (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT)
 
#define SDM_CH_SCAMP_VAL_MASK   (0xFFFFU)
 
#define SDM_CH_SCAMP_VAL_SHIFT   (0U)
 
#define SDM_CH_SCAMP_VAL_GET(x)   (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT)
 
#define SDM_CH_SCHTL_VAL_MASK   (0xFFFFU)
 
#define SDM_CH_SCHTL_VAL_SHIFT   (0U)
 
#define SDM_CH_SCHTL_VAL_SET(x)   (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK)
 
#define SDM_CH_SCHTL_VAL_GET(x)   (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT)
 
#define SDM_CH_SCHTLZ_VAL_MASK   (0xFFFFU)
 
#define SDM_CH_SCHTLZ_VAL_SHIFT   (0U)
 
#define SDM_CH_SCHTLZ_VAL_SET(x)   (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK)
 
#define SDM_CH_SCHTLZ_VAL_GET(x)   (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT)
 
#define SDM_CH_SCLLT_VAL_MASK   (0xFFFFU)
 
#define SDM_CH_SCLLT_VAL_SHIFT   (0U)
 
#define SDM_CH_SCLLT_VAL_SET(x)   (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK)
 
#define SDM_CH_SCLLT_VAL_GET(x)   (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT)
 
#define SDM_CH_SCCTRL_HZ_EN_MASK   (0x800000UL)
 
#define SDM_CH_SCCTRL_HZ_EN_SHIFT   (23U)
 
#define SDM_CH_SCCTRL_HZ_EN_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK)
 
#define SDM_CH_SCCTRL_HZ_EN_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT)
 
#define SDM_CH_SCCTRL_MF_IE_MASK   (0x400000UL)
 
#define SDM_CH_SCCTRL_MF_IE_SHIFT   (22U)
 
#define SDM_CH_SCCTRL_MF_IE_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK)
 
#define SDM_CH_SCCTRL_MF_IE_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT)
 
#define SDM_CH_SCCTRL_HL_IE_MASK   (0x200000UL)
 
#define SDM_CH_SCCTRL_HL_IE_SHIFT   (21U)
 
#define SDM_CH_SCCTRL_HL_IE_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK)
 
#define SDM_CH_SCCTRL_HL_IE_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT)
 
#define SDM_CH_SCCTRL_LL_IE_MASK   (0x100000UL)
 
#define SDM_CH_SCCTRL_LL_IE_SHIFT   (20U)
 
#define SDM_CH_SCCTRL_LL_IE_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK)
 
#define SDM_CH_SCCTRL_LL_IE_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT)
 
#define SDM_CH_SCCTRL_SGD_ORDR_MASK   (0xC0000UL)
 
#define SDM_CH_SCCTRL_SGD_ORDR_SHIFT   (18U)
 
#define SDM_CH_SCCTRL_SGD_ORDR_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK)
 
#define SDM_CH_SCCTRL_SGD_ORDR_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT)
 
#define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK   (0x1F0U)
 
#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT   (4U)
 
#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK)
 
#define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT)
 
#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK   (0xEU)
 
#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT   (1U)
 
#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK)
 
#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT)
 
#define SDM_CH_SCCTRL_EN_MASK   (0x1U)
 
#define SDM_CH_SCCTRL_EN_SHIFT   (0U)
 
#define SDM_CH_SCCTRL_EN_SET(x)   (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK)
 
#define SDM_CH_SCCTRL_EN_GET(x)   (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT)
 
#define SDM_CH_SCST_HZ_MASK   (0x8U)
 
#define SDM_CH_SCST_HZ_SHIFT   (3U)
 
#define SDM_CH_SCST_HZ_SET(x)   (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK)
 
#define SDM_CH_SCST_HZ_GET(x)   (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT)
 
#define SDM_CH_SCST_MF_MASK   (0x4U)
 
#define SDM_CH_SCST_MF_SHIFT   (2U)
 
#define SDM_CH_SCST_MF_SET(x)   (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK)
 
#define SDM_CH_SCST_MF_GET(x)   (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT)
 
#define SDM_CH_SCST_CMPH_MASK   (0x2U)
 
#define SDM_CH_SCST_CMPH_SHIFT   (1U)
 
#define SDM_CH_SCST_CMPH_SET(x)   (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK)
 
#define SDM_CH_SCST_CMPH_GET(x)   (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT)
 
#define SDM_CH_SCST_CMPL_MASK   (0x1U)
 
#define SDM_CH_SCST_CMPL_SHIFT   (0U)
 
#define SDM_CH_SCST_CMPL_SET(x)   (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK)
 
#define SDM_CH_SCST_CMPL_GET(x)   (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT)
 
#define SDM_CH_0   (0UL)
 
#define SDM_CH_1   (1UL)
 
#define SDM_CH_2   (2UL)
 
#define SDM_CH_3   (3UL)
 

Macro Definition Documentation

◆ SDM_CH_0

#define SDM_CH_0   (0UL)

◆ SDM_CH_1

#define SDM_CH_1   (1UL)

◆ SDM_CH_2

#define SDM_CH_2   (2UL)

◆ SDM_CH_3

#define SDM_CH_3   (3UL)

◆ SDM_CH_SCAMP_VAL_GET

#define SDM_CH_SCAMP_VAL_GET (   x)    (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT)

◆ SDM_CH_SCAMP_VAL_MASK

#define SDM_CH_SCAMP_VAL_MASK   (0xFFFFU)

◆ SDM_CH_SCAMP_VAL_SHIFT

#define SDM_CH_SCAMP_VAL_SHIFT   (0U)

◆ SDM_CH_SCCTRL_CIC_DEC_RATIO_GET

#define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT)

◆ SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK

#define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK   (0x1F0U)

◆ SDM_CH_SCCTRL_CIC_DEC_RATIO_SET

#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK)

◆ SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT

#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT   (4U)

◆ SDM_CH_SCCTRL_EN_GET

#define SDM_CH_SCCTRL_EN_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT)

◆ SDM_CH_SCCTRL_EN_MASK

#define SDM_CH_SCCTRL_EN_MASK   (0x1U)

◆ SDM_CH_SCCTRL_EN_SET

#define SDM_CH_SCCTRL_EN_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK)

◆ SDM_CH_SCCTRL_EN_SHIFT

#define SDM_CH_SCCTRL_EN_SHIFT   (0U)

◆ SDM_CH_SCCTRL_HL_IE_GET

#define SDM_CH_SCCTRL_HL_IE_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT)

◆ SDM_CH_SCCTRL_HL_IE_MASK

#define SDM_CH_SCCTRL_HL_IE_MASK   (0x200000UL)

◆ SDM_CH_SCCTRL_HL_IE_SET

#define SDM_CH_SCCTRL_HL_IE_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK)

◆ SDM_CH_SCCTRL_HL_IE_SHIFT

#define SDM_CH_SCCTRL_HL_IE_SHIFT   (21U)

◆ SDM_CH_SCCTRL_HZ_EN_GET

#define SDM_CH_SCCTRL_HZ_EN_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT)

◆ SDM_CH_SCCTRL_HZ_EN_MASK

#define SDM_CH_SCCTRL_HZ_EN_MASK   (0x800000UL)

◆ SDM_CH_SCCTRL_HZ_EN_SET

#define SDM_CH_SCCTRL_HZ_EN_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK)

◆ SDM_CH_SCCTRL_HZ_EN_SHIFT

#define SDM_CH_SCCTRL_HZ_EN_SHIFT   (23U)

◆ SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET

#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT)

◆ SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK

#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK   (0xEU)

◆ SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET

#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK)

◆ SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT

#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT   (1U)

◆ SDM_CH_SCCTRL_LL_IE_GET

#define SDM_CH_SCCTRL_LL_IE_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT)

◆ SDM_CH_SCCTRL_LL_IE_MASK

#define SDM_CH_SCCTRL_LL_IE_MASK   (0x100000UL)

◆ SDM_CH_SCCTRL_LL_IE_SET

#define SDM_CH_SCCTRL_LL_IE_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK)

◆ SDM_CH_SCCTRL_LL_IE_SHIFT

#define SDM_CH_SCCTRL_LL_IE_SHIFT   (20U)

◆ SDM_CH_SCCTRL_MF_IE_GET

#define SDM_CH_SCCTRL_MF_IE_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT)

◆ SDM_CH_SCCTRL_MF_IE_MASK

#define SDM_CH_SCCTRL_MF_IE_MASK   (0x400000UL)

◆ SDM_CH_SCCTRL_MF_IE_SET

#define SDM_CH_SCCTRL_MF_IE_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK)

◆ SDM_CH_SCCTRL_MF_IE_SHIFT

#define SDM_CH_SCCTRL_MF_IE_SHIFT   (22U)

◆ SDM_CH_SCCTRL_SGD_ORDR_GET

#define SDM_CH_SCCTRL_SGD_ORDR_GET (   x)    (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT)

◆ SDM_CH_SCCTRL_SGD_ORDR_MASK

#define SDM_CH_SCCTRL_SGD_ORDR_MASK   (0xC0000UL)

◆ SDM_CH_SCCTRL_SGD_ORDR_SET

#define SDM_CH_SCCTRL_SGD_ORDR_SET (   x)    (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK)

◆ SDM_CH_SCCTRL_SGD_ORDR_SHIFT

#define SDM_CH_SCCTRL_SGD_ORDR_SHIFT   (18U)

◆ SDM_CH_SCHTL_VAL_GET

#define SDM_CH_SCHTL_VAL_GET (   x)    (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT)

◆ SDM_CH_SCHTL_VAL_MASK

#define SDM_CH_SCHTL_VAL_MASK   (0xFFFFU)

◆ SDM_CH_SCHTL_VAL_SET

#define SDM_CH_SCHTL_VAL_SET (   x)    (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK)

◆ SDM_CH_SCHTL_VAL_SHIFT

#define SDM_CH_SCHTL_VAL_SHIFT   (0U)

◆ SDM_CH_SCHTLZ_VAL_GET

#define SDM_CH_SCHTLZ_VAL_GET (   x)    (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT)

◆ SDM_CH_SCHTLZ_VAL_MASK

#define SDM_CH_SCHTLZ_VAL_MASK   (0xFFFFU)

◆ SDM_CH_SCHTLZ_VAL_SET

#define SDM_CH_SCHTLZ_VAL_SET (   x)    (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK)

◆ SDM_CH_SCHTLZ_VAL_SHIFT

#define SDM_CH_SCHTLZ_VAL_SHIFT   (0U)

◆ SDM_CH_SCLLT_VAL_GET

#define SDM_CH_SCLLT_VAL_GET (   x)    (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT)

◆ SDM_CH_SCLLT_VAL_MASK

#define SDM_CH_SCLLT_VAL_MASK   (0xFFFFU)

◆ SDM_CH_SCLLT_VAL_SET

#define SDM_CH_SCLLT_VAL_SET (   x)    (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK)

◆ SDM_CH_SCLLT_VAL_SHIFT

#define SDM_CH_SCLLT_VAL_SHIFT   (0U)

◆ SDM_CH_SCST_CMPH_GET

#define SDM_CH_SCST_CMPH_GET (   x)    (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT)

◆ SDM_CH_SCST_CMPH_MASK

#define SDM_CH_SCST_CMPH_MASK   (0x2U)

◆ SDM_CH_SCST_CMPH_SET

#define SDM_CH_SCST_CMPH_SET (   x)    (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK)

◆ SDM_CH_SCST_CMPH_SHIFT

#define SDM_CH_SCST_CMPH_SHIFT   (1U)

◆ SDM_CH_SCST_CMPL_GET

#define SDM_CH_SCST_CMPL_GET (   x)    (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT)

◆ SDM_CH_SCST_CMPL_MASK

#define SDM_CH_SCST_CMPL_MASK   (0x1U)

◆ SDM_CH_SCST_CMPL_SET

#define SDM_CH_SCST_CMPL_SET (   x)    (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK)

◆ SDM_CH_SCST_CMPL_SHIFT

#define SDM_CH_SCST_CMPL_SHIFT   (0U)

◆ SDM_CH_SCST_HZ_GET

#define SDM_CH_SCST_HZ_GET (   x)    (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT)

◆ SDM_CH_SCST_HZ_MASK

#define SDM_CH_SCST_HZ_MASK   (0x8U)

◆ SDM_CH_SCST_HZ_SET

#define SDM_CH_SCST_HZ_SET (   x)    (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK)

◆ SDM_CH_SCST_HZ_SHIFT

#define SDM_CH_SCST_HZ_SHIFT   (3U)

◆ SDM_CH_SCST_MF_GET

#define SDM_CH_SCST_MF_GET (   x)    (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT)

◆ SDM_CH_SCST_MF_MASK

#define SDM_CH_SCST_MF_MASK   (0x4U)

◆ SDM_CH_SCST_MF_SET

#define SDM_CH_SCST_MF_SET (   x)    (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK)

◆ SDM_CH_SCST_MF_SHIFT

#define SDM_CH_SCST_MF_SHIFT   (2U)

◆ SDM_CH_SDATA_VAL_GET

#define SDM_CH_SDATA_VAL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT)

◆ SDM_CH_SDATA_VAL_MASK

#define SDM_CH_SDATA_VAL_MASK   (0xFFFFFFFFUL)

◆ SDM_CH_SDATA_VAL_SHIFT

#define SDM_CH_SDATA_VAL_SHIFT   (0U)

◆ SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET

#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT)

◆ SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK

#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK   (0x7F8U)

◆ SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET

#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK)

◆ SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT

#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT   (3U)

◆ SDM_CH_SDCTRLE_CIC_GATE_EN_GET

#define SDM_CH_SDCTRLE_CIC_GATE_EN_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT)

◆ SDM_CH_SDCTRLE_CIC_GATE_EN_MASK

#define SDM_CH_SDCTRLE_CIC_GATE_EN_MASK   (0x2000000UL)

◆ SDM_CH_SDCTRLE_CIC_GATE_EN_SET

#define SDM_CH_SDCTRLE_CIC_GATE_EN_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK)

◆ SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT

#define SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT   (25U)

◆ SDM_CH_SDCTRLE_CIC_GATE_POL_GET

#define SDM_CH_SDCTRLE_CIC_GATE_POL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT)

◆ SDM_CH_SDCTRLE_CIC_GATE_POL_MASK

#define SDM_CH_SDCTRLE_CIC_GATE_POL_MASK   (0x40000000UL)

◆ SDM_CH_SDCTRLE_CIC_GATE_POL_SET

#define SDM_CH_SDCTRLE_CIC_GATE_POL_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK)

◆ SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT

#define SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT   (30U)

◆ SDM_CH_SDCTRLE_CIC_GATE_SEL_GET

#define SDM_CH_SDCTRLE_CIC_GATE_SEL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT)

◆ SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK

#define SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK   (0x3C000000UL)

◆ SDM_CH_SDCTRLE_CIC_GATE_SEL_SET

#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK)

◆ SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT

#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT   (26U)

◆ SDM_CH_SDCTRLE_CIC_GATE_TYPE_GET

#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT)

◆ SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK

#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK   (0x80000000UL)

◆ SDM_CH_SDCTRLE_CIC_GATE_TYPE_SET

#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK)

◆ SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT

#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT   (31U)

◆ SDM_CH_SDCTRLE_CIC_SCL_GET

#define SDM_CH_SDCTRLE_CIC_SCL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT)

◆ SDM_CH_SDCTRLE_CIC_SCL_MASK

#define SDM_CH_SDCTRLE_CIC_SCL_MASK   (0x7800U)

◆ SDM_CH_SDCTRLE_CIC_SCL_SET

#define SDM_CH_SDCTRLE_CIC_SCL_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK)

◆ SDM_CH_SDCTRLE_CIC_SCL_SHIFT

#define SDM_CH_SDCTRLE_CIC_SCL_SHIFT   (11U)

◆ SDM_CH_SDCTRLE_DATA_S_T_GET

#define SDM_CH_SDCTRLE_DATA_S_T_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_DATA_S_T_MASK) >> SDM_CH_SDCTRLE_DATA_S_T_SHIFT)

◆ SDM_CH_SDCTRLE_DATA_S_T_MASK

#define SDM_CH_SDCTRLE_DATA_S_T_MASK   (0x100000UL)

◆ SDM_CH_SDCTRLE_DATA_S_T_SET

#define SDM_CH_SDCTRLE_DATA_S_T_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_DATA_S_T_SHIFT) & SDM_CH_SDCTRLE_DATA_S_T_MASK)

◆ SDM_CH_SDCTRLE_DATA_S_T_SHIFT

#define SDM_CH_SDCTRLE_DATA_S_T_SHIFT   (20U)

◆ SDM_CH_SDCTRLE_DFIFO_S_T_GET

#define SDM_CH_SDCTRLE_DFIFO_S_T_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK) >> SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT)

◆ SDM_CH_SDCTRLE_DFIFO_S_T_MASK

#define SDM_CH_SDCTRLE_DFIFO_S_T_MASK   (0x200000UL)

◆ SDM_CH_SDCTRLE_DFIFO_S_T_SET

#define SDM_CH_SDCTRLE_DFIFO_S_T_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK)

◆ SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT

#define SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT   (21U)

◆ SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET

#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT)

◆ SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK

#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK   (0x7U)

◆ SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET

#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK)

◆ SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT

#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT   (0U)

◆ SDM_CH_SDCTRLE_PWMSYNC_GET

#define SDM_CH_SDCTRLE_PWMSYNC_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT)

◆ SDM_CH_SDCTRLE_PWMSYNC_MASK

#define SDM_CH_SDCTRLE_PWMSYNC_MASK   (0x10000UL)

◆ SDM_CH_SDCTRLE_PWMSYNC_SET

#define SDM_CH_SDCTRLE_PWMSYNC_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK)

◆ SDM_CH_SDCTRLE_PWMSYNC_SHIFT

#define SDM_CH_SDCTRLE_PWMSYNC_SHIFT   (16U)

◆ SDM_CH_SDCTRLE_SGD_ORDR_GET

#define SDM_CH_SDCTRLE_SGD_ORDR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT)

◆ SDM_CH_SDCTRLE_SGD_ORDR_MASK

#define SDM_CH_SDCTRLE_SGD_ORDR_MASK   (0x60000UL)

◆ SDM_CH_SDCTRLE_SGD_ORDR_SET

#define SDM_CH_SDCTRLE_SGD_ORDR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK)

◆ SDM_CH_SDCTRLE_SGD_ORDR_SHIFT

#define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT   (17U)

◆ SDM_CH_SDCTRLE_TIMESTAMP_TYPE_GET

#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK) >> SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT)

◆ SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK

#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK   (0x400000UL)

◆ SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SET

#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK)

◆ SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT

#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT   (22U)

◆ SDM_CH_SDCTRLP_D32_GET

#define SDM_CH_SDCTRLP_D32_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT)

◆ SDM_CH_SDCTRLP_D32_MASK

#define SDM_CH_SDCTRLP_D32_MASK   (0x4U)

◆ SDM_CH_SDCTRLP_D32_SET

#define SDM_CH_SDCTRLP_D32_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK)

◆ SDM_CH_SDCTRLP_D32_SHIFT

#define SDM_CH_SDCTRLP_D32_SHIFT   (2U)

◆ SDM_CH_SDCTRLP_DFFOVIE_GET

#define SDM_CH_SDCTRLP_DFFOVIE_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT)

◆ SDM_CH_SDCTRLP_DFFOVIE_MASK

#define SDM_CH_SDCTRLP_DFFOVIE_MASK   (0x8000U)

◆ SDM_CH_SDCTRLP_DFFOVIE_SET

#define SDM_CH_SDCTRLP_DFFOVIE_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK)

◆ SDM_CH_SDCTRLP_DFFOVIE_SHIFT

#define SDM_CH_SDCTRLP_DFFOVIE_SHIFT   (15U)

◆ SDM_CH_SDCTRLP_DR_OPT_GET

#define SDM_CH_SDCTRLP_DR_OPT_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT)

◆ SDM_CH_SDCTRLP_DR_OPT_MASK

#define SDM_CH_SDCTRLP_DR_OPT_MASK   (0x2U)

◆ SDM_CH_SDCTRLP_DR_OPT_SET

#define SDM_CH_SDCTRLP_DR_OPT_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK)

◆ SDM_CH_SDCTRLP_DR_OPT_SHIFT

#define SDM_CH_SDCTRLP_DR_OPT_SHIFT   (1U)

◆ SDM_CH_SDCTRLP_DRIE_GET

#define SDM_CH_SDCTRLP_DRIE_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT)

◆ SDM_CH_SDCTRLP_DRIE_MASK

#define SDM_CH_SDCTRLP_DRIE_MASK   (0x2000U)

◆ SDM_CH_SDCTRLP_DRIE_SET

#define SDM_CH_SDCTRLP_DRIE_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK)

◆ SDM_CH_SDCTRLP_DRIE_SHIFT

#define SDM_CH_SDCTRLP_DRIE_SHIFT   (13U)

◆ SDM_CH_SDCTRLP_DSATIE_GET

#define SDM_CH_SDCTRLP_DSATIE_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT)

◆ SDM_CH_SDCTRLP_DSATIE_MASK

#define SDM_CH_SDCTRLP_DSATIE_MASK   (0x4000U)

◆ SDM_CH_SDCTRLP_DSATIE_SET

#define SDM_CH_SDCTRLP_DSATIE_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK)

◆ SDM_CH_SDCTRLP_DSATIE_SHIFT

#define SDM_CH_SDCTRLP_DSATIE_SHIFT   (14U)

◆ SDM_CH_SDCTRLP_EN_GET

#define SDM_CH_SDCTRLP_EN_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT)

◆ SDM_CH_SDCTRLP_EN_MASK

#define SDM_CH_SDCTRLP_EN_MASK   (0x1U)

◆ SDM_CH_SDCTRLP_EN_SET

#define SDM_CH_SDCTRLP_EN_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK)

◆ SDM_CH_SDCTRLP_EN_SHIFT

#define SDM_CH_SDCTRLP_EN_SHIFT   (0U)

◆ SDM_CH_SDCTRLP_FFSYNCCLREN_GET

#define SDM_CH_SDCTRLP_FFSYNCCLREN_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT)

◆ SDM_CH_SDCTRLP_FFSYNCCLREN_MASK

#define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK   (0x40U)

◆ SDM_CH_SDCTRLP_FFSYNCCLREN_SET

#define SDM_CH_SDCTRLP_FFSYNCCLREN_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK)

◆ SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT

#define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT   (6U)

◆ SDM_CH_SDCTRLP_MANCH_THR_GET

#define SDM_CH_SDCTRLP_MANCH_THR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT)

◆ SDM_CH_SDCTRLP_MANCH_THR_MASK

#define SDM_CH_SDCTRLP_MANCH_THR_MASK   (0xFE000000UL)

◆ SDM_CH_SDCTRLP_MANCH_THR_SET

#define SDM_CH_SDCTRLP_MANCH_THR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK)

◆ SDM_CH_SDCTRLP_MANCH_THR_SHIFT

#define SDM_CH_SDCTRLP_MANCH_THR_SHIFT   (25U)

◆ SDM_CH_SDCTRLP_SYNCSEL_GET

#define SDM_CH_SDCTRLP_SYNCSEL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT)

◆ SDM_CH_SDCTRLP_SYNCSEL_MASK

#define SDM_CH_SDCTRLP_SYNCSEL_MASK   (0x1F80U)

◆ SDM_CH_SDCTRLP_SYNCSEL_SET

#define SDM_CH_SDCTRLP_SYNCSEL_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK)

◆ SDM_CH_SDCTRLP_SYNCSEL_SHIFT

#define SDM_CH_SDCTRLP_SYNCSEL_SHIFT   (7U)

◆ SDM_CH_SDCTRLP_WDOG_THR_GET

#define SDM_CH_SDCTRLP_WDOG_THR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT)

◆ SDM_CH_SDCTRLP_WDOG_THR_MASK

#define SDM_CH_SDCTRLP_WDOG_THR_MASK   (0x1FE0000UL)

◆ SDM_CH_SDCTRLP_WDOG_THR_SET

#define SDM_CH_SDCTRLP_WDOG_THR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK)

◆ SDM_CH_SDCTRLP_WDOG_THR_SHIFT

#define SDM_CH_SDCTRLP_WDOG_THR_SHIFT   (17U)

◆ SDM_CH_SDCTRLP_WTSYNACLR_GET

#define SDM_CH_SDCTRLP_WTSYNACLR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT)

◆ SDM_CH_SDCTRLP_WTSYNACLR_MASK

#define SDM_CH_SDCTRLP_WTSYNACLR_MASK   (0x20U)

◆ SDM_CH_SDCTRLP_WTSYNACLR_SET

#define SDM_CH_SDCTRLP_WTSYNACLR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK)

◆ SDM_CH_SDCTRLP_WTSYNACLR_SHIFT

#define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT   (5U)

◆ SDM_CH_SDCTRLP_WTSYNCEN_GET

#define SDM_CH_SDCTRLP_WTSYNCEN_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT)

◆ SDM_CH_SDCTRLP_WTSYNCEN_MASK

#define SDM_CH_SDCTRLP_WTSYNCEN_MASK   (0x8U)

◆ SDM_CH_SDCTRLP_WTSYNCEN_SET

#define SDM_CH_SDCTRLP_WTSYNCEN_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK)

◆ SDM_CH_SDCTRLP_WTSYNCEN_SHIFT

#define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT   (3U)

◆ SDM_CH_SDCTRLP_WTSYNMCLR_GET

#define SDM_CH_SDCTRLP_WTSYNMCLR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT)

◆ SDM_CH_SDCTRLP_WTSYNMCLR_MASK

#define SDM_CH_SDCTRLP_WTSYNMCLR_MASK   (0x10U)

◆ SDM_CH_SDCTRLP_WTSYNMCLR_SET

#define SDM_CH_SDCTRLP_WTSYNMCLR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK)

◆ SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT

#define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT   (4U)

◆ SDM_CH_SDFIFO_VAL_GET

#define SDM_CH_SDFIFO_VAL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT)

◆ SDM_CH_SDFIFO_VAL_MASK

#define SDM_CH_SDFIFO_VAL_MASK   (0xFFFFFFFFUL)

◆ SDM_CH_SDFIFO_VAL_SHIFT

#define SDM_CH_SDFIFO_VAL_SHIFT   (0U)

◆ SDM_CH_SDFIFOCTRL_GATE_SAMPLES_GET

#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_GET (   x)    (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK) >> SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT)

◆ SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK

#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK   (0xFF0000UL)

◆ SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SET

#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SET (   x)    (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK)

◆ SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT

#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT   (16U)

◆ SDM_CH_SDFIFOCTRL_THRSH_GET

#define SDM_CH_SDFIFOCTRL_THRSH_GET (   x)    (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT)

◆ SDM_CH_SDFIFOCTRL_THRSH_MASK

#define SDM_CH_SDFIFOCTRL_THRSH_MASK   (0x1F0U)

◆ SDM_CH_SDFIFOCTRL_THRSH_SET

#define SDM_CH_SDFIFOCTRL_THRSH_SET (   x)    (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK)

◆ SDM_CH_SDFIFOCTRL_THRSH_SHIFT

#define SDM_CH_SDFIFOCTRL_THRSH_SHIFT   (4U)

◆ SDM_CH_SDST_DOV_ERR_GET

#define SDM_CH_SDST_DOV_ERR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT)

◆ SDM_CH_SDST_DOV_ERR_MASK

#define SDM_CH_SDST_DOV_ERR_MASK   (0x80U)

◆ SDM_CH_SDST_DOV_ERR_SET

#define SDM_CH_SDST_DOV_ERR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK)

◆ SDM_CH_SDST_DOV_ERR_SHIFT

#define SDM_CH_SDST_DOV_ERR_SHIFT   (7U)

◆ SDM_CH_SDST_DSAT_ERR_GET

#define SDM_CH_SDST_DSAT_ERR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT)

◆ SDM_CH_SDST_DSAT_ERR_MASK

#define SDM_CH_SDST_DSAT_ERR_MASK   (0x40U)

◆ SDM_CH_SDST_DSAT_ERR_SET

#define SDM_CH_SDST_DSAT_ERR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK)

◆ SDM_CH_SDST_DSAT_ERR_SHIFT

#define SDM_CH_SDST_DSAT_ERR_SHIFT   (6U)

◆ SDM_CH_SDST_FIFO_DR_GET

#define SDM_CH_SDST_FIFO_DR_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT)

◆ SDM_CH_SDST_FIFO_DR_MASK

#define SDM_CH_SDST_FIFO_DR_MASK   (0x200U)

◆ SDM_CH_SDST_FIFO_DR_SET

#define SDM_CH_SDST_FIFO_DR_SET (   x)    (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK)

◆ SDM_CH_SDST_FIFO_DR_SHIFT

#define SDM_CH_SDST_FIFO_DR_SHIFT   (9U)

◆ SDM_CH_SDST_FILL_GET

#define SDM_CH_SDST_FILL_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT)

◆ SDM_CH_SDST_FILL_MASK

#define SDM_CH_SDST_FILL_MASK   (0x1FU)

◆ SDM_CH_SDST_FILL_SHIFT

#define SDM_CH_SDST_FILL_SHIFT   (0U)

◆ SDM_CH_SDST_PERIOD_MCLK_GET

#define SDM_CH_SDST_PERIOD_MCLK_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT)

◆ SDM_CH_SDST_PERIOD_MCLK_MASK

#define SDM_CH_SDST_PERIOD_MCLK_MASK   (0x7F800000UL)

◆ SDM_CH_SDST_PERIOD_MCLK_SHIFT

#define SDM_CH_SDST_PERIOD_MCLK_SHIFT   (23U)

◆ SDM_CH_SDST_SDATA_D0_T1_GET

#define SDM_CH_SDST_SDATA_D0_T1_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_SDATA_D0_T1_MASK) >> SDM_CH_SDST_SDATA_D0_T1_SHIFT)

◆ SDM_CH_SDST_SDATA_D0_T1_MASK

#define SDM_CH_SDST_SDATA_D0_T1_MASK   (0x2000U)

◆ SDM_CH_SDST_SDATA_D0_T1_SHIFT

#define SDM_CH_SDST_SDATA_D0_T1_SHIFT   (13U)

◆ SDM_CH_SDST_SDFIFO_D0_T1_GET

#define SDM_CH_SDST_SDFIFO_D0_T1_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_SDFIFO_D0_T1_MASK) >> SDM_CH_SDST_SDFIFO_D0_T1_SHIFT)

◆ SDM_CH_SDST_SDFIFO_D0_T1_MASK

#define SDM_CH_SDST_SDFIFO_D0_T1_MASK   (0x1000U)

◆ SDM_CH_SDST_SDFIFO_D0_T1_SHIFT

#define SDM_CH_SDST_SDFIFO_D0_T1_SHIFT   (12U)

◆ SDM_CH_SDST_WTSYNFLG_GET

#define SDM_CH_SDST_WTSYNFLG_GET (   x)    (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT)

◆ SDM_CH_SDST_WTSYNFLG_MASK

#define SDM_CH_SDST_WTSYNFLG_MASK   (0x20U)

◆ SDM_CH_SDST_WTSYNFLG_SHIFT

#define SDM_CH_SDST_WTSYNFLG_SHIFT   (5U)

◆ SDM_CTRL_CH_EN_GET

#define SDM_CTRL_CH_EN_GET (   x)    (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT)

◆ SDM_CTRL_CH_EN_MASK

#define SDM_CTRL_CH_EN_MASK   (0x3CU)

◆ SDM_CTRL_CH_EN_SET

#define SDM_CTRL_CH_EN_SET (   x)    (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK)

◆ SDM_CTRL_CH_EN_SHIFT

#define SDM_CTRL_CH_EN_SHIFT   (2U)

◆ SDM_CTRL_CHMD_GET

#define SDM_CTRL_CHMD_GET (   x)    (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT)

◆ SDM_CTRL_CHMD_MASK

#define SDM_CTRL_CHMD_MASK   (0x3FFC000UL)

◆ SDM_CTRL_CHMD_SET

#define SDM_CTRL_CHMD_SET (   x)    (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK)

◆ SDM_CTRL_CHMD_SHIFT

#define SDM_CTRL_CHMD_SHIFT   (14U)

◆ SDM_CTRL_IE_GET

#define SDM_CTRL_IE_GET (   x)    (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT)

◆ SDM_CTRL_IE_MASK

#define SDM_CTRL_IE_MASK   (0x2U)

◆ SDM_CTRL_IE_SET

#define SDM_CTRL_IE_SET (   x)    (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK)

◆ SDM_CTRL_IE_SHIFT

#define SDM_CTRL_IE_SHIFT   (1U)

◆ SDM_CTRL_SFTRST_GET

#define SDM_CTRL_SFTRST_GET (   x)    (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT)

◆ SDM_CTRL_SFTRST_MASK

#define SDM_CTRL_SFTRST_MASK   (0x80000000UL)

◆ SDM_CTRL_SFTRST_SET

#define SDM_CTRL_SFTRST_SET (   x)    (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK)

◆ SDM_CTRL_SFTRST_SHIFT

#define SDM_CTRL_SFTRST_SHIFT   (31U)

◆ SDM_CTRL_SYNC_MCLK_GET

#define SDM_CTRL_SYNC_MCLK_GET (   x)    (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT)

◆ SDM_CTRL_SYNC_MCLK_MASK

#define SDM_CTRL_SYNC_MCLK_MASK   (0x3C00U)

◆ SDM_CTRL_SYNC_MCLK_SET

#define SDM_CTRL_SYNC_MCLK_SET (   x)    (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK)

◆ SDM_CTRL_SYNC_MCLK_SHIFT

#define SDM_CTRL_SYNC_MCLK_SHIFT   (10U)

◆ SDM_CTRL_SYNC_MDAT_GET

#define SDM_CTRL_SYNC_MDAT_GET (   x)    (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT)

◆ SDM_CTRL_SYNC_MDAT_MASK

#define SDM_CTRL_SYNC_MDAT_MASK   (0x3C0U)

◆ SDM_CTRL_SYNC_MDAT_SET

#define SDM_CTRL_SYNC_MDAT_SET (   x)    (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK)

◆ SDM_CTRL_SYNC_MDAT_SHIFT

#define SDM_CTRL_SYNC_MDAT_SHIFT   (6U)

◆ SDM_INT_EN_CH0DRY_GET

#define SDM_INT_EN_CH0DRY_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT)

◆ SDM_INT_EN_CH0DRY_MASK

#define SDM_INT_EN_CH0DRY_MASK   (0x10U)

◆ SDM_INT_EN_CH0DRY_SET

#define SDM_INT_EN_CH0DRY_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK)

◆ SDM_INT_EN_CH0DRY_SHIFT

#define SDM_INT_EN_CH0DRY_SHIFT   (4U)

◆ SDM_INT_EN_CH0ERR_GET

#define SDM_INT_EN_CH0ERR_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT)

◆ SDM_INT_EN_CH0ERR_MASK

#define SDM_INT_EN_CH0ERR_MASK   (0x1U)

◆ SDM_INT_EN_CH0ERR_SET

#define SDM_INT_EN_CH0ERR_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK)

◆ SDM_INT_EN_CH0ERR_SHIFT

#define SDM_INT_EN_CH0ERR_SHIFT   (0U)

◆ SDM_INT_EN_CH1DRY_GET

#define SDM_INT_EN_CH1DRY_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT)

◆ SDM_INT_EN_CH1DRY_MASK

#define SDM_INT_EN_CH1DRY_MASK   (0x20U)

◆ SDM_INT_EN_CH1DRY_SET

#define SDM_INT_EN_CH1DRY_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK)

◆ SDM_INT_EN_CH1DRY_SHIFT

#define SDM_INT_EN_CH1DRY_SHIFT   (5U)

◆ SDM_INT_EN_CH1ERR_GET

#define SDM_INT_EN_CH1ERR_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT)

◆ SDM_INT_EN_CH1ERR_MASK

#define SDM_INT_EN_CH1ERR_MASK   (0x2U)

◆ SDM_INT_EN_CH1ERR_SET

#define SDM_INT_EN_CH1ERR_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK)

◆ SDM_INT_EN_CH1ERR_SHIFT

#define SDM_INT_EN_CH1ERR_SHIFT   (1U)

◆ SDM_INT_EN_CH2DRY_GET

#define SDM_INT_EN_CH2DRY_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT)

◆ SDM_INT_EN_CH2DRY_MASK

#define SDM_INT_EN_CH2DRY_MASK   (0x40U)

◆ SDM_INT_EN_CH2DRY_SET

#define SDM_INT_EN_CH2DRY_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK)

◆ SDM_INT_EN_CH2DRY_SHIFT

#define SDM_INT_EN_CH2DRY_SHIFT   (6U)

◆ SDM_INT_EN_CH2ERR_GET

#define SDM_INT_EN_CH2ERR_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT)

◆ SDM_INT_EN_CH2ERR_MASK

#define SDM_INT_EN_CH2ERR_MASK   (0x4U)

◆ SDM_INT_EN_CH2ERR_SET

#define SDM_INT_EN_CH2ERR_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK)

◆ SDM_INT_EN_CH2ERR_SHIFT

#define SDM_INT_EN_CH2ERR_SHIFT   (2U)

◆ SDM_INT_EN_CH3DRY_GET

#define SDM_INT_EN_CH3DRY_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT)

◆ SDM_INT_EN_CH3DRY_MASK

#define SDM_INT_EN_CH3DRY_MASK   (0x80U)

◆ SDM_INT_EN_CH3DRY_SET

#define SDM_INT_EN_CH3DRY_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK)

◆ SDM_INT_EN_CH3DRY_SHIFT

#define SDM_INT_EN_CH3DRY_SHIFT   (7U)

◆ SDM_INT_EN_CH3ERR_GET

#define SDM_INT_EN_CH3ERR_GET (   x)    (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT)

◆ SDM_INT_EN_CH3ERR_MASK

#define SDM_INT_EN_CH3ERR_MASK   (0x8U)

◆ SDM_INT_EN_CH3ERR_SET

#define SDM_INT_EN_CH3ERR_SET (   x)    (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK)

◆ SDM_INT_EN_CH3ERR_SHIFT

#define SDM_INT_EN_CH3ERR_SHIFT   (3U)

◆ SDM_STATUS_CH0DRY_GET

#define SDM_STATUS_CH0DRY_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT)

◆ SDM_STATUS_CH0DRY_MASK

#define SDM_STATUS_CH0DRY_MASK   (0x10U)

◆ SDM_STATUS_CH0DRY_SHIFT

#define SDM_STATUS_CH0DRY_SHIFT   (4U)

◆ SDM_STATUS_CH0ERR_GET

#define SDM_STATUS_CH0ERR_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT)

◆ SDM_STATUS_CH0ERR_MASK

#define SDM_STATUS_CH0ERR_MASK   (0x1U)

◆ SDM_STATUS_CH0ERR_SHIFT

#define SDM_STATUS_CH0ERR_SHIFT   (0U)

◆ SDM_STATUS_CH1DRY_GET

#define SDM_STATUS_CH1DRY_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT)

◆ SDM_STATUS_CH1DRY_MASK

#define SDM_STATUS_CH1DRY_MASK   (0x20U)

◆ SDM_STATUS_CH1DRY_SHIFT

#define SDM_STATUS_CH1DRY_SHIFT   (5U)

◆ SDM_STATUS_CH1ERR_GET

#define SDM_STATUS_CH1ERR_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT)

◆ SDM_STATUS_CH1ERR_MASK

#define SDM_STATUS_CH1ERR_MASK   (0x2U)

◆ SDM_STATUS_CH1ERR_SHIFT

#define SDM_STATUS_CH1ERR_SHIFT   (1U)

◆ SDM_STATUS_CH2DRY_GET

#define SDM_STATUS_CH2DRY_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT)

◆ SDM_STATUS_CH2DRY_MASK

#define SDM_STATUS_CH2DRY_MASK   (0x40U)

◆ SDM_STATUS_CH2DRY_SHIFT

#define SDM_STATUS_CH2DRY_SHIFT   (6U)

◆ SDM_STATUS_CH2ERR_GET

#define SDM_STATUS_CH2ERR_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT)

◆ SDM_STATUS_CH2ERR_MASK

#define SDM_STATUS_CH2ERR_MASK   (0x4U)

◆ SDM_STATUS_CH2ERR_SHIFT

#define SDM_STATUS_CH2ERR_SHIFT   (2U)

◆ SDM_STATUS_CH3DRY_GET

#define SDM_STATUS_CH3DRY_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT)

◆ SDM_STATUS_CH3DRY_MASK

#define SDM_STATUS_CH3DRY_MASK   (0x80U)

◆ SDM_STATUS_CH3DRY_SHIFT

#define SDM_STATUS_CH3DRY_SHIFT   (7U)

◆ SDM_STATUS_CH3ERR_GET

#define SDM_STATUS_CH3ERR_GET (   x)    (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT)

◆ SDM_STATUS_CH3ERR_MASK

#define SDM_STATUS_CH3ERR_MASK   (0x8U)

◆ SDM_STATUS_CH3ERR_SHIFT

#define SDM_STATUS_CH3ERR_SHIFT   (3U)