HPM SDK
HPMicro Software Development Kit
hpm_clc_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_CLC_H
10 #define HPM_CLC_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t MODE; /* 0x0: mode ctrl */
15  __RW uint32_t ADC_EXPECT; /* 0x4: adc expect */
16  __RW uint32_t ADC_CHAN; /* 0x8: adc used channel */
17  __RW uint32_t ADC_OFFSET; /* 0xC: adc used offset */
18  __RW uint32_t EADC_LOWTH; /* 0x10: eadc_lowth value used in error adc cofficient selection */
19  __RW uint32_t EADC_HIGHTH; /* 0x14: eadc_highth value used in error adc cofficient selection */
20  __RW uint32_t EADC_MIDLOWTH; /* 0x18: eadc_midlowth value used in error adc cofficient selection */
21  __RW uint32_t EADC_MIDHIGHTH; /* 0x1C: eadc_midhighth value used in error adc cofficient selection */
22  __RW uint32_t P2Z2_CLAMP_LO; /* 0x20: 2p2z output clamp low threshold */
23  __RW uint32_t P2Z2_CLAMP_HI; /* 0x24: 2p2z output clamp high threshold */
24  __RW uint32_t P3Z3_CLAMP_LO; /* 0x28: 3p3z output clamp low threshold */
25  __RW uint32_t P3Z3_CLAMP_HI; /* 0x2C: 3p3z output clamp high threshold */
26  __R uint8_t RESERVED0[16]; /* 0x30 - 0x3F: Reserved */
27  struct {
28  __RW uint32_t COEFF_B0; /* 0x40: zone b0 */
29  __RW uint32_t COEFF_B1; /* 0x44: zone b1 */
30  __RW uint32_t COEFF_B2; /* 0x48: zone b2 */
31  __RW uint32_t COEFF_B3; /* 0x4C: zone b3 */
32  __RW uint32_t COEFF_A0; /* 0x50: zone a0 */
33  __RW uint32_t COEFF_A1; /* 0x54: zone a1 */
34  __RW uint32_t COEFF_A2; /* 0x58: zone a2 */
35  __RW uint32_t COEFF_KS; /* 0x5C: zone kscaling */
36  } COEFF[3];
37  __RW uint32_t PWM_PERIOD; /* 0xA0: pwm_period */
38  __R uint32_t OUTPUT_VALUE; /* 0xA4: output value */
39  __R uint32_t TIMESTAMP; /* 0xA8: adc timestamp used */
40  __RW uint32_t EADC_CURR; /* 0xAC: error adc latest value */
41  __RW uint32_t EADC_PRE0; /* 0xB0: error adc previous0 value */
42  __RW uint32_t EADC_PRE1; /* 0xB4: error adc previous1 value */
43  __RW uint32_t P2Z2_CURR; /* 0xB8: 2p2z latest value */
44  __RW uint32_t P2Z2_PRE0; /* 0xBC: 2p2z previous0 value */
45  __R uint8_t RESERVED1[4]; /* 0xC0 - 0xC3: Reserved */
46  __RW uint32_t P3Z3_CURR; /* 0xC4: 3p3z latest value */
47  __R uint8_t RESERVED2[4]; /* 0xC8 - 0xCB: Reserved */
48  __RW uint32_t P3Z3_FORBID_LO; /* 0xCC: 3p3z output forbid low threshold */
49  __RW uint32_t P3Z3_FORBID_MD; /* 0xD0: 3p3z output forbid middle threshold */
50  __RW uint32_t P3Z3_FORBID_HI; /* 0xD4: 3p3z output forbid high threshold */
51  __RW uint32_t LIND; /* 0xD8: inductance used in decoupling */
52  __RW uint32_t KE; /* 0xDC: Ke used in decoupling */
53  __RW uint32_t ADC_SW; /* 0xE0: adc software inject value */
54  __RW uint32_t SPEED_SW; /* 0xE4: speed software inject value */
55  __RW uint32_t DECOUPLE_SCALING; /* 0xE8: decoupling scaling ratio */
56  __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */
57  __W uint32_t STATUS; /* 0xFC: irq_status */
58  } VDVQ_CHAN[2];
59  __W uint32_t DQ_ADC_SW_READY; /* 0x200: enable d/q chan software inject adc value */
60 } CLC_Type;
61 
62 
63 /* Bitfield definition for register of struct array VDVQ_CHAN: MODE */
64 /*
65  * ENABLE_CLC (RW)
66  *
67  * enable CLC
68  */
69 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK (0x80000000UL)
70 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT (31U)
71 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK)
72 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT)
73 
74 /*
75  * MASK_MODE (RW)
76  *
77  * open mode: CLC keep working even if bad irq status ocurred
78  */
79 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK (0x1000000UL)
80 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT (24U)
81 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK)
82 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT)
83 
84 /*
85  * DQ_MODE (RW)
86  *
87  * dq mode
88  */
89 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK (0x10000UL)
90 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT (16U)
91 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK)
92 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT)
93 
94 /*
95  * ENABLE_IRQ (RW)
96  *
97  * enable irq:
98  * irq_data_in_forbid , // 10
99  * irq_forb_err_boundary , // 9
100  * irq_p3z3_over_lo , // 8
101  * irq_p3z3_over_hi , // 7
102  * irq_p3z3_err_boundary , // 6
103  * irq_z2_over_sf , // 5
104  * irq_z2_over_lo , // 4
105  * irq_z2_over_hi , // 3
106  * irq_z2_err_boundary , // 2
107  * irq_coef_err_boundary , // 1
108  * irq_valid_clc // 0
109  */
110 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK (0x7FFU)
111 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT (0U)
112 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK)
113 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT)
114 
115 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_EXPECT */
116 /*
117  * ADC_EXPECT (RW)
118  *
119  * adc expect value
120  */
121 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK (0xFFFFFFFFUL)
122 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT (0U)
123 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK)
124 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK) >> CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT)
125 
126 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_CHAN */
127 /*
128  * ADC_CHAN (RW)
129  *
130  * adc used chan ID
131  */
132 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK (0x1FU)
133 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT (0U)
134 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK)
135 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK) >> CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT)
136 
137 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_OFFSET */
138 /*
139  * ADC_OFFSET (RW)
140  *
141  * adc used offset
142  */
143 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK (0xFFFFFFFFUL)
144 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT (0U)
145 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK)
146 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK) >> CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT)
147 
148 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_LOWTH */
149 /*
150  * EADC_LOWTH (RW)
151  *
152  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
153  */
154 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK (0xFFFFFFFFUL)
155 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT (0U)
156 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK)
157 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT)
158 
159 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_HIGHTH */
160 /*
161  * EADC_HIGHTH (RW)
162  *
163  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
164  */
165 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK (0xFFFFFFFFUL)
166 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT (0U)
167 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK)
168 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT)
169 
170 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_MIDLOWTH */
171 /*
172  * EADC_MIDLOWTH (RW)
173  *
174  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
175  */
176 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK (0xFFFFFFFFUL)
177 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT (0U)
178 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK)
179 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT)
180 
181 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_MIDHIGHTH */
182 /*
183  * EADC_MIDHIGHTH (RW)
184  *
185  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
186  */
187 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK (0xFFFFFFFFUL)
188 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT (0U)
189 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK)
190 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT)
191 
192 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CLAMP_LO */
193 /*
194  * 2P2Z_CLAMP_LO (RW)
195  *
196  * 2p2z output clamp low threshold
197  */
198 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK (0xFFFFFFFFUL)
199 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT (0U)
200 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK)
201 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT)
202 
203 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CLAMP_HI */
204 /*
205  * 2P2Z_CLAMP_HI (RW)
206  *
207  * 2p2z output clamp high threshold
208  */
209 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK (0xFFFFFFFFUL)
210 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT (0U)
211 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK)
212 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT)
213 
214 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CLAMP_LO */
215 /*
216  * 3P3Z_CLAMP_LO (RW)
217  *
218  * 3p3z output clamp low threshold
219  */
220 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK (0xFFFFFFFFUL)
221 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT (0U)
222 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK)
223 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT)
224 
225 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CLAMP_HI */
226 /*
227  * 3P3Z_CLAMP_HI (RW)
228  *
229  * 3p3z output clamp high threshold
230  */
231 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK (0xFFFFFFFFUL)
232 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT (0U)
233 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK)
234 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT)
235 
236 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B0 */
237 /*
238  * COEFF_B0 (RW)
239  *
240  * coefficient b0
241  */
242 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK (0xFFFFFFFFUL)
243 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT (0U)
244 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK)
245 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT)
246 
247 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B1 */
248 /*
249  * COEFF_B1 (RW)
250  *
251  * coefficient b1
252  */
253 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK (0xFFFFFFFFUL)
254 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT (0U)
255 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK)
256 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT)
257 
258 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B2 */
259 /*
260  * COEFF_B2 (RW)
261  *
262  * coefficient b2
263  */
264 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK (0xFFFFFFFFUL)
265 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT (0U)
266 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK)
267 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT)
268 
269 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B3 */
270 /*
271  * COEFF_B3 (RW)
272  *
273  * coefficient b3
274  */
275 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK (0xFFFFFFFFUL)
276 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT (0U)
277 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK)
278 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT)
279 
280 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A0 */
281 /*
282  * COEFF_A0 (RW)
283  *
284  * coefficient a0
285  */
286 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK (0xFFFFFFFFUL)
287 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT (0U)
288 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK)
289 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT)
290 
291 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A1 */
292 /*
293  * COEFF_A1 (RW)
294  *
295  * coefficient a1
296  */
297 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK (0xFFFFFFFFUL)
298 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT (0U)
299 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK)
300 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT)
301 
302 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A2 */
303 /*
304  * COEFF_A2 (RW)
305  *
306  * coefficient a2
307  */
308 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK (0xFFFFFFFFUL)
309 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT (0U)
310 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK)
311 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT)
312 
313 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_KS */
314 /*
315  * COEFF_KSCALING (RW)
316  *
317  * coefficient kscaling
318  */
319 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK (0x1FU)
320 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT (0U)
321 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK)
322 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT)
323 
324 /* Bitfield definition for register of struct array VDVQ_CHAN: PWM_PERIOD */
325 /*
326  * PWM_PERIOD (RW)
327  *
328  * pwm_period
329  */
330 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK (0xFFFFFFFFUL)
331 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT (0U)
332 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK)
333 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK) >> CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT)
334 
335 /* Bitfield definition for register of struct array VDVQ_CHAN: OUTPUT_VALUE */
336 /*
337  * OUTPUT_VALUE (RO)
338  *
339  * output_value
340  */
341 #define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK (0xFFFFFFFFUL)
342 #define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT (0U)
343 #define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK) >> CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT)
344 
345 /* Bitfield definition for register of struct array VDVQ_CHAN: TIMESTAMP */
346 /*
347  * TIMESTAMP (RO)
348  *
349  * timestamp
350  */
351 #define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL)
352 #define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT (0U)
353 #define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK) >> CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT)
354 
355 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_CURR */
356 /*
357  * EADC_CURR (RW)
358  *
359  * error adc latest value
360  */
361 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK (0xFFFFFFFFUL)
362 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT (0U)
363 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK)
364 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK) >> CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT)
365 
366 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_PRE0 */
367 /*
368  * EADC_PRE0 (RW)
369  *
370  * error adc previous 0 value
371  */
372 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK (0xFFFFFFFFUL)
373 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT (0U)
374 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK)
375 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK) >> CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT)
376 
377 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_PRE1 */
378 /*
379  * EADC_PRE1 (RW)
380  *
381  * error adc previous 1 value
382  */
383 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK (0xFFFFFFFFUL)
384 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT (0U)
385 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK)
386 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK) >> CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT)
387 
388 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CURR */
389 /*
390  * 2P2Z_CURR (RW)
391  *
392  * 2p2z latest value
393  */
394 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK (0xFFFFFFFFUL)
395 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT (0U)
396 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK)
397 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK) >> CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT)
398 
399 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_PRE0 */
400 /*
401  * 2P2Z_PRE0 (RW)
402  *
403  * 2p2z previous 0 value
404  */
405 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK (0xFFFFFFFFUL)
406 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT (0U)
407 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK)
408 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK) >> CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT)
409 
410 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CURR */
411 /*
412  * 3P3Z_CURR (RW)
413  *
414  * 3p3z latest value
415  */
416 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK (0xFFFFFFFFUL)
417 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT (0U)
418 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK)
419 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK) >> CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT)
420 
421 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_LO */
422 /*
423  * 3P3Z_FORBID_LO (RW)
424  *
425  * 3p3z output forbid low threshold
426  */
427 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK (0xFFFFFFFFUL)
428 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT (0U)
429 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK)
430 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT)
431 
432 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_MD */
433 /*
434  * 3P3Z_FORBID_MD (RW)
435  *
436  * 3p3z output forbid middle threshold
437  */
438 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK (0xFFFFFFFFUL)
439 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT (0U)
440 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK)
441 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT)
442 
443 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_HI */
444 /*
445  * 3P3Z_FORBID_HI (RW)
446  *
447  * 3p3z output forbid high threshold
448  */
449 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK (0xFFFFFFFFUL)
450 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT (0U)
451 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK)
452 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT)
453 
454 /* Bitfield definition for register of struct array VDVQ_CHAN: LIND */
455 /*
456  * LIND (RW)
457  *
458  * VD/VQ inductance used in decoupling
459  */
460 #define CLC_VDVQ_CHAN_LIND_LIND_MASK (0xFFFFFFFFUL)
461 #define CLC_VDVQ_CHAN_LIND_LIND_SHIFT (0U)
462 #define CLC_VDVQ_CHAN_LIND_LIND_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_LIND_LIND_SHIFT) & CLC_VDVQ_CHAN_LIND_LIND_MASK)
463 #define CLC_VDVQ_CHAN_LIND_LIND_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_LIND_LIND_MASK) >> CLC_VDVQ_CHAN_LIND_LIND_SHIFT)
464 
465 /* Bitfield definition for register of struct array VDVQ_CHAN: KE */
466 /*
467  * KE (RW)
468  *
469  * VD/VQ inductance used in decoupling
470  */
471 #define CLC_VDVQ_CHAN_KE_KE_MASK (0xFFFFFFFFUL)
472 #define CLC_VDVQ_CHAN_KE_KE_SHIFT (0U)
473 #define CLC_VDVQ_CHAN_KE_KE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_KE_KE_SHIFT) & CLC_VDVQ_CHAN_KE_KE_MASK)
474 #define CLC_VDVQ_CHAN_KE_KE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_KE_KE_MASK) >> CLC_VDVQ_CHAN_KE_KE_SHIFT)
475 
476 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_SW */
477 /*
478  * ADC_SW (RW)
479  *
480  * adc software inject value
481  */
482 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK (0xFFFFFFFFUL)
483 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT (0U)
484 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK)
485 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK) >> CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT)
486 
487 /* Bitfield definition for register of struct array VDVQ_CHAN: SPEED_SW */
488 /*
489  * SPEED_SW (RW)
490  *
491  * speed software inject value
492  */
493 #define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK (0xFFFFFFFFUL)
494 #define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT (0U)
495 #define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT) & CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK)
496 #define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK) >> CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT)
497 
498 /* Bitfield definition for register of struct array VDVQ_CHAN: DECOUPLE_SCALING */
499 /*
500  * DECOUPLE_SCALING (RW)
501  *
502  * decoupling scaling ratio
503  */
504 #define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK (0xFFFFFFFFUL)
505 #define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT (0U)
506 #define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT) & CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK)
507 #define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK) >> CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT)
508 
509 /* Bitfield definition for register of struct array VDVQ_CHAN: STATUS */
510 /*
511  * STATUS (W1C)
512  *
513  * status, write 1 to clear it. :
514  * irq_data_in_forbid , // 10
515  * irq_forb_err_boundary , // 9
516  * irq_p3z3_over_lo , // 8
517  * irq_p3z3_over_hi , // 7
518  * irq_p3z3_err_boundary , // 6
519  * irq_z2_over_sf , // 5
520  * irq_z2_over_lo , // 4
521  * irq_z2_over_hi , // 3
522  * irq_z2_err_boundary , // 2
523  * irq_coef_err_boundary , // 1
524  * irq_valid_clc // 0
525  */
526 #define CLC_VDVQ_CHAN_STATUS_STATUS_MASK (0x7FFU)
527 #define CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT (0U)
528 #define CLC_VDVQ_CHAN_STATUS_STATUS_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK)
529 #define CLC_VDVQ_CHAN_STATUS_STATUS_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK) >> CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT)
530 
531 /* Bitfield definition for register: DQ_ADC_SW_READY */
532 /*
533  * DQ_ADC_SW_READY (W1C)
534  *
535  * enable d/q chan software inject adc value
536  */
537 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK (0x1U)
538 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT (0U)
539 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SET(x) (((uint32_t)(x) << CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK)
540 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_GET(x) (((uint32_t)(x) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK) >> CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT)
541 
542 
543 
544 /* COEFF register group index macro definition */
545 #define CLC_COEFF_0 (0UL)
546 #define CLC_COEFF_1 (1UL)
547 #define CLC_COEFF_2 (2UL)
548 
549 /* VDVQ_CHAN register group index macro definition */
550 #define CLC_VDVQ_CHAN_VD (0UL)
551 #define CLC_VDVQ_CHAN_VQ (1UL)
552 
553 
554 #endif /* HPM_CLC_H */
CLC_Type
Definition: hpm_clc_regs.h:12