hpm_clc_regs.h File Reference

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Data Structures
struct	CLC_Type

Macros
#define	CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK   (0x80000000UL)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT   (31U)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_CLC_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT)
#define	CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK   (0x1000000UL)
#define	CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT   (24U)
#define	CLC_VDVQ_CHAN_MODE_MASK_MODE_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK)
#define	CLC_VDVQ_CHAN_MODE_MASK_MODE_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT)
#define	CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK   (0x10000UL)
#define	CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT   (16U)
#define	CLC_VDVQ_CHAN_MODE_DQ_MODE_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK)
#define	CLC_VDVQ_CHAN_MODE_DQ_MODE_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK   (0x7FFU)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK)
#define	CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT)
#define	CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK)
#define	CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK) >> CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT)
#define	CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK   (0x1FU)
#define	CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK)
#define	CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK) >> CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT)
#define	CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK)
#define	CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK) >> CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK)
#define	CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK)
#define	CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK)
#define	CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK)
#define	CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK)
#define	CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK)
#define	CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK   (0x1FU)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK)
#define	CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT)
#define	CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK)
#define	CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK) >> CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT)
#define	CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK) >> CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT)
#define	CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK) >> CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK)
#define	CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK) >> CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK)
#define	CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK) >> CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT)
#define	CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK)
#define	CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK) >> CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT)
#define	CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK)
#define	CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK) >> CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT)
#define	CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK)
#define	CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK) >> CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT)
#define	CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK)
#define	CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK) >> CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK)
#define	CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT)
#define	CLC_VDVQ_CHAN_LIND_LIND_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_LIND_LIND_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_LIND_LIND_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_LIND_LIND_SHIFT) & CLC_VDVQ_CHAN_LIND_LIND_MASK)
#define	CLC_VDVQ_CHAN_LIND_LIND_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_LIND_LIND_MASK) >> CLC_VDVQ_CHAN_LIND_LIND_SHIFT)
#define	CLC_VDVQ_CHAN_KE_KE_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_KE_KE_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_KE_KE_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_KE_KE_SHIFT) & CLC_VDVQ_CHAN_KE_KE_MASK)
#define	CLC_VDVQ_CHAN_KE_KE_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_KE_KE_MASK) >> CLC_VDVQ_CHAN_KE_KE_SHIFT)
#define	CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK)
#define	CLC_VDVQ_CHAN_ADC_SW_ADC_SW_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK) >> CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT)
#define	CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT) & CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK)
#define	CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK) >> CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT)
#define	CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK   (0xFFFFFFFFUL)
#define	CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT) & CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK)
#define	CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK) >> CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT)
#define	CLC_VDVQ_CHAN_STATUS_STATUS_MASK   (0x7FFU)
#define	CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT   (0U)
#define	CLC_VDVQ_CHAN_STATUS_STATUS_SET(x)   (((uint32_t)(x) << CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK)
#define	CLC_VDVQ_CHAN_STATUS_STATUS_GET(x)   (((uint32_t)(x) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK) >> CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT)
#define	CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK   (0x1U)
#define	CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT   (0U)
#define	CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SET(x)   (((uint32_t)(x) << CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK)
#define	CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_GET(x)   (((uint32_t)(x) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK) >> CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT)
#define	CLC_COEFF_0   (0UL)
#define	CLC_COEFF_1   (1UL)
#define	CLC_COEFF_2   (2UL)
#define	CLC_VDVQ_CHAN_VD   (0UL)
#define	CLC_VDVQ_CHAN_VQ   (1UL)

Macro Definition Documentation

CLC_COEFF_0

#define CLC_COEFF_0   (0UL)

CLC_COEFF_1

#define CLC_COEFF_1   (1UL)

CLC_COEFF_2

#define CLC_COEFF_2   (2UL)

CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_GET

#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_GET

(

x

)

(((uint32_t)(x) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK) >> CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT)

CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK

#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK   (0x1U)

CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SET

#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SET

(

x

)

(((uint32_t)(x) << CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK)

CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT

#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT   (0U)

CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_GET

#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK) >> CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT)

CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK

#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK   (0x1FU)

CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SET

#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK)

CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT

#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT   (0U)

CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_GET

#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK) >> CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT)

CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK

#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SET

#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK)

CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT

#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT   (0U)

CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_GET

#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK) >> CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT)

CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK

#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SET

#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK)

CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT

#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT   (0U)

CLC_VDVQ_CHAN_ADC_SW_ADC_SW_GET

#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK) >> CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT)

CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK

#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SET

#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK)

CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT

#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT   (0U)

CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_GET

#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT)

CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK

#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK   (0x1FU)

CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SET

#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK)

CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT

#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT   (0U)

CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_GET

#define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK) >> CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT)

CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK

#define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SET

#define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT) & CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_MASK)

CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT

#define CLC_VDVQ_CHAN_DECOUPLE_SCALING_DECOUPLE_SCALING_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_GET

#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK) >> CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT)

CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK

#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SET

#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK)

CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT

#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_GET

#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT)

CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK

#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SET

#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK)

CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT

#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_GET

#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT)

CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK

#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SET

#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK)

CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT

#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_GET

#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT)

CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK

#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SET

#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK)

CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT

#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_GET

#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT)

CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK

#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SET

#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK)

CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT

#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_GET

#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK) >> CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT)

CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK

#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SET

#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK)

CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT

#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT   (0U)

CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_GET

#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK) >> CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT)

CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK

#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SET

#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK)

CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT

#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT   (0U)

CLC_VDVQ_CHAN_KE_KE_GET

#define CLC_VDVQ_CHAN_KE_KE_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_KE_KE_MASK) >> CLC_VDVQ_CHAN_KE_KE_SHIFT)

CLC_VDVQ_CHAN_KE_KE_MASK

#define CLC_VDVQ_CHAN_KE_KE_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_KE_KE_SET

#define CLC_VDVQ_CHAN_KE_KE_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_KE_KE_SHIFT) & CLC_VDVQ_CHAN_KE_KE_MASK)

CLC_VDVQ_CHAN_KE_KE_SHIFT

#define CLC_VDVQ_CHAN_KE_KE_SHIFT   (0U)

CLC_VDVQ_CHAN_LIND_LIND_GET

#define CLC_VDVQ_CHAN_LIND_LIND_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_LIND_LIND_MASK) >> CLC_VDVQ_CHAN_LIND_LIND_SHIFT)

CLC_VDVQ_CHAN_LIND_LIND_MASK

#define CLC_VDVQ_CHAN_LIND_LIND_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_LIND_LIND_SET

#define CLC_VDVQ_CHAN_LIND_LIND_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_LIND_LIND_SHIFT) & CLC_VDVQ_CHAN_LIND_LIND_MASK)

CLC_VDVQ_CHAN_LIND_LIND_SHIFT

#define CLC_VDVQ_CHAN_LIND_LIND_SHIFT   (0U)

CLC_VDVQ_CHAN_MODE_DQ_MODE_GET

#define CLC_VDVQ_CHAN_MODE_DQ_MODE_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT)

CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK

#define CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK   (0x10000UL)

CLC_VDVQ_CHAN_MODE_DQ_MODE_SET

#define CLC_VDVQ_CHAN_MODE_DQ_MODE_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK)

CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT

#define CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT   (16U)

CLC_VDVQ_CHAN_MODE_ENABLE_CLC_GET

#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT)

CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK

#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK   (0x80000000UL)

CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SET

#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK)

CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT

#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT   (31U)

CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_GET

#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT)

CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK

#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK   (0x7FFU)

CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET

#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK)

CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT

#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT   (0U)

CLC_VDVQ_CHAN_MODE_MASK_MODE_GET

#define CLC_VDVQ_CHAN_MODE_MASK_MODE_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT)

CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK

#define CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK   (0x1000000UL)

CLC_VDVQ_CHAN_MODE_MASK_MODE_SET

#define CLC_VDVQ_CHAN_MODE_MASK_MODE_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK)

CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT

#define CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT   (24U)

CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_GET

#define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK) >> CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT)

CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK

#define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT

#define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT   (0U)

CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_GET

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT)

CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SET

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK)

CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT   (0U)

CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_GET

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT)

CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SET

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK)

CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT

#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT   (0U)

CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_GET

#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK) >> CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT)

CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK

#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SET

#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK)

CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT

#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT   (0U)

CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_GET

#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK) >> CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT)

CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK

#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SET

#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK)

CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT

#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT   (0U)

CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_GET

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT)

CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SET

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK)

CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT   (0U)

CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_GET

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT)

CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SET

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK)

CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT

#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT   (0U)

CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_GET

#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK) >> CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT)

CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK

#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SET

#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK)

CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT

#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT   (0U)

CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_GET

#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT)

CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK

#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SET

#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK)

CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT

#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT   (0U)

CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_GET

#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT)

CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK

#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SET

#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK)

CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT

#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT   (0U)

CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_GET

#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT)

CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK

#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SET

#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK)

CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT

#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT   (0U)

CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_GET

#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK) >> CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT)

CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK

#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SET

#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK)

CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT

#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT   (0U)

CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_GET

#define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK) >> CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT)

CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK

#define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SET

#define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT) & CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_MASK)

CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT

#define CLC_VDVQ_CHAN_SPEED_SW_SPEED_SW_SHIFT   (0U)

CLC_VDVQ_CHAN_STATUS_STATUS_GET

#define CLC_VDVQ_CHAN_STATUS_STATUS_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK) >> CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT)

CLC_VDVQ_CHAN_STATUS_STATUS_MASK

#define CLC_VDVQ_CHAN_STATUS_STATUS_MASK   (0x7FFU)

CLC_VDVQ_CHAN_STATUS_STATUS_SET

#define CLC_VDVQ_CHAN_STATUS_STATUS_SET

(

x

)

(((uint32_t)(x) << CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK)

CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT

#define CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT   (0U)

CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_GET

#define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_GET

(

x

)

(((uint32_t)(x) & CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK) >> CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT)

CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK

#define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK   (0xFFFFFFFFUL)

CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT

#define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT   (0U)

CLC_VDVQ_CHAN_VD

#define CLC_VDVQ_CHAN_VD   (0UL)

CLC_VDVQ_CHAN_VQ

#define CLC_VDVQ_CHAN_VQ   (1UL)