Data Structures
struct	I2S_Type

Macros
#define	I2S_CTRL_FRC_ALIGN_FBUF_MASK (0x80000UL)

#define	I2S_CTRL_FRC_ALIGN_FBUF_SHIFT (19U)

#define	I2S_CTRL_FRC_ALIGN_FBUF_SET(x) (((uint32_t)(x) << I2S_CTRL_FRC_ALIGN_FBUF_SHIFT) & I2S_CTRL_FRC_ALIGN_FBUF_MASK)

#define	I2S_CTRL_FRC_ALIGN_FBUF_GET(x) (((uint32_t)(x) & I2S_CTRL_FRC_ALIGN_FBUF_MASK) >> I2S_CTRL_FRC_ALIGN_FBUF_SHIFT)

#define	I2S_CTRL_SFTRST_RX_MASK (0x40000UL)

#define	I2S_CTRL_SFTRST_RX_SHIFT (18U)

#define	I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK)

#define	I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT)

#define	I2S_CTRL_SFTRST_TX_MASK (0x20000UL)

#define	I2S_CTRL_SFTRST_TX_SHIFT (17U)

#define	I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK)

#define	I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT)

#define	I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL)

#define	I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U)

#define	I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK)

#define	I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT)

#define	I2S_CTRL_TXDNIE_MASK (0x8000U)

#define	I2S_CTRL_TXDNIE_SHIFT (15U)

#define	I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK)

#define	I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT)

#define	I2S_CTRL_RXDAIE_MASK (0x4000U)

#define	I2S_CTRL_RXDAIE_SHIFT (14U)

#define	I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK)

#define	I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT)

#define	I2S_CTRL_ERRIE_MASK (0x2000U)

#define	I2S_CTRL_ERRIE_SHIFT (13U)

#define	I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK)

#define	I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT)

#define	I2S_CTRL_TX_DMA_EN_MASK (0x1000U)

#define	I2S_CTRL_TX_DMA_EN_SHIFT (12U)

#define	I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK)

#define	I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT)

#define	I2S_CTRL_RX_DMA_EN_MASK (0x800U)

#define	I2S_CTRL_RX_DMA_EN_SHIFT (11U)

#define	I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK)

#define	I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT)

#define	I2S_CTRL_TXFIFOCLR_MASK (0x400U)

#define	I2S_CTRL_TXFIFOCLR_SHIFT (10U)

#define	I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK)

#define	I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT)

#define	I2S_CTRL_RXFIFOCLR_MASK (0x200U)

#define	I2S_CTRL_RXFIFOCLR_SHIFT (9U)

#define	I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK)

#define	I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT)

#define	I2S_CTRL_TX_EN_MASK (0x1E0U)

#define	I2S_CTRL_TX_EN_SHIFT (5U)

#define	I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK)

#define	I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT)

#define	I2S_CTRL_RX_EN_MASK (0x1EU)

#define	I2S_CTRL_RX_EN_SHIFT (1U)

#define	I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK)

#define	I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT)

#define	I2S_CTRL_I2S_EN_MASK (0x1U)

#define	I2S_CTRL_I2S_EN_SHIFT (0U)

#define	I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK)

#define	I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT)

#define	I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL)

#define	I2S_RFIFO_FILLINGS_RX3_SHIFT (24U)

#define	I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT)

#define	I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL)

#define	I2S_RFIFO_FILLINGS_RX2_SHIFT (16U)

#define	I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT)

#define	I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U)

#define	I2S_RFIFO_FILLINGS_RX1_SHIFT (8U)

#define	I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT)

#define	I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU)

#define	I2S_RFIFO_FILLINGS_RX0_SHIFT (0U)

#define	I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT)

#define	I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL)

#define	I2S_TFIFO_FILLINGS_TX3_SHIFT (24U)

#define	I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT)

#define	I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL)

#define	I2S_TFIFO_FILLINGS_TX2_SHIFT (16U)

#define	I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT)

#define	I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U)

#define	I2S_TFIFO_FILLINGS_TX1_SHIFT (8U)

#define	I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT)

#define	I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU)

#define	I2S_TFIFO_FILLINGS_TX0_SHIFT (0U)

#define	I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT)

#define	I2S_FIFO_THRESH_TX_MASK (0xFF00U)

#define	I2S_FIFO_THRESH_TX_SHIFT (8U)

#define	I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK)

#define	I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT)

#define	I2S_FIFO_THRESH_RX_MASK (0xFFU)

#define	I2S_FIFO_THRESH_RX_SHIFT (0U)

#define	I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK)

#define	I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT)

#define	I2S_STA_TX_UD_MASK (0x1E000UL)

#define	I2S_STA_TX_UD_SHIFT (13U)

#define	I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK)

#define	I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT)

#define	I2S_STA_RX_OV_MASK (0x1E00U)

#define	I2S_STA_RX_OV_SHIFT (9U)

#define	I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK)

#define	I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT)

#define	I2S_STA_TX_DN_MASK (0x1E0U)

#define	I2S_STA_TX_DN_SHIFT (5U)

#define	I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT)

#define	I2S_STA_RX_DA_MASK (0x1EU)

#define	I2S_STA_RX_DA_SHIFT (1U)

#define	I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT)

#define	I2S_RXD_D_MASK (0xFFFFFFFFUL)

#define	I2S_RXD_D_SHIFT (0U)

#define	I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT)

#define	I2S_TXD_D_MASK (0xFFFFFFFFUL)

#define	I2S_TXD_D_SHIFT (0U)

#define	I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK)

#define	I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT)

#define	I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL)

#define	I2S_CFGR_BCLK_GATEOFF_SHIFT (30U)

#define	I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK)

#define	I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT)

#define	I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL)

#define	I2S_CFGR_BCLK_DIV_SHIFT (21U)

#define	I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK)

#define	I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT)

#define	I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL)

#define	I2S_CFGR_INV_BCLK_OUT_SHIFT (20U)

#define	I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK)

#define	I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT)

#define	I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL)

#define	I2S_CFGR_INV_BCLK_IN_SHIFT (19U)

#define	I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK)

#define	I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT)

#define	I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL)

#define	I2S_CFGR_INV_FCLK_OUT_SHIFT (18U)

#define	I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK)

#define	I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT)

#define	I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL)

#define	I2S_CFGR_INV_FCLK_IN_SHIFT (17U)

#define	I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK)

#define	I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT)

#define	I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL)

#define	I2S_CFGR_INV_MCLK_OUT_SHIFT (16U)

#define	I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK)

#define	I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT)

#define	I2S_CFGR_INV_MCLK_IN_MASK (0x8000U)

#define	I2S_CFGR_INV_MCLK_IN_SHIFT (15U)

#define	I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK)

#define	I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT)

#define	I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U)

#define	I2S_CFGR_BCLK_SEL_OP_SHIFT (14U)

#define	I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK)

#define	I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT)

#define	I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U)

#define	I2S_CFGR_FCLK_SEL_OP_SHIFT (13U)

#define	I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK)

#define	I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT)

#define	I2S_CFGR_MCK_SEL_OP_MASK (0x1000U)

#define	I2S_CFGR_MCK_SEL_OP_SHIFT (12U)

#define	I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK)

#define	I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT)

#define	I2S_CFGR_FRAME_EDGE_MASK (0x800U)

#define	I2S_CFGR_FRAME_EDGE_SHIFT (11U)

#define	I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK)

#define	I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT)

#define	I2S_CFGR_CH_MAX_MASK (0x7C0U)

#define	I2S_CFGR_CH_MAX_SHIFT (6U)

#define	I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK)

#define	I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT)

#define	I2S_CFGR_TDM_EN_MASK (0x20U)

#define	I2S_CFGR_TDM_EN_SHIFT (5U)

#define	I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK)

#define	I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT)

#define	I2S_CFGR_STD_MASK (0x18U)

#define	I2S_CFGR_STD_SHIFT (3U)

#define	I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK)

#define	I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT)

#define	I2S_CFGR_DATSIZ_MASK (0x6U)

#define	I2S_CFGR_DATSIZ_SHIFT (1U)

#define	I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK)

#define	I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT)

#define	I2S_CFGR_CHSIZ_MASK (0x1U)

#define	I2S_CFGR_CHSIZ_SHIFT (0U)

#define	I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK)

#define	I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT)

#define	I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U)

#define	I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U)

#define	I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK)

#define	I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT)

#define	I2S_MISC_CFGR_MCLKOE_MASK (0x1U)

#define	I2S_MISC_CFGR_MCLKOE_SHIFT (0U)

#define	I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK)

#define	I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT)

#define	I2S_RXDSLOT_EN_MASK (0xFFFFU)

#define	I2S_RXDSLOT_EN_SHIFT (0U)

#define	I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK)

#define	I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT)

#define	I2S_TXDSLOT_EN_MASK (0xFFFFU)

#define	I2S_TXDSLOT_EN_SHIFT (0U)

#define	I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK)

#define	I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT)

#define	I2S_RXD_DATA0 (0UL)

#define	I2S_RXD_DATA1 (1UL)

#define	I2S_RXD_DATA2 (2UL)

#define	I2S_RXD_DATA3 (3UL)

#define	I2S_TXD_DATA0 (0UL)

#define	I2S_TXD_DATA1 (1UL)

#define	I2S_TXD_DATA2 (2UL)

#define	I2S_TXD_DATA3 (3UL)

#define	I2S_RXDSLOT_DATA0 (0UL)

#define	I2S_RXDSLOT_DATA1 (1UL)

#define	I2S_RXDSLOT_DATA2 (2UL)

#define	I2S_RXDSLOT_DATA3 (3UL)

#define	I2S_TXDSLOT_DATA0 (0UL)

#define	I2S_TXDSLOT_DATA1 (1UL)

#define	I2S_TXDSLOT_DATA2 (2UL)

#define	I2S_TXDSLOT_DATA3 (3UL)

Macro Definition Documentation

◆ I2S_CFGR_BCLK_DIV_GET

#define I2S_CFGR_BCLK_DIV_GET ( x ) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT)

◆ I2S_CFGR_BCLK_DIV_MASK

#define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL)

◆ I2S_CFGR_BCLK_DIV_SET

#define I2S_CFGR_BCLK_DIV_SET ( x ) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK)

◆ I2S_CFGR_BCLK_DIV_SHIFT

#define I2S_CFGR_BCLK_DIV_SHIFT (21U)

◆ I2S_CFGR_BCLK_GATEOFF_GET

#define I2S_CFGR_BCLK_GATEOFF_GET ( x ) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT)

◆ I2S_CFGR_BCLK_GATEOFF_MASK

#define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL)

◆ I2S_CFGR_BCLK_GATEOFF_SET

#define I2S_CFGR_BCLK_GATEOFF_SET ( x ) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK)

◆ I2S_CFGR_BCLK_GATEOFF_SHIFT

#define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U)

◆ I2S_CFGR_BCLK_SEL_OP_GET

#define I2S_CFGR_BCLK_SEL_OP_GET ( x ) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT)

◆ I2S_CFGR_BCLK_SEL_OP_MASK

#define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U)

◆ I2S_CFGR_BCLK_SEL_OP_SET

#define I2S_CFGR_BCLK_SEL_OP_SET ( x ) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK)

◆ I2S_CFGR_BCLK_SEL_OP_SHIFT

#define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U)

◆ I2S_CFGR_CH_MAX_GET

#define I2S_CFGR_CH_MAX_GET ( x ) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT)

◆ I2S_CFGR_CH_MAX_MASK

#define I2S_CFGR_CH_MAX_MASK (0x7C0U)

◆ I2S_CFGR_CH_MAX_SET

#define I2S_CFGR_CH_MAX_SET ( x ) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK)

◆ I2S_CFGR_CH_MAX_SHIFT

#define I2S_CFGR_CH_MAX_SHIFT (6U)

◆ I2S_CFGR_CHSIZ_GET

#define I2S_CFGR_CHSIZ_GET ( x ) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT)

◆ I2S_CFGR_CHSIZ_MASK

#define I2S_CFGR_CHSIZ_MASK (0x1U)

◆ I2S_CFGR_CHSIZ_SET

#define I2S_CFGR_CHSIZ_SET ( x ) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK)

◆ I2S_CFGR_CHSIZ_SHIFT

#define I2S_CFGR_CHSIZ_SHIFT (0U)

◆ I2S_CFGR_DATSIZ_GET

#define I2S_CFGR_DATSIZ_GET ( x ) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT)

◆ I2S_CFGR_DATSIZ_MASK

#define I2S_CFGR_DATSIZ_MASK (0x6U)

◆ I2S_CFGR_DATSIZ_SET

#define I2S_CFGR_DATSIZ_SET ( x ) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK)

◆ I2S_CFGR_DATSIZ_SHIFT

#define I2S_CFGR_DATSIZ_SHIFT (1U)

◆ I2S_CFGR_FCLK_SEL_OP_GET

#define I2S_CFGR_FCLK_SEL_OP_GET ( x ) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT)

◆ I2S_CFGR_FCLK_SEL_OP_MASK

#define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U)

◆ I2S_CFGR_FCLK_SEL_OP_SET

#define I2S_CFGR_FCLK_SEL_OP_SET ( x ) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK)

◆ I2S_CFGR_FCLK_SEL_OP_SHIFT

#define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U)

◆ I2S_CFGR_FRAME_EDGE_GET

#define I2S_CFGR_FRAME_EDGE_GET ( x ) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT)

◆ I2S_CFGR_FRAME_EDGE_MASK

#define I2S_CFGR_FRAME_EDGE_MASK (0x800U)

◆ I2S_CFGR_FRAME_EDGE_SET

#define I2S_CFGR_FRAME_EDGE_SET ( x ) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK)

◆ I2S_CFGR_FRAME_EDGE_SHIFT

#define I2S_CFGR_FRAME_EDGE_SHIFT (11U)

◆ I2S_CFGR_INV_BCLK_IN_GET

#define I2S_CFGR_INV_BCLK_IN_GET ( x ) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT)

◆ I2S_CFGR_INV_BCLK_IN_MASK

#define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL)

◆ I2S_CFGR_INV_BCLK_IN_SET

#define I2S_CFGR_INV_BCLK_IN_SET ( x ) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK)

◆ I2S_CFGR_INV_BCLK_IN_SHIFT

#define I2S_CFGR_INV_BCLK_IN_SHIFT (19U)

◆ I2S_CFGR_INV_BCLK_OUT_GET

#define I2S_CFGR_INV_BCLK_OUT_GET ( x ) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT)

◆ I2S_CFGR_INV_BCLK_OUT_MASK

#define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL)

◆ I2S_CFGR_INV_BCLK_OUT_SET

#define I2S_CFGR_INV_BCLK_OUT_SET ( x ) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK)

◆ I2S_CFGR_INV_BCLK_OUT_SHIFT

#define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U)

◆ I2S_CFGR_INV_FCLK_IN_GET

#define I2S_CFGR_INV_FCLK_IN_GET ( x ) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT)

◆ I2S_CFGR_INV_FCLK_IN_MASK

#define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL)

◆ I2S_CFGR_INV_FCLK_IN_SET

#define I2S_CFGR_INV_FCLK_IN_SET ( x ) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK)

◆ I2S_CFGR_INV_FCLK_IN_SHIFT

#define I2S_CFGR_INV_FCLK_IN_SHIFT (17U)

◆ I2S_CFGR_INV_FCLK_OUT_GET

#define I2S_CFGR_INV_FCLK_OUT_GET ( x ) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT)

◆ I2S_CFGR_INV_FCLK_OUT_MASK

#define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL)

◆ I2S_CFGR_INV_FCLK_OUT_SET

#define I2S_CFGR_INV_FCLK_OUT_SET ( x ) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK)

◆ I2S_CFGR_INV_FCLK_OUT_SHIFT

#define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U)

◆ I2S_CFGR_INV_MCLK_IN_GET

#define I2S_CFGR_INV_MCLK_IN_GET ( x ) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT)

◆ I2S_CFGR_INV_MCLK_IN_MASK

#define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U)

◆ I2S_CFGR_INV_MCLK_IN_SET

#define I2S_CFGR_INV_MCLK_IN_SET ( x ) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK)

◆ I2S_CFGR_INV_MCLK_IN_SHIFT

#define I2S_CFGR_INV_MCLK_IN_SHIFT (15U)

◆ I2S_CFGR_INV_MCLK_OUT_GET

#define I2S_CFGR_INV_MCLK_OUT_GET ( x ) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT)

◆ I2S_CFGR_INV_MCLK_OUT_MASK

#define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL)

◆ I2S_CFGR_INV_MCLK_OUT_SET

#define I2S_CFGR_INV_MCLK_OUT_SET ( x ) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK)

◆ I2S_CFGR_INV_MCLK_OUT_SHIFT

#define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U)

◆ I2S_CFGR_MCK_SEL_OP_GET

#define I2S_CFGR_MCK_SEL_OP_GET ( x ) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT)

◆ I2S_CFGR_MCK_SEL_OP_MASK

#define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U)

◆ I2S_CFGR_MCK_SEL_OP_SET

#define I2S_CFGR_MCK_SEL_OP_SET ( x ) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK)

◆ I2S_CFGR_MCK_SEL_OP_SHIFT

#define I2S_CFGR_MCK_SEL_OP_SHIFT (12U)

◆ I2S_CFGR_STD_GET

#define I2S_CFGR_STD_GET ( x ) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT)

◆ I2S_CFGR_STD_MASK

#define I2S_CFGR_STD_MASK (0x18U)

◆ I2S_CFGR_STD_SET

#define I2S_CFGR_STD_SET ( x ) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK)

◆ I2S_CFGR_STD_SHIFT

#define I2S_CFGR_STD_SHIFT (3U)

◆ I2S_CFGR_TDM_EN_GET

#define I2S_CFGR_TDM_EN_GET ( x ) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT)

◆ I2S_CFGR_TDM_EN_MASK

#define I2S_CFGR_TDM_EN_MASK (0x20U)

◆ I2S_CFGR_TDM_EN_SET

#define I2S_CFGR_TDM_EN_SET ( x ) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK)

◆ I2S_CFGR_TDM_EN_SHIFT

#define I2S_CFGR_TDM_EN_SHIFT (5U)

◆ I2S_CTRL_ERRIE_GET

#define I2S_CTRL_ERRIE_GET ( x ) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT)

◆ I2S_CTRL_ERRIE_MASK

#define I2S_CTRL_ERRIE_MASK (0x2000U)

◆ I2S_CTRL_ERRIE_SET

#define I2S_CTRL_ERRIE_SET ( x ) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK)

◆ I2S_CTRL_ERRIE_SHIFT

#define I2S_CTRL_ERRIE_SHIFT (13U)

◆ I2S_CTRL_FRC_ALIGN_FBUF_GET

#define I2S_CTRL_FRC_ALIGN_FBUF_GET ( x ) (((uint32_t)(x) & I2S_CTRL_FRC_ALIGN_FBUF_MASK) >> I2S_CTRL_FRC_ALIGN_FBUF_SHIFT)

◆ I2S_CTRL_FRC_ALIGN_FBUF_MASK

#define I2S_CTRL_FRC_ALIGN_FBUF_MASK (0x80000UL)

◆ I2S_CTRL_FRC_ALIGN_FBUF_SET

#define I2S_CTRL_FRC_ALIGN_FBUF_SET ( x ) (((uint32_t)(x) << I2S_CTRL_FRC_ALIGN_FBUF_SHIFT) & I2S_CTRL_FRC_ALIGN_FBUF_MASK)

◆ I2S_CTRL_FRC_ALIGN_FBUF_SHIFT

#define I2S_CTRL_FRC_ALIGN_FBUF_SHIFT (19U)

◆ I2S_CTRL_I2S_EN_GET

#define I2S_CTRL_I2S_EN_GET ( x ) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT)

◆ I2S_CTRL_I2S_EN_MASK

#define I2S_CTRL_I2S_EN_MASK (0x1U)

◆ I2S_CTRL_I2S_EN_SET

#define I2S_CTRL_I2S_EN_SET ( x ) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK)

◆ I2S_CTRL_I2S_EN_SHIFT

#define I2S_CTRL_I2S_EN_SHIFT (0U)

◆ I2S_CTRL_RX_DMA_EN_GET

#define I2S_CTRL_RX_DMA_EN_GET ( x ) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT)

◆ I2S_CTRL_RX_DMA_EN_MASK

#define I2S_CTRL_RX_DMA_EN_MASK (0x800U)

◆ I2S_CTRL_RX_DMA_EN_SET

#define I2S_CTRL_RX_DMA_EN_SET ( x ) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK)

◆ I2S_CTRL_RX_DMA_EN_SHIFT

#define I2S_CTRL_RX_DMA_EN_SHIFT (11U)

◆ I2S_CTRL_RX_EN_GET

#define I2S_CTRL_RX_EN_GET ( x ) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT)

◆ I2S_CTRL_RX_EN_MASK

#define I2S_CTRL_RX_EN_MASK (0x1EU)

◆ I2S_CTRL_RX_EN_SET

#define I2S_CTRL_RX_EN_SET ( x ) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK)

◆ I2S_CTRL_RX_EN_SHIFT

#define I2S_CTRL_RX_EN_SHIFT (1U)

◆ I2S_CTRL_RXDAIE_GET

#define I2S_CTRL_RXDAIE_GET ( x ) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT)

◆ I2S_CTRL_RXDAIE_MASK

#define I2S_CTRL_RXDAIE_MASK (0x4000U)

◆ I2S_CTRL_RXDAIE_SET

#define I2S_CTRL_RXDAIE_SET ( x ) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK)

◆ I2S_CTRL_RXDAIE_SHIFT

#define I2S_CTRL_RXDAIE_SHIFT (14U)

◆ I2S_CTRL_RXFIFOCLR_GET

#define I2S_CTRL_RXFIFOCLR_GET ( x ) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT)

◆ I2S_CTRL_RXFIFOCLR_MASK

#define I2S_CTRL_RXFIFOCLR_MASK (0x200U)

◆ I2S_CTRL_RXFIFOCLR_SET

#define I2S_CTRL_RXFIFOCLR_SET ( x ) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK)

◆ I2S_CTRL_RXFIFOCLR_SHIFT

#define I2S_CTRL_RXFIFOCLR_SHIFT (9U)

◆ I2S_CTRL_SFTRST_CLKGEN_GET

#define I2S_CTRL_SFTRST_CLKGEN_GET ( x ) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT)

◆ I2S_CTRL_SFTRST_CLKGEN_MASK

#define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL)

◆ I2S_CTRL_SFTRST_CLKGEN_SET

#define I2S_CTRL_SFTRST_CLKGEN_SET ( x ) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK)

◆ I2S_CTRL_SFTRST_CLKGEN_SHIFT

#define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U)

◆ I2S_CTRL_SFTRST_RX_GET

#define I2S_CTRL_SFTRST_RX_GET ( x ) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT)

◆ I2S_CTRL_SFTRST_RX_MASK

#define I2S_CTRL_SFTRST_RX_MASK (0x40000UL)

◆ I2S_CTRL_SFTRST_RX_SET

#define I2S_CTRL_SFTRST_RX_SET ( x ) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK)

◆ I2S_CTRL_SFTRST_RX_SHIFT

#define I2S_CTRL_SFTRST_RX_SHIFT (18U)

◆ I2S_CTRL_SFTRST_TX_GET

#define I2S_CTRL_SFTRST_TX_GET ( x ) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT)

◆ I2S_CTRL_SFTRST_TX_MASK

#define I2S_CTRL_SFTRST_TX_MASK (0x20000UL)

◆ I2S_CTRL_SFTRST_TX_SET

#define I2S_CTRL_SFTRST_TX_SET ( x ) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK)

◆ I2S_CTRL_SFTRST_TX_SHIFT

#define I2S_CTRL_SFTRST_TX_SHIFT (17U)

◆ I2S_CTRL_TX_DMA_EN_GET

#define I2S_CTRL_TX_DMA_EN_GET ( x ) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT)

◆ I2S_CTRL_TX_DMA_EN_MASK

#define I2S_CTRL_TX_DMA_EN_MASK (0x1000U)

◆ I2S_CTRL_TX_DMA_EN_SET

#define I2S_CTRL_TX_DMA_EN_SET ( x ) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK)

◆ I2S_CTRL_TX_DMA_EN_SHIFT

#define I2S_CTRL_TX_DMA_EN_SHIFT (12U)

◆ I2S_CTRL_TX_EN_GET

#define I2S_CTRL_TX_EN_GET ( x ) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT)

◆ I2S_CTRL_TX_EN_MASK

#define I2S_CTRL_TX_EN_MASK (0x1E0U)

◆ I2S_CTRL_TX_EN_SET

#define I2S_CTRL_TX_EN_SET ( x ) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK)

◆ I2S_CTRL_TX_EN_SHIFT

#define I2S_CTRL_TX_EN_SHIFT (5U)

◆ I2S_CTRL_TXDNIE_GET

#define I2S_CTRL_TXDNIE_GET ( x ) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT)

◆ I2S_CTRL_TXDNIE_MASK

#define I2S_CTRL_TXDNIE_MASK (0x8000U)

◆ I2S_CTRL_TXDNIE_SET

#define I2S_CTRL_TXDNIE_SET ( x ) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK)

◆ I2S_CTRL_TXDNIE_SHIFT

#define I2S_CTRL_TXDNIE_SHIFT (15U)

◆ I2S_CTRL_TXFIFOCLR_GET

#define I2S_CTRL_TXFIFOCLR_GET ( x ) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT)

◆ I2S_CTRL_TXFIFOCLR_MASK

#define I2S_CTRL_TXFIFOCLR_MASK (0x400U)

◆ I2S_CTRL_TXFIFOCLR_SET

#define I2S_CTRL_TXFIFOCLR_SET ( x ) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK)

◆ I2S_CTRL_TXFIFOCLR_SHIFT

#define I2S_CTRL_TXFIFOCLR_SHIFT (10U)

◆ I2S_FIFO_THRESH_RX_GET

#define I2S_FIFO_THRESH_RX_GET ( x ) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT)

◆ I2S_FIFO_THRESH_RX_MASK

#define I2S_FIFO_THRESH_RX_MASK (0xFFU)

◆ I2S_FIFO_THRESH_RX_SET

#define I2S_FIFO_THRESH_RX_SET ( x ) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK)

◆ I2S_FIFO_THRESH_RX_SHIFT

#define I2S_FIFO_THRESH_RX_SHIFT (0U)

◆ I2S_FIFO_THRESH_TX_GET

#define I2S_FIFO_THRESH_TX_GET ( x ) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT)

◆ I2S_FIFO_THRESH_TX_MASK

#define I2S_FIFO_THRESH_TX_MASK (0xFF00U)

◆ I2S_FIFO_THRESH_TX_SET

#define I2S_FIFO_THRESH_TX_SET ( x ) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK)

◆ I2S_FIFO_THRESH_TX_SHIFT

#define I2S_FIFO_THRESH_TX_SHIFT (8U)

◆ I2S_MISC_CFGR_MCLK_GATEOFF_GET

#define I2S_MISC_CFGR_MCLK_GATEOFF_GET ( x ) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT)

◆ I2S_MISC_CFGR_MCLK_GATEOFF_MASK

#define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U)

◆ I2S_MISC_CFGR_MCLK_GATEOFF_SET

#define I2S_MISC_CFGR_MCLK_GATEOFF_SET ( x ) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK)

◆ I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT

#define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U)

◆ I2S_MISC_CFGR_MCLKOE_GET

#define I2S_MISC_CFGR_MCLKOE_GET ( x ) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT)

◆ I2S_MISC_CFGR_MCLKOE_MASK

#define I2S_MISC_CFGR_MCLKOE_MASK (0x1U)

◆ I2S_MISC_CFGR_MCLKOE_SET

#define I2S_MISC_CFGR_MCLKOE_SET ( x ) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK)

◆ I2S_MISC_CFGR_MCLKOE_SHIFT

#define I2S_MISC_CFGR_MCLKOE_SHIFT (0U)

◆ I2S_RFIFO_FILLINGS_RX0_GET

#define I2S_RFIFO_FILLINGS_RX0_GET ( x ) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT)

◆ I2S_RFIFO_FILLINGS_RX0_MASK

#define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU)

◆ I2S_RFIFO_FILLINGS_RX0_SHIFT

#define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U)

◆ I2S_RFIFO_FILLINGS_RX1_GET

#define I2S_RFIFO_FILLINGS_RX1_GET ( x ) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT)

◆ I2S_RFIFO_FILLINGS_RX1_MASK

#define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U)

◆ I2S_RFIFO_FILLINGS_RX1_SHIFT

#define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U)

◆ I2S_RFIFO_FILLINGS_RX2_GET

#define I2S_RFIFO_FILLINGS_RX2_GET ( x ) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT)

◆ I2S_RFIFO_FILLINGS_RX2_MASK

#define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL)

◆ I2S_RFIFO_FILLINGS_RX2_SHIFT

#define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U)

◆ I2S_RFIFO_FILLINGS_RX3_GET

#define I2S_RFIFO_FILLINGS_RX3_GET ( x ) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT)

◆ I2S_RFIFO_FILLINGS_RX3_MASK

#define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL)

◆ I2S_RFIFO_FILLINGS_RX3_SHIFT

#define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U)

◆ I2S_RXD_D_GET

#define I2S_RXD_D_GET ( x ) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT)

◆ I2S_RXD_D_MASK

#define I2S_RXD_D_MASK (0xFFFFFFFFUL)

◆ I2S_RXD_D_SHIFT

#define I2S_RXD_D_SHIFT (0U)

◆ I2S_RXD_DATA0

#define I2S_RXD_DATA0 (0UL)

◆ I2S_RXD_DATA1

#define I2S_RXD_DATA1 (1UL)

◆ I2S_RXD_DATA2

#define I2S_RXD_DATA2 (2UL)

◆ I2S_RXD_DATA3

#define I2S_RXD_DATA3 (3UL)

◆ I2S_RXDSLOT_DATA0

#define I2S_RXDSLOT_DATA0 (0UL)

◆ I2S_RXDSLOT_DATA1

#define I2S_RXDSLOT_DATA1 (1UL)

◆ I2S_RXDSLOT_DATA2

#define I2S_RXDSLOT_DATA2 (2UL)

◆ I2S_RXDSLOT_DATA3

#define I2S_RXDSLOT_DATA3 (3UL)

◆ I2S_RXDSLOT_EN_GET

#define I2S_RXDSLOT_EN_GET ( x ) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT)

◆ I2S_RXDSLOT_EN_MASK

#define I2S_RXDSLOT_EN_MASK (0xFFFFU)

◆ I2S_RXDSLOT_EN_SET

#define I2S_RXDSLOT_EN_SET ( x ) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK)

◆ I2S_RXDSLOT_EN_SHIFT

#define I2S_RXDSLOT_EN_SHIFT (0U)

◆ I2S_STA_RX_DA_GET

#define I2S_STA_RX_DA_GET ( x ) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT)

◆ I2S_STA_RX_DA_MASK

#define I2S_STA_RX_DA_MASK (0x1EU)

◆ I2S_STA_RX_DA_SHIFT

#define I2S_STA_RX_DA_SHIFT (1U)

◆ I2S_STA_RX_OV_GET

#define I2S_STA_RX_OV_GET ( x ) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT)

◆ I2S_STA_RX_OV_MASK

#define I2S_STA_RX_OV_MASK (0x1E00U)

◆ I2S_STA_RX_OV_SET

#define I2S_STA_RX_OV_SET ( x ) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK)

◆ I2S_STA_RX_OV_SHIFT

#define I2S_STA_RX_OV_SHIFT (9U)

◆ I2S_STA_TX_DN_GET

#define I2S_STA_TX_DN_GET ( x ) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT)

◆ I2S_STA_TX_DN_MASK

#define I2S_STA_TX_DN_MASK (0x1E0U)

◆ I2S_STA_TX_DN_SHIFT

#define I2S_STA_TX_DN_SHIFT (5U)

◆ I2S_STA_TX_UD_GET

#define I2S_STA_TX_UD_GET ( x ) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT)

◆ I2S_STA_TX_UD_MASK

#define I2S_STA_TX_UD_MASK (0x1E000UL)

◆ I2S_STA_TX_UD_SET

#define I2S_STA_TX_UD_SET ( x ) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK)

◆ I2S_STA_TX_UD_SHIFT

#define I2S_STA_TX_UD_SHIFT (13U)

◆ I2S_TFIFO_FILLINGS_TX0_GET

#define I2S_TFIFO_FILLINGS_TX0_GET ( x ) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT)

◆ I2S_TFIFO_FILLINGS_TX0_MASK

#define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU)

◆ I2S_TFIFO_FILLINGS_TX0_SHIFT

#define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U)

◆ I2S_TFIFO_FILLINGS_TX1_GET

#define I2S_TFIFO_FILLINGS_TX1_GET ( x ) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT)

◆ I2S_TFIFO_FILLINGS_TX1_MASK

#define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U)

◆ I2S_TFIFO_FILLINGS_TX1_SHIFT

#define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U)

◆ I2S_TFIFO_FILLINGS_TX2_GET

#define I2S_TFIFO_FILLINGS_TX2_GET ( x ) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT)

◆ I2S_TFIFO_FILLINGS_TX2_MASK

#define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL)

◆ I2S_TFIFO_FILLINGS_TX2_SHIFT

#define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U)

◆ I2S_TFIFO_FILLINGS_TX3_GET

#define I2S_TFIFO_FILLINGS_TX3_GET ( x ) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT)

◆ I2S_TFIFO_FILLINGS_TX3_MASK

#define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL)

◆ I2S_TFIFO_FILLINGS_TX3_SHIFT

#define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U)

◆ I2S_TXD_D_GET

#define I2S_TXD_D_GET ( x ) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT)

◆ I2S_TXD_D_MASK

#define I2S_TXD_D_MASK (0xFFFFFFFFUL)

◆ I2S_TXD_D_SET

#define I2S_TXD_D_SET ( x ) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK)

◆ I2S_TXD_D_SHIFT

#define I2S_TXD_D_SHIFT (0U)

◆ I2S_TXD_DATA0

#define I2S_TXD_DATA0 (0UL)

◆ I2S_TXD_DATA1

#define I2S_TXD_DATA1 (1UL)

◆ I2S_TXD_DATA2

#define I2S_TXD_DATA2 (2UL)

◆ I2S_TXD_DATA3

#define I2S_TXD_DATA3 (3UL)

◆ I2S_TXDSLOT_DATA0

#define I2S_TXDSLOT_DATA0 (0UL)

◆ I2S_TXDSLOT_DATA1

#define I2S_TXDSLOT_DATA1 (1UL)

◆ I2S_TXDSLOT_DATA2

#define I2S_TXDSLOT_DATA2 (2UL)

◆ I2S_TXDSLOT_DATA3

#define I2S_TXDSLOT_DATA3 (3UL)

◆ I2S_TXDSLOT_EN_GET

#define I2S_TXDSLOT_EN_GET ( x ) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT)

◆ I2S_TXDSLOT_EN_MASK

#define I2S_TXDSLOT_EN_MASK (0xFFFFU)

◆ I2S_TXDSLOT_EN_SET

#define I2S_TXDSLOT_EN_SET ( x ) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK)

◆ I2S_TXDSLOT_EN_SHIFT

#define I2S_TXDSLOT_EN_SHIFT (0U)

Data Structures

Macros