HPM SDK
HPMicro Software Development Kit
hpm_qeov2_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEOV2_H
10 #define HPM_QEOV2_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t MODE; /* 0x0: analog waves mode */
15  __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */
16  __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */
17  __RW uint32_t VD_INJECT; /* 0x14: wave vd inject value */
18  __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */
19  __RW uint32_t VQ_INJECT; /* 0x20: wave vq inject value */
20  __R uint8_t RESERVED1[8]; /* 0x24 - 0x2B: Reserved */
21  __W uint32_t VD_VQ_LOAD; /* 0x2C: load wave0/1/2 vd vq value */
22  __RW uint32_t AMPLITUDE[3]; /* 0x30 - 0x38: wave0 amplitude */
23  __RW uint32_t MID_POINT[3]; /* 0x3C - 0x44: wave0 output middle point offset */
24  struct {
25  __RW uint32_t MIN_LEVEL0; /* 0x48: wave0 low area limit value */
26  __RW uint32_t MAX_LEVEL0; /* 0x4C: wave0 high area limit value */
27  } LIMIT0[3];
28  struct {
29  __RW uint32_t MIN_LEVEL1; /* 0x60: wave0 low area limit value level1 */
30  __RW uint32_t MAX_LEVEL1; /* 0x64: wave0 high area limit value level1 */
31  } LIMIT1[3];
32  __RW uint32_t DEADZONE_SHIFT[3]; /* 0x78 - 0x80: deadzone_shifter_wave0 */
33  __RW uint32_t PWM_CYCLE; /* 0x84: pwm_cycle */
34  } WAVE;
35  __R uint8_t RESERVED0[120]; /* 0x88 - 0xFF: Reserved */
36  struct {
37  __RW uint32_t MODE; /* 0x100: wave_a/b/z output mode */
38  __RW uint32_t RESOLUTION; /* 0x104: resolution of wave_a/b/z */
39  __RW uint32_t PHASE_SHIFT[3]; /* 0x108 - 0x110: wave_a phase shifter */
40  __RW uint32_t LINE_WIDTH; /* 0x114: Two-phase orthogonality wave 1/4 period */
41  __RW uint32_t WDOG_WIDTH; /* 0x118: wdog width of qeo */
42  __W uint32_t POSTION_SYNC; /* 0x11C: sync abz owned postion */
43  __RW uint32_t OVERALL_OFFSET; /* 0x120: abz overall position offset */
44  __RW uint32_t Z_START; /* 0x124: zero phase start line num */
45  __RW uint32_t Z_END; /* 0x128: zero phase end line num */
46  __RW uint32_t Z_OFFSET; /* 0x12C: zero phase start and end 1/4 line num */
47  __RW uint32_t Z_PULSE_WIDTH; /* 0x130: zero pulse witdth */
48  } ABZ;
49  __R uint8_t RESERVED1[12]; /* 0x134 - 0x13F: Reserved */
50  struct {
51  __RW uint32_t MODE; /* 0x140: pwm mode */
52  __RW uint32_t RESOLUTION; /* 0x144: resolution of pwm */
53  __RW uint32_t PHASE_SHIFT[4]; /* 0x148 - 0x154: pwm_a phase shifter */
54  __RW uint32_t PHASE_TABLE[24]; /* 0x158 - 0x1B4: pwm_phase_table 0 */
55  } PWM;
56  __R uint8_t RESERVED2[64]; /* 0x1B8 - 0x1F7: Reserved */
57  __RW uint32_t POSTION_SOFTWARE; /* 0x1F8: softwave inject postion */
58  __RW uint32_t POSTION_SEL; /* 0x1FC: select softwave inject postion */
59  __R uint32_t STATUS; /* 0x200: qeo status */
60  __R uint32_t DEBUG0; /* 0x204: qeo debug 0 */
61  __R uint32_t DEBUG1; /* 0x208: qeo debug 1 */
62  __R uint32_t DEBUG2; /* 0x20C: qeo debug 2 */
63  __R uint32_t DEBUG3; /* 0x210: qeo debug 3 */
64  __R uint32_t DEBUG4; /* 0x214: qeo debug 4 */
65  __R uint32_t DEBUG5; /* 0x218: qeo debug 5 */
66 } QEOV2_Type;
67 
68 
69 /* Bitfield definition for register of struct WAVE: MODE */
70 /*
71  * WAVE2_ABOVE_MAX_LIMIT (RW)
72  *
73  * wave2 above max limit mode.
74  * 0: output all bits are 1.
75  * 1: output 0x0.
76  * 2: output as level_max_limit2.level0_max_limit
77  */
78 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL)
79 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U)
80 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK)
81 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT)
82 
83 /*
84  * WAVE2_HIGH_AREA1_LIMIT (RW)
85  *
86  * wave2 high area1 limit mode.
87  * 0: output all bits are 1.
88  * 1: output as level_max_limit2.level0_max_limit
89  */
90 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL)
91 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U)
92 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK)
93 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT)
94 
95 /*
96  * WAVE2_HIGH_AREA0_LIMIT (RW)
97  *
98  * wave2 high area0 limit mode.
99  * 0: output all bits are 1.
100  * 1: output as level_max_limit2.level0_max_limit
101  */
102 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL)
103 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U)
104 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK)
105 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT)
106 
107 /*
108  * WAVE2_LOW_AREA1_LIMIT (RW)
109  *
110  * wave2 low area1 limit mode.
111  * 0: output 0.
112  * 1: output as level_min_limit2.level1_min_limit
113  */
114 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL)
115 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U)
116 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK)
117 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT)
118 
119 /*
120  * WAVE2_LOW_AREA0_LIMIT (RW)
121  *
122  * wave2 low area0 limit mode.
123  * 0: output 0.
124  * 1: output as level_min_limit2.level1_min_limit
125  */
126 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL)
127 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U)
128 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK)
129 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT)
130 
131 /*
132  * WAVE2_BELOW_MIN_LIMIT (RW)
133  *
134  * wave2 below min limit mode.
135  * 0: output 0.
136  * 1: output all bits are 1.
137  * 2: output as level_min_limit2.level1_min_limit
138  */
139 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL)
140 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U)
141 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK)
142 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT)
143 
144 /*
145  * WAVE1_ABOVE_MAX_LIMIT (RW)
146  *
147  * wave1 above max limit mode.
148  * 0: output all bits are 1.
149  * 1: output 0x0.
150  * 2: output as level_max_limit1.level0_max_limit
151  */
152 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL)
153 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U)
154 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK)
155 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT)
156 
157 /*
158  * WAVE1_HIGH_AREA1_LIMIT (RW)
159  *
160  * wave1 high area1 limit mode.
161  * 0: output all bits are 1.
162  * 1: output as level_max_limit1.level0_max_limit
163  */
164 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL)
165 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U)
166 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK)
167 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT)
168 
169 /*
170  * WAVE1_HIGH_AREA0_LIMIT (RW)
171  *
172  * wave1 high area0 limit mode.
173  * 0: output all bits are 1.
174  * 1: output as level_max_limit1.level0_max_limit
175  */
176 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL)
177 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U)
178 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK)
179 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT)
180 
181 /*
182  * WAVE1_LOW_AREA1_LIMIT (RW)
183  *
184  * wave1 low area1 limit mode.
185  * 0: output 0.
186  * 1: output as level_min_limit1.level1_min_limit
187  */
188 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL)
189 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U)
190 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK)
191 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT)
192 
193 /*
194  * WAVE1_LOW_AREA0_LIMIT (RW)
195  *
196  * wave1 low area0 limit mode.
197  * 0: output 0.
198  * 1: output as level_min_limit1.level1_min_limit
199  */
200 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL)
201 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U)
202 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK)
203 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT)
204 
205 /*
206  * WAVE1_BELOW_MIN_LIMIT (RW)
207  *
208  * wave1 below min limit mode.
209  * 0: output 0.
210  * 1: output all bits are 1.
211  * 2: output as level_min_limit1.level1_min_limit
212  */
213 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL)
214 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U)
215 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK)
216 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT)
217 
218 /*
219  * WAVE0_ABOVE_MAX_LIMIT (RW)
220  *
221  * wave0 above max limit mode.
222  * 0: output all bits are 1.
223  * 1: output 0x0.
224  * 2: output as level_max_limit0.level0_max_limit
225  */
226 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U)
227 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U)
228 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK)
229 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT)
230 
231 /*
232  * WAVE0_HIGH_AREA1_LIMIT (RW)
233  *
234  * wave0 high area1 limit mode.
235  * 0: output all bits are 1.
236  * 1: output as level_max_limit0.level0_max_limit
237  */
238 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U)
239 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U)
240 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK)
241 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT)
242 
243 /*
244  * WAVE0_HIGH_AREA0_LIMIT (RW)
245  *
246  * wave0 high area0 limit mode.
247  * 0: output all bits are 1.
248  * 1: output as level_max_limit0.level0_max_limit
249  */
250 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U)
251 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U)
252 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK)
253 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT)
254 
255 /*
256  * WAVE0_LOW_AREA1_LIMIT (RW)
257  *
258  * wave0 low area1 limit mode.
259  * 0: output 0.
260  * 1: output as level_min_limit0.level1_min_limit
261  */
262 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U)
263 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U)
264 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK)
265 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT)
266 
267 /*
268  * WAVE0_LOW_AREA0_LIMIT (RW)
269  *
270  * wave0 low area0 limit mode.
271  * 0: output 0.
272  * 1: output as level_min_limit0.level1_min_limit
273  */
274 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U)
275 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U)
276 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK)
277 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT)
278 
279 /*
280  * WAVE0_BELOW_MIN_LIMIT (RW)
281  *
282  * wave0 below min limit mode.
283  * 0: output 0.
284  * 1: output all bits are 1.
285  * 2: output as level_min_limit0.level1_min_limit
286  */
287 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U)
288 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U)
289 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK)
290 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT)
291 
292 /*
293  * SADDLE_TYPE (RW)
294  *
295  * saddle type seclect;
296  * 0:standard saddle.
297  * 1: triple-cos saddle.
298  */
299 #define QEOV2_WAVE_MODE_SADDLE_TYPE_MASK (0x80U)
300 #define QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT (7U)
301 #define QEOV2_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK)
302 #define QEOV2_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK) >> QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT)
303 
304 /*
305  * ENABLE_DQ_VALID (RW)
306  *
307  * enable vd or vq valid to trigger analog wave calcuation
308  * 0: disable.
309  * 1: enable.
310  */
311 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK (0x40U)
312 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT (6U)
313 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK)
314 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT)
315 
316 /*
317  * ENABLE_POS_VALID (RW)
318  *
319  * enable position valid to trigger analog wave calcuation
320  * 0: disable.
321  * 1: enable.
322  */
323 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK (0x20U)
324 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT (5U)
325 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK)
326 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT)
327 
328 /*
329  * EN_WAVE_VD_VQ_INJECT (RW)
330  *
331  * wave VdVq inject enable.
332  * 0: disable VdVq inject.
333  * 1: enable VdVq inject.
334  */
335 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK (0x10U)
336 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT (4U)
337 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK)
338 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK) >> QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT)
339 
340 /*
341  * VD_VQ_SEL (RW)
342  *
343  * vd_vq sel ctrl:
344  * 0: from CLC.
345  * 1: from software.
346  */
347 #define QEOV2_WAVE_MODE_VD_VQ_SEL_MASK (0x4U)
348 #define QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT (2U)
349 #define QEOV2_WAVE_MODE_VD_VQ_SEL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK)
350 #define QEOV2_WAVE_MODE_VD_VQ_SEL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK) >> QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT)
351 
352 /*
353  * WAVES_OUTPUT_TYPE (RW)
354  *
355  * wave0/1/2 output mode.
356  * 0: cosine wave.
357  * 1: saddle wave.
358  * 2. abs cosine wave.
359  * 3. saw wave
360  */
361 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U)
362 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U)
363 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK)
364 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT)
365 
366 /* Bitfield definition for register of struct WAVE: RESOLUTION */
367 /*
368  * LINES (RW)
369  *
370  * wave0/1/2 resolution
371  */
372 #define QEOV2_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
373 #define QEOV2_WAVE_RESOLUTION_LINES_SHIFT (0U)
374 #define QEOV2_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_WAVE_RESOLUTION_LINES_SHIFT) & QEOV2_WAVE_RESOLUTION_LINES_MASK)
375 #define QEOV2_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_WAVE_RESOLUTION_LINES_MASK) >> QEOV2_WAVE_RESOLUTION_LINES_SHIFT)
376 
377 /* Bitfield definition for register of struct WAVE: WAVE0 */
378 /*
379  * VAL (RW)
380  *
381  * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period
382  */
383 #define QEOV2_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
384 #define QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT (0U)
385 #define QEOV2_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK)
386 #define QEOV2_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK) >> QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT)
387 
388 /* Bitfield definition for register of struct WAVE: VD_INJECT */
389 /*
390  * VD_VAL (RW)
391  *
392  * Vd inject value
393  */
394 #define QEOV2_WAVE_VD_INJECT_VD_VAL_MASK (0xFFFFFFFFUL)
395 #define QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT (0U)
396 #define QEOV2_WAVE_VD_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK)
397 #define QEOV2_WAVE_VD_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK) >> QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT)
398 
399 /* Bitfield definition for register of struct WAVE: VQ_INJECT */
400 /*
401  * VQ_VAL (RW)
402  *
403  * Vq inject value
404  */
405 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK (0xFFFFFFFFUL)
406 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT (0U)
407 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK)
408 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK) >> QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT)
409 
410 /* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */
411 /*
412  * LOAD (WO)
413  *
414  * load wave0/1/2 vd vq value. always read 0
415  * 0: vd vq keep previous value.
416  * 1: load wave0/1/2 vd vq value at sametime.
417  */
418 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U)
419 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U)
420 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK)
421 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT)
422 
423 /* Bitfield definition for register of struct WAVE: WAVE0 */
424 /*
425  * EN_SCAL (RW)
426  *
427  * enable wave amplitude scaling. 0: disable; 1: enable
428  */
429 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL)
430 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U)
431 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK)
432 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT)
433 
434 /*
435  * AMP_VAL (RW)
436  *
437  * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value.
438  */
439 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU)
440 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U)
441 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK)
442 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT)
443 
444 /* Bitfield definition for register of struct WAVE: WAVE0 */
445 /*
446  * VAL (RW)
447  *
448  * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value.
449  */
450 #define QEOV2_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL)
451 #define QEOV2_WAVE_MID_POINT_VAL_SHIFT (0U)
452 #define QEOV2_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MID_POINT_VAL_SHIFT) & QEOV2_WAVE_MID_POINT_VAL_MASK)
453 #define QEOV2_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MID_POINT_VAL_MASK) >> QEOV2_WAVE_MID_POINT_VAL_SHIFT)
454 
455 /* Bitfield definition for register of struct WAVE: MIN_LEVEL0 */
456 /*
457  * LIMIT_LEVEL0 (RW)
458  *
459  * low area limit level0
460  */
461 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL)
462 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT (0U)
463 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK)
464 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT)
465 
466 /* Bitfield definition for register of struct WAVE: MAX_LEVEL0 */
467 /*
468  * LIMIT_LEVEL0 (RW)
469  *
470  * high area limit level0
471  */
472 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL)
473 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT (0U)
474 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK)
475 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT)
476 
477 /* Bitfield definition for register of struct WAVE: MIN_LEVEL1 */
478 /*
479  * LIMIT_LEVEL1 (RW)
480  *
481  * low area limit level1
482  */
483 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL)
484 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT (0U)
485 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK)
486 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT)
487 
488 /* Bitfield definition for register of struct WAVE: MAX_LEVEL1 */
489 /*
490  * LIMIT_LEVEL1 (RW)
491  *
492  * high area limit level1
493  */
494 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL)
495 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT (0U)
496 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK)
497 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT)
498 
499 /* Bitfield definition for register of struct WAVE: WAVE0 */
500 /*
501  * VAL (RW)
502  *
503  * wave0 deadzone shifter value
504  */
505 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
506 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U)
507 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK)
508 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT)
509 
510 /* Bitfield definition for register of struct WAVE: PWM_CYCLE */
511 /*
512  * VAL (RW)
513  *
514  * pwm_cycle
515  */
516 #define QEOV2_WAVE_PWM_CYCLE_VAL_MASK (0xFFFFFFFFUL)
517 #define QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT (0U)
518 #define QEOV2_WAVE_PWM_CYCLE_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK)
519 #define QEOV2_WAVE_PWM_CYCLE_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK) >> QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT)
520 
521 /* Bitfield definition for register of struct ABZ: MODE */
522 /*
523  * ABZ_OUTPUT_ENABLE (RW)
524  *
525  * abz output enable：
526  * 0：abz output disable, all keep 0
527  * 1：abz output enable.
528  */
529 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK (0x80000000UL)
530 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT (31U)
531 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK)
532 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK) >> QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT)
533 
534 /*
535  * REVERSE_EDGE_TYPE (RW)
536  *
537  * pulse reverse wave，reverse edge point:
538  * 0: between pulse's posedge and negedge, min period dedicated by the num line_width
539  * 1: edge change point flow pulse's negedge.
540  */
541 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL)
542 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U)
543 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK)
544 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT)
545 
546 /*
547  * POSITION_SYNC_MODE (RW)
548  *
549  * position sync mode:
550  * 0: only sync integer line part into qeo own position.
551  * 1: sync integer and fraction part into qeo own position.
552  */
553 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK (0x8000000UL)
554 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT (27U)
555 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK)
556 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK) >> QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT)
557 
558 /*
559  * EN_WDOG (RW)
560  *
561  * enable abz wdog:
562  * 0: disable abz wdog.
563  * 1: enable abz wdog.
564  */
565 #define QEOV2_ABZ_MODE_EN_WDOG_MASK (0x1000000UL)
566 #define QEOV2_ABZ_MODE_EN_WDOG_SHIFT (24U)
567 #define QEOV2_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_EN_WDOG_SHIFT) & QEOV2_ABZ_MODE_EN_WDOG_MASK)
568 #define QEOV2_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_EN_WDOG_MASK) >> QEOV2_ABZ_MODE_EN_WDOG_SHIFT)
569 
570 /*
571  * Z_POLARITY (RW)
572  *
573  * wave_z polarity.
574  * 0: normal output.
575  * 1: invert normal output
576  */
577 #define QEOV2_ABZ_MODE_Z_POLARITY_MASK (0x100000UL)
578 #define QEOV2_ABZ_MODE_Z_POLARITY_SHIFT (20U)
579 #define QEOV2_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_POLARITY_SHIFT) & QEOV2_ABZ_MODE_Z_POLARITY_MASK)
580 #define QEOV2_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_POLARITY_MASK) >> QEOV2_ABZ_MODE_Z_POLARITY_SHIFT)
581 
582 /*
583  * B_POLARITY (RW)
584  *
585  * wave_b polarity.
586  * 0: normal output.
587  * 1: invert normal output
588  */
589 #define QEOV2_ABZ_MODE_B_POLARITY_MASK (0x10000UL)
590 #define QEOV2_ABZ_MODE_B_POLARITY_SHIFT (16U)
591 #define QEOV2_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_B_POLARITY_SHIFT) & QEOV2_ABZ_MODE_B_POLARITY_MASK)
592 #define QEOV2_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_B_POLARITY_MASK) >> QEOV2_ABZ_MODE_B_POLARITY_SHIFT)
593 
594 /*
595  * A_POLARITY (RW)
596  *
597  * wave_a polarity.
598  * 0: normal output.
599  * 1: invert normal output
600  */
601 #define QEOV2_ABZ_MODE_A_POLARITY_MASK (0x1000U)
602 #define QEOV2_ABZ_MODE_A_POLARITY_SHIFT (12U)
603 #define QEOV2_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_A_POLARITY_SHIFT) & QEOV2_ABZ_MODE_A_POLARITY_MASK)
604 #define QEOV2_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_A_POLARITY_MASK) >> QEOV2_ABZ_MODE_A_POLARITY_SHIFT)
605 
606 /*
607  * Z_TYPE (RW)
608  *
609  * wave_z type:
610  * 0: zero pulse type, start and end line number decided by z_start、z_end and z_offset.
611  * 1: zero pulse type, z output start to high when position= z_start, and mantain numbers of 1/4 line cfg in z_pulse_width register
612  * 2: reserved
613  * 3: wave_z output as tree-phase wave same as wave_a/wave_b
614  */
615 #define QEOV2_ABZ_MODE_Z_TYPE_MASK (0x300U)
616 #define QEOV2_ABZ_MODE_Z_TYPE_SHIFT (8U)
617 #define QEOV2_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_TYPE_SHIFT) & QEOV2_ABZ_MODE_Z_TYPE_MASK)
618 #define QEOV2_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_TYPE_MASK) >> QEOV2_ABZ_MODE_Z_TYPE_SHIFT)
619 
620 /*
621  * B_TYPE (RW)
622  *
623  * wave_b type:
624  * 0: Two-phase orthogonality wave_b.
625  * 1: reverse wave of pulse/reverse type.
626  * 2: down wave of up/down type.
627  * 3: Three-phase orthogonality wave_b.
628  */
629 #define QEOV2_ABZ_MODE_B_TYPE_MASK (0x30U)
630 #define QEOV2_ABZ_MODE_B_TYPE_SHIFT (4U)
631 #define QEOV2_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_B_TYPE_SHIFT) & QEOV2_ABZ_MODE_B_TYPE_MASK)
632 #define QEOV2_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_B_TYPE_MASK) >> QEOV2_ABZ_MODE_B_TYPE_SHIFT)
633 
634 /*
635  * A_TYPE (RW)
636  *
637  * wave_a type:
638  * 0: Two-phase orthogonality wave_a.
639  * 1: pulse wave of pulse/reverse type.
640  * 2: up wave of up/down type.
641  * 3: Three-phase orthogonality wave_a.
642  */
643 #define QEOV2_ABZ_MODE_A_TYPE_MASK (0x3U)
644 #define QEOV2_ABZ_MODE_A_TYPE_SHIFT (0U)
645 #define QEOV2_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_A_TYPE_SHIFT) & QEOV2_ABZ_MODE_A_TYPE_MASK)
646 #define QEOV2_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_A_TYPE_MASK) >> QEOV2_ABZ_MODE_A_TYPE_SHIFT)
647 
648 /* Bitfield definition for register of struct ABZ: RESOLUTION */
649 /*
650  * LINES (RW)
651  *
652  * wave_a/b/z resolution
653  */
654 #define QEOV2_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
655 #define QEOV2_ABZ_RESOLUTION_LINES_SHIFT (0U)
656 #define QEOV2_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_ABZ_RESOLUTION_LINES_SHIFT) & QEOV2_ABZ_RESOLUTION_LINES_MASK)
657 #define QEOV2_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_ABZ_RESOLUTION_LINES_MASK) >> QEOV2_ABZ_RESOLUTION_LINES_SHIFT)
658 
659 /* Bitfield definition for register of struct ABZ: A */
660 /*
661  * VAL (RW)
662  *
663  * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period.
664  */
665 #define QEOV2_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
666 #define QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT (0U)
667 #define QEOV2_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK)
668 #define QEOV2_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK) >> QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT)
669 
670 /* Bitfield definition for register of struct ABZ: LINE_WIDTH */
671 /*
672  * LINE (RW)
673  *
674  * the num of system clk by 1/4 period when using as Two-phase orthogonality.
675  */
676 #define QEOV2_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL)
677 #define QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT (0U)
678 #define QEOV2_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK)
679 #define QEOV2_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK) >> QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT)
680 
681 /* Bitfield definition for register of struct ABZ: WDOG_WIDTH */
682 /*
683  * WIDTH (RW)
684  *
685  * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk.
686  */
687 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL)
688 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U)
689 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK)
690 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT)
691 
692 /* Bitfield definition for register of struct ABZ: POSTION_SYNC */
693 /*
694  * POSTION (WO)
695  *
696  * load next valid postion into abz owned postion. always read 0
697  * 0: sync abz owned postion with next valid postion.
698  * 1: not sync.
699  */
700 #define QEOV2_ABZ_POSTION_SYNC_POSTION_MASK (0x1U)
701 #define QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT (0U)
702 #define QEOV2_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK)
703 #define QEOV2_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK) >> QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT)
704 
705 /* Bitfield definition for register of struct ABZ: OVERALL_OFFSET */
706 /*
707  * VAL (RW)
708  *
709  * abz position overall offset, it affects abz position before resolution convert
710  */
711 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK (0xFFFFFFFFUL)
712 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT (0U)
713 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK)
714 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK) >> QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT)
715 
716 /* Bitfield definition for register of struct ABZ: Z_START */
717 /*
718  * Z_START (RW)
719  *
720  * number of Z start line
721  */
722 #define QEOV2_ABZ_Z_START_Z_START_MASK (0xFFFFFFFFUL)
723 #define QEOV2_ABZ_Z_START_Z_START_SHIFT (0U)
724 #define QEOV2_ABZ_Z_START_Z_START_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_START_Z_START_SHIFT) & QEOV2_ABZ_Z_START_Z_START_MASK)
725 #define QEOV2_ABZ_Z_START_Z_START_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_START_Z_START_MASK) >> QEOV2_ABZ_Z_START_Z_START_SHIFT)
726 
727 /* Bitfield definition for register of struct ABZ: Z_END */
728 /*
729  * Z_END (RW)
730  *
731  * number of Z end line
732  */
733 #define QEOV2_ABZ_Z_END_Z_END_MASK (0xFFFFFFFFUL)
734 #define QEOV2_ABZ_Z_END_Z_END_SHIFT (0U)
735 #define QEOV2_ABZ_Z_END_Z_END_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_END_Z_END_SHIFT) & QEOV2_ABZ_Z_END_Z_END_MASK)
736 #define QEOV2_ABZ_Z_END_Z_END_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_END_Z_END_MASK) >> QEOV2_ABZ_Z_END_Z_END_SHIFT)
737 
738 /* Bitfield definition for register of struct ABZ: Z_OFFSET */
739 /*
740  * Z_END_OFFSET (RW)
741  *
742  * number of Z end 1/4 line
743  */
744 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK (0x300U)
745 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT (8U)
746 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK)
747 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT)
748 
749 /*
750  * Z_START_OFFSET (RW)
751  *
752  * number of Z start 1/4 line
753  */
754 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK (0x30U)
755 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT (4U)
756 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK)
757 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT)
758 
759 /* Bitfield definition for register of struct ABZ: Z_PULSE_WIDTH */
760 /*
761  * VAL (RW)
762  *
763  * number of z_pulse_width
764  */
765 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK (0xFFFFFFFFUL)
766 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT (0U)
767 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK)
768 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK) >> QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT)
769 
770 /* Bitfield definition for register of struct PWM: MODE */
771 /*
772  * PWM7_SAFETY (RW)
773  *
774  * PWM safety mode phase table
775  */
776 #define QEOV2_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL)
777 #define QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT (30U)
778 #define QEOV2_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK)
779 #define QEOV2_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT)
780 
781 /*
782  * PWM6_SAFETY (RW)
783  *
784  * PWM safety mode phase table
785  */
786 #define QEOV2_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL)
787 #define QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT (28U)
788 #define QEOV2_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK)
789 #define QEOV2_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT)
790 
791 /*
792  * PWM5_SAFETY (RW)
793  *
794  * PWM safety mode phase table
795  */
796 #define QEOV2_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL)
797 #define QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT (26U)
798 #define QEOV2_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK)
799 #define QEOV2_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT)
800 
801 /*
802  * PWM4_SAFETY (RW)
803  *
804  * PWM safety mode phase table
805  */
806 #define QEOV2_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL)
807 #define QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT (24U)
808 #define QEOV2_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK)
809 #define QEOV2_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT)
810 
811 /*
812  * PWM3_SAFETY (RW)
813  *
814  * PWM safety mode phase table
815  */
816 #define QEOV2_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL)
817 #define QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT (22U)
818 #define QEOV2_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK)
819 #define QEOV2_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT)
820 
821 /*
822  * PWM2_SAFETY (RW)
823  *
824  * PWM safety mode phase table
825  */
826 #define QEOV2_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL)
827 #define QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT (20U)
828 #define QEOV2_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK)
829 #define QEOV2_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT)
830 
831 /*
832  * PWM1_SAFETY (RW)
833  *
834  * PWM safety mode phase table
835  */
836 #define QEOV2_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL)
837 #define QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT (18U)
838 #define QEOV2_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK)
839 #define QEOV2_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT)
840 
841 /*
842  * PWM0_SAFETY (RW)
843  *
844  * PWM safety mode phase table
845  */
846 #define QEOV2_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL)
847 #define QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT (16U)
848 #define QEOV2_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK)
849 #define QEOV2_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT)
850 
851 /*
852  * ENABLE_PWM (RW)
853  *
854  * enable PWM force output
855  * 0: disable
856  * 1: enable
857  */
858 #define QEOV2_PWM_MODE_ENABLE_PWM_MASK (0x8000U)
859 #define QEOV2_PWM_MODE_ENABLE_PWM_SHIFT (15U)
860 #define QEOV2_PWM_MODE_ENABLE_PWM_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_ENABLE_PWM_SHIFT) & QEOV2_PWM_MODE_ENABLE_PWM_MASK)
861 #define QEOV2_PWM_MODE_ENABLE_PWM_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_ENABLE_PWM_MASK) >> QEOV2_PWM_MODE_ENABLE_PWM_SHIFT)
862 
863 /*
864  * PWM_ENTER_SAFETY_MODE (RW)
865  *
866  * PWM enter safety mode
867  * 0: not enter
868  * 1: enter
869  */
870 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U)
871 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U)
872 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK)
873 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT)
874 
875 /*
876  * PWM_SAFETY_BYPASS (RW)
877  *
878  * PWM safety mode bypass
879  * 0: not bypass
880  * 1: bypass
881  */
882 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U)
883 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U)
884 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK)
885 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT)
886 
887 /*
888  * REVISE_UP_DN (RW)
889  *
890  * exchange PWM pairs’ output
891  * 0: not exchange.
892  * 1: exchange.
893  */
894 #define QEOV2_PWM_MODE_REVISE_UP_DN_MASK (0x10U)
895 #define QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT (4U)
896 #define QEOV2_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK)
897 #define QEOV2_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK) >> QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT)
898 
899 /*
900  * PHASE_NUM (RW)
901  *
902  * pwm force phase number.
903  */
904 #define QEOV2_PWM_MODE_PHASE_NUM_MASK (0xFU)
905 #define QEOV2_PWM_MODE_PHASE_NUM_SHIFT (0U)
906 #define QEOV2_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PHASE_NUM_SHIFT) & QEOV2_PWM_MODE_PHASE_NUM_MASK)
907 #define QEOV2_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PHASE_NUM_MASK) >> QEOV2_PWM_MODE_PHASE_NUM_SHIFT)
908 
909 /* Bitfield definition for register of struct PWM: RESOLUTION */
910 /*
911  * LINES (RW)
912  *
913  * pwm resolution
914  */
915 #define QEOV2_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
916 #define QEOV2_PWM_RESOLUTION_LINES_SHIFT (0U)
917 #define QEOV2_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_PWM_RESOLUTION_LINES_SHIFT) & QEOV2_PWM_RESOLUTION_LINES_MASK)
918 #define QEOV2_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_PWM_RESOLUTION_LINES_MASK) >> QEOV2_PWM_RESOLUTION_LINES_SHIFT)
919 
920 /* Bitfield definition for register of struct PWM: A */
921 /*
922  * VAL (RW)
923  *
924  * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period
925  */
926 #define QEOV2_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
927 #define QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT (0U)
928 #define QEOV2_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK)
929 #define QEOV2_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK) >> QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT)
930 
931 /* Bitfield definition for register of struct PWM: POSEDGE0 */
932 /*
933  * PWM7 (RW)
934  *
935  * pwm phase table value
936  */
937 #define QEOV2_PWM_PHASE_TABLE_PWM7_MASK (0xC000U)
938 #define QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT (14U)
939 #define QEOV2_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK)
940 #define QEOV2_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT)
941 
942 /*
943  * PWM6 (RW)
944  *
945  * pwm phase table value
946  */
947 #define QEOV2_PWM_PHASE_TABLE_PWM6_MASK (0x3000U)
948 #define QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT (12U)
949 #define QEOV2_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK)
950 #define QEOV2_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT)
951 
952 /*
953  * PWM5 (RW)
954  *
955  * pwm phase table value
956  */
957 #define QEOV2_PWM_PHASE_TABLE_PWM5_MASK (0xC00U)
958 #define QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT (10U)
959 #define QEOV2_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK)
960 #define QEOV2_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT)
961 
962 /*
963  * PWM4 (RW)
964  *
965  * pwm phase table value
966  */
967 #define QEOV2_PWM_PHASE_TABLE_PWM4_MASK (0x300U)
968 #define QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT (8U)
969 #define QEOV2_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK)
970 #define QEOV2_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT)
971 
972 /*
973  * PWM3 (RW)
974  *
975  * pwm phase table value
976  */
977 #define QEOV2_PWM_PHASE_TABLE_PWM3_MASK (0xC0U)
978 #define QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT (6U)
979 #define QEOV2_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK)
980 #define QEOV2_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT)
981 
982 /*
983  * PWM2 (RW)
984  *
985  * pwm phase table value
986  */
987 #define QEOV2_PWM_PHASE_TABLE_PWM2_MASK (0x30U)
988 #define QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT (4U)
989 #define QEOV2_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK)
990 #define QEOV2_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT)
991 
992 /*
993  * PWM1 (RW)
994  *
995  * pwm phase table value
996  */
997 #define QEOV2_PWM_PHASE_TABLE_PWM1_MASK (0xCU)
998 #define QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT (2U)
999 #define QEOV2_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK)
1000 #define QEOV2_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT)
1001 
1002 /*
1003  * PWM0 (RW)
1004  *
1005  * pwm phase table value
1006  */
1007 #define QEOV2_PWM_PHASE_TABLE_PWM0_MASK (0x3U)
1008 #define QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT (0U)
1009 #define QEOV2_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK)
1010 #define QEOV2_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT)
1011 
1012 /* Bitfield definition for register: POSTION_SOFTWARE */
1013 /*
1014  * POSTION_SOFTWAVE (RW)
1015  *
1016  * softwave inject postion
1017  */
1018 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL)
1019 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U)
1020 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK)
1021 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT)
1022 
1023 /* Bitfield definition for register: POSTION_SEL */
1024 /*
1025  * POSTION_SEL (RW)
1026  *
1027  * enable softwave inject postion.
1028  * 0: disable.
1029  * 1: enable.
1030  */
1031 #define QEOV2_POSTION_SEL_POSTION_SEL_MASK (0x1U)
1032 #define QEOV2_POSTION_SEL_POSTION_SEL_SHIFT (0U)
1033 #define QEOV2_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEOV2_POSTION_SEL_POSTION_SEL_SHIFT) & QEOV2_POSTION_SEL_POSTION_SEL_MASK)
1034 #define QEOV2_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEOV2_POSTION_SEL_POSTION_SEL_MASK) >> QEOV2_POSTION_SEL_POSTION_SEL_SHIFT)
1035 
1036 /* Bitfield definition for register: STATUS */
1037 /*
1038  * PWM_FOURCE (RO)
1039  *
1040  * qeo_pwm_force observe
1041  */
1042 #define QEOV2_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL)
1043 #define QEOV2_STATUS_PWM_FOURCE_SHIFT (16U)
1044 #define QEOV2_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEOV2_STATUS_PWM_FOURCE_MASK) >> QEOV2_STATUS_PWM_FOURCE_SHIFT)
1045 
1046 /*
1047  * PWM_SAFETY (RO)
1048  *
1049  * pwm_fault status
1050  */
1051 #define QEOV2_STATUS_PWM_SAFETY_MASK (0x1U)
1052 #define QEOV2_STATUS_PWM_SAFETY_SHIFT (0U)
1053 #define QEOV2_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_STATUS_PWM_SAFETY_MASK) >> QEOV2_STATUS_PWM_SAFETY_SHIFT)
1054 
1055 /* Bitfield definition for register: DEBUG0 */
1056 /*
1057  * VALUE_DAC0 (RO)
1058  *
1059  * wave0
1060  */
1061 #define QEOV2_DEBUG0_VALUE_DAC0_MASK (0xFFFFFFFFUL)
1062 #define QEOV2_DEBUG0_VALUE_DAC0_SHIFT (0U)
1063 #define QEOV2_DEBUG0_VALUE_DAC0_GET(x) (((uint32_t)(x) & QEOV2_DEBUG0_VALUE_DAC0_MASK) >> QEOV2_DEBUG0_VALUE_DAC0_SHIFT)
1064 
1065 /* Bitfield definition for register: DEBUG1 */
1066 /*
1067  * QEO_FINISH (RO)
1068  *
1069  * qeo finish observe
1070  */
1071 #define QEOV2_DEBUG1_QEO_FINISH_MASK (0x10000000UL)
1072 #define QEOV2_DEBUG1_QEO_FINISH_SHIFT (28U)
1073 #define QEOV2_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_QEO_FINISH_MASK) >> QEOV2_DEBUG1_QEO_FINISH_SHIFT)
1074 
1075 /*
1076  * PAD_Z (RO)
1077  *
1078  * pad_z observe
1079  */
1080 #define QEOV2_DEBUG1_PAD_Z_MASK (0x1000000UL)
1081 #define QEOV2_DEBUG1_PAD_Z_SHIFT (24U)
1082 #define QEOV2_DEBUG1_PAD_Z_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_Z_MASK) >> QEOV2_DEBUG1_PAD_Z_SHIFT)
1083 
1084 /*
1085  * PAD_B (RO)
1086  *
1087  * pad_b observe
1088  */
1089 #define QEOV2_DEBUG1_PAD_B_MASK (0x100000UL)
1090 #define QEOV2_DEBUG1_PAD_B_SHIFT (20U)
1091 #define QEOV2_DEBUG1_PAD_B_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_B_MASK) >> QEOV2_DEBUG1_PAD_B_SHIFT)
1092 
1093 /*
1094  * PAD_A (RO)
1095  *
1096  * pad_a observe
1097  */
1098 #define QEOV2_DEBUG1_PAD_A_MASK (0x10000UL)
1099 #define QEOV2_DEBUG1_PAD_A_SHIFT (16U)
1100 #define QEOV2_DEBUG1_PAD_A_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_A_MASK) >> QEOV2_DEBUG1_PAD_A_SHIFT)
1101 
1102 /* Bitfield definition for register: DEBUG2 */
1103 /*
1104  * ABZ_OWN_POSTION (RO)
1105  *
1106  * abz_own_postion observe
1107  */
1108 #define QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL)
1109 #define QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U)
1110 #define QEOV2_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT)
1111 
1112 /* Bitfield definition for register: DEBUG3 */
1113 /*
1114  * ABZ_OWN_POSTION (RO)
1115  *
1116  * abz_own_postion observe
1117  */
1118 #define QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL)
1119 #define QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U)
1120 #define QEOV2_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT)
1121 
1122 /* Bitfield definition for register: DEBUG4 */
1123 /*
1124  * VALUE_DAC1 (RO)
1125  *
1126  * wave1
1127  */
1128 #define QEOV2_DEBUG4_VALUE_DAC1_MASK (0xFFFFFFFFUL)
1129 #define QEOV2_DEBUG4_VALUE_DAC1_SHIFT (0U)
1130 #define QEOV2_DEBUG4_VALUE_DAC1_GET(x) (((uint32_t)(x) & QEOV2_DEBUG4_VALUE_DAC1_MASK) >> QEOV2_DEBUG4_VALUE_DAC1_SHIFT)
1131 
1132 /* Bitfield definition for register: DEBUG5 */
1133 /*
1134  * VALUE_DAC2 (RO)
1135  *
1136  * wave2
1137  */
1138 #define QEOV2_DEBUG5_VALUE_DAC2_MASK (0xFFFFFFFFUL)
1139 #define QEOV2_DEBUG5_VALUE_DAC2_SHIFT (0U)
1140 #define QEOV2_DEBUG5_VALUE_DAC2_GET(x) (((uint32_t)(x) & QEOV2_DEBUG5_VALUE_DAC2_MASK) >> QEOV2_DEBUG5_VALUE_DAC2_SHIFT)
1141 
1142 
1143 
1144 /* PHASE_SHIFT register group index macro definition */
1145 #define QEOV2_WAVE_PHASE_SHIFT_WAVE0 (0UL)
1146 #define QEOV2_WAVE_PHASE_SHIFT_WAVE1 (1UL)
1147 #define QEOV2_WAVE_PHASE_SHIFT_WAVE2 (2UL)
1148 
1149 /* AMPLITUDE register group index macro definition */
1150 #define QEOV2_WAVE_AMPLITUDE_WAVE0 (0UL)
1151 #define QEOV2_WAVE_AMPLITUDE_WAVE1 (1UL)
1152 #define QEOV2_WAVE_AMPLITUDE_WAVE2 (2UL)
1153 
1154 /* MID_POINT register group index macro definition */
1155 #define QEOV2_WAVE_MID_POINT_WAVE0 (0UL)
1156 #define QEOV2_WAVE_MID_POINT_WAVE1 (1UL)
1157 #define QEOV2_WAVE_MID_POINT_WAVE2 (2UL)
1158 
1159 /* LIMIT0 register group index macro definition */
1160 #define QEOV2_LIMIT0_WAVE0 (0UL)
1161 #define QEOV2_LIMIT0_WAVE1 (1UL)
1162 #define QEOV2_LIMIT0_WAVE2 (2UL)
1163 
1164 /* LIMIT1 register group index macro definition */
1165 #define QEOV2_LIMIT1_WAVE0 (0UL)
1166 #define QEOV2_LIMIT1_WAVE1 (1UL)
1167 #define QEOV2_LIMIT1_WAVE2 (2UL)
1168 
1169 /* DEADZONE_SHIFT register group index macro definition */
1170 #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE0 (0UL)
1171 #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE1 (1UL)
1172 #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE2 (2UL)
1173 
1174 /* PHASE_SHIFT register group index macro definition */
1175 #define QEOV2_ABZ_PHASE_SHIFT_A (0UL)
1176 #define QEOV2_ABZ_PHASE_SHIFT_B (1UL)
1177 #define QEOV2_ABZ_PHASE_SHIFT_Z (2UL)
1178 
1179 /* PHASE_SHIFT register group index macro definition */
1180 #define QEOV2_PWM_PHASE_SHIFT_A (0UL)
1181 #define QEOV2_PWM_PHASE_SHIFT_B (1UL)
1182 #define QEOV2_PWM_PHASE_SHIFT_C (2UL)
1183 #define QEOV2_PWM_PHASE_SHIFT_D (3UL)
1184 
1185 /* PHASE_TABLE register group index macro definition */
1186 #define QEOV2_PWM_PHASE_TABLE_POSEDGE0 (0UL)
1187 #define QEOV2_PWM_PHASE_TABLE_POSEDGE1 (1UL)
1188 #define QEOV2_PWM_PHASE_TABLE_POSEDGE2 (2UL)
1189 #define QEOV2_PWM_PHASE_TABLE_POSEDGE3 (3UL)
1190 #define QEOV2_PWM_PHASE_TABLE_POSEDGE4 (4UL)
1191 #define QEOV2_PWM_PHASE_TABLE_POSEDGE5 (5UL)
1192 #define QEOV2_PWM_PHASE_TABLE_POSEDGE6 (6UL)
1193 #define QEOV2_PWM_PHASE_TABLE_POSEDGE7 (7UL)
1194 #define QEOV2_PWM_PHASE_TABLE_POSEDGE8 (8UL)
1195 #define QEOV2_PWM_PHASE_TABLE_POSEDGE9 (9UL)
1196 #define QEOV2_PWM_PHASE_TABLE_POSEDGE10 (10UL)
1197 #define QEOV2_PWM_PHASE_TABLE_POSEDGE11 (11UL)
1198 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE0 (12UL)
1199 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE1 (13UL)
1200 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE2 (14UL)
1201 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE3 (15UL)
1202 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE4 (16UL)
1203 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE5 (17UL)
1204 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE6 (18UL)
1205 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE7 (19UL)
1206 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE8 (20UL)
1207 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE9 (21UL)
1208 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE10 (22UL)
1209 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE11 (23UL)
1210 
1211 
1212 #endif /* HPM_QEOV2_H */
QEOV2_Type
Definition: hpm_qeov2_regs.h:12