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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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Go to the source code of this file.
Data Structures | |
| struct | QEOV2_Type |
| #define QEOV2_ABZ_LINE_WIDTH_LINE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK) >> QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT) |
| #define QEOV2_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_LINE_WIDTH_LINE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK) |
| #define QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT (0U) |
| #define QEOV2_ABZ_MODE_A_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_A_POLARITY_MASK) >> QEOV2_ABZ_MODE_A_POLARITY_SHIFT) |
| #define QEOV2_ABZ_MODE_A_POLARITY_MASK (0x1000U) |
| #define QEOV2_ABZ_MODE_A_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_A_POLARITY_SHIFT) & QEOV2_ABZ_MODE_A_POLARITY_MASK) |
| #define QEOV2_ABZ_MODE_A_POLARITY_SHIFT (12U) |
| #define QEOV2_ABZ_MODE_A_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_A_TYPE_MASK) >> QEOV2_ABZ_MODE_A_TYPE_SHIFT) |
| #define QEOV2_ABZ_MODE_A_TYPE_MASK (0x3U) |
| #define QEOV2_ABZ_MODE_A_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_A_TYPE_SHIFT) & QEOV2_ABZ_MODE_A_TYPE_MASK) |
| #define QEOV2_ABZ_MODE_A_TYPE_SHIFT (0U) |
| #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK) >> QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT) |
| #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK (0x80000000UL) |
| #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK) |
| #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT (31U) |
| #define QEOV2_ABZ_MODE_B_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_B_POLARITY_MASK) >> QEOV2_ABZ_MODE_B_POLARITY_SHIFT) |
| #define QEOV2_ABZ_MODE_B_POLARITY_MASK (0x10000UL) |
| #define QEOV2_ABZ_MODE_B_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_B_POLARITY_SHIFT) & QEOV2_ABZ_MODE_B_POLARITY_MASK) |
| #define QEOV2_ABZ_MODE_B_POLARITY_SHIFT (16U) |
| #define QEOV2_ABZ_MODE_B_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_B_TYPE_MASK) >> QEOV2_ABZ_MODE_B_TYPE_SHIFT) |
| #define QEOV2_ABZ_MODE_B_TYPE_MASK (0x30U) |
| #define QEOV2_ABZ_MODE_B_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_B_TYPE_SHIFT) & QEOV2_ABZ_MODE_B_TYPE_MASK) |
| #define QEOV2_ABZ_MODE_B_TYPE_SHIFT (4U) |
| #define QEOV2_ABZ_MODE_EN_WDOG_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_EN_WDOG_MASK) >> QEOV2_ABZ_MODE_EN_WDOG_SHIFT) |
| #define QEOV2_ABZ_MODE_EN_WDOG_MASK (0x1000000UL) |
| #define QEOV2_ABZ_MODE_EN_WDOG_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_EN_WDOG_SHIFT) & QEOV2_ABZ_MODE_EN_WDOG_MASK) |
| #define QEOV2_ABZ_MODE_EN_WDOG_SHIFT (24U) |
| #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK) >> QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT) |
| #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK (0x8000000UL) |
| #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK) |
| #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT (27U) |
| #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) |
| #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL) |
| #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) |
| #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U) |
| #define QEOV2_ABZ_MODE_Z_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_POLARITY_MASK) >> QEOV2_ABZ_MODE_Z_POLARITY_SHIFT) |
| #define QEOV2_ABZ_MODE_Z_POLARITY_MASK (0x100000UL) |
| #define QEOV2_ABZ_MODE_Z_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_POLARITY_SHIFT) & QEOV2_ABZ_MODE_Z_POLARITY_MASK) |
| #define QEOV2_ABZ_MODE_Z_POLARITY_SHIFT (20U) |
| #define QEOV2_ABZ_MODE_Z_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_TYPE_MASK) >> QEOV2_ABZ_MODE_Z_TYPE_SHIFT) |
| #define QEOV2_ABZ_MODE_Z_TYPE_MASK (0x300U) |
| #define QEOV2_ABZ_MODE_Z_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_TYPE_SHIFT) & QEOV2_ABZ_MODE_Z_TYPE_MASK) |
| #define QEOV2_ABZ_MODE_Z_TYPE_SHIFT (8U) |
| #define QEOV2_ABZ_OVERALL_OFFSET_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK) >> QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT) |
| #define QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_OVERALL_OFFSET_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK) |
| #define QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT (0U) |
| #define QEOV2_ABZ_PHASE_SHIFT_A (0UL) |
| #define QEOV2_ABZ_PHASE_SHIFT_B (1UL) |
| #define QEOV2_ABZ_PHASE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK) >> QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT) |
| #define QEOV2_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_PHASE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK) |
| #define QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT (0U) |
| #define QEOV2_ABZ_PHASE_SHIFT_Z (2UL) |
| #define QEOV2_ABZ_POSTION_SYNC_POSTION_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK) >> QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT) |
| #define QEOV2_ABZ_POSTION_SYNC_POSTION_MASK (0x1U) |
| #define QEOV2_ABZ_POSTION_SYNC_POSTION_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK) |
| #define QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT (0U) |
| #define QEOV2_ABZ_RESOLUTION_LINES_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_RESOLUTION_LINES_MASK) >> QEOV2_ABZ_RESOLUTION_LINES_SHIFT) |
| #define QEOV2_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_RESOLUTION_LINES_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_RESOLUTION_LINES_SHIFT) & QEOV2_ABZ_RESOLUTION_LINES_MASK) |
| #define QEOV2_ABZ_RESOLUTION_LINES_SHIFT (0U) |
| #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT) |
| #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK) |
| #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U) |
| #define QEOV2_ABZ_Z_END_Z_END_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_Z_END_Z_END_MASK) >> QEOV2_ABZ_Z_END_Z_END_SHIFT) |
| #define QEOV2_ABZ_Z_END_Z_END_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_Z_END_Z_END_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_Z_END_Z_END_SHIFT) & QEOV2_ABZ_Z_END_Z_END_MASK) |
| #define QEOV2_ABZ_Z_END_Z_END_SHIFT (0U) |
| #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT) |
| #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK (0x300U) |
| #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK) |
| #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT (8U) |
| #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT) |
| #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK (0x30U) |
| #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK) |
| #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT (4U) |
| #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK) >> QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT) |
| #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK) |
| #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT (0U) |
| #define QEOV2_ABZ_Z_START_Z_START_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_ABZ_Z_START_Z_START_MASK) >> QEOV2_ABZ_Z_START_Z_START_SHIFT) |
| #define QEOV2_ABZ_Z_START_Z_START_MASK (0xFFFFFFFFUL) |
| #define QEOV2_ABZ_Z_START_Z_START_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_ABZ_Z_START_Z_START_SHIFT) & QEOV2_ABZ_Z_START_Z_START_MASK) |
| #define QEOV2_ABZ_Z_START_Z_START_SHIFT (0U) |
| #define QEOV2_DEBUG0_VALUE_DAC0_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG0_VALUE_DAC0_MASK) >> QEOV2_DEBUG0_VALUE_DAC0_SHIFT) |
| #define QEOV2_DEBUG0_VALUE_DAC0_MASK (0xFFFFFFFFUL) |
| #define QEOV2_DEBUG0_VALUE_DAC0_SHIFT (0U) |
| #define QEOV2_DEBUG1_PAD_A_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG1_PAD_A_MASK) >> QEOV2_DEBUG1_PAD_A_SHIFT) |
| #define QEOV2_DEBUG1_PAD_A_MASK (0x10000UL) |
| #define QEOV2_DEBUG1_PAD_A_SHIFT (16U) |
| #define QEOV2_DEBUG1_PAD_B_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG1_PAD_B_MASK) >> QEOV2_DEBUG1_PAD_B_SHIFT) |
| #define QEOV2_DEBUG1_PAD_B_MASK (0x100000UL) |
| #define QEOV2_DEBUG1_PAD_B_SHIFT (20U) |
| #define QEOV2_DEBUG1_PAD_Z_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG1_PAD_Z_MASK) >> QEOV2_DEBUG1_PAD_Z_SHIFT) |
| #define QEOV2_DEBUG1_PAD_Z_MASK (0x1000000UL) |
| #define QEOV2_DEBUG1_PAD_Z_SHIFT (24U) |
| #define QEOV2_DEBUG1_QEO_FINISH_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG1_QEO_FINISH_MASK) >> QEOV2_DEBUG1_QEO_FINISH_SHIFT) |
| #define QEOV2_DEBUG1_QEO_FINISH_MASK (0x10000000UL) |
| #define QEOV2_DEBUG1_QEO_FINISH_SHIFT (28U) |
| #define QEOV2_DEBUG2_ABZ_OWN_POSTION_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT) |
| #define QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) |
| #define QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U) |
| #define QEOV2_DEBUG3_ABZ_OWN_POSTION_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT) |
| #define QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) |
| #define QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U) |
| #define QEOV2_DEBUG4_VALUE_DAC1_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG4_VALUE_DAC1_MASK) >> QEOV2_DEBUG4_VALUE_DAC1_SHIFT) |
| #define QEOV2_DEBUG4_VALUE_DAC1_MASK (0xFFFFFFFFUL) |
| #define QEOV2_DEBUG4_VALUE_DAC1_SHIFT (0U) |
| #define QEOV2_DEBUG5_VALUE_DAC2_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_DEBUG5_VALUE_DAC2_MASK) >> QEOV2_DEBUG5_VALUE_DAC2_SHIFT) |
| #define QEOV2_DEBUG5_VALUE_DAC2_MASK (0xFFFFFFFFUL) |
| #define QEOV2_DEBUG5_VALUE_DAC2_SHIFT (0U) |
| #define QEOV2_LIMIT0_WAVE0 (0UL) |
| #define QEOV2_LIMIT0_WAVE1 (1UL) |
| #define QEOV2_LIMIT0_WAVE2 (2UL) |
| #define QEOV2_LIMIT1_WAVE0 (0UL) |
| #define QEOV2_LIMIT1_WAVE1 (1UL) |
| #define QEOV2_LIMIT1_WAVE2 (2UL) |
| #define QEOV2_POSTION_SEL_POSTION_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_POSTION_SEL_POSTION_SEL_MASK) >> QEOV2_POSTION_SEL_POSTION_SEL_SHIFT) |
| #define QEOV2_POSTION_SEL_POSTION_SEL_MASK (0x1U) |
| #define QEOV2_POSTION_SEL_POSTION_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_POSTION_SEL_POSTION_SEL_SHIFT) & QEOV2_POSTION_SEL_POSTION_SEL_MASK) |
| #define QEOV2_POSTION_SEL_POSTION_SEL_SHIFT (0U) |
| #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) |
| #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL) |
| #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) |
| #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U) |
| #define QEOV2_PWM_MODE_ENABLE_PWM_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_ENABLE_PWM_MASK) >> QEOV2_PWM_MODE_ENABLE_PWM_SHIFT) |
| #define QEOV2_PWM_MODE_ENABLE_PWM_MASK (0x8000U) |
| #define QEOV2_PWM_MODE_ENABLE_PWM_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_ENABLE_PWM_SHIFT) & QEOV2_PWM_MODE_ENABLE_PWM_MASK) |
| #define QEOV2_PWM_MODE_ENABLE_PWM_SHIFT (15U) |
| #define QEOV2_PWM_MODE_PHASE_NUM_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PHASE_NUM_MASK) >> QEOV2_PWM_MODE_PHASE_NUM_SHIFT) |
| #define QEOV2_PWM_MODE_PHASE_NUM_MASK (0xFU) |
| #define QEOV2_PWM_MODE_PHASE_NUM_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PHASE_NUM_SHIFT) & QEOV2_PWM_MODE_PHASE_NUM_MASK) |
| #define QEOV2_PWM_MODE_PHASE_NUM_SHIFT (0U) |
| #define QEOV2_PWM_MODE_PWM0_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL) |
| #define QEOV2_PWM_MODE_PWM0_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT (16U) |
| #define QEOV2_PWM_MODE_PWM1_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL) |
| #define QEOV2_PWM_MODE_PWM1_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT (18U) |
| #define QEOV2_PWM_MODE_PWM2_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL) |
| #define QEOV2_PWM_MODE_PWM2_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT (20U) |
| #define QEOV2_PWM_MODE_PWM3_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL) |
| #define QEOV2_PWM_MODE_PWM3_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT (22U) |
| #define QEOV2_PWM_MODE_PWM4_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL) |
| #define QEOV2_PWM_MODE_PWM4_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT (24U) |
| #define QEOV2_PWM_MODE_PWM5_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL) |
| #define QEOV2_PWM_MODE_PWM5_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT (26U) |
| #define QEOV2_PWM_MODE_PWM6_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL) |
| #define QEOV2_PWM_MODE_PWM6_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT (28U) |
| #define QEOV2_PWM_MODE_PWM7_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT) |
| #define QEOV2_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL) |
| #define QEOV2_PWM_MODE_PWM7_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK) |
| #define QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT (30U) |
| #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) |
| #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U) |
| #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) |
| #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U) |
| #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) |
| #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U) |
| #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK) |
| #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U) |
| #define QEOV2_PWM_MODE_REVISE_UP_DN_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK) >> QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT) |
| #define QEOV2_PWM_MODE_REVISE_UP_DN_MASK (0x10U) |
| #define QEOV2_PWM_MODE_REVISE_UP_DN_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK) |
| #define QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT (4U) |
| #define QEOV2_PWM_PHASE_SHIFT_A (0UL) |
| #define QEOV2_PWM_PHASE_SHIFT_B (1UL) |
| #define QEOV2_PWM_PHASE_SHIFT_C (2UL) |
| #define QEOV2_PWM_PHASE_SHIFT_D (3UL) |
| #define QEOV2_PWM_PHASE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK) >> QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT) |
| #define QEOV2_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_PWM_PHASE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK) |
| #define QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT (0U) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE0 (12UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE1 (13UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE10 (22UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE11 (23UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE2 (14UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE3 (15UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE4 (16UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE5 (17UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE6 (18UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE7 (19UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE8 (20UL) |
| #define QEOV2_PWM_PHASE_TABLE_NEGEDGE9 (21UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE0 (0UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE1 (1UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE10 (10UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE11 (11UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE2 (2UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE3 (3UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE4 (4UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE5 (5UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE6 (6UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE7 (7UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE8 (8UL) |
| #define QEOV2_PWM_PHASE_TABLE_POSEDGE9 (9UL) |
| #define QEOV2_PWM_PHASE_TABLE_PWM0_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM0_MASK (0x3U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM0_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT (0U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM1_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM1_MASK (0xCU) |
| #define QEOV2_PWM_PHASE_TABLE_PWM1_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT (2U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM2_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM2_MASK (0x30U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM2_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT (4U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM3_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM3_MASK (0xC0U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM3_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT (6U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM4_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM4_MASK (0x300U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM4_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT (8U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM5_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM5_MASK (0xC00U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM5_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT (10U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM6_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM6_MASK (0x3000U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM6_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT (12U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM7_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT) |
| #define QEOV2_PWM_PHASE_TABLE_PWM7_MASK (0xC000U) |
| #define QEOV2_PWM_PHASE_TABLE_PWM7_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK) |
| #define QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT (14U) |
| #define QEOV2_PWM_RESOLUTION_LINES_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_PWM_RESOLUTION_LINES_MASK) >> QEOV2_PWM_RESOLUTION_LINES_SHIFT) |
| #define QEOV2_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) |
| #define QEOV2_PWM_RESOLUTION_LINES_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_PWM_RESOLUTION_LINES_SHIFT) & QEOV2_PWM_RESOLUTION_LINES_MASK) |
| #define QEOV2_PWM_RESOLUTION_LINES_SHIFT (0U) |
| #define QEOV2_STATUS_PWM_FOURCE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_STATUS_PWM_FOURCE_MASK) >> QEOV2_STATUS_PWM_FOURCE_SHIFT) |
| #define QEOV2_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL) |
| #define QEOV2_STATUS_PWM_FOURCE_SHIFT (16U) |
| #define QEOV2_STATUS_PWM_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_STATUS_PWM_SAFETY_MASK) >> QEOV2_STATUS_PWM_SAFETY_SHIFT) |
| #define QEOV2_STATUS_PWM_SAFETY_MASK (0x1U) |
| #define QEOV2_STATUS_PWM_SAFETY_SHIFT (0U) |
| #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT) |
| #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU) |
| #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK) |
| #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U) |
| #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT) |
| #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL) |
| #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK) |
| #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U) |
| #define QEOV2_WAVE_AMPLITUDE_WAVE0 (0UL) |
| #define QEOV2_WAVE_AMPLITUDE_WAVE1 (1UL) |
| #define QEOV2_WAVE_AMPLITUDE_WAVE2 (2UL) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE0 (0UL) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE1 (1UL) |
| #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE2 (2UL) |
| #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT) |
| #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK) |
| #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT (0U) |
| #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT) |
| #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK) |
| #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT (0U) |
| #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT) |
| #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK) |
| #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT (0U) |
| #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT) |
| #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK) |
| #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT (0U) |
| #define QEOV2_WAVE_MID_POINT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MID_POINT_VAL_MASK) >> QEOV2_WAVE_MID_POINT_VAL_SHIFT) |
| #define QEOV2_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_MID_POINT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MID_POINT_VAL_SHIFT) & QEOV2_WAVE_MID_POINT_VAL_MASK) |
| #define QEOV2_WAVE_MID_POINT_VAL_SHIFT (0U) |
| #define QEOV2_WAVE_MID_POINT_WAVE0 (0UL) |
| #define QEOV2_WAVE_MID_POINT_WAVE1 (1UL) |
| #define QEOV2_WAVE_MID_POINT_WAVE2 (2UL) |
| #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK) >> QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT) |
| #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK (0x10U) |
| #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK) |
| #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT (4U) |
| #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT) |
| #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK (0x40U) |
| #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK) |
| #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT (6U) |
| #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT) |
| #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK (0x20U) |
| #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK) |
| #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT (5U) |
| #define QEOV2_WAVE_MODE_SADDLE_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK) >> QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT) |
| #define QEOV2_WAVE_MODE_SADDLE_TYPE_MASK (0x80U) |
| #define QEOV2_WAVE_MODE_SADDLE_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK) |
| #define QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT (7U) |
| #define QEOV2_WAVE_MODE_VD_VQ_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK) >> QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT) |
| #define QEOV2_WAVE_MODE_VD_VQ_SEL_MASK (0x4U) |
| #define QEOV2_WAVE_MODE_VD_VQ_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK) |
| #define QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT (2U) |
| #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U) |
| #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U) |
| #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U) |
| #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U) |
| #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL) |
| #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U) |
| #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL) |
| #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U) |
| #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL) |
| #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U) |
| #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL) |
| #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) |
| #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U) |
| #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) |
| #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U) |
| #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) |
| #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U) |
| #define QEOV2_WAVE_PHASE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK) >> QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT) |
| #define QEOV2_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_PHASE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK) |
| #define QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT (0U) |
| #define QEOV2_WAVE_PHASE_SHIFT_WAVE0 (0UL) |
| #define QEOV2_WAVE_PHASE_SHIFT_WAVE1 (1UL) |
| #define QEOV2_WAVE_PHASE_SHIFT_WAVE2 (2UL) |
| #define QEOV2_WAVE_PWM_CYCLE_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK) >> QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT) |
| #define QEOV2_WAVE_PWM_CYCLE_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_PWM_CYCLE_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK) |
| #define QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT (0U) |
| #define QEOV2_WAVE_RESOLUTION_LINES_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_RESOLUTION_LINES_MASK) >> QEOV2_WAVE_RESOLUTION_LINES_SHIFT) |
| #define QEOV2_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_RESOLUTION_LINES_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_RESOLUTION_LINES_SHIFT) & QEOV2_WAVE_RESOLUTION_LINES_MASK) |
| #define QEOV2_WAVE_RESOLUTION_LINES_SHIFT (0U) |
| #define QEOV2_WAVE_VD_INJECT_VD_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK) >> QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT) |
| #define QEOV2_WAVE_VD_INJECT_VD_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_VD_INJECT_VD_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK) |
| #define QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT (0U) |
| #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT) |
| #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U) |
| #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK) |
| #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U) |
| #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK) >> QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT) |
| #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK (0xFFFFFFFFUL) |
| #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK) |
| #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT (0U) |
1.9.1