HPM SDK
HPMicro Software Development Kit
hpm_sei_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SEI_H
10 #define HPM_SEI_H
11 
12 typedef struct {
13  struct {
14  struct {
15  __RW uint32_t CTRL; /* 0x0: Engine control register */
16  __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */
17  __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */
18  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
19  __R uint32_t EXE_STA; /* 0x10: Execution status */
20  __R uint32_t EXE_PTR; /* 0x14: Execution pointer */
21  __R uint32_t EXE_INST; /* 0x18: Execution instruction */
22  __R uint32_t WDG_STA; /* 0x1C: Watch dog status */
23  } ENGINE;
24  struct {
25  __RW uint32_t CTRL; /* 0x20: Transceiver control register */
26  __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */
27  __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */
28  __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */
29  __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */
30  __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
31  __R uint32_t PIN; /* 0x38: Transceiver pin status */
32  __R uint32_t STATE; /* 0x3C: FSM of asynchronous */
33  } XCVR;
34  struct {
35  __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */
36  __W uint32_t SW; /* 0x44: Software trigger */
37  __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */
38  __RW uint32_t PRD; /* 0x4C: Trigger period */
39  __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */
40  __RW uint32_t IN_DIV; /* 0x54: Trigger input divider */
41  __R uint8_t RESERVED0[8]; /* 0x58 - 0x5F: Reserved */
42  __R uint32_t PRD_STS; /* 0x60: Period trigger status */
43  __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */
44  __R uint32_t DIV_STS; /* 0x68: Trigger input divider status */
45  __R uint8_t RESERVED1[20]; /* 0x6C - 0x7F: Reserved */
46  } TRG;
47  struct {
48  __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */
49  __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */
50  __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */
51  __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */
52  } TRG_TABLE;
53  struct {
54  __RW uint32_t MODE; /* 0xC0: command register mode */
55  __RW uint32_t IDX; /* 0xC4: command register configuration */
56  __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */
57  __RW uint32_t CMD; /* 0xE0: command */
58  __RW uint32_t SET; /* 0xE4: command bit set register */
59  __RW uint32_t CLR; /* 0xE8: command bit clear register */
60  __RW uint32_t INV; /* 0xEC: command bit invert register */
61  __R uint32_t IN; /* 0xF0: Commad input */
62  __R uint32_t OUT; /* 0xF4: Command output */
63  __RW uint32_t STS; /* 0xF8: Command status */
64  __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */
65  } CMD;
66  struct {
67  __RW uint32_t MIN; /* 0x100: command start value */
68  __RW uint32_t MAX; /* 0x104: command end value */
69  __RW uint32_t MSK; /* 0x108: command compare bit enable */
70  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
71  __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */
72  __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */
73  __RW uint32_t PTC; /* 0x118: command pointer 8 - 11 */
74  __RW uint32_t PTD; /* 0x11C: command pointer 12 - 15 */
75  } CMD_TABLE[8];
76  struct {
77  __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */
78  __RW uint32_t CFG; /* 0x210: Latch configuration */
79  __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */
80  __R uint32_t TIME; /* 0x218: Latch time */
81  __R uint32_t STS; /* 0x21C: Latch status */
82  } LATCH[4];
83  struct {
84  __RW uint32_t SMP_EN; /* 0x280: Sample selection register */
85  __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */
86  __RW uint32_t SMP_DAT; /* 0x288: Sample data */
87  __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */
88  __RW uint32_t SMP_POS; /* 0x290: Sample override position */
89  __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */
90  __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */
91  __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */
92  __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */
93  __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */
94  __RW uint32_t UPD_DAT; /* 0x2A8: Update data */
95  __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */
96  __RW uint32_t UPD_POS; /* 0x2B0: Update override position */
97  __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */
98  __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */
99  __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */
100  __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */
101  __R uint32_t SMP_STS; /* 0x2C4: Sample status */
102  __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */
103  __R uint32_t TIME_IN; /* 0x2CC: input time */
104  __R uint32_t POS_IN; /* 0x2D0: Input position */
105  __R uint32_t REV_IN; /* 0x2D4: Input revolution */
106  __R uint32_t SPD_IN; /* 0x2D8: Input speed */
107  __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */
108  __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */
109  __R uint32_t UPD_STS; /* 0x2E4: Update status */
110  __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */
111  } POS;
112  struct {
113  __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */
114  __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */
115  __R uint32_t INT_STS; /* 0x308: Interrupt status */
116  __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */
117  __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */
118  __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */
119  __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */
120  __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */
121  } IRQ;
122  __RW uint32_t DMA_EN; /* 0x320: DMA Enable */
123  __R uint8_t RESERVED0[220]; /* 0x324 - 0x3FF: Reserved */
124  } CTRL[13];
125  __RW uint32_t INSTR[256]; /* 0x3400 - 0x37FC: Instructions */
126  struct {
127  __RW uint32_t MODE; /* 0x3800: */
128  __RW uint32_t IDX; /* 0x3804: Data register bit index */
129  __RW uint32_t GOLD; /* 0x3808: Gold data for data check */
130  __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */
131  __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */
132  __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */
133  __RW uint32_t DATA; /* 0x3820: Data value */
134  __RW uint32_t SET; /* 0x3824: Data bit set */
135  __RW uint32_t CLR; /* 0x3828: Data bit clear */
136  __RW uint32_t INV; /* 0x382C: Data bit invert */
137  __R uint32_t IN; /* 0x3830: Data input */
138  __R uint32_t OUT; /* 0x3834: Data output */
139  __RW uint32_t STS; /* 0x3838: Data status */
140  __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */
141  } DAT[32];
142 } SEI_Type;
143 
144 
145 /* Bitfield definition for register of struct array CTRL: CTRL */
146 /*
147  * WATCH (RW)
148  *
149  * Enable watch dog
150  * 0: Watch dog disabled
151  * 1: Watch dog enabled
152  */
153 #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL)
154 #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U)
155 #define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK)
156 #define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT)
157 
158 /*
159  * ARMING (RW)
160  *
161  * Wait for trigger before excuting
162  * 0: Execute on enable
163  * 1: Wait trigger before exection after enabled
164  */
165 #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL)
166 #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U)
167 #define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK)
168 #define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT)
169 
170 /*
171  * EXCEPT (RW)
172  *
173  * Explain timout as exception
174  * 0: when timeout, pointer move to next instruction
175  * 1: when timeout, pointer jump to timeout vector
176  */
177 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U)
178 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U)
179 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK)
180 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT)
181 
182 /*
183  * REWIND (RW)
184  *
185  * Rewind execution pointer
186  * 0: run
187  * 1: clean status and rewind
188  */
189 #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U)
190 #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U)
191 #define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK)
192 #define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT)
193 
194 /*
195  * ENABLE (RW)
196  *
197  * Enable
198  * 0: disable
199  * 1: enable
200  */
201 #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U)
202 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U)
203 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK)
204 #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT)
205 
206 /* Bitfield definition for register of struct array CTRL: PTR_CFG */
207 /*
208  * DAT_CDM (RW)
209  *
210  * Select DATA register to receive CDM bit in BiSSC slave mode
211  * 0: ignore
212  * 1: command
213  * 2: data register 2
214  * 3: data register 3
215  * ...
216  * 29:data register 29
217  * 30: value 0 when send, ignore in receive
218  * 31: value1 when send, ignore in receive
219  */
220 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL)
221 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U)
222 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK)
223 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT)
224 
225 /*
226  * DAT_BASE (RW)
227  *
228  * Bias for data register access, if calculated index bigger than 32, index will wrap around
229  * 0: real data index
230  * 1: access index is 1 greater than instruction address
231  * 2: access index is 2 greater than instruction address
232  * ...
233  * 31: access index is 31 greater than instruction address
234  */
235 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL)
236 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U)
237 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
238 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT)
239 
240 /*
241  * POINTER_WDOG (RW)
242  *
243  * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME
244  */
245 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U)
246 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U)
247 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
248 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT)
249 
250 /*
251  * POINTER_INIT (RW)
252  *
253  * Initial execute pointer
254  */
255 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU)
256 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U)
257 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
258 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT)
259 
260 /* Bitfield definition for register of struct array CTRL: WDG_CFG */
261 /*
262  * WDOG_TIME (RW)
263  *
264  * Time out count for each instruction, counter in bit time.
265  */
266 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU)
267 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U)
268 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK)
269 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT)
270 
271 /* Bitfield definition for register of struct array CTRL: EXE_STA */
272 /*
273  * TRIGERED (RO)
274  *
275  * Execution has been triggered
276  * 0: Execution not triggered
277  * 1: Execution triggered
278  */
279 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL)
280 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U)
281 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT)
282 
283 /*
284  * ARMED (RO)
285  *
286  * Waiting for trigger for execution
287  * 0: Not in waiting status
288  * 1: In waiting status
289  */
290 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL)
291 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U)
292 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT)
293 
294 /*
295  * EXPIRE (RO)
296  *
297  * Watchdog timer expired
298  * 0: Not expired
299  * 1: Expired
300  */
301 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U)
302 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U)
303 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT)
304 
305 /*
306  * STALL (RO)
307  *
308  * Program finished
309  * 0: Program is executing
310  * 1: Program finished
311  */
312 #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U)
313 #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U)
314 #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT)
315 
316 /* Bitfield definition for register of struct array CTRL: EXE_PTR */
317 /*
318  * HALT_CNT (RO)
319  *
320  * Halt count in halt instrution
321  */
322 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL)
323 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U)
324 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT)
325 
326 /*
327  * BIT_CNT (RO)
328  *
329  * Bit count in send and receive instruction execution
330  */
331 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL)
332 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U)
333 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT)
334 
335 /*
336  * POINTER (RO)
337  *
338  * Current program pointer
339  */
340 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU)
341 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U)
342 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT)
343 
344 /* Bitfield definition for register of struct array CTRL: EXE_INST */
345 /*
346  * INST (RO)
347  *
348  * Current instruction
349  */
350 #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL)
351 #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U)
352 #define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT)
353 
354 /* Bitfield definition for register of struct array CTRL: WDG_STA */
355 /*
356  * WDOG_CNT (RO)
357  *
358  * Current watch dog counter value
359  */
360 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU)
361 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U)
362 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT)
363 
364 /* Bitfield definition for register of struct array CTRL: CTRL */
365 /*
366  * TRISMP (RW)
367  *
368  * Tipple sampe
369  * 0: sample 1 time for data transition
370  * 1: sample 3 times in receive and result in 2oo3
371  */
372 #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U)
373 #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U)
374 #define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK)
375 #define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT)
376 
377 /*
378  * PAR_CLR (WC)
379  *
380  * Clear parity error, this is a self clear bit
381  * 0: no effect
382  * 1: clear parity error
383  */
384 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U)
385 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U)
386 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK)
387 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT)
388 
389 /*
390  * RESTART (WC)
391  *
392  * Restart transceiver, this is a self clear bit
393  * 0: no effect
394  * 1: reset transceiver
395  */
396 #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U)
397 #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U)
398 #define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK)
399 #define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT)
400 
401 /*
402  * MODE (RW)
403  *
404  * Transceiver mode
405  * 0: synchronous maaster
406  * 1: synchronous slave
407  * 2: asynchronous mode
408  * 3: asynchronous mode
409  */
410 #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U)
411 #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U)
412 #define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK)
413 #define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT)
414 
415 /* Bitfield definition for register of struct array CTRL: TYPE_CFG */
416 /*
417  * WAIT_LEN (RW)
418  *
419  * Number of extra stop bit for asynchronous mode
420  * 0: 1 bit
421  * 1: 2 bit
422  * ...
423  * 255: 256 bit
424  */
425 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL)
426 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U)
427 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK)
428 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT)
429 
430 /*
431  * DATA_LEN (RW)
432  *
433  * Number of data bit for asynchronous mode
434  * 0: 1 bit
435  * 1: 2 bit
436  * ...
437  * 31: 32 bit
438  */
439 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL)
440 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U)
441 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK)
442 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT)
443 
444 /*
445  * PAR_POL (RW)
446  *
447  * Polarity of parity for asynchronous mode
448  * 0: even
449  * 1: odd
450  */
451 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U)
452 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U)
453 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK)
454 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT)
455 
456 /*
457  * PAR_EN (RW)
458  *
459  * enable parity check for asynchronous mode
460  * 0: disable
461  * 1: enable
462  */
463 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U)
464 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U)
465 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK)
466 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT)
467 
468 /*
469  * DA_IDLEZ (RW)
470  *
471  * Idle state driver of data line
472  * 0: output
473  * 1: high-Z
474  */
475 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U)
476 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U)
477 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK)
478 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT)
479 
480 /*
481  * CK_IDLEZ (RW)
482  *
483  * Idle state driver of clock line
484  * 0: output
485  * 1: high-Z
486  */
487 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U)
488 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U)
489 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK)
490 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT)
491 
492 /*
493  * DA_IDLEV (RW)
494  *
495  * Idle state value of data line
496  * 0: data'0'
497  * 1: data'1'
498  */
499 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U)
500 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U)
501 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK)
502 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT)
503 
504 /*
505  * CK_IDLEV (RW)
506  *
507  * Idle state value of clock line
508  * 0: data'0'
509  * 1: data'1'
510  */
511 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U)
512 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U)
513 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK)
514 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT)
515 
516 /* Bitfield definition for register of struct array CTRL: BAUD_CFG */
517 /*
518  * SYNC_POINT (RW)
519  *
520  * Baud synchronous time, minmum bit time
521  */
522 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL)
523 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U)
524 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK)
525 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT)
526 
527 /*
528  * BAUD_DIV (RW)
529  *
530  * Baud rate, bit time in system clock cycle
531  */
532 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU)
533 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U)
534 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK)
535 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT)
536 
537 /* Bitfield definition for register of struct array CTRL: DATA_CFG */
538 /*
539  * TXD_POINT (RW)
540  *
541  * data transmit point in system clcok cycle
542  */
543 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL)
544 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U)
545 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK)
546 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT)
547 
548 /*
549  * RXD_POINT (RW)
550  *
551  * data receive point in system clcok cycle
552  */
553 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU)
554 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U)
555 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK)
556 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT)
557 
558 /* Bitfield definition for register of struct array CTRL: CLK_CFG */
559 /*
560  * CK1_POINT (RW)
561  *
562  * clock point 1 in system clcok cycle
563  */
564 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL)
565 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U)
566 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK)
567 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT)
568 
569 /*
570  * CK0_POINT (RW)
571  *
572  * clock point 0 in system clcok cycle
573  */
574 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU)
575 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U)
576 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK)
577 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT)
578 
579 /* Bitfield definition for register of struct array CTRL: PIN */
580 /*
581  * OE_CK (RO)
582  *
583  * CK drive state
584  * 0: input
585  * 1: output
586  */
587 #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL)
588 #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U)
589 #define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT)
590 
591 /*
592  * DI_CK (RO)
593  *
594  * CK state
595  * 0: data 0
596  * 1: data 1
597  */
598 #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL)
599 #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U)
600 #define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT)
601 
602 /*
603  * DO_CK (RO)
604  *
605  * CK output
606  * 0: data 0
607  * 1: data 1
608  */
609 #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL)
610 #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U)
611 #define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT)
612 
613 /*
614  * OE_RX (RO)
615  *
616  * RX drive state
617  * 0: input
618  * 1: output
619  */
620 #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL)
621 #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U)
622 #define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT)
623 
624 /*
625  * DI_RX (RO)
626  *
627  * RX state
628  * 0: data 0
629  * 1: data 1
630  */
631 #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL)
632 #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U)
633 #define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT)
634 
635 /*
636  * DO_RX (RO)
637  *
638  * RX output
639  * 0: data 0
640  * 1: data 1
641  */
642 #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL)
643 #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U)
644 #define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT)
645 
646 /*
647  * OE_DE (RO)
648  *
649  * DE drive state
650  * 0: input
651  * 1: output
652  */
653 #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U)
654 #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U)
655 #define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT)
656 
657 /*
658  * DI_DE (RO)
659  *
660  * DE state
661  * 0: data 0
662  * 1: data 1
663  */
664 #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U)
665 #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U)
666 #define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT)
667 
668 /*
669  * DO_DE (RO)
670  *
671  * DE output
672  * 0: data 0
673  * 1: data 1
674  */
675 #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U)
676 #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U)
677 #define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT)
678 
679 /*
680  * OE_TX (RO)
681  *
682  * TX drive state
683  * 0: input
684  * 1: output
685  */
686 #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U)
687 #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U)
688 #define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT)
689 
690 /*
691  * DI_TX (RO)
692  *
693  * TX state
694  * 0: data 0
695  * 1: data 1
696  */
697 #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U)
698 #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U)
699 #define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT)
700 
701 /*
702  * DO_TX (RO)
703  *
704  * TX output
705  * 0: data 0
706  * 1: data 1
707  */
708 #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U)
709 #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U)
710 #define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT)
711 
712 /* Bitfield definition for register of struct array CTRL: STATE */
713 /*
714  * RECV_STATE (RO)
715  *
716  * FSM of asynchronous receive
717  */
718 #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL)
719 #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U)
720 #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT)
721 
722 /*
723  * SEND_STATE (RO)
724  *
725  * FSM of asynchronous transmit
726  */
727 #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL)
728 #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U)
729 #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT)
730 
731 /*
732  * PAR_ERR (RO)
733  *
734  * Parity bit error
735  */
736 #define SEI_CTRL_XCVR_STATE_PAR_ERR_MASK (0x100U)
737 #define SEI_CTRL_XCVR_STATE_PAR_ERR_SHIFT (8U)
738 #define SEI_CTRL_XCVR_STATE_PAR_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_PAR_ERR_MASK) >> SEI_CTRL_XCVR_STATE_PAR_ERR_SHIFT)
739 
740 /* Bitfield definition for register of struct array CTRL: IN_CFG */
741 /*
742  * REWIND_EN (RW)
743  *
744  * enable rewind cmd register by LATCH
745  */
746 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK (0x80000000UL)
747 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT (31U)
748 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK)
749 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT)
750 
751 /*
752  * REWIND_SEL (RW)
753  *
754  * select one LATCH to rewind CMD register
755  * 0:LATCH[0]
756  * 1:LATCH[1]
757  * 2:LATCH[2]
758  * 3:LATCH[3]
759  */
760 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK (0x3000000UL)
761 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT (24U)
762 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK)
763 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT)
764 
765 /*
766  * PRD_EN (RW)
767  *
768  * Enable period trigger (tigger 2)
769  * 0: periodical trigger disabled
770  * 1: periodical trigger enabled
771  */
772 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL)
773 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U)
774 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK)
775 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT)
776 
777 /*
778  * SYNC_SEL (RW)
779  *
780  * Synchronize sigal selection (tigger 2)
781  * 0: trigger in 0
782  * 1: trigger in 1
783  * ...
784  * 7: trigger in 7
785  */
786 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL)
787 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U)
788 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK)
789 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT)
790 
791 /*
792  * IN1_EN (RW)
793  *
794  * Enable trigger 1
795  * 0: disable trigger 1
796  * 1: enable trigger 1
797  */
798 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U)
799 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U)
800 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK)
801 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT)
802 
803 /*
804  * IN1_SEL (RW)
805  *
806  * Trigger 1 sigal selection
807  * 0: trigger in 0
808  * 1: trigger in 1
809  * ...
810  * 7: trigger in 7
811  */
812 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U)
813 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U)
814 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK)
815 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT)
816 
817 /*
818  * IN0_EN (RW)
819  *
820  * Enable trigger 0
821  * 0: disable trigger 1
822  * 1: enable trigger 1
823  */
824 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U)
825 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U)
826 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK)
827 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT)
828 
829 /*
830  * IN0_SEL (RW)
831  *
832  * Trigger 0 sigal selection
833  * 0: trigger in 0
834  * 1: trigger in 1
835  * ...
836  * 7: trigger in 7
837  */
838 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U)
839 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U)
840 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK)
841 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT)
842 
843 /* Bitfield definition for register of struct array CTRL: SW */
844 /*
845  * SOFT (WC)
846  *
847  * Software trigger (tigger 3). this bit is self-clear
848  * 0: trigger source disabled
849  * 1: trigger source enabled
850  */
851 #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U)
852 #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U)
853 #define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK)
854 #define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT)
855 
856 /* Bitfield definition for register of struct array CTRL: PRD_CFG */
857 /*
858  * ARMING (RW)
859  *
860  * Wait for trigger synchronous before trigger
861  * 0: Trigger directly
862  * 1: Wait trigger source before period trigger
863  */
864 #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL)
865 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U)
866 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK)
867 #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT)
868 
869 /*
870  * SYNC (RW)
871  *
872  * Synchronous
873  * 0: Not synchronous
874  * 1: Synchronous every trigger source
875  */
876 #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U)
877 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U)
878 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK)
879 #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT)
880 
881 /* Bitfield definition for register of struct array CTRL: PRD */
882 /*
883  * PERIOD (RW)
884  *
885  * Trigger period
886  */
887 #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL)
888 #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U)
889 #define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK)
890 #define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT)
891 
892 /* Bitfield definition for register of struct array CTRL: OUT_CFG */
893 /*
894  * OUT3_EN (RW)
895  *
896  * Enable trigger 3
897  * 0: disable trigger 3
898  * 1: enable trigger 3
899  */
900 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL)
901 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U)
902 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK)
903 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT)
904 
905 /*
906  * OUT3_SEL (RW)
907  *
908  * Trigger 3 sigal selection
909  * 0: trigger out 0
910  * 1: trigger out 1
911  * ...
912  * 7: trigger out 7
913  */
914 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL)
915 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U)
916 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK)
917 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT)
918 
919 /*
920  * OUT2_EN (RW)
921  *
922  * Enable trigger 2
923  * 0: disable trigger 2
924  * 1: enable trigger 2
925  */
926 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL)
927 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U)
928 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK)
929 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT)
930 
931 /*
932  * OUT2_SEL (RW)
933  *
934  * Trigger 2 sigal selection
935  * 0: trigger out 0
936  * 1: trigger out 1
937  * ...
938  * 7: trigger out 7
939  */
940 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL)
941 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U)
942 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK)
943 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT)
944 
945 /*
946  * OUT1_EN (RW)
947  *
948  * Enable trigger 1
949  * 0: disable trigger 1
950  * 1: enable trigger 1
951  */
952 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U)
953 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U)
954 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK)
955 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT)
956 
957 /*
958  * OUT1_SEL (RW)
959  *
960  * Trigger 1 sigal selection
961  * 0: trigger out 0
962  * 1: trigger out 1
963  * ...
964  * 7: trigger out 7
965  */
966 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U)
967 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U)
968 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK)
969 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT)
970 
971 /*
972  * OUT0_EN (RW)
973  *
974  * Enable trigger 0
975  * 0: disable trigger 1
976  * 1: enable trigger 1
977  */
978 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U)
979 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U)
980 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK)
981 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT)
982 
983 /*
984  * OUT0_SEL (RW)
985  *
986  * Trigger 0 sigal selection
987  * 0: trigger out 0
988  * 1: trigger out 1
989  * ...
990  * 7: trigger out 7
991  */
992 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U)
993 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U)
994 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK)
995 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT)
996 
997 /* Bitfield definition for register of struct array CTRL: IN_DIV */
998 /*
999  * IN1_DIV (RW)
1000  *
1001  * The divider of trigger in 1.
1002  * 0x0: disable divider
1003  * 0x1: divider by 2
1004  * 0x2: divider by 3
1005  * ...
1006  * 0xFF: divider by 256
1007  */
1008 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_MASK (0xFF00U)
1009 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_SHIFT (8U)
1010 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_DIV_IN1_DIV_SHIFT) & SEI_CTRL_TRG_IN_DIV_IN1_DIV_MASK)
1011 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_DIV_IN1_DIV_MASK) >> SEI_CTRL_TRG_IN_DIV_IN1_DIV_SHIFT)
1012 
1013 /*
1014  * IN0_DIV (RW)
1015  *
1016  * The divider of trigger in 0.
1017  * 0x0: disable divider
1018  * 0x1: divider by 2
1019  * 0x2: divider by 3
1020  * ...
1021  * 0xFF: divider by 256
1022  */
1023 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_MASK (0xFFU)
1024 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_SHIFT (0U)
1025 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_DIV_IN0_DIV_SHIFT) & SEI_CTRL_TRG_IN_DIV_IN0_DIV_MASK)
1026 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_DIV_IN0_DIV_MASK) >> SEI_CTRL_TRG_IN_DIV_IN0_DIV_SHIFT)
1027 
1028 /* Bitfield definition for register of struct array CTRL: PRD_STS */
1029 /*
1030  * TRIGERED (RO)
1031  *
1032  * Period has been triggered
1033  * 0: Not triggered
1034  * 1: Triggered
1035  */
1036 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL)
1037 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U)
1038 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT)
1039 
1040 /*
1041  * ARMED (RO)
1042  *
1043  * Waiting for trigger
1044  * 0: Not in waiting status
1045  * 1: In waiting status
1046  */
1047 #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL)
1048 #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U)
1049 #define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT)
1050 
1051 /* Bitfield definition for register of struct array CTRL: PRD_CNT */
1052 /*
1053  * PERIOD_CNT (RO)
1054  *
1055  * Trigger period counter
1056  */
1057 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL)
1058 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U)
1059 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT)
1060 
1061 /* Bitfield definition for register of struct array CTRL: DIV_STS */
1062 /*
1063  * IN1_CNT (RO)
1064  *
1065  * The divider counter for trigger in 1, trigger valid when counter is 0.
1066  */
1067 #define SEI_CTRL_TRG_DIV_STS_IN1_CNT_MASK (0xFF00U)
1068 #define SEI_CTRL_TRG_DIV_STS_IN1_CNT_SHIFT (8U)
1069 #define SEI_CTRL_TRG_DIV_STS_IN1_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_DIV_STS_IN1_CNT_MASK) >> SEI_CTRL_TRG_DIV_STS_IN1_CNT_SHIFT)
1070 
1071 /*
1072  * IN0_CNT (RO)
1073  *
1074  * The divider counter for trigger in 0, trigger valid when counter is 0.
1075  */
1076 #define SEI_CTRL_TRG_DIV_STS_IN0_CNT_MASK (0xFFU)
1077 #define SEI_CTRL_TRG_DIV_STS_IN0_CNT_SHIFT (0U)
1078 #define SEI_CTRL_TRG_DIV_STS_IN0_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_DIV_STS_IN0_CNT_MASK) >> SEI_CTRL_TRG_DIV_STS_IN0_CNT_SHIFT)
1079 
1080 /* Bitfield definition for register of struct array CTRL: 0 */
1081 /*
1082  * CMD_TRIGGER0 (RW)
1083  *
1084  * Trigger command
1085  */
1086 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL)
1087 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U)
1088 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK)
1089 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT)
1090 
1091 /* Bitfield definition for register of struct array CTRL: 0 */
1092 /*
1093  * TRIGGER0_TIME (RO)
1094  *
1095  * Trigger time
1096  */
1097 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL)
1098 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U)
1099 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT)
1100 
1101 /* Bitfield definition for register of struct array CTRL: MODE */
1102 /*
1103  * WLEN (RW)
1104  *
1105  * word length
1106  * 0: 1 bit
1107  * 1: 2 bit
1108  * ...
1109  * 31: 32 bit
1110  */
1111 #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL)
1112 #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U)
1113 #define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK)
1114 #define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT)
1115 
1116 /*
1117  * WORDER (RW)
1118  *
1119  * word order
1120  * 0: sample as bit order
1121  * 1: different from bit order
1122  */
1123 #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U)
1124 #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U)
1125 #define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK)
1126 #define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT)
1127 
1128 /*
1129  * BORDER (RW)
1130  *
1131  * bit order
1132  * 0: LSB first
1133  * 1: MSB first
1134  */
1135 #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U)
1136 #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U)
1137 #define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK)
1138 #define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT)
1139 
1140 /*
1141  * SIGNED (RW)
1142  *
1143  * Signed
1144  * 0: unsigned value
1145  * 1: signed value
1146  */
1147 #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U)
1148 #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U)
1149 #define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK)
1150 #define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT)
1151 
1152 /*
1153  * REWIND (WC)
1154  *
1155  * Write 1 to rewind read/write pointer, this is a self clear bit
1156  */
1157 #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U)
1158 #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U)
1159 #define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK)
1160 #define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT)
1161 
1162 /*
1163  * MODE (RW)
1164  *
1165  * Data mode(CMD register only support data mode)
1166  * 0: data mode
1167  * 1: check mode
1168  * 2: CRC mode
1169  */
1170 #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U)
1171 #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U)
1172 #define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK)
1173 #define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT)
1174 
1175 /* Bitfield definition for register of struct array CTRL: IDX */
1176 /*
1177  * LAST_BIT (RW)
1178  *
1179  * Last bit index for tranceive
1180  */
1181 #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL)
1182 #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U)
1183 #define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK)
1184 #define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT)
1185 
1186 /*
1187  * FIRST_BIT (RW)
1188  *
1189  * First bit index for tranceive
1190  */
1191 #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL)
1192 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U)
1193 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK)
1194 #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT)
1195 
1196 /*
1197  * MAX_BIT (RW)
1198  *
1199  * Highest bit index
1200  */
1201 #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U)
1202 #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U)
1203 #define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK)
1204 #define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT)
1205 
1206 /*
1207  * MIN_BIT (RW)
1208  *
1209  * Lowest bit index
1210  */
1211 #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU)
1212 #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U)
1213 #define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK)
1214 #define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT)
1215 
1216 /* Bitfield definition for register of struct array CTRL: CMD */
1217 /*
1218  * DATA (RW)
1219  *
1220  * DATA
1221  */
1222 #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL)
1223 #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U)
1224 #define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK)
1225 #define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT)
1226 
1227 /* Bitfield definition for register of struct array CTRL: SET */
1228 /*
1229  * DATA_SET (RW)
1230  *
1231  * DATA bit set
1232  */
1233 #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL)
1234 #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U)
1235 #define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK)
1236 #define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT)
1237 
1238 /* Bitfield definition for register of struct array CTRL: CLR */
1239 /*
1240  * DATA_CLR (RW)
1241  *
1242  * DATA bit clear
1243  */
1244 #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
1245 #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U)
1246 #define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK)
1247 #define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT)
1248 
1249 /* Bitfield definition for register of struct array CTRL: INV */
1250 /*
1251  * DATA_TGL (RW)
1252  *
1253  * DATA bit toggle
1254  */
1255 #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL)
1256 #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U)
1257 #define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK)
1258 #define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT)
1259 
1260 /* Bitfield definition for register of struct array CTRL: IN */
1261 /*
1262  * DATA_IN (RO)
1263  *
1264  * Commad input
1265  */
1266 #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL)
1267 #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U)
1268 #define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT)
1269 
1270 /* Bitfield definition for register of struct array CTRL: OUT */
1271 /*
1272  * DATA_OUT (RO)
1273  *
1274  * Command output
1275  */
1276 #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
1277 #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U)
1278 #define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT)
1279 
1280 /* Bitfield definition for register of struct array CTRL: STS */
1281 /*
1282  * WORD_IDX (RO)
1283  *
1284  * Word index
1285  */
1286 #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL)
1287 #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U)
1288 #define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT)
1289 
1290 /*
1291  * WORD_CNT (RO)
1292  *
1293  * Word counter
1294  */
1295 #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U)
1296 #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U)
1297 #define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT)
1298 
1299 /*
1300  * BIT_IDX (RO)
1301  *
1302  * Bit index
1303  */
1304 #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU)
1305 #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U)
1306 #define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT)
1307 
1308 /* Bitfield definition for register of struct array CTRL: MIN */
1309 /*
1310  * CMD_MIN (RW)
1311  *
1312  * minimum command value
1313  */
1314 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL)
1315 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U)
1316 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK)
1317 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT)
1318 
1319 /* Bitfield definition for register of struct array CTRL: MAX */
1320 /*
1321  * CMD_MAX (RW)
1322  *
1323  * maximum command value
1324  */
1325 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL)
1326 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U)
1327 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK)
1328 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT)
1329 
1330 /* Bitfield definition for register of struct array CTRL: MSK */
1331 /*
1332  * CMD_MASK (RW)
1333  *
1334  * compare mask
1335  */
1336 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL)
1337 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U)
1338 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK)
1339 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT)
1340 
1341 /* Bitfield definition for register of struct array CTRL: PTA */
1342 /*
1343  * PTR3 (RW)
1344  *
1345  * pointer3
1346  */
1347 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL)
1348 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U)
1349 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK)
1350 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT)
1351 
1352 /*
1353  * PTR2 (RW)
1354  *
1355  * pointer2
1356  */
1357 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL)
1358 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U)
1359 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK)
1360 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT)
1361 
1362 /*
1363  * PTR1 (RW)
1364  *
1365  * pointer1
1366  */
1367 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U)
1368 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U)
1369 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK)
1370 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT)
1371 
1372 /*
1373  * PTR0 (RW)
1374  *
1375  * pointer0
1376  */
1377 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU)
1378 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U)
1379 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK)
1380 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT)
1381 
1382 /* Bitfield definition for register of struct array CTRL: PTB */
1383 /*
1384  * PTR7 (RW)
1385  *
1386  * pointer7
1387  */
1388 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL)
1389 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U)
1390 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK)
1391 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT)
1392 
1393 /*
1394  * PTR6 (RW)
1395  *
1396  * pointer6
1397  */
1398 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL)
1399 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U)
1400 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK)
1401 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT)
1402 
1403 /*
1404  * PTR5 (RW)
1405  *
1406  * pointer5
1407  */
1408 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U)
1409 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U)
1410 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK)
1411 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT)
1412 
1413 /*
1414  * PTR4 (RW)
1415  *
1416  * pointer4
1417  */
1418 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU)
1419 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U)
1420 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK)
1421 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT)
1422 
1423 /* Bitfield definition for register of struct array CTRL: PTC */
1424 /*
1425  * PTR11 (RW)
1426  *
1427  * pointer11
1428  */
1429 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK (0xFF000000UL)
1430 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT (24U)
1431 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK)
1432 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT)
1433 
1434 /*
1435  * PTR10 (RW)
1436  *
1437  * pointer10
1438  */
1439 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK (0xFF0000UL)
1440 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT (16U)
1441 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK)
1442 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT)
1443 
1444 /*
1445  * PTR9 (RW)
1446  *
1447  * pointer9
1448  */
1449 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK (0xFF00U)
1450 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT (8U)
1451 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK)
1452 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT)
1453 
1454 /*
1455  * PTR8 (RW)
1456  *
1457  * pointer8
1458  */
1459 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK (0xFFU)
1460 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT (0U)
1461 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK)
1462 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT)
1463 
1464 /* Bitfield definition for register of struct array CTRL: PTD */
1465 /*
1466  * PTR15 (RW)
1467  *
1468  * pointer15
1469  */
1470 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK (0xFF000000UL)
1471 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT (24U)
1472 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK)
1473 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT)
1474 
1475 /*
1476  * PTR14 (RW)
1477  *
1478  * pointer14
1479  */
1480 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK (0xFF0000UL)
1481 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT (16U)
1482 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK)
1483 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT)
1484 
1485 /*
1486  * PTR13 (RW)
1487  *
1488  * pointer13
1489  */
1490 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK (0xFF00U)
1491 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT (8U)
1492 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK)
1493 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT)
1494 
1495 /*
1496  * PTR12 (RW)
1497  *
1498  * pointer12
1499  */
1500 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK (0xFFU)
1501 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT (0U)
1502 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK)
1503 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT)
1504 
1505 /* Bitfield definition for register of struct array CTRL: 0_1 */
1506 /*
1507  * POINTER (RW)
1508  *
1509  * pointer
1510  */
1511 #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL)
1512 #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U)
1513 #define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK)
1514 #define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT)
1515 
1516 /*
1517  * CFG_TM (RW)
1518  *
1519  * timeout
1520  * 0: high
1521  * 1: low
1522  * 2: rise
1523  * 3: fall
1524  */
1525 #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL)
1526 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U)
1527 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK)
1528 #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT)
1529 
1530 /*
1531  * CFG_RXD (RW)
1532  *
1533  * data received
1534  * 0: high
1535  * 1: low
1536  * 2: rise
1537  * 3: fall
1538  */
1539 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK (0xC000U)
1540 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT (14U)
1541 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK)
1542 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT)
1543 
1544 /*
1545  * CFG_TXD (RW)
1546  *
1547  * data send
1548  * 0: high
1549  * 1: low
1550  * 2: rise
1551  * 3: fall
1552  */
1553 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U)
1554 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U)
1555 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK)
1556 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT)
1557 
1558 /*
1559  * CFG_CLK (RW)
1560  *
1561  * clock
1562  * 0: high
1563  * 1: low
1564  * 2: rise
1565  * 3: fall
1566  */
1567 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U)
1568 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U)
1569 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK)
1570 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT)
1571 
1572 /*
1573  * CFG_PTR (RW)
1574  *
1575  * pointer
1576  * 0: match
1577  * 1: not match
1578  * 2:entry
1579  * 3:leave
1580  */
1581 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U)
1582 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U)
1583 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK)
1584 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT)
1585 
1586 /*
1587  * OV_TM (RW)
1588  *
1589  * override timeout check
1590  */
1591 #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U)
1592 #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U)
1593 #define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK)
1594 #define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT)
1595 
1596 /*
1597  * OV_RXD (RW)
1598  *
1599  * override RX data check
1600  */
1601 #define SEI_CTRL_LATCH_TRAN_OV_RXD_MASK (0x8U)
1602 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT (3U)
1603 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK)
1604 #define SEI_CTRL_LATCH_TRAN_OV_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT)
1605 
1606 /*
1607  * OV_TXD (RW)
1608  *
1609  * override TX data check
1610  */
1611 #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U)
1612 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U)
1613 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK)
1614 #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT)
1615 
1616 /*
1617  * OV_CLK (RW)
1618  *
1619  * override clock check
1620  */
1621 #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U)
1622 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U)
1623 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK)
1624 #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT)
1625 
1626 /*
1627  * OV_PTR (RW)
1628  *
1629  * override pointer check
1630  */
1631 #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U)
1632 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U)
1633 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK)
1634 #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT)
1635 
1636 /* Bitfield definition for register of struct array CTRL: CFG */
1637 /*
1638  * EN (RW)
1639  *
1640  * Enable latch
1641  * 0: disable
1642  * 1: enable
1643  */
1644 #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL)
1645 #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U)
1646 #define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK)
1647 #define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT)
1648 
1649 /*
1650  * SELECT (RW)
1651  *
1652  * Output select
1653  * 0: state0-state1
1654  * 1: state1-state2
1655  * 2: state2-state3
1656  * 3: state3-state0
1657  */
1658 #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL)
1659 #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U)
1660 #define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK)
1661 #define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT)
1662 
1663 /*
1664  * DELAY (RW)
1665  *
1666  * Delay in system clock cycle, for state transition
1667  */
1668 #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU)
1669 #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U)
1670 #define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK)
1671 #define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT)
1672 
1673 /* Bitfield definition for register of struct array CTRL: TIME */
1674 /*
1675  * LAT_TIME (RO)
1676  *
1677  * Latch time
1678  */
1679 #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL)
1680 #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U)
1681 #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT)
1682 
1683 /* Bitfield definition for register of struct array CTRL: STS */
1684 /*
1685  * STATE (RO)
1686  *
1687  * State
1688  */
1689 #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL)
1690 #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U)
1691 #define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT)
1692 
1693 /*
1694  * LAT_CNT (RO)
1695  *
1696  * Latch counter
1697  */
1698 #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU)
1699 #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U)
1700 #define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT)
1701 
1702 /* Bitfield definition for register of struct array CTRL: SMP_EN */
1703 /*
1704  * ACC_EN (RW)
1705  *
1706  * Position include acceleration
1707  * 0: use acceleration from sample override acceleration register
1708  * 1: use acceleration from motor group
1709  */
1710 #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL)
1711 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U)
1712 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK)
1713 #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT)
1714 
1715 /*
1716  * ACC_SEL (RW)
1717  *
1718  * Data register for acceleration transfer
1719  */
1720 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL)
1721 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U)
1722 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK)
1723 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT)
1724 
1725 /*
1726  * SPD_EN (RW)
1727  *
1728  * Position include speed
1729  * 0: use speed from sample override speed register
1730  * 1: use speed from motor group
1731  */
1732 #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL)
1733 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U)
1734 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK)
1735 #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT)
1736 
1737 /*
1738  * SPD_SEL (RW)
1739  *
1740  * Data register for speed transfer
1741  */
1742 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL)
1743 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U)
1744 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK)
1745 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT)
1746 
1747 /*
1748  * REV_EN (RW)
1749  *
1750  * Position include revolution
1751  * 0: use revolution from sample override revolution register
1752  * 1: use revolution from motor group
1753  */
1754 #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U)
1755 #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U)
1756 #define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK)
1757 #define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT)
1758 
1759 /*
1760  * REV_SEL (RW)
1761  *
1762  * Data register for revolution transfer
1763  */
1764 #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U)
1765 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U)
1766 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK)
1767 #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT)
1768 
1769 /*
1770  * POS_EN (RW)
1771  *
1772  * Position include position
1773  * 0: use position from sample override position register
1774  * 1: use position from motor group
1775  */
1776 #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U)
1777 #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U)
1778 #define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK)
1779 #define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT)
1780 
1781 /*
1782  * POS_SEL (RW)
1783  *
1784  * Data register for position transfer
1785  */
1786 #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU)
1787 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U)
1788 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK)
1789 #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT)
1790 
1791 /* Bitfield definition for register of struct array CTRL: SMP_CFG */
1792 /*
1793  * ONCE (RW)
1794  *
1795  * Sample one time
1796  * 0: Sample during windows time
1797  * 1: Close sample window after first sample
1798  */
1799 #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL)
1800 #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U)
1801 #define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK)
1802 #define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT)
1803 
1804 /*
1805  * LAT_SEL (RW)
1806  *
1807  * Latch selection
1808  * 0: latch 0
1809  * 1: latch 1
1810  * 2: latch 2
1811  * 3: latch 3
1812  */
1813 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL)
1814 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U)
1815 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK)
1816 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT)
1817 
1818 /*
1819  * WINDOW (RW)
1820  *
1821  * Sample window, in clock cycle
1822  */
1823 #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU)
1824 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U)
1825 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK)
1826 #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT)
1827 
1828 /* Bitfield definition for register of struct array CTRL: SMP_DAT */
1829 /*
1830  * DAT_SEL (RW)
1831  *
1832  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when SAMPLE happens.
1833  * Note: CRC register will be cleared automatically by SAMPLE if select the DATA register used for CRC.
1834  */
1835 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1836 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U)
1837 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK)
1838 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT)
1839 
1840 /* Bitfield definition for register of struct array CTRL: SMP_POS */
1841 /*
1842  * POS (RW)
1843  *
1844  * Sample override position
1845  */
1846 #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL)
1847 #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U)
1848 #define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK)
1849 #define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT)
1850 
1851 /* Bitfield definition for register of struct array CTRL: SMP_REV */
1852 /*
1853  * REV (RW)
1854  *
1855  * Sample override revolution
1856  */
1857 #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL)
1858 #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U)
1859 #define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK)
1860 #define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT)
1861 
1862 /* Bitfield definition for register of struct array CTRL: SMP_SPD */
1863 /*
1864  * SPD (RW)
1865  *
1866  * Sample override speed
1867  */
1868 #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL)
1869 #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U)
1870 #define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK)
1871 #define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT)
1872 
1873 /* Bitfield definition for register of struct array CTRL: SMP_ACC */
1874 /*
1875  * ACC (RW)
1876  *
1877  * Sample override accelerate
1878  */
1879 #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL)
1880 #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U)
1881 #define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK)
1882 #define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT)
1883 
1884 /* Bitfield definition for register of struct array CTRL: UPD_EN */
1885 /*
1886  * ACC_EN (RW)
1887  *
1888  * Position include acceleration
1889  * 0: use acceleration from update override acceleration register
1890  * 1: use acceleration from data register
1891  */
1892 #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL)
1893 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U)
1894 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK)
1895 #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT)
1896 
1897 /*
1898  * ACC_SEL (RW)
1899  *
1900  * Data register for acceleration transfer
1901  */
1902 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL)
1903 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U)
1904 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK)
1905 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT)
1906 
1907 /*
1908  * SPD_EN (RW)
1909  *
1910  * Position include speed
1911  * 0: use speed from update override speed register
1912  * 1: use speed from data register
1913  */
1914 #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL)
1915 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U)
1916 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK)
1917 #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT)
1918 
1919 /*
1920  * SPD_SEL (RW)
1921  *
1922  * Data register for speed transfer
1923  */
1924 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL)
1925 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U)
1926 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK)
1927 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT)
1928 
1929 /*
1930  * REV_EN (RW)
1931  *
1932  * Position include revolution
1933  * 0: use revolution from update override revolution register
1934  * 1: use revolution from data register
1935  */
1936 #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U)
1937 #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U)
1938 #define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK)
1939 #define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT)
1940 
1941 /*
1942  * REV_SEL (RW)
1943  *
1944  * Data register for revolution transfer
1945  */
1946 #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U)
1947 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U)
1948 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK)
1949 #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT)
1950 
1951 /*
1952  * POS_EN (RW)
1953  *
1954  * Position include position
1955  * 0: use position from update override position register
1956  * 1: use position from data register
1957  */
1958 #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U)
1959 #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U)
1960 #define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK)
1961 #define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT)
1962 
1963 /*
1964  * POS_SEL (RW)
1965  *
1966  * Data register for position transfer
1967  */
1968 #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU)
1969 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U)
1970 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK)
1971 #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT)
1972 
1973 /* Bitfield definition for register of struct array CTRL: UPD_CFG */
1974 /*
1975  * TIME_OVRD (RW)
1976  *
1977  * Use override time
1978  * 0: use time sample from motor group
1979  * 1: use override time
1980  */
1981 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL)
1982 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U)
1983 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK)
1984 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT)
1985 
1986 /*
1987  * ONERR (RW)
1988  *
1989  * Sample one time
1990  * 0: Sample during windows time
1991  * 1: Close sample window after first sample
1992  */
1993 #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL)
1994 #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U)
1995 #define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK)
1996 #define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT)
1997 
1998 /*
1999  * LAT_SEL (RW)
2000  *
2001  * Latch selection
2002  * 0: latch 0
2003  * 1: latch 1
2004  * 2: latch 2
2005  * 3: latch 3
2006  */
2007 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL)
2008 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U)
2009 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK)
2010 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT)
2011 
2012 /* Bitfield definition for register of struct array CTRL: UPD_DAT */
2013 /*
2014  * DAT_SEL (RW)
2015  *
2016  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when UPDATE happen.
2017  * Note: CRC register will be cleared automatically by UPDATE if select the DATA register used for CRC.
2018  */
2019 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
2020 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U)
2021 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK)
2022 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT)
2023 
2024 /* Bitfield definition for register of struct array CTRL: UPD_TIME */
2025 /*
2026  * TIME (RW)
2027  *
2028  * Update override time
2029  */
2030 #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL)
2031 #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U)
2032 #define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK)
2033 #define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT)
2034 
2035 /* Bitfield definition for register of struct array CTRL: UPD_POS */
2036 /*
2037  * POS (RW)
2038  *
2039  * Update override position
2040  */
2041 #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL)
2042 #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U)
2043 #define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK)
2044 #define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT)
2045 
2046 /* Bitfield definition for register of struct array CTRL: UPD_REV */
2047 /*
2048  * REV (RW)
2049  *
2050  * Update override revolution
2051  */
2052 #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL)
2053 #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U)
2054 #define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK)
2055 #define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT)
2056 
2057 /* Bitfield definition for register of struct array CTRL: UPD_SPD */
2058 /*
2059  * SPD (RW)
2060  *
2061  * Update override speed
2062  */
2063 #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL)
2064 #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U)
2065 #define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK)
2066 #define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT)
2067 
2068 /* Bitfield definition for register of struct array CTRL: UPD_ACC */
2069 /*
2070  * ACC (RW)
2071  *
2072  * Update override accelerate
2073  */
2074 #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL)
2075 #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U)
2076 #define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK)
2077 #define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT)
2078 
2079 /* Bitfield definition for register of struct array CTRL: SMP_VAL */
2080 /*
2081  * ACC (RO)
2082  *
2083  * Position include acceleration
2084  */
2085 #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL)
2086 #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U)
2087 #define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT)
2088 
2089 /*
2090  * SPD (RO)
2091  *
2092  * Position include speed
2093  */
2094 #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL)
2095 #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U)
2096 #define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT)
2097 
2098 /*
2099  * REV (RO)
2100  *
2101  * Position include revolution
2102  */
2103 #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U)
2104 #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U)
2105 #define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT)
2106 
2107 /*
2108  * POS (RO)
2109  *
2110  * Position include position
2111  */
2112 #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U)
2113 #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U)
2114 #define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT)
2115 
2116 /* Bitfield definition for register of struct array CTRL: SMP_STS */
2117 /*
2118  * OCCUR (RO)
2119  *
2120  * Sample occured
2121  * 0: Sample not happened
2122  * 1: Sample occured
2123  */
2124 #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL)
2125 #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U)
2126 #define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT)
2127 
2128 /*
2129  * WIN_CNT (RO)
2130  *
2131  * Sample window counter
2132  */
2133 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU)
2134 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U)
2135 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT)
2136 
2137 /* Bitfield definition for register of struct array CTRL: TIME_IN */
2138 /*
2139  * TIME (RO)
2140  *
2141  * input time
2142  */
2143 #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL)
2144 #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U)
2145 #define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT)
2146 
2147 /* Bitfield definition for register of struct array CTRL: POS_IN */
2148 /*
2149  * POS (RO)
2150  *
2151  * Input position
2152  */
2153 #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL)
2154 #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U)
2155 #define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT)
2156 
2157 /* Bitfield definition for register of struct array CTRL: REV_IN */
2158 /*
2159  * REV (RO)
2160  *
2161  * Input revolution
2162  */
2163 #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL)
2164 #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U)
2165 #define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT)
2166 
2167 /* Bitfield definition for register of struct array CTRL: SPD_IN */
2168 /*
2169  * SPD (RO)
2170  *
2171  * Input speed
2172  */
2173 #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL)
2174 #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U)
2175 #define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT)
2176 
2177 /* Bitfield definition for register of struct array CTRL: ACC_IN */
2178 /*
2179  * ACC (RO)
2180  *
2181  * Input accelerate
2182  */
2183 #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL)
2184 #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U)
2185 #define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT)
2186 
2187 /* Bitfield definition for register of struct array CTRL: UPD_STS */
2188 /*
2189  * UPD_ERR (RO)
2190  *
2191  * Update error
2192  * 0: data receive normally
2193  * 1: data receive error
2194  */
2195 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL)
2196 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U)
2197 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT)
2198 
2199 /* Bitfield definition for register of struct array CTRL: INT_EN */
2200 /*
2201  * TRG_ERR3 (RW)
2202  *
2203  * Trigger3 failed
2204  */
2205 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL)
2206 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U)
2207 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK)
2208 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT)
2209 
2210 /*
2211  * TRG_ERR2 (RW)
2212  *
2213  * Trigger2 failed
2214  */
2215 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL)
2216 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U)
2217 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK)
2218 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT)
2219 
2220 /*
2221  * TRG_ERR1 (RW)
2222  *
2223  * Trigger1 failed
2224  */
2225 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL)
2226 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U)
2227 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK)
2228 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT)
2229 
2230 /*
2231  * TRG_ERR0 (RW)
2232  *
2233  * Trigger0 failed
2234  */
2235 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL)
2236 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U)
2237 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK)
2238 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT)
2239 
2240 /*
2241  * TRIGER3 (RW)
2242  *
2243  * Trigger3
2244  */
2245 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL)
2246 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U)
2247 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK)
2248 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT)
2249 
2250 /*
2251  * TRIGER2 (RW)
2252  *
2253  * Trigger2
2254  */
2255 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL)
2256 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U)
2257 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK)
2258 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT)
2259 
2260 /*
2261  * TRIGER1 (RW)
2262  *
2263  * Trigger1
2264  */
2265 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL)
2266 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U)
2267 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK)
2268 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT)
2269 
2270 /*
2271  * TRIGER0 (RW)
2272  *
2273  * Trigger0
2274  */
2275 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL)
2276 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U)
2277 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK)
2278 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT)
2279 
2280 /*
2281  * SMP_ERR (RW)
2282  *
2283  * Sample error
2284  */
2285 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL)
2286 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U)
2287 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK)
2288 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT)
2289 
2290 /*
2291  * LATCH3 (RW)
2292  *
2293  * Latch3
2294  */
2295 #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL)
2296 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U)
2297 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK)
2298 #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT)
2299 
2300 /*
2301  * LATCH2 (RW)
2302  *
2303  * Latch2
2304  */
2305 #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL)
2306 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U)
2307 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK)
2308 #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT)
2309 
2310 /*
2311  * LATCH1 (RW)
2312  *
2313  * Latch1
2314  */
2315 #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL)
2316 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U)
2317 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK)
2318 #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT)
2319 
2320 /*
2321  * LATCH0 (RW)
2322  *
2323  * Latch0
2324  */
2325 #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL)
2326 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U)
2327 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK)
2328 #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT)
2329 
2330 /*
2331  * TIMEOUT (RW)
2332  *
2333  * Timeout
2334  */
2335 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U)
2336 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U)
2337 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK)
2338 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT)
2339 
2340 /*
2341  * TRX_ERR (RW)
2342  *
2343  * Transfer error
2344  */
2345 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U)
2346 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U)
2347 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK)
2348 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT)
2349 
2350 /*
2351  * INSTR1_END (RW)
2352  *
2353  * Instruction 1 end
2354  */
2355 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U)
2356 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U)
2357 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK)
2358 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT)
2359 
2360 /*
2361  * INSTR0_END (RW)
2362  *
2363  * Instruction 0 end
2364  */
2365 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U)
2366 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U)
2367 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK)
2368 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT)
2369 
2370 /*
2371  * PTR1_END (RW)
2372  *
2373  * Pointer 1 end
2374  */
2375 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U)
2376 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U)
2377 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK)
2378 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT)
2379 
2380 /*
2381  * PTR0_END (RW)
2382  *
2383  * Pointer 0 end
2384  */
2385 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U)
2386 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U)
2387 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK)
2388 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT)
2389 
2390 /*
2391  * INSTR1_ST (RW)
2392  *
2393  * Instruction 1 start
2394  */
2395 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U)
2396 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U)
2397 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK)
2398 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT)
2399 
2400 /*
2401  * INSTR0_ST (RW)
2402  *
2403  * Instruction 0 start
2404  */
2405 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U)
2406 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U)
2407 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK)
2408 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT)
2409 
2410 /*
2411  * PTR1_ST (RW)
2412  *
2413  * Pointer 1 start
2414  */
2415 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U)
2416 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U)
2417 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK)
2418 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT)
2419 
2420 /*
2421  * PTR0_ST (RW)
2422  *
2423  * Pointer 0 start
2424  */
2425 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U)
2426 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U)
2427 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK)
2428 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT)
2429 
2430 /*
2431  * WDOG (RW)
2432  *
2433  * Watch dog
2434  */
2435 #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U)
2436 #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U)
2437 #define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK)
2438 #define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT)
2439 
2440 /*
2441  * EXCEPT (RW)
2442  *
2443  * Exception
2444  */
2445 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U)
2446 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U)
2447 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK)
2448 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT)
2449 
2450 /*
2451  * STALL (RW)
2452  *
2453  * Stall
2454  */
2455 #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U)
2456 #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U)
2457 #define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK)
2458 #define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT)
2459 
2460 /* Bitfield definition for register of struct array CTRL: INT_FLAG */
2461 /*
2462  * TRG_ERR3 (W1C)
2463  *
2464  * Trigger3 failed
2465  */
2466 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL)
2467 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U)
2468 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK)
2469 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT)
2470 
2471 /*
2472  * TRG_ERR2 (W1C)
2473  *
2474  * Trigger2 failed
2475  */
2476 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL)
2477 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U)
2478 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK)
2479 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT)
2480 
2481 /*
2482  * TRG_ERR1 (W1C)
2483  *
2484  * Trigger1 failed
2485  */
2486 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL)
2487 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U)
2488 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK)
2489 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT)
2490 
2491 /*
2492  * TRG_ERR0 (W1C)
2493  *
2494  * Trigger0 failed
2495  */
2496 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL)
2497 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U)
2498 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK)
2499 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT)
2500 
2501 /*
2502  * TRIGER3 (W1C)
2503  *
2504  * Trigger3
2505  */
2506 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL)
2507 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U)
2508 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK)
2509 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT)
2510 
2511 /*
2512  * TRIGER2 (W1C)
2513  *
2514  * Trigger2
2515  */
2516 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL)
2517 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U)
2518 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK)
2519 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT)
2520 
2521 /*
2522  * TRIGER1 (W1C)
2523  *
2524  * Trigger1
2525  */
2526 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL)
2527 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U)
2528 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK)
2529 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT)
2530 
2531 /*
2532  * TRIGER0 (W1C)
2533  *
2534  * Trigger0
2535  */
2536 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL)
2537 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U)
2538 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK)
2539 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT)
2540 
2541 /*
2542  * SMP_ERR (W1C)
2543  *
2544  * Sample error
2545  */
2546 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL)
2547 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U)
2548 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK)
2549 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT)
2550 
2551 /*
2552  * LATCH3 (W1C)
2553  *
2554  * Latch3
2555  */
2556 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL)
2557 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U)
2558 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK)
2559 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT)
2560 
2561 /*
2562  * LATCH2 (W1C)
2563  *
2564  * Latch2
2565  */
2566 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL)
2567 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U)
2568 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK)
2569 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT)
2570 
2571 /*
2572  * LATCH1 (W1C)
2573  *
2574  * Latch1
2575  */
2576 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL)
2577 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U)
2578 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK)
2579 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT)
2580 
2581 /*
2582  * LATCH0 (W1C)
2583  *
2584  * Latch0
2585  */
2586 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL)
2587 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U)
2588 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK)
2589 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT)
2590 
2591 /*
2592  * TIMEOUT (W1C)
2593  *
2594  * Timeout
2595  */
2596 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U)
2597 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U)
2598 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK)
2599 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT)
2600 
2601 /*
2602  * TRX_ERR (W1C)
2603  *
2604  * Transfer error
2605  */
2606 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U)
2607 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U)
2608 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK)
2609 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT)
2610 
2611 /*
2612  * INSTR1_END (W1C)
2613  *
2614  * Instruction 1 end
2615  */
2616 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U)
2617 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U)
2618 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK)
2619 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT)
2620 
2621 /*
2622  * INSTR0_END (W1C)
2623  *
2624  * Instruction 0 end
2625  */
2626 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U)
2627 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U)
2628 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK)
2629 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT)
2630 
2631 /*
2632  * PTR1_END (W1C)
2633  *
2634  * Pointer 1 end
2635  */
2636 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U)
2637 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U)
2638 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK)
2639 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT)
2640 
2641 /*
2642  * PTR0_END (W1C)
2643  *
2644  * Pointer 0 end
2645  */
2646 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U)
2647 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U)
2648 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK)
2649 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT)
2650 
2651 /*
2652  * INSTR1_ST (W1C)
2653  *
2654  * Instruction 1 start
2655  */
2656 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U)
2657 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U)
2658 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK)
2659 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT)
2660 
2661 /*
2662  * INSTR0_ST (W1C)
2663  *
2664  * Instruction 0 start
2665  */
2666 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U)
2667 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U)
2668 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK)
2669 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT)
2670 
2671 /*
2672  * PTR1_ST (W1C)
2673  *
2674  * Pointer 1 start
2675  */
2676 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U)
2677 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U)
2678 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK)
2679 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT)
2680 
2681 /*
2682  * PTR0_ST (W1C)
2683  *
2684  * Pointer 0 start
2685  */
2686 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U)
2687 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U)
2688 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK)
2689 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT)
2690 
2691 /*
2692  * WDOG (W1C)
2693  *
2694  * Watch dog
2695  */
2696 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U)
2697 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U)
2698 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK)
2699 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT)
2700 
2701 /*
2702  * EXCEPT (W1C)
2703  *
2704  * Exception
2705  */
2706 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U)
2707 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U)
2708 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK)
2709 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT)
2710 
2711 /*
2712  * STALL (W1C)
2713  *
2714  * Stall
2715  */
2716 #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U)
2717 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U)
2718 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK)
2719 #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT)
2720 
2721 /* Bitfield definition for register of struct array CTRL: INT_STS */
2722 /*
2723  * TRG_ERR3 (RO)
2724  *
2725  * Trigger3 failed
2726  */
2727 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL)
2728 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U)
2729 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT)
2730 
2731 /*
2732  * TRG_ERR2 (RO)
2733  *
2734  * Trigger2 failed
2735  */
2736 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL)
2737 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U)
2738 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT)
2739 
2740 /*
2741  * TRG_ERR1 (RO)
2742  *
2743  * Trigger1 failed
2744  */
2745 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL)
2746 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U)
2747 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT)
2748 
2749 /*
2750  * TRG_ERR0 (RO)
2751  *
2752  * Trigger0 failed
2753  */
2754 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL)
2755 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U)
2756 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT)
2757 
2758 /*
2759  * TRIGER3 (RO)
2760  *
2761  * Trigger3
2762  */
2763 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL)
2764 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U)
2765 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT)
2766 
2767 /*
2768  * TRIGER2 (RO)
2769  *
2770  * Trigger2
2771  */
2772 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL)
2773 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U)
2774 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT)
2775 
2776 /*
2777  * TRIGER1 (RO)
2778  *
2779  * Trigger1
2780  */
2781 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL)
2782 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U)
2783 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT)
2784 
2785 /*
2786  * TRIGER0 (RO)
2787  *
2788  * Trigger0
2789  */
2790 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL)
2791 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U)
2792 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT)
2793 
2794 /*
2795  * SMP_ERR (RO)
2796  *
2797  * Sample error
2798  */
2799 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL)
2800 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U)
2801 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT)
2802 
2803 /*
2804  * LATCH3 (RO)
2805  *
2806  * Latch3
2807  */
2808 #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL)
2809 #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U)
2810 #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT)
2811 
2812 /*
2813  * LATCH2 (RO)
2814  *
2815  * Latch2
2816  */
2817 #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL)
2818 #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U)
2819 #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT)
2820 
2821 /*
2822  * LATCH1 (RO)
2823  *
2824  * Latch1
2825  */
2826 #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL)
2827 #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U)
2828 #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT)
2829 
2830 /*
2831  * LATCH0 (RO)
2832  *
2833  * Latch0
2834  */
2835 #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL)
2836 #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U)
2837 #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT)
2838 
2839 /*
2840  * TIMEOUT (RO)
2841  *
2842  * Timeout
2843  */
2844 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U)
2845 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U)
2846 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT)
2847 
2848 /*
2849  * TRX_ERR (RO)
2850  *
2851  * Transfer error
2852  */
2853 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U)
2854 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U)
2855 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT)
2856 
2857 /*
2858  * INSTR1_END (RO)
2859  *
2860  * Instruction 1 end
2861  */
2862 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U)
2863 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U)
2864 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT)
2865 
2866 /*
2867  * INSTR0_END (RO)
2868  *
2869  * Instruction 0 end
2870  */
2871 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U)
2872 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U)
2873 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT)
2874 
2875 /*
2876  * PTR1_END (RO)
2877  *
2878  * Pointer 1 end
2879  */
2880 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U)
2881 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U)
2882 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT)
2883 
2884 /*
2885  * PTR0_END (RO)
2886  *
2887  * Pointer 0 end
2888  */
2889 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U)
2890 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U)
2891 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT)
2892 
2893 /*
2894  * INSTR1_ST (RO)
2895  *
2896  * Instruction 1 start
2897  */
2898 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U)
2899 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U)
2900 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT)
2901 
2902 /*
2903  * INSTR0_ST (RO)
2904  *
2905  * Instruction 0 start
2906  */
2907 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U)
2908 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U)
2909 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT)
2910 
2911 /*
2912  * PTR1_ST (RO)
2913  *
2914  * Pointer 1 start
2915  */
2916 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U)
2917 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U)
2918 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT)
2919 
2920 /*
2921  * PTR0_ST (RO)
2922  *
2923  * Pointer 0 start
2924  */
2925 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U)
2926 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U)
2927 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT)
2928 
2929 /*
2930  * WDOG (RO)
2931  *
2932  * Watch dog
2933  */
2934 #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U)
2935 #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U)
2936 #define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT)
2937 
2938 /*
2939  * EXCEPT (RO)
2940  *
2941  * Exception
2942  */
2943 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U)
2944 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U)
2945 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT)
2946 
2947 /*
2948  * STALL (RO)
2949  *
2950  * Stall
2951  */
2952 #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U)
2953 #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U)
2954 #define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT)
2955 
2956 /* Bitfield definition for register of struct array CTRL: POINTER0 */
2957 /*
2958  * POINTER (RW)
2959  *
2960  * Match pointer 0
2961  */
2962 #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU)
2963 #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U)
2964 #define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK)
2965 #define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT)
2966 
2967 /* Bitfield definition for register of struct array CTRL: POINTER1 */
2968 /*
2969  * POINTER (RW)
2970  *
2971  * Match pointer 1
2972  */
2973 #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU)
2974 #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U)
2975 #define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK)
2976 #define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT)
2977 
2978 /* Bitfield definition for register of struct array CTRL: INSTR0 */
2979 /*
2980  * INSTR (RW)
2981  *
2982  * Match instruction 0
2983  */
2984 #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL)
2985 #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U)
2986 #define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK)
2987 #define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT)
2988 
2989 /* Bitfield definition for register of struct array CTRL: INSTR1 */
2990 /*
2991  * INSTR (RW)
2992  *
2993  * Match instruction 1
2994  */
2995 #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL)
2996 #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U)
2997 #define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK)
2998 #define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT)
2999 
3000 /* Bitfield definition for register of struct array CTRL: DMA_EN */
3001 /*
3002  * TRG_ERR3 (RW)
3003  *
3004  * Trigger3 failed
3005  */
3006 #define SEI_CTRL_DMA_EN_TRG_ERR3_MASK (0x80000000UL)
3007 #define SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT (31U)
3008 #define SEI_CTRL_DMA_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK)
3009 #define SEI_CTRL_DMA_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT)
3010 
3011 /*
3012  * TRG_ERR2 (RW)
3013  *
3014  * Trigger2 failed
3015  */
3016 #define SEI_CTRL_DMA_EN_TRG_ERR2_MASK (0x40000000UL)
3017 #define SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT (30U)
3018 #define SEI_CTRL_DMA_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK)
3019 #define SEI_CTRL_DMA_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT)
3020 
3021 /*
3022  * TRG_ERR1 (RW)
3023  *
3024  * Trigger1 failed
3025  */
3026 #define SEI_CTRL_DMA_EN_TRG_ERR1_MASK (0x20000000UL)
3027 #define SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT (29U)
3028 #define SEI_CTRL_DMA_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK)
3029 #define SEI_CTRL_DMA_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT)
3030 
3031 /*
3032  * TRG_ERR0 (RW)
3033  *
3034  * Trigger0 failed
3035  */
3036 #define SEI_CTRL_DMA_EN_TRG_ERR0_MASK (0x10000000UL)
3037 #define SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT (28U)
3038 #define SEI_CTRL_DMA_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK)
3039 #define SEI_CTRL_DMA_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT)
3040 
3041 /*
3042  * TRIGER3 (RW)
3043  *
3044  * Trigger3
3045  */
3046 #define SEI_CTRL_DMA_EN_TRIGER3_MASK (0x8000000UL)
3047 #define SEI_CTRL_DMA_EN_TRIGER3_SHIFT (27U)
3048 #define SEI_CTRL_DMA_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER3_SHIFT) & SEI_CTRL_DMA_EN_TRIGER3_MASK)
3049 #define SEI_CTRL_DMA_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER3_MASK) >> SEI_CTRL_DMA_EN_TRIGER3_SHIFT)
3050 
3051 /*
3052  * TRIGER2 (RW)
3053  *
3054  * Trigger2
3055  */
3056 #define SEI_CTRL_DMA_EN_TRIGER2_MASK (0x4000000UL)
3057 #define SEI_CTRL_DMA_EN_TRIGER2_SHIFT (26U)
3058 #define SEI_CTRL_DMA_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER2_SHIFT) & SEI_CTRL_DMA_EN_TRIGER2_MASK)
3059 #define SEI_CTRL_DMA_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER2_MASK) >> SEI_CTRL_DMA_EN_TRIGER2_SHIFT)
3060 
3061 /*
3062  * TRIGER1 (RW)
3063  *
3064  * Trigger1
3065  */
3066 #define SEI_CTRL_DMA_EN_TRIGER1_MASK (0x2000000UL)
3067 #define SEI_CTRL_DMA_EN_TRIGER1_SHIFT (25U)
3068 #define SEI_CTRL_DMA_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER1_SHIFT) & SEI_CTRL_DMA_EN_TRIGER1_MASK)
3069 #define SEI_CTRL_DMA_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER1_MASK) >> SEI_CTRL_DMA_EN_TRIGER1_SHIFT)
3070 
3071 /*
3072  * TRIGER0 (RW)
3073  *
3074  * Trigger0
3075  */
3076 #define SEI_CTRL_DMA_EN_TRIGER0_MASK (0x1000000UL)
3077 #define SEI_CTRL_DMA_EN_TRIGER0_SHIFT (24U)
3078 #define SEI_CTRL_DMA_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER0_SHIFT) & SEI_CTRL_DMA_EN_TRIGER0_MASK)
3079 #define SEI_CTRL_DMA_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER0_MASK) >> SEI_CTRL_DMA_EN_TRIGER0_SHIFT)
3080 
3081 /*
3082  * SMP_ERR (RW)
3083  *
3084  * Sample error
3085  */
3086 #define SEI_CTRL_DMA_EN_SMP_ERR_MASK (0x100000UL)
3087 #define SEI_CTRL_DMA_EN_SMP_ERR_SHIFT (20U)
3088 #define SEI_CTRL_DMA_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) & SEI_CTRL_DMA_EN_SMP_ERR_MASK)
3089 #define SEI_CTRL_DMA_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) >> SEI_CTRL_DMA_EN_SMP_ERR_SHIFT)
3090 
3091 /*
3092  * LATCH3 (RW)
3093  *
3094  * Latch3
3095  */
3096 #define SEI_CTRL_DMA_EN_LATCH3_MASK (0x80000UL)
3097 #define SEI_CTRL_DMA_EN_LATCH3_SHIFT (19U)
3098 #define SEI_CTRL_DMA_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH3_SHIFT) & SEI_CTRL_DMA_EN_LATCH3_MASK)
3099 #define SEI_CTRL_DMA_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH3_MASK) >> SEI_CTRL_DMA_EN_LATCH3_SHIFT)
3100 
3101 /*
3102  * LATCH2 (RW)
3103  *
3104  * Latch2
3105  */
3106 #define SEI_CTRL_DMA_EN_LATCH2_MASK (0x40000UL)
3107 #define SEI_CTRL_DMA_EN_LATCH2_SHIFT (18U)
3108 #define SEI_CTRL_DMA_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH2_SHIFT) & SEI_CTRL_DMA_EN_LATCH2_MASK)
3109 #define SEI_CTRL_DMA_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH2_MASK) >> SEI_CTRL_DMA_EN_LATCH2_SHIFT)
3110 
3111 /*
3112  * LATCH1 (RW)
3113  *
3114  * Latch1
3115  */
3116 #define SEI_CTRL_DMA_EN_LATCH1_MASK (0x20000UL)
3117 #define SEI_CTRL_DMA_EN_LATCH1_SHIFT (17U)
3118 #define SEI_CTRL_DMA_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH1_SHIFT) & SEI_CTRL_DMA_EN_LATCH1_MASK)
3119 #define SEI_CTRL_DMA_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH1_MASK) >> SEI_CTRL_DMA_EN_LATCH1_SHIFT)
3120 
3121 /*
3122  * LATCH0 (RW)
3123  *
3124  * Latch0
3125  */
3126 #define SEI_CTRL_DMA_EN_LATCH0_MASK (0x10000UL)
3127 #define SEI_CTRL_DMA_EN_LATCH0_SHIFT (16U)
3128 #define SEI_CTRL_DMA_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH0_SHIFT) & SEI_CTRL_DMA_EN_LATCH0_MASK)
3129 #define SEI_CTRL_DMA_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH0_MASK) >> SEI_CTRL_DMA_EN_LATCH0_SHIFT)
3130 
3131 /*
3132  * TIMEOUT (RW)
3133  *
3134  * Timeout
3135  */
3136 #define SEI_CTRL_DMA_EN_TIMEOUT_MASK (0x2000U)
3137 #define SEI_CTRL_DMA_EN_TIMEOUT_SHIFT (13U)
3138 #define SEI_CTRL_DMA_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) & SEI_CTRL_DMA_EN_TIMEOUT_MASK)
3139 #define SEI_CTRL_DMA_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) >> SEI_CTRL_DMA_EN_TIMEOUT_SHIFT)
3140 
3141 /*
3142  * TRX_ERR (RW)
3143  *
3144  * Transfer error
3145  */
3146 #define SEI_CTRL_DMA_EN_TRX_ERR_MASK (0x1000U)
3147 #define SEI_CTRL_DMA_EN_TRX_ERR_SHIFT (12U)
3148 #define SEI_CTRL_DMA_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) & SEI_CTRL_DMA_EN_TRX_ERR_MASK)
3149 #define SEI_CTRL_DMA_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) >> SEI_CTRL_DMA_EN_TRX_ERR_SHIFT)
3150 
3151 /*
3152  * INSTR1_END (RW)
3153  *
3154  * Instruction 1 end
3155  */
3156 #define SEI_CTRL_DMA_EN_INSTR1_END_MASK (0x800U)
3157 #define SEI_CTRL_DMA_EN_INSTR1_END_SHIFT (11U)
3158 #define SEI_CTRL_DMA_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_END_MASK)
3159 #define SEI_CTRL_DMA_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) >> SEI_CTRL_DMA_EN_INSTR1_END_SHIFT)
3160 
3161 /*
3162  * INSTR0_END (RW)
3163  *
3164  * Instruction 0 end
3165  */
3166 #define SEI_CTRL_DMA_EN_INSTR0_END_MASK (0x400U)
3167 #define SEI_CTRL_DMA_EN_INSTR0_END_SHIFT (10U)
3168 #define SEI_CTRL_DMA_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_END_MASK)
3169 #define SEI_CTRL_DMA_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) >> SEI_CTRL_DMA_EN_INSTR0_END_SHIFT)
3170 
3171 /*
3172  * PTR1_END (RW)
3173  *
3174  * Pointer 1 end
3175  */
3176 #define SEI_CTRL_DMA_EN_PTR1_END_MASK (0x200U)
3177 #define SEI_CTRL_DMA_EN_PTR1_END_SHIFT (9U)
3178 #define SEI_CTRL_DMA_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_END_SHIFT) & SEI_CTRL_DMA_EN_PTR1_END_MASK)
3179 #define SEI_CTRL_DMA_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_END_MASK) >> SEI_CTRL_DMA_EN_PTR1_END_SHIFT)
3180 
3181 /*
3182  * PTR0_END (RW)
3183  *
3184  * Pointer 0 end
3185  */
3186 #define SEI_CTRL_DMA_EN_PTR0_END_MASK (0x100U)
3187 #define SEI_CTRL_DMA_EN_PTR0_END_SHIFT (8U)
3188 #define SEI_CTRL_DMA_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_END_SHIFT) & SEI_CTRL_DMA_EN_PTR0_END_MASK)
3189 #define SEI_CTRL_DMA_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_END_MASK) >> SEI_CTRL_DMA_EN_PTR0_END_SHIFT)
3190 
3191 /*
3192  * INSTR1_ST (RW)
3193  *
3194  * Instruction 1 start
3195  */
3196 #define SEI_CTRL_DMA_EN_INSTR1_ST_MASK (0x80U)
3197 #define SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT (7U)
3198 #define SEI_CTRL_DMA_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK)
3199 #define SEI_CTRL_DMA_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT)
3200 
3201 /*
3202  * INSTR0_ST (RW)
3203  *
3204  * Instruction 0 start
3205  */
3206 #define SEI_CTRL_DMA_EN_INSTR0_ST_MASK (0x40U)
3207 #define SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT (6U)
3208 #define SEI_CTRL_DMA_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK)
3209 #define SEI_CTRL_DMA_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT)
3210 
3211 /*
3212  * PTR1_ST (RW)
3213  *
3214  * Pointer 1 start
3215  */
3216 #define SEI_CTRL_DMA_EN_PTR1_ST_MASK (0x20U)
3217 #define SEI_CTRL_DMA_EN_PTR1_ST_SHIFT (5U)
3218 #define SEI_CTRL_DMA_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR1_ST_MASK)
3219 #define SEI_CTRL_DMA_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) >> SEI_CTRL_DMA_EN_PTR1_ST_SHIFT)
3220 
3221 /*
3222  * PTR0_ST (RW)
3223  *
3224  * Pointer 0 start
3225  */
3226 #define SEI_CTRL_DMA_EN_PTR0_ST_MASK (0x10U)
3227 #define SEI_CTRL_DMA_EN_PTR0_ST_SHIFT (4U)
3228 #define SEI_CTRL_DMA_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR0_ST_MASK)
3229 #define SEI_CTRL_DMA_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) >> SEI_CTRL_DMA_EN_PTR0_ST_SHIFT)
3230 
3231 /*
3232  * WDOG (RW)
3233  *
3234  * Watch dog
3235  */
3236 #define SEI_CTRL_DMA_EN_WDOG_MASK (0x4U)
3237 #define SEI_CTRL_DMA_EN_WDOG_SHIFT (2U)
3238 #define SEI_CTRL_DMA_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_WDOG_SHIFT) & SEI_CTRL_DMA_EN_WDOG_MASK)
3239 #define SEI_CTRL_DMA_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_WDOG_MASK) >> SEI_CTRL_DMA_EN_WDOG_SHIFT)
3240 
3241 /*
3242  * EXCEPT (RW)
3243  *
3244  * Exception
3245  */
3246 #define SEI_CTRL_DMA_EN_EXCEPT_MASK (0x2U)
3247 #define SEI_CTRL_DMA_EN_EXCEPT_SHIFT (1U)
3248 #define SEI_CTRL_DMA_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_EXCEPT_SHIFT) & SEI_CTRL_DMA_EN_EXCEPT_MASK)
3249 #define SEI_CTRL_DMA_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_EXCEPT_MASK) >> SEI_CTRL_DMA_EN_EXCEPT_SHIFT)
3250 
3251 /*
3252  * STALL (RW)
3253  *
3254  * Stall
3255  */
3256 #define SEI_CTRL_DMA_EN_STALL_MASK (0x1U)
3257 #define SEI_CTRL_DMA_EN_STALL_SHIFT (0U)
3258 #define SEI_CTRL_DMA_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_STALL_SHIFT) & SEI_CTRL_DMA_EN_STALL_MASK)
3259 #define SEI_CTRL_DMA_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_STALL_MASK) >> SEI_CTRL_DMA_EN_STALL_SHIFT)
3260 
3261 /* Bitfield definition for register array: INSTR */
3262 /*
3263  * OP (RW)
3264  *
3265  * operation
3266  * 0: halt
3267  * 1: jump
3268  * 2: send with timeout check
3269  * 3: send without timout check
3270  * 4: wait with timeout check
3271  * 5: wait without timout check
3272  * 6: receive with timeout check
3273  * 7: receive without timout check
3274  */
3275 #define SEI_INSTR_OP_MASK (0x1C000000UL)
3276 #define SEI_INSTR_OP_SHIFT (26U)
3277 #define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK)
3278 #define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT)
3279 
3280 /*
3281  * CK (RW)
3282  *
3283  * clock
3284  * 0: low
3285  * 1: rise-fall
3286  * 2: fall-rise
3287  * 3: high
3288  */
3289 #define SEI_INSTR_CK_MASK (0x3000000UL)
3290 #define SEI_INSTR_CK_SHIFT (24U)
3291 #define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK)
3292 #define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT)
3293 
3294 /*
3295  * CRC (RW)
3296  *
3297  * CRC register
3298  * 0: don't calculate CRC
3299  * 1: do not set this value
3300  * 2: data register 2
3301  * 3: data register 3
3302  * ...
3303  * 29: data register 29
3304  * 30: value 0 when send, wait 0 in receive
3305  * 31: value1 when send, wait 1 in receive
3306  */
3307 #define SEI_INSTR_CRC_MASK (0x1F0000UL)
3308 #define SEI_INSTR_CRC_SHIFT (16U)
3309 #define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK)
3310 #define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT)
3311 
3312 /*
3313  * DAT (RW)
3314  *
3315  * DATA register
3316  * 0: ignore data
3317  * 1: command
3318  * 2: data register 2
3319  * 3: data register 3
3320  * ...
3321  * 29: data register 29
3322  * 30: value 0 when send, wait 0 in receive
3323  * 31: value1 when send, wait 1 in receive
3324  */
3325 #define SEI_INSTR_DAT_MASK (0x1F00U)
3326 #define SEI_INSTR_DAT_SHIFT (8U)
3327 #define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK)
3328 #define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT)
3329 
3330 /*
3331  * OPR (RW)
3332  *
3333  * a. When OP is 0, this area is the halt time in baudrate, 0 represents infinite time.
3334  * b. When OP is 1, this area is the the pointer to the command table.
3335  * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer;
3336  * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER;
3337  * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER.
3338  * c. When OP is 2-7, this area is the data length as fellow:
3339  * 0: 1 bit
3340  * 1: 2 bit
3341  * ...
3342  * 31: 32 bit
3343  */
3344 #define SEI_INSTR_OPR_MASK (0x1FU)
3345 #define SEI_INSTR_OPR_SHIFT (0U)
3346 #define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK)
3347 #define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT)
3348 
3349 /* Bitfield definition for register of struct array DAT: MODE */
3350 /*
3351  * CRC_LEN (RW)
3352  *
3353  * CRC length
3354  * 0: 1 bit
3355  * 1: 2 bit
3356  * ...
3357  * 31: 32 bit
3358  */
3359 #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL)
3360 #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U)
3361 #define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK)
3362 #define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT)
3363 
3364 /*
3365  * WLEN (RW)
3366  *
3367  * word length
3368  * 0: 1 bit
3369  * 1: 2 bit
3370  * ...
3371  * 31: 32 bit
3372  */
3373 #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL)
3374 #define SEI_DAT_MODE_WLEN_SHIFT (16U)
3375 #define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK)
3376 #define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT)
3377 
3378 /*
3379  * CRC_SHIFT (RW)
3380  *
3381  * CRC shift mode, this mode is used to perform repeat code check
3382  * 0: CRC
3383  * 1: shift mode
3384  */
3385 #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U)
3386 #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U)
3387 #define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK)
3388 #define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT)
3389 
3390 /*
3391  * CRC_INV (RW)
3392  *
3393  * CRC invert
3394  * 0: use CRC
3395  * 1: use inverted CRC
3396  */
3397 #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U)
3398 #define SEI_DAT_MODE_CRC_INV_SHIFT (12U)
3399 #define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK)
3400 #define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT)
3401 
3402 /*
3403  * WORDER (RW)
3404  *
3405  * word order
3406  * 0: sample as bit order
3407  * 1: different from bit order
3408  */
3409 #define SEI_DAT_MODE_WORDER_MASK (0x800U)
3410 #define SEI_DAT_MODE_WORDER_SHIFT (11U)
3411 #define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK)
3412 #define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT)
3413 
3414 /*
3415  * BORDER (RW)
3416  *
3417  * bit order
3418  * 0: LSB first
3419  * 1: MSB first
3420  */
3421 #define SEI_DAT_MODE_BORDER_MASK (0x400U)
3422 #define SEI_DAT_MODE_BORDER_SHIFT (10U)
3423 #define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK)
3424 #define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT)
3425 
3426 /*
3427  * SIGNED (RW)
3428  *
3429  * Signed
3430  * 0: unsigned value
3431  * 1: signed value
3432  */
3433 #define SEI_DAT_MODE_SIGNED_MASK (0x200U)
3434 #define SEI_DAT_MODE_SIGNED_SHIFT (9U)
3435 #define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK)
3436 #define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT)
3437 
3438 /*
3439  * REWIND (RW)
3440  *
3441  * Write 1 to rewind read/write pointer, this is a self clear bit
3442  */
3443 #define SEI_DAT_MODE_REWIND_MASK (0x100U)
3444 #define SEI_DAT_MODE_REWIND_SHIFT (8U)
3445 #define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK)
3446 #define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT)
3447 
3448 /*
3449  * MODE (RW)
3450  *
3451  * Data mode
3452  * 0: data mode
3453  * 1: check mode
3454  * 2: CRC mode
3455  */
3456 #define SEI_DAT_MODE_MODE_MASK (0x3U)
3457 #define SEI_DAT_MODE_MODE_SHIFT (0U)
3458 #define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK)
3459 #define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT)
3460 
3461 /* Bitfield definition for register of struct array DAT: IDX */
3462 /*
3463  * LAST_BIT (RW)
3464  *
3465  * Last bit index for tranceive
3466  */
3467 #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL)
3468 #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U)
3469 #define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK)
3470 #define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT)
3471 
3472 /*
3473  * FIRST_BIT (RW)
3474  *
3475  * First bit index for tranceive
3476  */
3477 #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL)
3478 #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U)
3479 #define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK)
3480 #define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT)
3481 
3482 /*
3483  * MAX_BIT (RW)
3484  *
3485  * Highest bit index
3486  */
3487 #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U)
3488 #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U)
3489 #define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK)
3490 #define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT)
3491 
3492 /*
3493  * MIN_BIT (RW)
3494  *
3495  * Lowest bit index
3496  */
3497 #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU)
3498 #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U)
3499 #define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK)
3500 #define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT)
3501 
3502 /* Bitfield definition for register of struct array DAT: GOLD */
3503 /*
3504  * GOLD_VALUE (RW)
3505  *
3506  * Gold value for check mode
3507  */
3508 #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
3509 #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U)
3510 #define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK)
3511 #define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT)
3512 
3513 /* Bitfield definition for register of struct array DAT: CRCINIT */
3514 /*
3515  * CRC_INIT (RW)
3516  *
3517  * CRC initial value
3518  */
3519 #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
3520 #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U)
3521 #define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK)
3522 #define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT)
3523 
3524 /* Bitfield definition for register of struct array DAT: CRCPOLY */
3525 /*
3526  * CRC_POLY (RW)
3527  *
3528  * CRC polymonial
3529  */
3530 #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
3531 #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U)
3532 #define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK)
3533 #define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT)
3534 
3535 /* Bitfield definition for register of struct array DAT: DATA */
3536 /*
3537  * DATA (RW)
3538  *
3539  * DATA
3540  */
3541 #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL)
3542 #define SEI_DAT_DATA_DATA_SHIFT (0U)
3543 #define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK)
3544 #define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT)
3545 
3546 /* Bitfield definition for register of struct array DAT: SET */
3547 /*
3548  * DATA_SET (RW)
3549  *
3550  * DATA bit set
3551  */
3552 #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL)
3553 #define SEI_DAT_SET_DATA_SET_SHIFT (0U)
3554 #define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK)
3555 #define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT)
3556 
3557 /* Bitfield definition for register of struct array DAT: CLR */
3558 /*
3559  * DATA_CLR (RW)
3560  *
3561  * DATA bit clear
3562  */
3563 #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
3564 #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U)
3565 #define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK)
3566 #define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT)
3567 
3568 /* Bitfield definition for register of struct array DAT: INV */
3569 /*
3570  * DATA_INV (RW)
3571  *
3572  * DATA bit toggle
3573  */
3574 #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL)
3575 #define SEI_DAT_INV_DATA_INV_SHIFT (0U)
3576 #define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK)
3577 #define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT)
3578 
3579 /* Bitfield definition for register of struct array DAT: IN */
3580 /*
3581  * DATA_IN (RO)
3582  *
3583  * Data input
3584  */
3585 #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL)
3586 #define SEI_DAT_IN_DATA_IN_SHIFT (0U)
3587 #define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT)
3588 
3589 /* Bitfield definition for register of struct array DAT: OUT */
3590 /*
3591  * DATA_OUT (RO)
3592  *
3593  * Data output
3594  */
3595 #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
3596 #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U)
3597 #define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT)
3598 
3599 /* Bitfield definition for register of struct array DAT: STS */
3600 /*
3601  * CRC_IDX (RO)
3602  *
3603  * CRC index
3604  */
3605 #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL)
3606 #define SEI_DAT_STS_CRC_IDX_SHIFT (24U)
3607 #define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT)
3608 
3609 /*
3610  * WORD_IDX (RO)
3611  *
3612  * Word index
3613  */
3614 #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL)
3615 #define SEI_DAT_STS_WORD_IDX_SHIFT (16U)
3616 #define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT)
3617 
3618 /*
3619  * WORD_CNT (RO)
3620  *
3621  * Word counter
3622  */
3623 #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U)
3624 #define SEI_DAT_STS_WORD_CNT_SHIFT (8U)
3625 #define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT)
3626 
3627 /*
3628  * BIT_IDX (RO)
3629  *
3630  * Bit index
3631  */
3632 #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU)
3633 #define SEI_DAT_STS_BIT_IDX_SHIFT (0U)
3634 #define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT)
3635 
3636 
3637 
3638 /* CMD register group index macro definition */
3639 #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL)
3640 #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL)
3641 #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL)
3642 #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL)
3643 
3644 /* TIME register group index macro definition */
3645 #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL)
3646 #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL)
3647 #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL)
3648 #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL)
3649 
3650 /* CMD_TABLE register group index macro definition */
3651 #define SEI_CMD_TABLE_0 (0UL)
3652 #define SEI_CMD_TABLE_1 (1UL)
3653 #define SEI_CMD_TABLE_2 (2UL)
3654 #define SEI_CMD_TABLE_3 (3UL)
3655 #define SEI_CMD_TABLE_4 (4UL)
3656 #define SEI_CMD_TABLE_5 (5UL)
3657 #define SEI_CMD_TABLE_6 (6UL)
3658 #define SEI_CMD_TABLE_7 (7UL)
3659 
3660 /* TRAN register group index macro definition */
3661 #define SEI_CTRL_LATCH_TRAN_0_1 (0UL)
3662 #define SEI_CTRL_LATCH_TRAN_1_2 (1UL)
3663 #define SEI_CTRL_LATCH_TRAN_2_3 (2UL)
3664 #define SEI_CTRL_LATCH_TRAN_3_0 (3UL)
3665 
3666 /* LATCH register group index macro definition */
3667 #define SEI_LATCH_0 (0UL)
3668 #define SEI_LATCH_1 (1UL)
3669 #define SEI_LATCH_2 (2UL)
3670 #define SEI_LATCH_3 (3UL)
3671 
3672 /* CTRL register group index macro definition */
3673 #define SEI_CTRL_0 (0UL)
3674 #define SEI_CTRL_1 (1UL)
3675 #define SEI_CTRL_2 (2UL)
3676 #define SEI_CTRL_3 (3UL)
3677 #define SEI_CTRL_4 (4UL)
3678 #define SEI_CTRL_5 (5UL)
3679 #define SEI_CTRL_6 (6UL)
3680 #define SEI_CTRL_7 (7UL)
3681 #define SEI_CTRL_8 (8UL)
3682 #define SEI_CTRL_9 (9UL)
3683 #define SEI_CTRL_10 (10UL)
3684 #define SEI_CTRL_11 (11UL)
3685 #define SEI_CTRL_12 (12UL)
3686 
3687 /* INSTR register group index macro definition */
3688 #define SEI_INSTR_0 (0UL)
3689 #define SEI_INSTR_1 (1UL)
3690 #define SEI_INSTR_2 (2UL)
3691 #define SEI_INSTR_3 (3UL)
3692 #define SEI_INSTR_4 (4UL)
3693 #define SEI_INSTR_5 (5UL)
3694 #define SEI_INSTR_6 (6UL)
3695 #define SEI_INSTR_7 (7UL)
3696 #define SEI_INSTR_8 (8UL)
3697 #define SEI_INSTR_9 (9UL)
3698 #define SEI_INSTR_10 (10UL)
3699 #define SEI_INSTR_11 (11UL)
3700 #define SEI_INSTR_12 (12UL)
3701 #define SEI_INSTR_13 (13UL)
3702 #define SEI_INSTR_14 (14UL)
3703 #define SEI_INSTR_15 (15UL)
3704 #define SEI_INSTR_16 (16UL)
3705 #define SEI_INSTR_17 (17UL)
3706 #define SEI_INSTR_18 (18UL)
3707 #define SEI_INSTR_19 (19UL)
3708 #define SEI_INSTR_20 (20UL)
3709 #define SEI_INSTR_21 (21UL)
3710 #define SEI_INSTR_22 (22UL)
3711 #define SEI_INSTR_23 (23UL)
3712 #define SEI_INSTR_24 (24UL)
3713 #define SEI_INSTR_25 (25UL)
3714 #define SEI_INSTR_26 (26UL)
3715 #define SEI_INSTR_27 (27UL)
3716 #define SEI_INSTR_28 (28UL)
3717 #define SEI_INSTR_29 (29UL)
3718 #define SEI_INSTR_30 (30UL)
3719 #define SEI_INSTR_31 (31UL)
3720 #define SEI_INSTR_32 (32UL)
3721 #define SEI_INSTR_33 (33UL)
3722 #define SEI_INSTR_34 (34UL)
3723 #define SEI_INSTR_35 (35UL)
3724 #define SEI_INSTR_36 (36UL)
3725 #define SEI_INSTR_37 (37UL)
3726 #define SEI_INSTR_38 (38UL)
3727 #define SEI_INSTR_39 (39UL)
3728 #define SEI_INSTR_40 (40UL)
3729 #define SEI_INSTR_41 (41UL)
3730 #define SEI_INSTR_42 (42UL)
3731 #define SEI_INSTR_43 (43UL)
3732 #define SEI_INSTR_44 (44UL)
3733 #define SEI_INSTR_45 (45UL)
3734 #define SEI_INSTR_46 (46UL)
3735 #define SEI_INSTR_47 (47UL)
3736 #define SEI_INSTR_48 (48UL)
3737 #define SEI_INSTR_49 (49UL)
3738 #define SEI_INSTR_50 (50UL)
3739 #define SEI_INSTR_51 (51UL)
3740 #define SEI_INSTR_52 (52UL)
3741 #define SEI_INSTR_53 (53UL)
3742 #define SEI_INSTR_54 (54UL)
3743 #define SEI_INSTR_55 (55UL)
3744 #define SEI_INSTR_56 (56UL)
3745 #define SEI_INSTR_57 (57UL)
3746 #define SEI_INSTR_58 (58UL)
3747 #define SEI_INSTR_59 (59UL)
3748 #define SEI_INSTR_60 (60UL)
3749 #define SEI_INSTR_61 (61UL)
3750 #define SEI_INSTR_62 (62UL)
3751 #define SEI_INSTR_63 (63UL)
3752 #define SEI_INSTR_64 (64UL)
3753 #define SEI_INSTR_65 (65UL)
3754 #define SEI_INSTR_66 (66UL)
3755 #define SEI_INSTR_67 (67UL)
3756 #define SEI_INSTR_68 (68UL)
3757 #define SEI_INSTR_69 (69UL)
3758 #define SEI_INSTR_70 (70UL)
3759 #define SEI_INSTR_71 (71UL)
3760 #define SEI_INSTR_72 (72UL)
3761 #define SEI_INSTR_73 (73UL)
3762 #define SEI_INSTR_74 (74UL)
3763 #define SEI_INSTR_75 (75UL)
3764 #define SEI_INSTR_76 (76UL)
3765 #define SEI_INSTR_77 (77UL)
3766 #define SEI_INSTR_78 (78UL)
3767 #define SEI_INSTR_79 (79UL)
3768 #define SEI_INSTR_80 (80UL)
3769 #define SEI_INSTR_81 (81UL)
3770 #define SEI_INSTR_82 (82UL)
3771 #define SEI_INSTR_83 (83UL)
3772 #define SEI_INSTR_84 (84UL)
3773 #define SEI_INSTR_85 (85UL)
3774 #define SEI_INSTR_86 (86UL)
3775 #define SEI_INSTR_87 (87UL)
3776 #define SEI_INSTR_88 (88UL)
3777 #define SEI_INSTR_89 (89UL)
3778 #define SEI_INSTR_90 (90UL)
3779 #define SEI_INSTR_91 (91UL)
3780 #define SEI_INSTR_92 (92UL)
3781 #define SEI_INSTR_93 (93UL)
3782 #define SEI_INSTR_94 (94UL)
3783 #define SEI_INSTR_95 (95UL)
3784 #define SEI_INSTR_96 (96UL)
3785 #define SEI_INSTR_97 (97UL)
3786 #define SEI_INSTR_98 (98UL)
3787 #define SEI_INSTR_99 (99UL)
3788 #define SEI_INSTR_100 (100UL)
3789 #define SEI_INSTR_101 (101UL)
3790 #define SEI_INSTR_102 (102UL)
3791 #define SEI_INSTR_103 (103UL)
3792 #define SEI_INSTR_104 (104UL)
3793 #define SEI_INSTR_105 (105UL)
3794 #define SEI_INSTR_106 (106UL)
3795 #define SEI_INSTR_107 (107UL)
3796 #define SEI_INSTR_108 (108UL)
3797 #define SEI_INSTR_109 (109UL)
3798 #define SEI_INSTR_110 (110UL)
3799 #define SEI_INSTR_111 (111UL)
3800 #define SEI_INSTR_112 (112UL)
3801 #define SEI_INSTR_113 (113UL)
3802 #define SEI_INSTR_114 (114UL)
3803 #define SEI_INSTR_115 (115UL)
3804 #define SEI_INSTR_116 (116UL)
3805 #define SEI_INSTR_117 (117UL)
3806 #define SEI_INSTR_118 (118UL)
3807 #define SEI_INSTR_119 (119UL)
3808 #define SEI_INSTR_120 (120UL)
3809 #define SEI_INSTR_121 (121UL)
3810 #define SEI_INSTR_122 (122UL)
3811 #define SEI_INSTR_123 (123UL)
3812 #define SEI_INSTR_124 (124UL)
3813 #define SEI_INSTR_125 (125UL)
3814 #define SEI_INSTR_126 (126UL)
3815 #define SEI_INSTR_127 (127UL)
3816 #define SEI_INSTR_128 (128UL)
3817 #define SEI_INSTR_129 (129UL)
3818 #define SEI_INSTR_130 (130UL)
3819 #define SEI_INSTR_131 (131UL)
3820 #define SEI_INSTR_132 (132UL)
3821 #define SEI_INSTR_133 (133UL)
3822 #define SEI_INSTR_134 (134UL)
3823 #define SEI_INSTR_135 (135UL)
3824 #define SEI_INSTR_136 (136UL)
3825 #define SEI_INSTR_137 (137UL)
3826 #define SEI_INSTR_138 (138UL)
3827 #define SEI_INSTR_139 (139UL)
3828 #define SEI_INSTR_140 (140UL)
3829 #define SEI_INSTR_141 (141UL)
3830 #define SEI_INSTR_142 (142UL)
3831 #define SEI_INSTR_143 (143UL)
3832 #define SEI_INSTR_144 (144UL)
3833 #define SEI_INSTR_145 (145UL)
3834 #define SEI_INSTR_146 (146UL)
3835 #define SEI_INSTR_147 (147UL)
3836 #define SEI_INSTR_148 (148UL)
3837 #define SEI_INSTR_149 (149UL)
3838 #define SEI_INSTR_150 (150UL)
3839 #define SEI_INSTR_151 (151UL)
3840 #define SEI_INSTR_152 (152UL)
3841 #define SEI_INSTR_153 (153UL)
3842 #define SEI_INSTR_154 (154UL)
3843 #define SEI_INSTR_155 (155UL)
3844 #define SEI_INSTR_156 (156UL)
3845 #define SEI_INSTR_157 (157UL)
3846 #define SEI_INSTR_158 (158UL)
3847 #define SEI_INSTR_159 (159UL)
3848 #define SEI_INSTR_160 (160UL)
3849 #define SEI_INSTR_161 (161UL)
3850 #define SEI_INSTR_162 (162UL)
3851 #define SEI_INSTR_163 (163UL)
3852 #define SEI_INSTR_164 (164UL)
3853 #define SEI_INSTR_165 (165UL)
3854 #define SEI_INSTR_166 (166UL)
3855 #define SEI_INSTR_167 (167UL)
3856 #define SEI_INSTR_168 (168UL)
3857 #define SEI_INSTR_169 (169UL)
3858 #define SEI_INSTR_170 (170UL)
3859 #define SEI_INSTR_171 (171UL)
3860 #define SEI_INSTR_172 (172UL)
3861 #define SEI_INSTR_173 (173UL)
3862 #define SEI_INSTR_174 (174UL)
3863 #define SEI_INSTR_175 (175UL)
3864 #define SEI_INSTR_176 (176UL)
3865 #define SEI_INSTR_177 (177UL)
3866 #define SEI_INSTR_178 (178UL)
3867 #define SEI_INSTR_179 (179UL)
3868 #define SEI_INSTR_180 (180UL)
3869 #define SEI_INSTR_181 (181UL)
3870 #define SEI_INSTR_182 (182UL)
3871 #define SEI_INSTR_183 (183UL)
3872 #define SEI_INSTR_184 (184UL)
3873 #define SEI_INSTR_185 (185UL)
3874 #define SEI_INSTR_186 (186UL)
3875 #define SEI_INSTR_187 (187UL)
3876 #define SEI_INSTR_188 (188UL)
3877 #define SEI_INSTR_189 (189UL)
3878 #define SEI_INSTR_190 (190UL)
3879 #define SEI_INSTR_191 (191UL)
3880 #define SEI_INSTR_192 (192UL)
3881 #define SEI_INSTR_193 (193UL)
3882 #define SEI_INSTR_194 (194UL)
3883 #define SEI_INSTR_195 (195UL)
3884 #define SEI_INSTR_196 (196UL)
3885 #define SEI_INSTR_197 (197UL)
3886 #define SEI_INSTR_198 (198UL)
3887 #define SEI_INSTR_199 (199UL)
3888 #define SEI_INSTR_200 (200UL)
3889 #define SEI_INSTR_201 (201UL)
3890 #define SEI_INSTR_202 (202UL)
3891 #define SEI_INSTR_203 (203UL)
3892 #define SEI_INSTR_204 (204UL)
3893 #define SEI_INSTR_205 (205UL)
3894 #define SEI_INSTR_206 (206UL)
3895 #define SEI_INSTR_207 (207UL)
3896 #define SEI_INSTR_208 (208UL)
3897 #define SEI_INSTR_209 (209UL)
3898 #define SEI_INSTR_210 (210UL)
3899 #define SEI_INSTR_211 (211UL)
3900 #define SEI_INSTR_212 (212UL)
3901 #define SEI_INSTR_213 (213UL)
3902 #define SEI_INSTR_214 (214UL)
3903 #define SEI_INSTR_215 (215UL)
3904 #define SEI_INSTR_216 (216UL)
3905 #define SEI_INSTR_217 (217UL)
3906 #define SEI_INSTR_218 (218UL)
3907 #define SEI_INSTR_219 (219UL)
3908 #define SEI_INSTR_220 (220UL)
3909 #define SEI_INSTR_221 (221UL)
3910 #define SEI_INSTR_222 (222UL)
3911 #define SEI_INSTR_223 (223UL)
3912 #define SEI_INSTR_224 (224UL)
3913 #define SEI_INSTR_225 (225UL)
3914 #define SEI_INSTR_226 (226UL)
3915 #define SEI_INSTR_227 (227UL)
3916 #define SEI_INSTR_228 (228UL)
3917 #define SEI_INSTR_229 (229UL)
3918 #define SEI_INSTR_230 (230UL)
3919 #define SEI_INSTR_231 (231UL)
3920 #define SEI_INSTR_232 (232UL)
3921 #define SEI_INSTR_233 (233UL)
3922 #define SEI_INSTR_234 (234UL)
3923 #define SEI_INSTR_235 (235UL)
3924 #define SEI_INSTR_236 (236UL)
3925 #define SEI_INSTR_237 (237UL)
3926 #define SEI_INSTR_238 (238UL)
3927 #define SEI_INSTR_239 (239UL)
3928 #define SEI_INSTR_240 (240UL)
3929 #define SEI_INSTR_241 (241UL)
3930 #define SEI_INSTR_242 (242UL)
3931 #define SEI_INSTR_243 (243UL)
3932 #define SEI_INSTR_244 (244UL)
3933 #define SEI_INSTR_245 (245UL)
3934 #define SEI_INSTR_246 (246UL)
3935 #define SEI_INSTR_247 (247UL)
3936 #define SEI_INSTR_248 (248UL)
3937 #define SEI_INSTR_249 (249UL)
3938 #define SEI_INSTR_250 (250UL)
3939 #define SEI_INSTR_251 (251UL)
3940 #define SEI_INSTR_252 (252UL)
3941 #define SEI_INSTR_253 (253UL)
3942 #define SEI_INSTR_254 (254UL)
3943 #define SEI_INSTR_255 (255UL)
3944 
3945 /* DAT register group index macro definition */
3946 #define SEI_DAT_0 (0UL)
3947 #define SEI_DAT_1 (1UL)
3948 #define SEI_DAT_2 (2UL)
3949 #define SEI_DAT_3 (3UL)
3950 #define SEI_DAT_4 (4UL)
3951 #define SEI_DAT_5 (5UL)
3952 #define SEI_DAT_6 (6UL)
3953 #define SEI_DAT_7 (7UL)
3954 #define SEI_DAT_8 (8UL)
3955 #define SEI_DAT_9 (9UL)
3956 #define SEI_DAT_10 (10UL)
3957 #define SEI_DAT_11 (11UL)
3958 #define SEI_DAT_12 (12UL)
3959 #define SEI_DAT_13 (13UL)
3960 #define SEI_DAT_14 (14UL)
3961 #define SEI_DAT_15 (15UL)
3962 #define SEI_DAT_16 (16UL)
3963 #define SEI_DAT_17 (17UL)
3964 #define SEI_DAT_18 (18UL)
3965 #define SEI_DAT_19 (19UL)
3966 #define SEI_DAT_20 (20UL)
3967 #define SEI_DAT_21 (21UL)
3968 #define SEI_DAT_22 (22UL)
3969 #define SEI_DAT_23 (23UL)
3970 #define SEI_DAT_24 (24UL)
3971 #define SEI_DAT_25 (25UL)
3972 #define SEI_DAT_26 (26UL)
3973 #define SEI_DAT_27 (27UL)
3974 #define SEI_DAT_28 (28UL)
3975 #define SEI_DAT_29 (29UL)
3976 #define SEI_DAT_30 (30UL)
3977 #define SEI_DAT_31 (31UL)
3978 
3979 
3980 #endif /* HPM_SEI_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
SEI_Type
Definition: hpm_sei_regs.h:12