HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_trgm_regs.h File Reference

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Data Structures

struct  TRGM_Type
 

Macros

#define TRGM_FILTCFG_OUTINV_MASK   (0x10000UL)
 
#define TRGM_FILTCFG_OUTINV_SHIFT   (16U)
 
#define TRGM_FILTCFG_OUTINV_SET(x)   (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK)
 
#define TRGM_FILTCFG_OUTINV_GET(x)   (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT)
 
#define TRGM_FILTCFG_MODE_MASK   (0xE000U)
 
#define TRGM_FILTCFG_MODE_SHIFT   (13U)
 
#define TRGM_FILTCFG_MODE_SET(x)   (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK)
 
#define TRGM_FILTCFG_MODE_GET(x)   (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT)
 
#define TRGM_FILTCFG_SYNCEN_MASK   (0x1000U)
 
#define TRGM_FILTCFG_SYNCEN_SHIFT   (12U)
 
#define TRGM_FILTCFG_SYNCEN_SET(x)   (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK)
 
#define TRGM_FILTCFG_SYNCEN_GET(x)   (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT)
 
#define TRGM_FILTCFG_FILTLEN_SHIFT_MASK   (0xE00U)
 
#define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT   (9U)
 
#define TRGM_FILTCFG_FILTLEN_SHIFT_SET(x)   (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK)
 
#define TRGM_FILTCFG_FILTLEN_SHIFT_GET(x)   (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT)
 
#define TRGM_FILTCFG_FILTLEN_BASE_MASK   (0x1FFU)
 
#define TRGM_FILTCFG_FILTLEN_BASE_SHIFT   (0U)
 
#define TRGM_FILTCFG_FILTLEN_BASE_SET(x)   (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK)
 
#define TRGM_FILTCFG_FILTLEN_BASE_GET(x)   (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)
 
#define TRGM_DMACFG_DMAMUX_EN_MASK   (0x80000000UL)
 
#define TRGM_DMACFG_DMAMUX_EN_SHIFT   (31U)
 
#define TRGM_DMACFG_DMAMUX_EN_SET(x)   (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK)
 
#define TRGM_DMACFG_DMAMUX_EN_GET(x)   (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT)
 
#define TRGM_DMACFG_DMASRCSEL_MASK   (0x3FU)
 
#define TRGM_DMACFG_DMASRCSEL_SHIFT   (0U)
 
#define TRGM_DMACFG_DMASRCSEL_SET(x)   (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK)
 
#define TRGM_DMACFG_DMASRCSEL_GET(x)   (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT)
 
#define TRGM_GCR_TRGOPEN_MASK   (0xFFFFFFFFUL)
 
#define TRGM_GCR_TRGOPEN_SHIFT   (0U)
 
#define TRGM_GCR_TRGOPEN_SET(x)   (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK)
 
#define TRGM_GCR_TRGOPEN_GET(x)   (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK   (0xFF000000UL)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT   (24U)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK   (0xFF0000UL)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT   (16U)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK   (0xFF00U)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT   (8U)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK   (0xFFU)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT   (0U)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK   (0xFF000000UL)
 
#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT   (24U)
 
#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK   (0xFF0000UL)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT   (16U)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK   (0xFF00U)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT   (8U)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK   (0xFFU)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT   (0U)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT)
 
#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK   (0xFFU)
 
#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT   (0U)
 
#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SET(x)   (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK)
 
#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_GET(x)   (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK   (0xFF000000UL)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT   (24U)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK   (0xFF0000UL)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT   (16U)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK   (0xFF00U)
 
#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT   (8U)
 
#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT)
 
#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK   (0xFFU)
 
#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT   (0U)
 
#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SET(x)   (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK)
 
#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_GET(x)   (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT)
 
#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK   (0xFF000000UL)
 
#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT   (24U)
 
#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SET(x)   (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK)
 
#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_GET(x)   (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT)
 
#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK   (0xFF0000UL)
 
#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT   (16U)
 
#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SET(x)   (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK)
 
#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_GET(x)   (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK   (0xFF00U)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT   (8U)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(x)   (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET(x)   (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK   (0xFFU)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT   (0U)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(x)   (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK)
 
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET(x)   (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT)
 
#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK   (0xFF00U)
 
#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT   (8U)
 
#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SET(x)   (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK)
 
#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_GET(x)   (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT)
 
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK   (0xFFU)
 
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT   (0U)
 
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(x)   (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK)
 
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET(x)   (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT)
 
#define TRGM_TRGM_IN_TRGM_IN_MASK   (0xFFFFFFFFUL)
 
#define TRGM_TRGM_IN_TRGM_IN_SHIFT   (0U)
 
#define TRGM_TRGM_IN_TRGM_IN_GET(x)   (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT)
 
#define TRGM_TRGM_OUT_TRGM_OUT_MASK   (0xFFFFFFFFUL)
 
#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT   (0U)
 
#define TRGM_TRGM_OUT_TRGM_OUT_GET(x)   (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK   (0x3F00U)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT   (8U)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SET(x)   (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_GET(x)   (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK   (0x3FU)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT   (0U)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SET(x)   (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK)
 
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_GET(x)   (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT)
 
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK   (0x8000U)
 
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT   (15U)
 
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SET(x)   (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK)
 
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_GET(x)   (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT)
 
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK   (0x80U)
 
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT   (7U)
 
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SET(x)   (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK)
 
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_GET(x)   (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT)
 
#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK   (0x80000000UL)
 
#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT   (31U)
 
#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_GET(x)   (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK) >> TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT)
 
#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_MASK   (0x3F00U)
 
#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_SHIFT   (8U)
 
#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_GET(x)   (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_MASK) >> TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_SHIFT)
 
#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_MASK   (0x3FU)
 
#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_SHIFT   (0U)
 
#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_GET(x)   (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_MASK) >> TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_SHIFT)
 
#define TRGM_TRGOCFG_OUTINV_MASK   (0x40000UL)
 
#define TRGM_TRGOCFG_OUTINV_SHIFT   (18U)
 
#define TRGM_TRGOCFG_OUTINV_SET(x)   (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK)
 
#define TRGM_TRGOCFG_OUTINV_GET(x)   (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT)
 
#define TRGM_TRGOCFG_FEDG2PEN_MASK   (0x20000UL)
 
#define TRGM_TRGOCFG_FEDG2PEN_SHIFT   (17U)
 
#define TRGM_TRGOCFG_FEDG2PEN_SET(x)   (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK)
 
#define TRGM_TRGOCFG_FEDG2PEN_GET(x)   (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT)
 
#define TRGM_TRGOCFG_REDG2PEN_MASK   (0x10000UL)
 
#define TRGM_TRGOCFG_REDG2PEN_SHIFT   (16U)
 
#define TRGM_TRGOCFG_REDG2PEN_SET(x)   (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK)
 
#define TRGM_TRGOCFG_REDG2PEN_GET(x)   (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT)
 
#define TRGM_TRGOCFG_TRIGOSEL_MASK   (0xFFU)
 
#define TRGM_TRGOCFG_TRIGOSEL_SHIFT   (0U)
 
#define TRGM_TRGOCFG_TRIGOSEL_SET(x)   (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK)
 
#define TRGM_TRGOCFG_TRIGOSEL_GET(x)   (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT)
 
#define TRGM_FILTCFG_PWM0_IN0   (0UL)
 
#define TRGM_FILTCFG_PWM0_IN1   (1UL)
 
#define TRGM_FILTCFG_PWM0_IN2   (2UL)
 
#define TRGM_FILTCFG_PWM0_IN3   (3UL)
 
#define TRGM_FILTCFG_PWM0_IN4   (4UL)
 
#define TRGM_FILTCFG_PWM0_IN5   (5UL)
 
#define TRGM_FILTCFG_PWM0_IN6   (6UL)
 
#define TRGM_FILTCFG_PWM0_IN7   (7UL)
 
#define TRGM_FILTCFG_PWM1_IN0   (8UL)
 
#define TRGM_FILTCFG_PWM1_IN1   (9UL)
 
#define TRGM_FILTCFG_PWM1_IN2   (10UL)
 
#define TRGM_FILTCFG_PWM1_IN3   (11UL)
 
#define TRGM_FILTCFG_PWM1_IN4   (12UL)
 
#define TRGM_FILTCFG_PWM1_IN5   (13UL)
 
#define TRGM_FILTCFG_PWM1_IN6   (14UL)
 
#define TRGM_FILTCFG_PWM1_IN7   (15UL)
 
#define TRGM_FILTCFG_PWM2_IN0   (16UL)
 
#define TRGM_FILTCFG_PWM2_IN1   (17UL)
 
#define TRGM_FILTCFG_PWM2_IN2   (18UL)
 
#define TRGM_FILTCFG_PWM2_IN3   (19UL)
 
#define TRGM_FILTCFG_PWM2_IN4   (20UL)
 
#define TRGM_FILTCFG_PWM2_IN5   (21UL)
 
#define TRGM_FILTCFG_PWM2_IN6   (22UL)
 
#define TRGM_FILTCFG_PWM2_IN7   (23UL)
 
#define TRGM_FILTCFG_PWM3_IN0   (24UL)
 
#define TRGM_FILTCFG_PWM3_IN1   (25UL)
 
#define TRGM_FILTCFG_PWM3_IN2   (26UL)
 
#define TRGM_FILTCFG_PWM3_IN3   (27UL)
 
#define TRGM_FILTCFG_PWM3_IN4   (28UL)
 
#define TRGM_FILTCFG_PWM3_IN5   (29UL)
 
#define TRGM_FILTCFG_PWM3_IN6   (30UL)
 
#define TRGM_FILTCFG_PWM3_IN7   (31UL)
 
#define TRGM_FILTCFG_TRGM_P_00   (32UL)
 
#define TRGM_FILTCFG_TRGM_P_01   (33UL)
 
#define TRGM_FILTCFG_TRGM_P_02   (34UL)
 
#define TRGM_FILTCFG_TRGM_P_03   (35UL)
 
#define TRGM_FILTCFG_TRGM_P_04   (36UL)
 
#define TRGM_FILTCFG_TRGM_P_05   (37UL)
 
#define TRGM_FILTCFG_TRGM_P_06   (38UL)
 
#define TRGM_FILTCFG_TRGM_P_07   (39UL)
 
#define TRGM_FILTCFG_TRGM_P_08   (40UL)
 
#define TRGM_FILTCFG_TRGM_P_09   (41UL)
 
#define TRGM_FILTCFG_TRGM_P_10   (42UL)
 
#define TRGM_FILTCFG_TRGM_P_11   (43UL)
 
#define TRGM_FILTCFG_TRGM_P_12   (44UL)
 
#define TRGM_FILTCFG_TRGM_P_13   (45UL)
 
#define TRGM_FILTCFG_TRGM_P_14   (46UL)
 
#define TRGM_FILTCFG_TRGM_P_15   (47UL)
 
#define TRGM_FILTCFG_TRGM_P_16   (48UL)
 
#define TRGM_FILTCFG_TRGM_P_17   (49UL)
 
#define TRGM_FILTCFG_TRGM_P_18   (50UL)
 
#define TRGM_FILTCFG_TRGM_P_19   (51UL)
 
#define TRGM_FILTCFG_TRGM_P_20   (52UL)
 
#define TRGM_FILTCFG_TRGM_P_21   (53UL)
 
#define TRGM_FILTCFG_TRGM_P_22   (54UL)
 
#define TRGM_FILTCFG_TRGM_P_23   (55UL)
 
#define TRGM_FILTCFG_TRGM_P_24   (56UL)
 
#define TRGM_FILTCFG_TRGM_P_25   (57UL)
 
#define TRGM_FILTCFG_TRGM_P_26   (58UL)
 
#define TRGM_FILTCFG_TRGM_P_27   (59UL)
 
#define TRGM_FILTCFG_TRGM_P_28   (60UL)
 
#define TRGM_FILTCFG_TRGM_P_29   (61UL)
 
#define TRGM_FILTCFG_TRGM_P_30   (62UL)
 
#define TRGM_FILTCFG_TRGM_P_31   (63UL)
 
#define TRGM_DMACFG_0   (0UL)
 
#define TRGM_DMACFG_1   (1UL)
 
#define TRGM_DMACFG_2   (2UL)
 
#define TRGM_DMACFG_3   (3UL)
 
#define TRGM_DMACFG_4   (4UL)
 
#define TRGM_DMACFG_5   (5UL)
 
#define TRGM_DMACFG_6   (6UL)
 
#define TRGM_DMACFG_7   (7UL)
 
#define TRGM_TRGM_IN_0   (0UL)
 
#define TRGM_TRGM_IN_1   (1UL)
 
#define TRGM_TRGM_IN_2   (2UL)
 
#define TRGM_TRGM_IN_3   (3UL)
 
#define TRGM_TRGM_IN_4   (4UL)
 
#define TRGM_TRGM_IN_5   (5UL)
 
#define TRGM_TRGM_IN_6   (6UL)
 
#define TRGM_TRGM_OUT_0   (0UL)
 
#define TRGM_TRGM_OUT_1   (1UL)
 
#define TRGM_TRGM_OUT_2   (2UL)
 
#define TRGM_TRGM_OUT_3   (3UL)
 
#define TRGM_TRGM_OUT_4   (4UL)
 
#define TRGM_TRGM_OUT_5   (5UL)
 
#define TRGM_TRGM_OUT_6   (6UL)
 
#define TRGM_TRGOCFG_TRGM_P_00   (0UL)
 
#define TRGM_TRGOCFG_TRGM_P_01   (1UL)
 
#define TRGM_TRGOCFG_TRGM_P_02   (2UL)
 
#define TRGM_TRGOCFG_TRGM_P_03   (3UL)
 
#define TRGM_TRGOCFG_TRGM_P_04   (4UL)
 
#define TRGM_TRGOCFG_TRGM_P_05   (5UL)
 
#define TRGM_TRGOCFG_TRGM_P_06   (6UL)
 
#define TRGM_TRGOCFG_TRGM_P_07   (7UL)
 
#define TRGM_TRGOCFG_TRGM_P_08   (8UL)
 
#define TRGM_TRGOCFG_TRGM_P_09   (9UL)
 
#define TRGM_TRGOCFG_TRGM_P_10   (10UL)
 
#define TRGM_TRGOCFG_TRGM_P_11   (11UL)
 
#define TRGM_TRGOCFG_TRGM_P_12   (12UL)
 
#define TRGM_TRGOCFG_TRGM_P_13   (13UL)
 
#define TRGM_TRGOCFG_TRGM_P_14   (14UL)
 
#define TRGM_TRGOCFG_TRGM_P_15   (15UL)
 
#define TRGM_TRGOCFG_TRGM_P_16   (16UL)
 
#define TRGM_TRGOCFG_TRGM_P_17   (17UL)
 
#define TRGM_TRGOCFG_TRGM_P_18   (18UL)
 
#define TRGM_TRGOCFG_TRGM_P_19   (19UL)
 
#define TRGM_TRGOCFG_TRGM_P_20   (20UL)
 
#define TRGM_TRGOCFG_TRGM_P_21   (21UL)
 
#define TRGM_TRGOCFG_TRGM_P_22   (22UL)
 
#define TRGM_TRGOCFG_TRGM_P_23   (23UL)
 
#define TRGM_TRGOCFG_TRGM_P_24   (24UL)
 
#define TRGM_TRGOCFG_TRGM_P_25   (25UL)
 
#define TRGM_TRGOCFG_TRGM_P_26   (26UL)
 
#define TRGM_TRGOCFG_TRGM_P_27   (27UL)
 
#define TRGM_TRGOCFG_TRGM_P_28   (28UL)
 
#define TRGM_TRGOCFG_TRGM_P_29   (29UL)
 
#define TRGM_TRGOCFG_TRGM_P_30   (30UL)
 
#define TRGM_TRGOCFG_TRGM_P_31   (31UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC0   (32UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC1   (33UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC2   (34UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC3   (35UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC4   (36UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC5   (37UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC6   (38UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC7   (39UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC8   (40UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC9   (41UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC10   (42UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC11   (43UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC12   (44UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC13   (45UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC14   (46UL)
 
#define TRGM_TRGOCFG_SDM_PWM_SOC15   (47UL)
 
#define TRGM_TRGOCFG_ADC0_STRGI   (48UL)
 
#define TRGM_TRGOCFG_ADC1_STRGI   (49UL)
 
#define TRGM_TRGOCFG_ADC2_STRGI   (50UL)
 
#define TRGM_TRGOCFG_ADC3_STRGI   (51UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI0A   (52UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI0B   (53UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI0C   (54UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI1A   (55UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI1B   (56UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI1C   (57UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI2A   (58UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI2B   (59UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI2C   (60UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI3A   (61UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI3B   (62UL)
 
#define TRGM_TRGOCFG_ADCX_PTRGI3C   (63UL)
 
#define TRGM_TRGOCFG_VSC0_TRIG_IN0   (64UL)
 
#define TRGM_TRGOCFG_VSC0_TRIG_IN1   (65UL)
 
#define TRGM_TRGOCFG_RDC0_TRIG_IN0   (66UL)
 
#define TRGM_TRGOCFG_RDC0_TRIG_IN1   (67UL)
 
#define TRGM_TRGOCFG_QEI0_TRIG_IN   (68UL)
 
#define TRGM_TRGOCFG_QEI1_TRIG_IN   (69UL)
 
#define TRGM_TRGOCFG_QEI0_PAUSE   (70UL)
 
#define TRGM_TRGOCFG_QEI1_PAUSE   (71UL)
 
#define TRGM_TRGOCFG_QEO0_TRIG_IN0   (72UL)
 
#define TRGM_TRGOCFG_QEO0_TRIG_IN1   (73UL)
 
#define TRGM_TRGOCFG_QEO1_TRIG_IN0   (74UL)
 
#define TRGM_TRGOCFG_QEO1_TRIG_IN1   (75UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN0   (76UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN1   (77UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN2   (78UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN3   (79UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN4   (80UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN5   (81UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN6   (82UL)
 
#define TRGM_TRGOCFG_SEI_TRIG_IN7   (83UL)
 
#define TRGM_TRGOCFG_ACMP0_CH0_WIN   (84UL)
 
#define TRGM_TRGOCFG_ACMP0_CH1_WIN   (85UL)
 
#define TRGM_TRGOCFG_ACMP1_CH0_WIN   (86UL)
 
#define TRGM_TRGOCFG_ACMP1_CH1_WIN   (87UL)
 
#define TRGM_TRGOCFG_ACMP2_CH0_WIN   (88UL)
 
#define TRGM_TRGOCFG_ACMP2_CH1_WIN   (89UL)
 
#define TRGM_TRGOCFG_ACMP3_CH0_WIN   (90UL)
 
#define TRGM_TRGOCFG_ACMP3_CH1_WIN   (91UL)
 
#define TRGM_TRGOCFG_DAC0_BUFTRG   (92UL)
 
#define TRGM_TRGOCFG_DAC1_BUFTRG   (93UL)
 
#define TRGM_TRGOCFG_GPTMR0_IN2   (94UL)
 
#define TRGM_TRGOCFG_GPTMR0_IN3   (95UL)
 
#define TRGM_TRGOCFG_GPTMR0_SYNCI   (96UL)
 
#define TRGM_TRGOCFG_GPTMR1_IN2   (97UL)
 
#define TRGM_TRGOCFG_GPTMR1_IN3   (98UL)
 
#define TRGM_TRGOCFG_GPTMR1_SYNCI   (99UL)
 
#define TRGM_TRGOCFG_GPTMR2_IN2   (100UL)
 
#define TRGM_TRGOCFG_GPTMR2_IN3   (101UL)
 
#define TRGM_TRGOCFG_GPTMR2_SYNCI   (102UL)
 
#define TRGM_TRGOCFG_GPTMR3_IN2   (103UL)
 
#define TRGM_TRGOCFG_GPTMR3_IN3   (104UL)
 
#define TRGM_TRGOCFG_GPTMR3_SYNCI   (105UL)
 
#define TRGM_TRGOCFG_PLB_IN_00   (106UL)
 
#define TRGM_TRGOCFG_PLB_IN_01   (107UL)
 
#define TRGM_TRGOCFG_PLB_IN_02   (108UL)
 
#define TRGM_TRGOCFG_PLB_IN_03   (109UL)
 
#define TRGM_TRGOCFG_PLB_IN_04   (110UL)
 
#define TRGM_TRGOCFG_PLB_IN_05   (111UL)
 
#define TRGM_TRGOCFG_PLB_IN_06   (112UL)
 
#define TRGM_TRGOCFG_PLB_IN_07   (113UL)
 
#define TRGM_TRGOCFG_PLB_IN_08   (114UL)
 
#define TRGM_TRGOCFG_PLB_IN_09   (115UL)
 
#define TRGM_TRGOCFG_PLB_IN_10   (116UL)
 
#define TRGM_TRGOCFG_PLB_IN_11   (117UL)
 
#define TRGM_TRGOCFG_PLB_IN_12   (118UL)
 
#define TRGM_TRGOCFG_PLB_IN_13   (119UL)
 
#define TRGM_TRGOCFG_PLB_IN_14   (120UL)
 
#define TRGM_TRGOCFG_PLB_IN_15   (121UL)
 
#define TRGM_TRGOCFG_PLB_IN_16   (122UL)
 
#define TRGM_TRGOCFG_PLB_IN_17   (123UL)
 
#define TRGM_TRGOCFG_PLB_IN_18   (124UL)
 
#define TRGM_TRGOCFG_PLB_IN_19   (125UL)
 
#define TRGM_TRGOCFG_PLB_IN_20   (126UL)
 
#define TRGM_TRGOCFG_PLB_IN_21   (127UL)
 
#define TRGM_TRGOCFG_PLB_IN_22   (128UL)
 
#define TRGM_TRGOCFG_PLB_IN_23   (129UL)
 
#define TRGM_TRGOCFG_PLB_IN_24   (130UL)
 
#define TRGM_TRGOCFG_PLB_IN_25   (131UL)
 
#define TRGM_TRGOCFG_PLB_IN_26   (132UL)
 
#define TRGM_TRGOCFG_PLB_IN_27   (133UL)
 
#define TRGM_TRGOCFG_PLB_IN_28   (134UL)
 
#define TRGM_TRGOCFG_PLB_IN_29   (135UL)
 
#define TRGM_TRGOCFG_PLB_IN_30   (136UL)
 
#define TRGM_TRGOCFG_PLB_IN_31   (137UL)
 
#define TRGM_TRGOCFG_PLB_IN_32   (138UL)
 
#define TRGM_TRGOCFG_PLB_IN_33   (139UL)
 
#define TRGM_TRGOCFG_PLB_IN_34   (140UL)
 
#define TRGM_TRGOCFG_PLB_IN_35   (141UL)
 
#define TRGM_TRGOCFG_PLB_IN_36   (142UL)
 
#define TRGM_TRGOCFG_PLB_IN_37   (143UL)
 
#define TRGM_TRGOCFG_PLB_IN_38   (144UL)
 
#define TRGM_TRGOCFG_PLB_IN_39   (145UL)
 
#define TRGM_TRGOCFG_PLB_IN_40   (146UL)
 
#define TRGM_TRGOCFG_PLB_IN_41   (147UL)
 
#define TRGM_TRGOCFG_PLB_IN_42   (148UL)
 
#define TRGM_TRGOCFG_PLB_IN_43   (149UL)
 
#define TRGM_TRGOCFG_PLB_IN_44   (150UL)
 
#define TRGM_TRGOCFG_PLB_IN_45   (151UL)
 
#define TRGM_TRGOCFG_PLB_IN_46   (152UL)
 
#define TRGM_TRGOCFG_PLB_IN_47   (153UL)
 
#define TRGM_TRGOCFG_PLB_IN_48   (154UL)
 
#define TRGM_TRGOCFG_PLB_IN_49   (155UL)
 
#define TRGM_TRGOCFG_PLB_IN_50   (156UL)
 
#define TRGM_TRGOCFG_PLB_IN_51   (157UL)
 
#define TRGM_TRGOCFG_PLB_IN_52   (158UL)
 
#define TRGM_TRGOCFG_PLB_IN_53   (159UL)
 
#define TRGM_TRGOCFG_PLB_IN_54   (160UL)
 
#define TRGM_TRGOCFG_PLB_IN_55   (161UL)
 
#define TRGM_TRGOCFG_PLB_IN_56   (162UL)
 
#define TRGM_TRGOCFG_PLB_IN_57   (163UL)
 
#define TRGM_TRGOCFG_PLB_IN_58   (164UL)
 
#define TRGM_TRGOCFG_PLB_IN_59   (165UL)
 
#define TRGM_TRGOCFG_PLB_IN_60   (166UL)
 
#define TRGM_TRGOCFG_PLB_IN_61   (167UL)
 
#define TRGM_TRGOCFG_PLB_IN_62   (168UL)
 
#define TRGM_TRGOCFG_PLB_IN_63   (169UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN0   (170UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN1   (171UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN2   (172UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN3   (173UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN4   (174UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN5   (175UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN6   (176UL)
 
#define TRGM_TRGOCFG_PWM0_TRIG_IN7   (177UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN0   (178UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN1   (179UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN2   (180UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN3   (181UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN4   (182UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN5   (183UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN6   (184UL)
 
#define TRGM_TRGOCFG_PWM1_TRIG_IN7   (185UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN0   (186UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN1   (187UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN2   (188UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN3   (189UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN4   (190UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN5   (191UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN6   (192UL)
 
#define TRGM_TRGOCFG_PWM2_TRIG_IN7   (193UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN0   (194UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN1   (195UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN2   (196UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN3   (197UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN4   (198UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN5   (199UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN6   (200UL)
 
#define TRGM_TRGOCFG_PWM3_TRIG_IN7   (201UL)
 
#define TRGM_TRGOCFG_CAN_PTPC0_CAP   (202UL)
 
#define TRGM_TRGOCFG_CAN_PTPC1_CAP   (203UL)
 
#define TRGM_TRGOCFG_UART_TRIG0   (204UL)
 
#define TRGM_TRGOCFG_UART_TRIG1   (205UL)
 
#define TRGM_TRGOCFG_SYNCTIMER_TRIG   (206UL)
 
#define TRGM_TRGOCFG_TRGM_IRQ0   (207UL)
 
#define TRGM_TRGOCFG_TRGM_IRQ1   (208UL)
 
#define TRGM_TRGOCFG_TRGM_DMA0   (209UL)
 
#define TRGM_TRGOCFG_TRGM_DMA1   (210UL)
 
#define TRGM_TRGOCFG_MTG0_TRIG_IN0   (211UL)
 
#define TRGM_TRGOCFG_MTG0_TRIG_IN1   (212UL)
 
#define TRGM_TRGOCFG_MTG0_TRIG_IN2   (213UL)
 
#define TRGM_TRGOCFG_MTG0_TRIG_IN3   (214UL)
 
#define TRGM_TRGOCFG_SYNT_TRIG_IN   (215UL)
 

Macro Definition Documentation

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_GET

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK   (0xFF0000UL)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SET

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT   (16U)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_GET

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK   (0xFF000000UL)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SET

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT   (24U)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_GET

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK   (0xFFU)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SET

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT   (0U)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_GET

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK   (0xFF00U)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SET

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT   (8U)

◆ TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_GET

#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK

#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK   (0xFF000000UL)

◆ TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SET

#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL1_CLC0_ID_ADC_SEL_SHIFT   (24U)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_GET

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK   (0xFFU)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SET

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC0_SEL_SHIFT   (0U)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_GET

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK   (0xFF00U)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SET

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC1_SEL_SHIFT   (8U)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_GET

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK   (0xFF0000UL)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SET

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL1_VSC0_ADC2_SEL_SHIFT   (16U)

◆ TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_GET

#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT)

◆ TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK

#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK   (0xFFU)

◆ TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SET

#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_MASK)

◆ TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT

#define TRGM_ADC_MATRIX_SEL2_CLC0_IQ_ADC_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_GET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_GET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_GET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_GET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SET

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_GET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_GET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_GET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_GET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SET

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_GET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_GET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_GET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_GET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SET

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_GET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_GET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_GET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_GET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SET

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT   (8U)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK   (0xFF0000UL)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT   (16U)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK   (0xFF000000UL)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT   (24U)

◆ TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK   (0xFFU)

◆ TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL7_DAC0_DAC_SEL_SHIFT   (0U)

◆ TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_GET

#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_GET (   x)    (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT)

◆ TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK

#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK   (0xFF00U)

◆ TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SET

#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SET (   x)    (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_MASK)

◆ TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT

#define TRGM_DAC_MATRIX_SEL7_DAC1_DAC_SEL_SHIFT   (8U)

◆ TRGM_DMACFG_0

#define TRGM_DMACFG_0   (0UL)

◆ TRGM_DMACFG_1

#define TRGM_DMACFG_1   (1UL)

◆ TRGM_DMACFG_2

#define TRGM_DMACFG_2   (2UL)

◆ TRGM_DMACFG_3

#define TRGM_DMACFG_3   (3UL)

◆ TRGM_DMACFG_4

#define TRGM_DMACFG_4   (4UL)

◆ TRGM_DMACFG_5

#define TRGM_DMACFG_5   (5UL)

◆ TRGM_DMACFG_6

#define TRGM_DMACFG_6   (6UL)

◆ TRGM_DMACFG_7

#define TRGM_DMACFG_7   (7UL)

◆ TRGM_DMACFG_DMAMUX_EN_GET

#define TRGM_DMACFG_DMAMUX_EN_GET (   x)    (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT)

◆ TRGM_DMACFG_DMAMUX_EN_MASK

#define TRGM_DMACFG_DMAMUX_EN_MASK   (0x80000000UL)

◆ TRGM_DMACFG_DMAMUX_EN_SET

#define TRGM_DMACFG_DMAMUX_EN_SET (   x)    (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK)

◆ TRGM_DMACFG_DMAMUX_EN_SHIFT

#define TRGM_DMACFG_DMAMUX_EN_SHIFT   (31U)

◆ TRGM_DMACFG_DMASRCSEL_GET

#define TRGM_DMACFG_DMASRCSEL_GET (   x)    (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT)

◆ TRGM_DMACFG_DMASRCSEL_MASK

#define TRGM_DMACFG_DMASRCSEL_MASK   (0x3FU)

◆ TRGM_DMACFG_DMASRCSEL_SET

#define TRGM_DMACFG_DMASRCSEL_SET (   x)    (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK)

◆ TRGM_DMACFG_DMASRCSEL_SHIFT

#define TRGM_DMACFG_DMASRCSEL_SHIFT   (0U)

◆ TRGM_FILTCFG_FILTLEN_BASE_GET

#define TRGM_FILTCFG_FILTLEN_BASE_GET (   x)    (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)

◆ TRGM_FILTCFG_FILTLEN_BASE_MASK

#define TRGM_FILTCFG_FILTLEN_BASE_MASK   (0x1FFU)

◆ TRGM_FILTCFG_FILTLEN_BASE_SET

#define TRGM_FILTCFG_FILTLEN_BASE_SET (   x)    (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK)

◆ TRGM_FILTCFG_FILTLEN_BASE_SHIFT

#define TRGM_FILTCFG_FILTLEN_BASE_SHIFT   (0U)

◆ TRGM_FILTCFG_FILTLEN_SHIFT_GET

#define TRGM_FILTCFG_FILTLEN_SHIFT_GET (   x)    (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT)

◆ TRGM_FILTCFG_FILTLEN_SHIFT_MASK

#define TRGM_FILTCFG_FILTLEN_SHIFT_MASK   (0xE00U)

◆ TRGM_FILTCFG_FILTLEN_SHIFT_SET

#define TRGM_FILTCFG_FILTLEN_SHIFT_SET (   x)    (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK)

◆ TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT

#define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT   (9U)

◆ TRGM_FILTCFG_MODE_GET

#define TRGM_FILTCFG_MODE_GET (   x)    (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT)

◆ TRGM_FILTCFG_MODE_MASK

#define TRGM_FILTCFG_MODE_MASK   (0xE000U)

◆ TRGM_FILTCFG_MODE_SET

#define TRGM_FILTCFG_MODE_SET (   x)    (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK)

◆ TRGM_FILTCFG_MODE_SHIFT

#define TRGM_FILTCFG_MODE_SHIFT   (13U)

◆ TRGM_FILTCFG_OUTINV_GET

#define TRGM_FILTCFG_OUTINV_GET (   x)    (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT)

◆ TRGM_FILTCFG_OUTINV_MASK

#define TRGM_FILTCFG_OUTINV_MASK   (0x10000UL)

◆ TRGM_FILTCFG_OUTINV_SET

#define TRGM_FILTCFG_OUTINV_SET (   x)    (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK)

◆ TRGM_FILTCFG_OUTINV_SHIFT

#define TRGM_FILTCFG_OUTINV_SHIFT   (16U)

◆ TRGM_FILTCFG_PWM0_IN0

#define TRGM_FILTCFG_PWM0_IN0   (0UL)

◆ TRGM_FILTCFG_PWM0_IN1

#define TRGM_FILTCFG_PWM0_IN1   (1UL)

◆ TRGM_FILTCFG_PWM0_IN2

#define TRGM_FILTCFG_PWM0_IN2   (2UL)

◆ TRGM_FILTCFG_PWM0_IN3

#define TRGM_FILTCFG_PWM0_IN3   (3UL)

◆ TRGM_FILTCFG_PWM0_IN4

#define TRGM_FILTCFG_PWM0_IN4   (4UL)

◆ TRGM_FILTCFG_PWM0_IN5

#define TRGM_FILTCFG_PWM0_IN5   (5UL)

◆ TRGM_FILTCFG_PWM0_IN6

#define TRGM_FILTCFG_PWM0_IN6   (6UL)

◆ TRGM_FILTCFG_PWM0_IN7

#define TRGM_FILTCFG_PWM0_IN7   (7UL)

◆ TRGM_FILTCFG_PWM1_IN0

#define TRGM_FILTCFG_PWM1_IN0   (8UL)

◆ TRGM_FILTCFG_PWM1_IN1

#define TRGM_FILTCFG_PWM1_IN1   (9UL)

◆ TRGM_FILTCFG_PWM1_IN2

#define TRGM_FILTCFG_PWM1_IN2   (10UL)

◆ TRGM_FILTCFG_PWM1_IN3

#define TRGM_FILTCFG_PWM1_IN3   (11UL)

◆ TRGM_FILTCFG_PWM1_IN4

#define TRGM_FILTCFG_PWM1_IN4   (12UL)

◆ TRGM_FILTCFG_PWM1_IN5

#define TRGM_FILTCFG_PWM1_IN5   (13UL)

◆ TRGM_FILTCFG_PWM1_IN6

#define TRGM_FILTCFG_PWM1_IN6   (14UL)

◆ TRGM_FILTCFG_PWM1_IN7

#define TRGM_FILTCFG_PWM1_IN7   (15UL)

◆ TRGM_FILTCFG_PWM2_IN0

#define TRGM_FILTCFG_PWM2_IN0   (16UL)

◆ TRGM_FILTCFG_PWM2_IN1

#define TRGM_FILTCFG_PWM2_IN1   (17UL)

◆ TRGM_FILTCFG_PWM2_IN2

#define TRGM_FILTCFG_PWM2_IN2   (18UL)

◆ TRGM_FILTCFG_PWM2_IN3

#define TRGM_FILTCFG_PWM2_IN3   (19UL)

◆ TRGM_FILTCFG_PWM2_IN4

#define TRGM_FILTCFG_PWM2_IN4   (20UL)

◆ TRGM_FILTCFG_PWM2_IN5

#define TRGM_FILTCFG_PWM2_IN5   (21UL)

◆ TRGM_FILTCFG_PWM2_IN6

#define TRGM_FILTCFG_PWM2_IN6   (22UL)

◆ TRGM_FILTCFG_PWM2_IN7

#define TRGM_FILTCFG_PWM2_IN7   (23UL)

◆ TRGM_FILTCFG_PWM3_IN0

#define TRGM_FILTCFG_PWM3_IN0   (24UL)

◆ TRGM_FILTCFG_PWM3_IN1

#define TRGM_FILTCFG_PWM3_IN1   (25UL)

◆ TRGM_FILTCFG_PWM3_IN2

#define TRGM_FILTCFG_PWM3_IN2   (26UL)

◆ TRGM_FILTCFG_PWM3_IN3

#define TRGM_FILTCFG_PWM3_IN3   (27UL)

◆ TRGM_FILTCFG_PWM3_IN4

#define TRGM_FILTCFG_PWM3_IN4   (28UL)

◆ TRGM_FILTCFG_PWM3_IN5

#define TRGM_FILTCFG_PWM3_IN5   (29UL)

◆ TRGM_FILTCFG_PWM3_IN6

#define TRGM_FILTCFG_PWM3_IN6   (30UL)

◆ TRGM_FILTCFG_PWM3_IN7

#define TRGM_FILTCFG_PWM3_IN7   (31UL)

◆ TRGM_FILTCFG_SYNCEN_GET

#define TRGM_FILTCFG_SYNCEN_GET (   x)    (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT)

◆ TRGM_FILTCFG_SYNCEN_MASK

#define TRGM_FILTCFG_SYNCEN_MASK   (0x1000U)

◆ TRGM_FILTCFG_SYNCEN_SET

#define TRGM_FILTCFG_SYNCEN_SET (   x)    (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK)

◆ TRGM_FILTCFG_SYNCEN_SHIFT

#define TRGM_FILTCFG_SYNCEN_SHIFT   (12U)

◆ TRGM_FILTCFG_TRGM_P_00

#define TRGM_FILTCFG_TRGM_P_00   (32UL)

◆ TRGM_FILTCFG_TRGM_P_01

#define TRGM_FILTCFG_TRGM_P_01   (33UL)

◆ TRGM_FILTCFG_TRGM_P_02

#define TRGM_FILTCFG_TRGM_P_02   (34UL)

◆ TRGM_FILTCFG_TRGM_P_03

#define TRGM_FILTCFG_TRGM_P_03   (35UL)

◆ TRGM_FILTCFG_TRGM_P_04

#define TRGM_FILTCFG_TRGM_P_04   (36UL)

◆ TRGM_FILTCFG_TRGM_P_05

#define TRGM_FILTCFG_TRGM_P_05   (37UL)

◆ TRGM_FILTCFG_TRGM_P_06

#define TRGM_FILTCFG_TRGM_P_06   (38UL)

◆ TRGM_FILTCFG_TRGM_P_07

#define TRGM_FILTCFG_TRGM_P_07   (39UL)

◆ TRGM_FILTCFG_TRGM_P_08

#define TRGM_FILTCFG_TRGM_P_08   (40UL)

◆ TRGM_FILTCFG_TRGM_P_09

#define TRGM_FILTCFG_TRGM_P_09   (41UL)

◆ TRGM_FILTCFG_TRGM_P_10

#define TRGM_FILTCFG_TRGM_P_10   (42UL)

◆ TRGM_FILTCFG_TRGM_P_11

#define TRGM_FILTCFG_TRGM_P_11   (43UL)

◆ TRGM_FILTCFG_TRGM_P_12

#define TRGM_FILTCFG_TRGM_P_12   (44UL)

◆ TRGM_FILTCFG_TRGM_P_13

#define TRGM_FILTCFG_TRGM_P_13   (45UL)

◆ TRGM_FILTCFG_TRGM_P_14

#define TRGM_FILTCFG_TRGM_P_14   (46UL)

◆ TRGM_FILTCFG_TRGM_P_15

#define TRGM_FILTCFG_TRGM_P_15   (47UL)

◆ TRGM_FILTCFG_TRGM_P_16

#define TRGM_FILTCFG_TRGM_P_16   (48UL)

◆ TRGM_FILTCFG_TRGM_P_17

#define TRGM_FILTCFG_TRGM_P_17   (49UL)

◆ TRGM_FILTCFG_TRGM_P_18

#define TRGM_FILTCFG_TRGM_P_18   (50UL)

◆ TRGM_FILTCFG_TRGM_P_19

#define TRGM_FILTCFG_TRGM_P_19   (51UL)

◆ TRGM_FILTCFG_TRGM_P_20

#define TRGM_FILTCFG_TRGM_P_20   (52UL)

◆ TRGM_FILTCFG_TRGM_P_21

#define TRGM_FILTCFG_TRGM_P_21   (53UL)

◆ TRGM_FILTCFG_TRGM_P_22

#define TRGM_FILTCFG_TRGM_P_22   (54UL)

◆ TRGM_FILTCFG_TRGM_P_23

#define TRGM_FILTCFG_TRGM_P_23   (55UL)

◆ TRGM_FILTCFG_TRGM_P_24

#define TRGM_FILTCFG_TRGM_P_24   (56UL)

◆ TRGM_FILTCFG_TRGM_P_25

#define TRGM_FILTCFG_TRGM_P_25   (57UL)

◆ TRGM_FILTCFG_TRGM_P_26

#define TRGM_FILTCFG_TRGM_P_26   (58UL)

◆ TRGM_FILTCFG_TRGM_P_27

#define TRGM_FILTCFG_TRGM_P_27   (59UL)

◆ TRGM_FILTCFG_TRGM_P_28

#define TRGM_FILTCFG_TRGM_P_28   (60UL)

◆ TRGM_FILTCFG_TRGM_P_29

#define TRGM_FILTCFG_TRGM_P_29   (61UL)

◆ TRGM_FILTCFG_TRGM_P_30

#define TRGM_FILTCFG_TRGM_P_30   (62UL)

◆ TRGM_FILTCFG_TRGM_P_31

#define TRGM_FILTCFG_TRGM_P_31   (63UL)

◆ TRGM_GCR_TRGOPEN_GET

#define TRGM_GCR_TRGOPEN_GET (   x)    (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT)

◆ TRGM_GCR_TRGOPEN_MASK

#define TRGM_GCR_TRGOPEN_MASK   (0xFFFFFFFFUL)

◆ TRGM_GCR_TRGOPEN_SET

#define TRGM_GCR_TRGOPEN_SET (   x)    (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK)

◆ TRGM_GCR_TRGOPEN_SHIFT

#define TRGM_GCR_TRGOPEN_SHIFT   (0U)

◆ TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_GET

#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_GET (   x)    (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT)

◆ TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK

#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK   (0xFF0000UL)

◆ TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SET

#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SET (   x)    (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_MASK)

◆ TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT

#define TRGM_POS_MATRIX_SEL0_MTG0_POS_SEL_SHIFT   (16U)

◆ TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_GET

#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_GET (   x)    (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT)

◆ TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK

#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK   (0xFF000000UL)

◆ TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SET

#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SET (   x)    (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_MASK)

◆ TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT

#define TRGM_POS_MATRIX_SEL0_QEO0_POS_SEL_SHIFT   (24U)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET (   x)    (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK   (0xFFU)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET (   x)    (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT   (0U)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET (   x)    (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK   (0xFF00U)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET (   x)    (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK)

◆ TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT

#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT   (8U)

◆ TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET

#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET (   x)    (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT)

◆ TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK

#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK   (0xFFU)

◆ TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET

#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET (   x)    (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK)

◆ TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT

#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT   (0U)

◆ TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_GET

#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_GET (   x)    (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT)

◆ TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK

#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK   (0xFF00U)

◆ TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SET

#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SET (   x)    (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_MASK)

◆ TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT

#define TRGM_POS_MATRIX_SEL1_VSC0_POS_SEL_SHIFT   (8U)

◆ TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_GET

#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_GET (   x)    (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT)

◆ TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK

#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK   (0x80U)

◆ TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SET

#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SET (   x)    (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK)

◆ TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT

#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT   (7U)

◆ TRGM_PWM_CALIB_CFG_CALIB_SW_START_GET

#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_GET (   x)    (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT)

◆ TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK

#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK   (0x8000U)

◆ TRGM_PWM_CALIB_CFG_CALIB_SW_START_SET

#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SET (   x)    (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK)

◆ TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT

#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT   (15U)

◆ TRGM_PWM_CALIB_STATUS0_CALIB_ON_GET

#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_GET (   x)    (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK) >> TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT)

◆ TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK

#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK   (0x80000000UL)

◆ TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT

#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT   (31U)

◆ TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_GET

#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_GET (   x)    (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_MASK) >> TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_SHIFT)

◆ TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_MASK

#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_MASK   (0x3F00U)

◆ TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_SHIFT

#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_N_SHIFT   (8U)

◆ TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_GET

#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_GET (   x)    (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_MASK) >> TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_SHIFT)

◆ TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_MASK

#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_MASK   (0x3FU)

◆ TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_SHIFT

#define TRGM_PWM_CALIB_STATUS1_CALIB_RESULT_P_SHIFT   (0U)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_GET

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_GET (   x)    (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK   (0x3F00U)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SET

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SET (   x)    (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_MASK)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_N_SW_SHIFT   (8U)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_GET

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_GET (   x)    (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK   (0x3FU)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SET

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SET (   x)    (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_MASK)

◆ TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT

#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_P_SW_SHIFT   (0U)

◆ TRGM_TRGM_IN_0

#define TRGM_TRGM_IN_0   (0UL)

◆ TRGM_TRGM_IN_1

#define TRGM_TRGM_IN_1   (1UL)

◆ TRGM_TRGM_IN_2

#define TRGM_TRGM_IN_2   (2UL)

◆ TRGM_TRGM_IN_3

#define TRGM_TRGM_IN_3   (3UL)

◆ TRGM_TRGM_IN_4

#define TRGM_TRGM_IN_4   (4UL)

◆ TRGM_TRGM_IN_5

#define TRGM_TRGM_IN_5   (5UL)

◆ TRGM_TRGM_IN_6

#define TRGM_TRGM_IN_6   (6UL)

◆ TRGM_TRGM_IN_TRGM_IN_GET

#define TRGM_TRGM_IN_TRGM_IN_GET (   x)    (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT)

◆ TRGM_TRGM_IN_TRGM_IN_MASK

#define TRGM_TRGM_IN_TRGM_IN_MASK   (0xFFFFFFFFUL)

◆ TRGM_TRGM_IN_TRGM_IN_SHIFT

#define TRGM_TRGM_IN_TRGM_IN_SHIFT   (0U)

◆ TRGM_TRGM_OUT_0

#define TRGM_TRGM_OUT_0   (0UL)

◆ TRGM_TRGM_OUT_1

#define TRGM_TRGM_OUT_1   (1UL)

◆ TRGM_TRGM_OUT_2

#define TRGM_TRGM_OUT_2   (2UL)

◆ TRGM_TRGM_OUT_3

#define TRGM_TRGM_OUT_3   (3UL)

◆ TRGM_TRGM_OUT_4

#define TRGM_TRGM_OUT_4   (4UL)

◆ TRGM_TRGM_OUT_5

#define TRGM_TRGM_OUT_5   (5UL)

◆ TRGM_TRGM_OUT_6

#define TRGM_TRGM_OUT_6   (6UL)

◆ TRGM_TRGM_OUT_TRGM_OUT_GET

#define TRGM_TRGM_OUT_TRGM_OUT_GET (   x)    (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT)

◆ TRGM_TRGM_OUT_TRGM_OUT_MASK

#define TRGM_TRGM_OUT_TRGM_OUT_MASK   (0xFFFFFFFFUL)

◆ TRGM_TRGM_OUT_TRGM_OUT_SHIFT

#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT   (0U)

◆ TRGM_TRGOCFG_ACMP0_CH0_WIN

#define TRGM_TRGOCFG_ACMP0_CH0_WIN   (84UL)

◆ TRGM_TRGOCFG_ACMP0_CH1_WIN

#define TRGM_TRGOCFG_ACMP0_CH1_WIN   (85UL)

◆ TRGM_TRGOCFG_ACMP1_CH0_WIN

#define TRGM_TRGOCFG_ACMP1_CH0_WIN   (86UL)

◆ TRGM_TRGOCFG_ACMP1_CH1_WIN

#define TRGM_TRGOCFG_ACMP1_CH1_WIN   (87UL)

◆ TRGM_TRGOCFG_ACMP2_CH0_WIN

#define TRGM_TRGOCFG_ACMP2_CH0_WIN   (88UL)

◆ TRGM_TRGOCFG_ACMP2_CH1_WIN

#define TRGM_TRGOCFG_ACMP2_CH1_WIN   (89UL)

◆ TRGM_TRGOCFG_ACMP3_CH0_WIN

#define TRGM_TRGOCFG_ACMP3_CH0_WIN   (90UL)

◆ TRGM_TRGOCFG_ACMP3_CH1_WIN

#define TRGM_TRGOCFG_ACMP3_CH1_WIN   (91UL)

◆ TRGM_TRGOCFG_ADC0_STRGI

#define TRGM_TRGOCFG_ADC0_STRGI   (48UL)

◆ TRGM_TRGOCFG_ADC1_STRGI

#define TRGM_TRGOCFG_ADC1_STRGI   (49UL)

◆ TRGM_TRGOCFG_ADC2_STRGI

#define TRGM_TRGOCFG_ADC2_STRGI   (50UL)

◆ TRGM_TRGOCFG_ADC3_STRGI

#define TRGM_TRGOCFG_ADC3_STRGI   (51UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI0A

#define TRGM_TRGOCFG_ADCX_PTRGI0A   (52UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI0B

#define TRGM_TRGOCFG_ADCX_PTRGI0B   (53UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI0C

#define TRGM_TRGOCFG_ADCX_PTRGI0C   (54UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI1A

#define TRGM_TRGOCFG_ADCX_PTRGI1A   (55UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI1B

#define TRGM_TRGOCFG_ADCX_PTRGI1B   (56UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI1C

#define TRGM_TRGOCFG_ADCX_PTRGI1C   (57UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI2A

#define TRGM_TRGOCFG_ADCX_PTRGI2A   (58UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI2B

#define TRGM_TRGOCFG_ADCX_PTRGI2B   (59UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI2C

#define TRGM_TRGOCFG_ADCX_PTRGI2C   (60UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI3A

#define TRGM_TRGOCFG_ADCX_PTRGI3A   (61UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI3B

#define TRGM_TRGOCFG_ADCX_PTRGI3B   (62UL)

◆ TRGM_TRGOCFG_ADCX_PTRGI3C

#define TRGM_TRGOCFG_ADCX_PTRGI3C   (63UL)

◆ TRGM_TRGOCFG_CAN_PTPC0_CAP

#define TRGM_TRGOCFG_CAN_PTPC0_CAP   (202UL)

◆ TRGM_TRGOCFG_CAN_PTPC1_CAP

#define TRGM_TRGOCFG_CAN_PTPC1_CAP   (203UL)

◆ TRGM_TRGOCFG_DAC0_BUFTRG

#define TRGM_TRGOCFG_DAC0_BUFTRG   (92UL)

◆ TRGM_TRGOCFG_DAC1_BUFTRG

#define TRGM_TRGOCFG_DAC1_BUFTRG   (93UL)

◆ TRGM_TRGOCFG_FEDG2PEN_GET

#define TRGM_TRGOCFG_FEDG2PEN_GET (   x)    (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT)

◆ TRGM_TRGOCFG_FEDG2PEN_MASK

#define TRGM_TRGOCFG_FEDG2PEN_MASK   (0x20000UL)

◆ TRGM_TRGOCFG_FEDG2PEN_SET

#define TRGM_TRGOCFG_FEDG2PEN_SET (   x)    (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK)

◆ TRGM_TRGOCFG_FEDG2PEN_SHIFT

#define TRGM_TRGOCFG_FEDG2PEN_SHIFT   (17U)

◆ TRGM_TRGOCFG_GPTMR0_IN2

#define TRGM_TRGOCFG_GPTMR0_IN2   (94UL)

◆ TRGM_TRGOCFG_GPTMR0_IN3

#define TRGM_TRGOCFG_GPTMR0_IN3   (95UL)

◆ TRGM_TRGOCFG_GPTMR0_SYNCI

#define TRGM_TRGOCFG_GPTMR0_SYNCI   (96UL)

◆ TRGM_TRGOCFG_GPTMR1_IN2

#define TRGM_TRGOCFG_GPTMR1_IN2   (97UL)

◆ TRGM_TRGOCFG_GPTMR1_IN3

#define TRGM_TRGOCFG_GPTMR1_IN3   (98UL)

◆ TRGM_TRGOCFG_GPTMR1_SYNCI

#define TRGM_TRGOCFG_GPTMR1_SYNCI   (99UL)

◆ TRGM_TRGOCFG_GPTMR2_IN2

#define TRGM_TRGOCFG_GPTMR2_IN2   (100UL)

◆ TRGM_TRGOCFG_GPTMR2_IN3

#define TRGM_TRGOCFG_GPTMR2_IN3   (101UL)

◆ TRGM_TRGOCFG_GPTMR2_SYNCI

#define TRGM_TRGOCFG_GPTMR2_SYNCI   (102UL)

◆ TRGM_TRGOCFG_GPTMR3_IN2

#define TRGM_TRGOCFG_GPTMR3_IN2   (103UL)

◆ TRGM_TRGOCFG_GPTMR3_IN3

#define TRGM_TRGOCFG_GPTMR3_IN3   (104UL)

◆ TRGM_TRGOCFG_GPTMR3_SYNCI

#define TRGM_TRGOCFG_GPTMR3_SYNCI   (105UL)

◆ TRGM_TRGOCFG_MTG0_TRIG_IN0

#define TRGM_TRGOCFG_MTG0_TRIG_IN0   (211UL)

◆ TRGM_TRGOCFG_MTG0_TRIG_IN1

#define TRGM_TRGOCFG_MTG0_TRIG_IN1   (212UL)

◆ TRGM_TRGOCFG_MTG0_TRIG_IN2

#define TRGM_TRGOCFG_MTG0_TRIG_IN2   (213UL)

◆ TRGM_TRGOCFG_MTG0_TRIG_IN3

#define TRGM_TRGOCFG_MTG0_TRIG_IN3   (214UL)

◆ TRGM_TRGOCFG_OUTINV_GET

#define TRGM_TRGOCFG_OUTINV_GET (   x)    (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT)

◆ TRGM_TRGOCFG_OUTINV_MASK

#define TRGM_TRGOCFG_OUTINV_MASK   (0x40000UL)

◆ TRGM_TRGOCFG_OUTINV_SET

#define TRGM_TRGOCFG_OUTINV_SET (   x)    (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK)

◆ TRGM_TRGOCFG_OUTINV_SHIFT

#define TRGM_TRGOCFG_OUTINV_SHIFT   (18U)

◆ TRGM_TRGOCFG_PLB_IN_00

#define TRGM_TRGOCFG_PLB_IN_00   (106UL)

◆ TRGM_TRGOCFG_PLB_IN_01

#define TRGM_TRGOCFG_PLB_IN_01   (107UL)

◆ TRGM_TRGOCFG_PLB_IN_02

#define TRGM_TRGOCFG_PLB_IN_02   (108UL)

◆ TRGM_TRGOCFG_PLB_IN_03

#define TRGM_TRGOCFG_PLB_IN_03   (109UL)

◆ TRGM_TRGOCFG_PLB_IN_04

#define TRGM_TRGOCFG_PLB_IN_04   (110UL)

◆ TRGM_TRGOCFG_PLB_IN_05

#define TRGM_TRGOCFG_PLB_IN_05   (111UL)

◆ TRGM_TRGOCFG_PLB_IN_06

#define TRGM_TRGOCFG_PLB_IN_06   (112UL)

◆ TRGM_TRGOCFG_PLB_IN_07

#define TRGM_TRGOCFG_PLB_IN_07   (113UL)

◆ TRGM_TRGOCFG_PLB_IN_08

#define TRGM_TRGOCFG_PLB_IN_08   (114UL)

◆ TRGM_TRGOCFG_PLB_IN_09

#define TRGM_TRGOCFG_PLB_IN_09   (115UL)

◆ TRGM_TRGOCFG_PLB_IN_10

#define TRGM_TRGOCFG_PLB_IN_10   (116UL)

◆ TRGM_TRGOCFG_PLB_IN_11

#define TRGM_TRGOCFG_PLB_IN_11   (117UL)

◆ TRGM_TRGOCFG_PLB_IN_12

#define TRGM_TRGOCFG_PLB_IN_12   (118UL)

◆ TRGM_TRGOCFG_PLB_IN_13

#define TRGM_TRGOCFG_PLB_IN_13   (119UL)

◆ TRGM_TRGOCFG_PLB_IN_14

#define TRGM_TRGOCFG_PLB_IN_14   (120UL)

◆ TRGM_TRGOCFG_PLB_IN_15

#define TRGM_TRGOCFG_PLB_IN_15   (121UL)

◆ TRGM_TRGOCFG_PLB_IN_16

#define TRGM_TRGOCFG_PLB_IN_16   (122UL)

◆ TRGM_TRGOCFG_PLB_IN_17

#define TRGM_TRGOCFG_PLB_IN_17   (123UL)

◆ TRGM_TRGOCFG_PLB_IN_18

#define TRGM_TRGOCFG_PLB_IN_18   (124UL)

◆ TRGM_TRGOCFG_PLB_IN_19

#define TRGM_TRGOCFG_PLB_IN_19   (125UL)

◆ TRGM_TRGOCFG_PLB_IN_20

#define TRGM_TRGOCFG_PLB_IN_20   (126UL)

◆ TRGM_TRGOCFG_PLB_IN_21

#define TRGM_TRGOCFG_PLB_IN_21   (127UL)

◆ TRGM_TRGOCFG_PLB_IN_22

#define TRGM_TRGOCFG_PLB_IN_22   (128UL)

◆ TRGM_TRGOCFG_PLB_IN_23

#define TRGM_TRGOCFG_PLB_IN_23   (129UL)

◆ TRGM_TRGOCFG_PLB_IN_24

#define TRGM_TRGOCFG_PLB_IN_24   (130UL)

◆ TRGM_TRGOCFG_PLB_IN_25

#define TRGM_TRGOCFG_PLB_IN_25   (131UL)

◆ TRGM_TRGOCFG_PLB_IN_26

#define TRGM_TRGOCFG_PLB_IN_26   (132UL)

◆ TRGM_TRGOCFG_PLB_IN_27

#define TRGM_TRGOCFG_PLB_IN_27   (133UL)

◆ TRGM_TRGOCFG_PLB_IN_28

#define TRGM_TRGOCFG_PLB_IN_28   (134UL)

◆ TRGM_TRGOCFG_PLB_IN_29

#define TRGM_TRGOCFG_PLB_IN_29   (135UL)

◆ TRGM_TRGOCFG_PLB_IN_30

#define TRGM_TRGOCFG_PLB_IN_30   (136UL)

◆ TRGM_TRGOCFG_PLB_IN_31

#define TRGM_TRGOCFG_PLB_IN_31   (137UL)

◆ TRGM_TRGOCFG_PLB_IN_32

#define TRGM_TRGOCFG_PLB_IN_32   (138UL)

◆ TRGM_TRGOCFG_PLB_IN_33

#define TRGM_TRGOCFG_PLB_IN_33   (139UL)

◆ TRGM_TRGOCFG_PLB_IN_34

#define TRGM_TRGOCFG_PLB_IN_34   (140UL)

◆ TRGM_TRGOCFG_PLB_IN_35

#define TRGM_TRGOCFG_PLB_IN_35   (141UL)

◆ TRGM_TRGOCFG_PLB_IN_36

#define TRGM_TRGOCFG_PLB_IN_36   (142UL)

◆ TRGM_TRGOCFG_PLB_IN_37

#define TRGM_TRGOCFG_PLB_IN_37   (143UL)

◆ TRGM_TRGOCFG_PLB_IN_38

#define TRGM_TRGOCFG_PLB_IN_38   (144UL)

◆ TRGM_TRGOCFG_PLB_IN_39

#define TRGM_TRGOCFG_PLB_IN_39   (145UL)

◆ TRGM_TRGOCFG_PLB_IN_40

#define TRGM_TRGOCFG_PLB_IN_40   (146UL)

◆ TRGM_TRGOCFG_PLB_IN_41

#define TRGM_TRGOCFG_PLB_IN_41   (147UL)

◆ TRGM_TRGOCFG_PLB_IN_42

#define TRGM_TRGOCFG_PLB_IN_42   (148UL)

◆ TRGM_TRGOCFG_PLB_IN_43

#define TRGM_TRGOCFG_PLB_IN_43   (149UL)

◆ TRGM_TRGOCFG_PLB_IN_44

#define TRGM_TRGOCFG_PLB_IN_44   (150UL)

◆ TRGM_TRGOCFG_PLB_IN_45

#define TRGM_TRGOCFG_PLB_IN_45   (151UL)

◆ TRGM_TRGOCFG_PLB_IN_46

#define TRGM_TRGOCFG_PLB_IN_46   (152UL)

◆ TRGM_TRGOCFG_PLB_IN_47

#define TRGM_TRGOCFG_PLB_IN_47   (153UL)

◆ TRGM_TRGOCFG_PLB_IN_48

#define TRGM_TRGOCFG_PLB_IN_48   (154UL)

◆ TRGM_TRGOCFG_PLB_IN_49

#define TRGM_TRGOCFG_PLB_IN_49   (155UL)

◆ TRGM_TRGOCFG_PLB_IN_50

#define TRGM_TRGOCFG_PLB_IN_50   (156UL)

◆ TRGM_TRGOCFG_PLB_IN_51

#define TRGM_TRGOCFG_PLB_IN_51   (157UL)

◆ TRGM_TRGOCFG_PLB_IN_52

#define TRGM_TRGOCFG_PLB_IN_52   (158UL)

◆ TRGM_TRGOCFG_PLB_IN_53

#define TRGM_TRGOCFG_PLB_IN_53   (159UL)

◆ TRGM_TRGOCFG_PLB_IN_54

#define TRGM_TRGOCFG_PLB_IN_54   (160UL)

◆ TRGM_TRGOCFG_PLB_IN_55

#define TRGM_TRGOCFG_PLB_IN_55   (161UL)

◆ TRGM_TRGOCFG_PLB_IN_56

#define TRGM_TRGOCFG_PLB_IN_56   (162UL)

◆ TRGM_TRGOCFG_PLB_IN_57

#define TRGM_TRGOCFG_PLB_IN_57   (163UL)

◆ TRGM_TRGOCFG_PLB_IN_58

#define TRGM_TRGOCFG_PLB_IN_58   (164UL)

◆ TRGM_TRGOCFG_PLB_IN_59

#define TRGM_TRGOCFG_PLB_IN_59   (165UL)

◆ TRGM_TRGOCFG_PLB_IN_60

#define TRGM_TRGOCFG_PLB_IN_60   (166UL)

◆ TRGM_TRGOCFG_PLB_IN_61

#define TRGM_TRGOCFG_PLB_IN_61   (167UL)

◆ TRGM_TRGOCFG_PLB_IN_62

#define TRGM_TRGOCFG_PLB_IN_62   (168UL)

◆ TRGM_TRGOCFG_PLB_IN_63

#define TRGM_TRGOCFG_PLB_IN_63   (169UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN0

#define TRGM_TRGOCFG_PWM0_TRIG_IN0   (170UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN1

#define TRGM_TRGOCFG_PWM0_TRIG_IN1   (171UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN2

#define TRGM_TRGOCFG_PWM0_TRIG_IN2   (172UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN3

#define TRGM_TRGOCFG_PWM0_TRIG_IN3   (173UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN4

#define TRGM_TRGOCFG_PWM0_TRIG_IN4   (174UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN5

#define TRGM_TRGOCFG_PWM0_TRIG_IN5   (175UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN6

#define TRGM_TRGOCFG_PWM0_TRIG_IN6   (176UL)

◆ TRGM_TRGOCFG_PWM0_TRIG_IN7

#define TRGM_TRGOCFG_PWM0_TRIG_IN7   (177UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN0

#define TRGM_TRGOCFG_PWM1_TRIG_IN0   (178UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN1

#define TRGM_TRGOCFG_PWM1_TRIG_IN1   (179UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN2

#define TRGM_TRGOCFG_PWM1_TRIG_IN2   (180UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN3

#define TRGM_TRGOCFG_PWM1_TRIG_IN3   (181UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN4

#define TRGM_TRGOCFG_PWM1_TRIG_IN4   (182UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN5

#define TRGM_TRGOCFG_PWM1_TRIG_IN5   (183UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN6

#define TRGM_TRGOCFG_PWM1_TRIG_IN6   (184UL)

◆ TRGM_TRGOCFG_PWM1_TRIG_IN7

#define TRGM_TRGOCFG_PWM1_TRIG_IN7   (185UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN0

#define TRGM_TRGOCFG_PWM2_TRIG_IN0   (186UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN1

#define TRGM_TRGOCFG_PWM2_TRIG_IN1   (187UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN2

#define TRGM_TRGOCFG_PWM2_TRIG_IN2   (188UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN3

#define TRGM_TRGOCFG_PWM2_TRIG_IN3   (189UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN4

#define TRGM_TRGOCFG_PWM2_TRIG_IN4   (190UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN5

#define TRGM_TRGOCFG_PWM2_TRIG_IN5   (191UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN6

#define TRGM_TRGOCFG_PWM2_TRIG_IN6   (192UL)

◆ TRGM_TRGOCFG_PWM2_TRIG_IN7

#define TRGM_TRGOCFG_PWM2_TRIG_IN7   (193UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN0

#define TRGM_TRGOCFG_PWM3_TRIG_IN0   (194UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN1

#define TRGM_TRGOCFG_PWM3_TRIG_IN1   (195UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN2

#define TRGM_TRGOCFG_PWM3_TRIG_IN2   (196UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN3

#define TRGM_TRGOCFG_PWM3_TRIG_IN3   (197UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN4

#define TRGM_TRGOCFG_PWM3_TRIG_IN4   (198UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN5

#define TRGM_TRGOCFG_PWM3_TRIG_IN5   (199UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN6

#define TRGM_TRGOCFG_PWM3_TRIG_IN6   (200UL)

◆ TRGM_TRGOCFG_PWM3_TRIG_IN7

#define TRGM_TRGOCFG_PWM3_TRIG_IN7   (201UL)

◆ TRGM_TRGOCFG_QEI0_PAUSE

#define TRGM_TRGOCFG_QEI0_PAUSE   (70UL)

◆ TRGM_TRGOCFG_QEI0_TRIG_IN

#define TRGM_TRGOCFG_QEI0_TRIG_IN   (68UL)

◆ TRGM_TRGOCFG_QEI1_PAUSE

#define TRGM_TRGOCFG_QEI1_PAUSE   (71UL)

◆ TRGM_TRGOCFG_QEI1_TRIG_IN

#define TRGM_TRGOCFG_QEI1_TRIG_IN   (69UL)

◆ TRGM_TRGOCFG_QEO0_TRIG_IN0

#define TRGM_TRGOCFG_QEO0_TRIG_IN0   (72UL)

◆ TRGM_TRGOCFG_QEO0_TRIG_IN1

#define TRGM_TRGOCFG_QEO0_TRIG_IN1   (73UL)

◆ TRGM_TRGOCFG_QEO1_TRIG_IN0

#define TRGM_TRGOCFG_QEO1_TRIG_IN0   (74UL)

◆ TRGM_TRGOCFG_QEO1_TRIG_IN1

#define TRGM_TRGOCFG_QEO1_TRIG_IN1   (75UL)

◆ TRGM_TRGOCFG_RDC0_TRIG_IN0

#define TRGM_TRGOCFG_RDC0_TRIG_IN0   (66UL)

◆ TRGM_TRGOCFG_RDC0_TRIG_IN1

#define TRGM_TRGOCFG_RDC0_TRIG_IN1   (67UL)

◆ TRGM_TRGOCFG_REDG2PEN_GET

#define TRGM_TRGOCFG_REDG2PEN_GET (   x)    (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT)

◆ TRGM_TRGOCFG_REDG2PEN_MASK

#define TRGM_TRGOCFG_REDG2PEN_MASK   (0x10000UL)

◆ TRGM_TRGOCFG_REDG2PEN_SET

#define TRGM_TRGOCFG_REDG2PEN_SET (   x)    (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK)

◆ TRGM_TRGOCFG_REDG2PEN_SHIFT

#define TRGM_TRGOCFG_REDG2PEN_SHIFT   (16U)

◆ TRGM_TRGOCFG_SDM_PWM_SOC0

#define TRGM_TRGOCFG_SDM_PWM_SOC0   (32UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC1

#define TRGM_TRGOCFG_SDM_PWM_SOC1   (33UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC10

#define TRGM_TRGOCFG_SDM_PWM_SOC10   (42UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC11

#define TRGM_TRGOCFG_SDM_PWM_SOC11   (43UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC12

#define TRGM_TRGOCFG_SDM_PWM_SOC12   (44UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC13

#define TRGM_TRGOCFG_SDM_PWM_SOC13   (45UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC14

#define TRGM_TRGOCFG_SDM_PWM_SOC14   (46UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC15

#define TRGM_TRGOCFG_SDM_PWM_SOC15   (47UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC2

#define TRGM_TRGOCFG_SDM_PWM_SOC2   (34UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC3

#define TRGM_TRGOCFG_SDM_PWM_SOC3   (35UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC4

#define TRGM_TRGOCFG_SDM_PWM_SOC4   (36UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC5

#define TRGM_TRGOCFG_SDM_PWM_SOC5   (37UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC6

#define TRGM_TRGOCFG_SDM_PWM_SOC6   (38UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC7

#define TRGM_TRGOCFG_SDM_PWM_SOC7   (39UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC8

#define TRGM_TRGOCFG_SDM_PWM_SOC8   (40UL)

◆ TRGM_TRGOCFG_SDM_PWM_SOC9

#define TRGM_TRGOCFG_SDM_PWM_SOC9   (41UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN0

#define TRGM_TRGOCFG_SEI_TRIG_IN0   (76UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN1

#define TRGM_TRGOCFG_SEI_TRIG_IN1   (77UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN2

#define TRGM_TRGOCFG_SEI_TRIG_IN2   (78UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN3

#define TRGM_TRGOCFG_SEI_TRIG_IN3   (79UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN4

#define TRGM_TRGOCFG_SEI_TRIG_IN4   (80UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN5

#define TRGM_TRGOCFG_SEI_TRIG_IN5   (81UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN6

#define TRGM_TRGOCFG_SEI_TRIG_IN6   (82UL)

◆ TRGM_TRGOCFG_SEI_TRIG_IN7

#define TRGM_TRGOCFG_SEI_TRIG_IN7   (83UL)

◆ TRGM_TRGOCFG_SYNCTIMER_TRIG

#define TRGM_TRGOCFG_SYNCTIMER_TRIG   (206UL)

◆ TRGM_TRGOCFG_SYNT_TRIG_IN

#define TRGM_TRGOCFG_SYNT_TRIG_IN   (215UL)

◆ TRGM_TRGOCFG_TRGM_DMA0

#define TRGM_TRGOCFG_TRGM_DMA0   (209UL)

◆ TRGM_TRGOCFG_TRGM_DMA1

#define TRGM_TRGOCFG_TRGM_DMA1   (210UL)

◆ TRGM_TRGOCFG_TRGM_IRQ0

#define TRGM_TRGOCFG_TRGM_IRQ0   (207UL)

◆ TRGM_TRGOCFG_TRGM_IRQ1

#define TRGM_TRGOCFG_TRGM_IRQ1   (208UL)

◆ TRGM_TRGOCFG_TRGM_P_00

#define TRGM_TRGOCFG_TRGM_P_00   (0UL)

◆ TRGM_TRGOCFG_TRGM_P_01

#define TRGM_TRGOCFG_TRGM_P_01   (1UL)

◆ TRGM_TRGOCFG_TRGM_P_02

#define TRGM_TRGOCFG_TRGM_P_02   (2UL)

◆ TRGM_TRGOCFG_TRGM_P_03

#define TRGM_TRGOCFG_TRGM_P_03   (3UL)

◆ TRGM_TRGOCFG_TRGM_P_04

#define TRGM_TRGOCFG_TRGM_P_04   (4UL)

◆ TRGM_TRGOCFG_TRGM_P_05

#define TRGM_TRGOCFG_TRGM_P_05   (5UL)

◆ TRGM_TRGOCFG_TRGM_P_06

#define TRGM_TRGOCFG_TRGM_P_06   (6UL)

◆ TRGM_TRGOCFG_TRGM_P_07

#define TRGM_TRGOCFG_TRGM_P_07   (7UL)

◆ TRGM_TRGOCFG_TRGM_P_08

#define TRGM_TRGOCFG_TRGM_P_08   (8UL)

◆ TRGM_TRGOCFG_TRGM_P_09

#define TRGM_TRGOCFG_TRGM_P_09   (9UL)

◆ TRGM_TRGOCFG_TRGM_P_10

#define TRGM_TRGOCFG_TRGM_P_10   (10UL)

◆ TRGM_TRGOCFG_TRGM_P_11

#define TRGM_TRGOCFG_TRGM_P_11   (11UL)

◆ TRGM_TRGOCFG_TRGM_P_12

#define TRGM_TRGOCFG_TRGM_P_12   (12UL)

◆ TRGM_TRGOCFG_TRGM_P_13

#define TRGM_TRGOCFG_TRGM_P_13   (13UL)

◆ TRGM_TRGOCFG_TRGM_P_14

#define TRGM_TRGOCFG_TRGM_P_14   (14UL)

◆ TRGM_TRGOCFG_TRGM_P_15

#define TRGM_TRGOCFG_TRGM_P_15   (15UL)

◆ TRGM_TRGOCFG_TRGM_P_16

#define TRGM_TRGOCFG_TRGM_P_16   (16UL)

◆ TRGM_TRGOCFG_TRGM_P_17

#define TRGM_TRGOCFG_TRGM_P_17   (17UL)

◆ TRGM_TRGOCFG_TRGM_P_18

#define TRGM_TRGOCFG_TRGM_P_18   (18UL)

◆ TRGM_TRGOCFG_TRGM_P_19

#define TRGM_TRGOCFG_TRGM_P_19   (19UL)

◆ TRGM_TRGOCFG_TRGM_P_20

#define TRGM_TRGOCFG_TRGM_P_20   (20UL)

◆ TRGM_TRGOCFG_TRGM_P_21

#define TRGM_TRGOCFG_TRGM_P_21   (21UL)

◆ TRGM_TRGOCFG_TRGM_P_22

#define TRGM_TRGOCFG_TRGM_P_22   (22UL)

◆ TRGM_TRGOCFG_TRGM_P_23

#define TRGM_TRGOCFG_TRGM_P_23   (23UL)

◆ TRGM_TRGOCFG_TRGM_P_24

#define TRGM_TRGOCFG_TRGM_P_24   (24UL)

◆ TRGM_TRGOCFG_TRGM_P_25

#define TRGM_TRGOCFG_TRGM_P_25   (25UL)

◆ TRGM_TRGOCFG_TRGM_P_26

#define TRGM_TRGOCFG_TRGM_P_26   (26UL)

◆ TRGM_TRGOCFG_TRGM_P_27

#define TRGM_TRGOCFG_TRGM_P_27   (27UL)

◆ TRGM_TRGOCFG_TRGM_P_28

#define TRGM_TRGOCFG_TRGM_P_28   (28UL)

◆ TRGM_TRGOCFG_TRGM_P_29

#define TRGM_TRGOCFG_TRGM_P_29   (29UL)

◆ TRGM_TRGOCFG_TRGM_P_30

#define TRGM_TRGOCFG_TRGM_P_30   (30UL)

◆ TRGM_TRGOCFG_TRGM_P_31

#define TRGM_TRGOCFG_TRGM_P_31   (31UL)

◆ TRGM_TRGOCFG_TRIGOSEL_GET

#define TRGM_TRGOCFG_TRIGOSEL_GET (   x)    (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT)

◆ TRGM_TRGOCFG_TRIGOSEL_MASK

#define TRGM_TRGOCFG_TRIGOSEL_MASK   (0xFFU)

◆ TRGM_TRGOCFG_TRIGOSEL_SET

#define TRGM_TRGOCFG_TRIGOSEL_SET (   x)    (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK)

◆ TRGM_TRGOCFG_TRIGOSEL_SHIFT

#define TRGM_TRGOCFG_TRIGOSEL_SHIFT   (0U)

◆ TRGM_TRGOCFG_UART_TRIG0

#define TRGM_TRGOCFG_UART_TRIG0   (204UL)

◆ TRGM_TRGOCFG_UART_TRIG1

#define TRGM_TRGOCFG_UART_TRIG1   (205UL)

◆ TRGM_TRGOCFG_VSC0_TRIG_IN0

#define TRGM_TRGOCFG_VSC0_TRIG_IN0   (64UL)

◆ TRGM_TRGOCFG_VSC0_TRIG_IN1

#define TRGM_TRGOCFG_VSC0_TRIG_IN1   (65UL)