hpm_adc12_drv.h

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/*
 * Copyright (c) 2021-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_ADC12_DRV_H
#define HPM_ADC12_DRV_H
 
#include "hpm_common.h"
#include "hpm_adc12_regs.h"
#include "hpm_soc_feature.h"
 
#define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE)  (TYPE > (uint32_t)adc12_sample_signal_count)
 
#define ADC12_IS_CHANNEL_INVALID(CH) (CH > ADC12_SOC_MAX_CH_NUM)
 
#define ADC12_IS_CHANNEL_SAMPLE_CYCLE_INVALID(CYC) (CYC == 0)
 
#define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM)
 
#define ADC12_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN)
 
#define ADC12_IS_SEQ_LEN_INVLAID(LEN)  ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_LEN))
 
#define ADC12_IS_SEQ_DMA_BUFF_LEN_INVLAID(LEN)  ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES))
 
#define ADC12_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN)  ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES))
 
typedef enum {
    adc12_sample_signal_single_ended = 0,
    adc12_sample_signal_differential = 1,
    adc12_sample_signal_count = 2
} adc12_sample_signal_t;
 
typedef enum {
    adc12_res_6_bits = 0,
    adc12_res_8_bits,
    adc12_res_10_bits,
    adc12_res_12_bits
} adc12_resolution_t;
 
typedef enum {
    adc12_conv_mode_oneshot = 0,
    adc12_conv_mode_period,
    adc12_conv_mode_sequence,
    adc12_conv_mode_preemption
} adc12_conversion_mode_t;
 
typedef enum {
    adc12_clock_divider_1 = 1,
    adc12_clock_divider_2,
    adc12_clock_divider_3,
    adc12_clock_divider_4,
    adc12_clock_divider_5,
    adc12_clock_divider_6,
    adc12_clock_divider_7,
    adc12_clock_divider_8,
    adc12_clock_divider_9,
    adc12_clock_divider_10,
    adc12_clock_divider_11,
    adc12_clock_divider_12,
    adc12_clock_divider_13,
    adc12_clock_divider_14,
    adc12_clock_divider_15,
    adc12_clock_divider_16,
} adc12_clock_divider_t;
 
typedef enum {
    adc12_event_trig_complete       = ADC12_INT_STS_TRIG_CMPT_MASK,
 
    adc12_event_trig_sw_conflict    = ADC12_INT_STS_TRIG_SW_CFLCT_MASK,
 
    adc12_event_trig_hw_conflict    = ADC12_INT_STS_TRIG_HW_CFLCT_MASK,
 
    adc12_event_read_conflict       = ADC12_INT_STS_READ_CFLCT_MASK,
 
    adc12_event_seq_sw_conflict     = ADC12_INT_STS_SEQ_SW_CFLCT_MASK,
 
    adc12_event_seq_hw_conflict     = ADC12_INT_STS_SEQ_HW_CFLCT_MASK,
 
    adc12_event_seq_dma_abort       = ADC12_INT_STS_SEQ_DMAABT_MASK,
 
    adc12_event_seq_full_complete   = ADC12_INT_STS_SEQ_CMPT_MASK,
 
    adc12_event_seq_single_complete = ADC12_INT_STS_SEQ_CVC_MASK,
 
    adc12_event_dma_fifo_full       = ADC12_INT_STS_DMA_FIFO_FULL_MASK
} adc12_irq_event_t;
 
typedef struct {
    uint8_t res;
    uint8_t conv_mode;
    uint8_t diff_sel;
    uint32_t adc_clk_div;
    bool wait_dis;
    bool sel_sync_ahb;
    bool adc_ahb_en;
} adc12_config_t;
 
typedef struct {
   uint8_t ch;
   uint8_t diff_sel;
   uint16_t thshdh;
   uint16_t thshdl;
   bool wdog_int_en;
   uint8_t sample_cycle_shift;
   uint32_t sample_cycle;
} adc12_channel_config_t;
 
typedef struct {
   uint8_t ch;
   uint16_t thshdh;
   uint16_t thshdl;
} adc12_channel_threshold_t;
 
typedef struct {
    uint32_t *start_addr;
    uint32_t buff_len_in_4bytes;
    uint32_t stop_pos;
    bool stop_en;
} adc12_dma_config_t;
 
typedef struct {
    uint32_t           :4;
    uint32_t result    :12;
    uint32_t seq_num   :4;
    uint32_t           :4;
    uint32_t adc_ch    :5;
    uint32_t           :2;
    uint32_t cycle_bit :1;
} adc12_seq_dma_data_t;
 
typedef struct {
    uint32_t           :4;
    uint32_t result    :12;
    uint32_t seq_num   :2;
    uint32_t           :2;
    uint32_t trig_ch   :4;
    uint32_t adc_ch    :5;
    uint32_t           :2;
    uint32_t cycle_bit :1;
} adc12_pmt_dma_data_t;
 
typedef struct {
    uint8_t ch;
    uint8_t prescale;
    uint8_t period_count;
} adc12_prd_config_t;
 
typedef struct {
    bool seq_int_en;
    uint8_t ch;
} adc12_seq_queue_config_t;
 
typedef struct {
    adc12_seq_queue_config_t queue[ADC_SOC_SEQ_MAX_LEN];
    bool restart_en;
    bool cont_en;
    bool sw_trig_en;
    bool hw_trig_en;
    uint8_t seq_len;
} adc12_seq_config_t;
 
typedef struct {
    bool    inten[ADC_SOC_MAX_TRIG_CH_LEN];
    uint8_t adc_ch[ADC_SOC_MAX_TRIG_CH_LEN];
    uint8_t trig_ch;
    uint8_t trig_len;
} adc12_pmt_config_t;
 
#ifdef __cplusplus
extern "C" {
#endif
void adc12_get_default_config(adc12_config_t *config);
 
void adc12_get_channel_default_config(adc12_channel_config_t *config);
 
hpm_stat_t adc12_deinit(ADC12_Type *ptr);
 
hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config);
 
hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config);
 
hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config);
 
hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config);
 
hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config);
 
hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config);
 
static inline void adc12_set_seq_stop_pos(ADC12_Type *ptr, uint16_t stop_pos)
{
    ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_STOP_POS_MASK)
                     | ADC12_SEQ_DMA_CFG_STOP_POS_SET(stop_pos);
}
 
static inline void adc12_init_pmt_dma(ADC12_Type *ptr, uint32_t addr)
{
    ptr->TRG_DMA_ADDR = addr & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK;
}
 
hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *config);
 
static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr)
{
    return ptr->INT_STS;
}
 
static inline void adc12_disable_busywait(ADC12_Type *ptr)
{
    ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_SET(1);
}
 
static inline void adc12_enable_busywait(ADC12_Type *ptr)
{
    ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK;
}
 
static inline void adc12_set_nonblocking_read(ADC12_Type *ptr)
{
    ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_MASK;
}
 
static inline void adc12_set_blocking_read(ADC12_Type *ptr)
{
    ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK;
}
 
static inline bool adc12_is_nonblocking_mode(ADC12_Type *ptr)
{
    return (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)  ? true : false);
}
 
static inline bool adc12_get_conv_valid_status(ADC12_Type *ptr, uint8_t ch)
{
    return ADC12_BUS_RESULT_VALID_GET(ptr->BUS_RESULT[ch]);
}
 
static inline void adc12_clear_status_flags(ADC12_Type *ptr, uint32_t mask)
{
    ptr->INT_STS = mask;
}
 
static inline void adc12_enable_interrupts(ADC12_Type *ptr, uint32_t mask)
{
    ptr->INT_EN |= mask;
}
 
static inline void adc12_disable_interrupts(ADC12_Type *ptr, uint32_t mask)
{
    ptr->INT_EN &= ~mask;
}
 
hpm_stat_t adc12_trigger_seq_by_sw(ADC12_Type *ptr);
 
hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch);
 
hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result);
 
hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result);
 
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_ADC12_DRV_H */