HPM SDK
HPMicro Software Development Kit
hpm_adc12_regs.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_ADC12_H
10 #define HPM_ADC12_H
11 
12 typedef struct {
13  __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */
14  __RW uint32_t TRG_DMA_ADDR; /* 0x30: */
15  __RW uint32_t TRG_SW_STA; /* 0x34: */
16  __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */
17  __R uint32_t BUS_RESULT[19]; /* 0x400 - 0x448: */
18  __R uint8_t RESERVED1[180]; /* 0x44C - 0x4FF: Reserved */
19  __RW uint32_t BUF_CFG0; /* 0x500: */
20  __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */
21  __RW uint32_t SEQ_CFG0; /* 0x800: */
22  __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */
23  __R uint32_t SEQ_WR_ADDR; /* 0x808: */
24  __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */
25  __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */
26  __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */
27  struct {
28  __RW uint32_t PRD_CFG; /* 0xC00: */
29  __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */
30  __R uint32_t PRD_RESULT; /* 0xC08: */
31  __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */
32  } PRD_CFG[19];
33  __R uint8_t RESERVED4[720]; /* 0xD30 - 0xFFF: Reserved */
34  __RW uint32_t SAMPLE_CFG[19]; /* 0x1000 - 0x1048: */
35  __R uint8_t RESERVED5[184]; /* 0x104C - 0x1103: Reserved */
36  __RW uint32_t CONV_CFG1; /* 0x1104: */
37  __RW uint32_t ADC_CFG0; /* 0x1108: */
38  __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */
39  __RW uint32_t INT_STS; /* 0x1110: */
40  __RW uint32_t INT_EN; /* 0x1114: */
41  __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */
42  __RW uint32_t ANA_CTRL0; /* 0x1200: */
43  __RW uint32_t ANA_CTRL1; /* 0x1204: */
44  __R uint8_t RESERVED8[8]; /* 0x1208 - 0x120F: Reserved */
45  __RW uint32_t ANA_STATUS; /* 0x1210: */
46 } ADC12_Type;
47 
48 
49 /* Bitfield definition for register array: CONFIG */
50 /*
51  * TRIG_LEN (WO)
52  *
53  * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3
54  */
55 #define ADC12_CONFIG_TRIG_LEN_MASK (0xC0000000UL)
56 #define ADC12_CONFIG_TRIG_LEN_SHIFT (30U)
57 #define ADC12_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC12_CONFIG_TRIG_LEN_SHIFT) & ADC12_CONFIG_TRIG_LEN_MASK)
58 #define ADC12_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC12_CONFIG_TRIG_LEN_MASK) >> ADC12_CONFIG_TRIG_LEN_SHIFT)
59 
60 /*
61  * INTEN3 (RW)
62  *
63  * interrupt enable for 4th conversion
64  */
65 #define ADC12_CONFIG_INTEN3_MASK (0x20000000UL)
66 #define ADC12_CONFIG_INTEN3_SHIFT (29U)
67 #define ADC12_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN3_SHIFT) & ADC12_CONFIG_INTEN3_MASK)
68 #define ADC12_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN3_MASK) >> ADC12_CONFIG_INTEN3_SHIFT)
69 
70 /*
71  * CHAN3 (RW)
72  *
73  * channel number for 4th conversion
74  */
75 #define ADC12_CONFIG_CHAN3_MASK (0x1F000000UL)
76 #define ADC12_CONFIG_CHAN3_SHIFT (24U)
77 #define ADC12_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN3_SHIFT) & ADC12_CONFIG_CHAN3_MASK)
78 #define ADC12_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN3_MASK) >> ADC12_CONFIG_CHAN3_SHIFT)
79 
80 /*
81  * INTEN2 (RW)
82  *
83  * interrupt enable for 3rd conversion
84  */
85 #define ADC12_CONFIG_INTEN2_MASK (0x200000UL)
86 #define ADC12_CONFIG_INTEN2_SHIFT (21U)
87 #define ADC12_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN2_SHIFT) & ADC12_CONFIG_INTEN2_MASK)
88 #define ADC12_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN2_MASK) >> ADC12_CONFIG_INTEN2_SHIFT)
89 
90 /*
91  * CHAN2 (RW)
92  *
93  * channel number for 3rd conversion
94  */
95 #define ADC12_CONFIG_CHAN2_MASK (0x1F0000UL)
96 #define ADC12_CONFIG_CHAN2_SHIFT (16U)
97 #define ADC12_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN2_SHIFT) & ADC12_CONFIG_CHAN2_MASK)
98 #define ADC12_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN2_MASK) >> ADC12_CONFIG_CHAN2_SHIFT)
99 
100 /*
101  * INTEN1 (RW)
102  *
103  * interrupt enable for 2nd conversion
104  */
105 #define ADC12_CONFIG_INTEN1_MASK (0x2000U)
106 #define ADC12_CONFIG_INTEN1_SHIFT (13U)
107 #define ADC12_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN1_SHIFT) & ADC12_CONFIG_INTEN1_MASK)
108 #define ADC12_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN1_MASK) >> ADC12_CONFIG_INTEN1_SHIFT)
109 
110 /*
111  * CHAN1 (RW)
112  *
113  * channel number for 2nd conversion
114  */
115 #define ADC12_CONFIG_CHAN1_MASK (0x1F00U)
116 #define ADC12_CONFIG_CHAN1_SHIFT (8U)
117 #define ADC12_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN1_SHIFT) & ADC12_CONFIG_CHAN1_MASK)
118 #define ADC12_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN1_MASK) >> ADC12_CONFIG_CHAN1_SHIFT)
119 
120 /*
121  * INTEN0 (RW)
122  *
123  * interrupt enable for 1st conversion
124  */
125 #define ADC12_CONFIG_INTEN0_MASK (0x20U)
126 #define ADC12_CONFIG_INTEN0_SHIFT (5U)
127 #define ADC12_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN0_SHIFT) & ADC12_CONFIG_INTEN0_MASK)
128 #define ADC12_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN0_MASK) >> ADC12_CONFIG_INTEN0_SHIFT)
129 
130 /*
131  * CHAN0 (RW)
132  *
133  * channel number for 1st conversion
134  */
135 #define ADC12_CONFIG_CHAN0_MASK (0x1FU)
136 #define ADC12_CONFIG_CHAN0_SHIFT (0U)
137 #define ADC12_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN0_SHIFT) & ADC12_CONFIG_CHAN0_MASK)
138 #define ADC12_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN0_MASK) >> ADC12_CONFIG_CHAN0_SHIFT)
139 
140 /* Bitfield definition for register: TRG_DMA_ADDR */
141 /*
142  * TRG_DMA_ADDR (RW)
143  *
144  * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)
145  */
146 #define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL)
147 #define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U)
148 #define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK)
149 #define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT)
150 
151 /* Bitfield definition for register: TRG_SW_STA */
152 /*
153  * TRG_SW_STA (RW)
154  *
155  * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it.
156  */
157 #define ADC12_TRG_SW_STA_TRG_SW_STA_MASK (0x10U)
158 #define ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT (4U)
159 #define ADC12_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC12_TRG_SW_STA_TRG_SW_STA_MASK)
160 #define ADC12_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC12_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT)
161 
162 /*
163  * TRIG_SW_INDEX (RW)
164  *
165  * which trigger for the SW trigger
166  * 0 for trig0a, 1 for trig0b…
167  * 3 for trig1a, …11 for trig3c
168  */
169 #define ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU)
170 #define ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U)
171 #define ADC12_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK)
172 #define ADC12_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT)
173 
174 /* Bitfield definition for register array: BUS_RESULT */
175 /*
176  * VALID (RO)
177  *
178  * set after conversion finished if wait_dis is set, cleared after software read.
179  * The first time read with 0 will trigger one new conversion.
180  * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set.
181  * the result may not realtime if software read once and wait long time to read again
182  */
183 #define ADC12_BUS_RESULT_VALID_MASK (0x10000UL)
184 #define ADC12_BUS_RESULT_VALID_SHIFT (16U)
185 #define ADC12_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_VALID_MASK) >> ADC12_BUS_RESULT_VALID_SHIFT)
186 
187 /*
188  * CHAN_RESULT (RO)
189  *
190  * read this register will trigger one adc conversion.
191  * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result
192  * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long
193  */
194 #define ADC12_BUS_RESULT_CHAN_RESULT_MASK (0xFFF0U)
195 #define ADC12_BUS_RESULT_CHAN_RESULT_SHIFT (4U)
196 #define ADC12_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_CHAN_RESULT_MASK) >> ADC12_BUS_RESULT_CHAN_RESULT_SHIFT)
197 
198 /* Bitfield definition for register: BUF_CFG0 */
199 /*
200  * WAIT_DIS (RW)
201  *
202  * set to disable read waiting, get result immediately but maybe not current conversion result.
203  */
204 #define ADC12_BUF_CFG0_WAIT_DIS_MASK (0x1U)
205 #define ADC12_BUF_CFG0_WAIT_DIS_SHIFT (0U)
206 #define ADC12_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC12_BUF_CFG0_WAIT_DIS_SHIFT) & ADC12_BUF_CFG0_WAIT_DIS_MASK)
207 #define ADC12_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC12_BUF_CFG0_WAIT_DIS_MASK) >> ADC12_BUF_CFG0_WAIT_DIS_SHIFT)
208 
209 /* Bitfield definition for register: SEQ_CFG0 */
210 /*
211  * CYCLE (RO)
212  *
213  * current dma write cycle bit
214  */
215 #define ADC12_SEQ_CFG0_CYCLE_MASK (0x80000000UL)
216 #define ADC12_SEQ_CFG0_CYCLE_SHIFT (31U)
217 #define ADC12_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_CYCLE_MASK) >> ADC12_SEQ_CFG0_CYCLE_SHIFT)
218 
219 /*
220  * SEQ_LEN (RW)
221  *
222  * sequence queue length, 0 for one, 0xF for 16
223  */
224 #define ADC12_SEQ_CFG0_SEQ_LEN_MASK (0xF00U)
225 #define ADC12_SEQ_CFG0_SEQ_LEN_SHIFT (8U)
226 #define ADC12_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC12_SEQ_CFG0_SEQ_LEN_MASK)
227 #define ADC12_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SEQ_LEN_MASK) >> ADC12_SEQ_CFG0_SEQ_LEN_SHIFT)
228 
229 /*
230  * RESTART_EN (RW)
231  *
232  * if set together with cont_en, HW will continue process the whole queue after trigger once.
233  * If cont_en is 0, this bit is not used
234  */
235 #define ADC12_SEQ_CFG0_RESTART_EN_MASK (0x10U)
236 #define ADC12_SEQ_CFG0_RESTART_EN_SHIFT (4U)
237 #define ADC12_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_RESTART_EN_SHIFT) & ADC12_SEQ_CFG0_RESTART_EN_MASK)
238 #define ADC12_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_RESTART_EN_MASK) >> ADC12_SEQ_CFG0_RESTART_EN_SHIFT)
239 
240 /*
241  * CONT_EN (RW)
242  *
243  * if set, HW will continue process the queue till end(seq_len) after trigger once
244  */
245 #define ADC12_SEQ_CFG0_CONT_EN_MASK (0x8U)
246 #define ADC12_SEQ_CFG0_CONT_EN_SHIFT (3U)
247 #define ADC12_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_CONT_EN_SHIFT) & ADC12_SEQ_CFG0_CONT_EN_MASK)
248 #define ADC12_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_CONT_EN_MASK) >> ADC12_SEQ_CFG0_CONT_EN_SHIFT)
249 
250 /*
251  * SW_TRIG (WO)
252  *
253  * SW trigger, pulse signal, cleared by HW one cycle later
254  */
255 #define ADC12_SEQ_CFG0_SW_TRIG_MASK (0x4U)
256 #define ADC12_SEQ_CFG0_SW_TRIG_SHIFT (2U)
257 #define ADC12_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SW_TRIG_SHIFT) & ADC12_SEQ_CFG0_SW_TRIG_MASK)
258 #define ADC12_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SW_TRIG_MASK) >> ADC12_SEQ_CFG0_SW_TRIG_SHIFT)
259 
260 /*
261  * SW_TRIG_EN (RW)
262  *
263  * set to enable SW trigger
264  */
265 #define ADC12_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U)
266 #define ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U)
267 #define ADC12_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC12_SEQ_CFG0_SW_TRIG_EN_MASK)
268 #define ADC12_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT)
269 
270 /*
271  * HW_TRIG_EN (RW)
272  *
273  * set to enable external HW trigger, only trigger on posedge
274  */
275 #define ADC12_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U)
276 #define ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U)
277 #define ADC12_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC12_SEQ_CFG0_HW_TRIG_EN_MASK)
278 #define ADC12_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT)
279 
280 /* Bitfield definition for register: SEQ_DMA_ADDR */
281 /*
282  * TAR_ADDR (RW)
283  *
284  * dma target address, should be 4-byte aligned
285  */
286 #define ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL)
287 #define ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U)
288 #define ADC12_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK)
289 #define ADC12_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT)
290 
291 /* Bitfield definition for register: SEQ_WR_ADDR */
292 /*
293  * SEQ_WR_POINTER (RO)
294  *
295  * HW update this field after each dma write, it indicate the next dma write pointer.
296  * dma write address is (tar_addr+seq_wr_pointer)*4
297  */
298 #define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFU)
299 #define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U)
300 #define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT)
301 
302 /* Bitfield definition for register: SEQ_DMA_CFG */
303 /*
304  * STOP_POS (RW)
305  *
306  * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet
307  */
308 #define ADC12_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL)
309 #define ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT (16U)
310 #define ADC12_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC12_SEQ_DMA_CFG_STOP_POS_MASK)
311 #define ADC12_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT)
312 
313 /*
314  * DMA_RST (RW)
315  *
316  * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set.
317  * SW should clear all cycle bit in buffer to 0 before clear dma_rst
318  */
319 #define ADC12_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U)
320 #define ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT (13U)
321 #define ADC12_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC12_SEQ_DMA_CFG_DMA_RST_MASK)
322 #define ADC12_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT)
323 
324 /*
325  * STOP_EN (RW)
326  *
327  * set to stop dma if reach the stop_pos
328  */
329 #define ADC12_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U)
330 #define ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT (12U)
331 #define ADC12_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC12_SEQ_DMA_CFG_STOP_EN_MASK)
332 #define ADC12_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT)
333 
334 /*
335  * BUF_LEN (RW)
336  *
337  * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4
338  * 0 for 4byte;
339  * 0xFFF for 16kbyte.
340  */
341 #define ADC12_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU)
342 #define ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U)
343 #define ADC12_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC12_SEQ_DMA_CFG_BUF_LEN_MASK)
344 #define ADC12_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT)
345 
346 /* Bitfield definition for register array: SEQ_QUE */
347 /*
348  * SEQ_INT_EN (RW)
349  *
350  * interrupt enable for current conversion
351  */
352 #define ADC12_SEQ_QUE_SEQ_INT_EN_MASK (0x20U)
353 #define ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT (5U)
354 #define ADC12_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC12_SEQ_QUE_SEQ_INT_EN_MASK)
355 #define ADC12_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT)
356 
357 /*
358  * CHAN_NUM_4_0 (RW)
359  *
360  * channel number for current conversion
361  */
362 #define ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU)
363 #define ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U)
364 #define ADC12_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK)
365 #define ADC12_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT)
366 
367 /* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */
368 /*
369  * PRESCALE (RW)
370  *
371  * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx
372  */
373 #define ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U)
374 #define ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U)
375 #define ADC12_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK)
376 #define ADC12_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)
377 
378 /*
379  * PRD (RW)
380  *
381  * conver period, with prescale.
382  * Set to 0 means disable current channel
383  */
384 #define ADC12_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU)
385 #define ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT (0U)
386 #define ADC12_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC12_PRD_CFG_PRD_CFG_PRD_MASK)
387 #define ADC12_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT)
388 
389 /* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */
390 /*
391  * THSHDH (RW)
392  *
393  * threshold high, assert interrupt(if enabled) if result exceed high or low.
394  */
395 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFF00000UL)
396 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (20U)
397 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK)
398 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT)
399 
400 /*
401  * THSHDL (RW)
402  *
403  * threshold low
404  */
405 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFF0U)
406 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (4U)
407 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK)
408 #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT)
409 
410 /* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */
411 /*
412  * CHAN_RESULT (RO)
413  *
414  * adc convert result, update after each valid conversion.
415  * it may be updated period according to config, also may be updated due to other queue convert the same channel
416  */
417 #define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFF0U)
418 #define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (4U)
419 #define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT)
420 
421 /* Bitfield definition for register array: SAMPLE_CFG */
422 /*
423  * DIFF_SEL (RW)
424  *
425  * set to 1 to select differential channel
426  */
427 #define ADC12_SAMPLE_CFG_DIFF_SEL_MASK (0x1000U)
428 #define ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT (12U)
429 #define ADC12_SAMPLE_CFG_DIFF_SEL_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT) & ADC12_SAMPLE_CFG_DIFF_SEL_MASK)
430 #define ADC12_SAMPLE_CFG_DIFF_SEL_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_DIFF_SEL_MASK) >> ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT)
431 
432 /*
433  * SAMPLE_CLOCK_NUMBER_SHIFT (RW)
434  *
435  * shift for sample_clock_number
436  */
437 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U)
438 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U)
439 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK)
440 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT)
441 
442 /*
443  * SAMPLE_CLOCK_NUMBER (RW)
444  *
445  * sample clock number, base on clock_period, default one period
446  */
447 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU)
448 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U)
449 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK)
450 #define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT)
451 
452 /* Bitfield definition for register: CONV_CFG1 */
453 /*
454  * CONVERT_CLOCK_NUMBER (RW)
455  *
456  * convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider);
457  * set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode;
458  * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divider to 2, then each ADC conversion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz).
459  */
460 #define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U)
461 #define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U)
462 #define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK)
463 #define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT)
464 
465 /*
466  * CLOCK_DIVIDER (RW)
467  *
468  * clock_period, N half clock cycle per half adc cycle
469  * 0 for same adc_clk and bus_clk,
470  * 1 for 1:2,
471  * 2 for 1:3,
472  * ...
473  * 15 for 1:16
474  * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk
475  */
476 #define ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU)
477 #define ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U)
478 #define ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK)
479 #define ADC12_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT)
480 
481 /* Bitfield definition for register: ADC_CFG0 */
482 /*
483  * SEL_SYNC_AHB (RW)
484  *
485  * set to 1 will enable sync AHB bus, to get better bus performance.
486  * Adc_clk must to be set to same as bus clock at this mode
487  */
488 #define ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL)
489 #define ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U)
490 #define ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK)
491 #define ADC12_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT)
492 
493 /*
494  * ADC_AHB_EN (RW)
495  *
496  * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;
497  */
498 #define ADC12_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL)
499 #define ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT (29U)
500 #define ADC12_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC12_ADC_CFG0_ADC_AHB_EN_MASK)
501 #define ADC12_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC12_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT)
502 
503 /* Bitfield definition for register: INT_STS */
504 /*
505  * TRIG_CMPT (RW1C)
506  *
507  * interrupt for one trigger conversion complete if enabled
508  */
509 #define ADC12_INT_STS_TRIG_CMPT_MASK (0x80000000UL)
510 #define ADC12_INT_STS_TRIG_CMPT_SHIFT (31U)
511 #define ADC12_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_CMPT_SHIFT) & ADC12_INT_STS_TRIG_CMPT_MASK)
512 #define ADC12_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_CMPT_MASK) >> ADC12_INT_STS_TRIG_CMPT_SHIFT)
513 
514 /*
515  * TRIG_SW_CFLCT (RW1C)
516  *
517  */
518 #define ADC12_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL)
519 #define ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT (30U)
520 #define ADC12_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK)
521 #define ADC12_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT)
522 
523 /*
524  * TRIG_HW_CFLCT (RW1C)
525  *
526  */
527 #define ADC12_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL)
528 #define ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT (29U)
529 #define ADC12_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK)
530 #define ADC12_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT)
531 
532 /*
533  * READ_CFLCT (RW1C)
534  *
535  * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel
536  */
537 #define ADC12_INT_STS_READ_CFLCT_MASK (0x10000000UL)
538 #define ADC12_INT_STS_READ_CFLCT_SHIFT (28U)
539 #define ADC12_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_READ_CFLCT_SHIFT) & ADC12_INT_STS_READ_CFLCT_MASK)
540 #define ADC12_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_READ_CFLCT_MASK) >> ADC12_INT_STS_READ_CFLCT_SHIFT)
541 
542 /*
543  * SEQ_SW_CFLCT (RW1C)
544  *
545  * sequence queue conflict interrupt, set if HW or SW trigger received during conversion
546  */
547 #define ADC12_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL)
548 #define ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT (27U)
549 #define ADC12_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK)
550 #define ADC12_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT)
551 
552 /*
553  * SEQ_HW_CFLCT (RW1C)
554  *
555  */
556 #define ADC12_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL)
557 #define ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT (26U)
558 #define ADC12_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK)
559 #define ADC12_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT)
560 
561 /*
562  * SEQ_DMAABT (RW1C)
563  *
564  * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set
565  */
566 #define ADC12_INT_STS_SEQ_DMAABT_MASK (0x2000000UL)
567 #define ADC12_INT_STS_SEQ_DMAABT_SHIFT (25U)
568 #define ADC12_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_DMAABT_SHIFT) & ADC12_INT_STS_SEQ_DMAABT_MASK)
569 #define ADC12_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_DMAABT_MASK) >> ADC12_INT_STS_SEQ_DMAABT_SHIFT)
570 
571 /*
572  * SEQ_CMPT (RW1C)
573  *
574  * the whole sequence complete interrupt
575  */
576 #define ADC12_INT_STS_SEQ_CMPT_MASK (0x1000000UL)
577 #define ADC12_INT_STS_SEQ_CMPT_SHIFT (24U)
578 #define ADC12_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_CMPT_SHIFT) & ADC12_INT_STS_SEQ_CMPT_MASK)
579 #define ADC12_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CMPT_MASK) >> ADC12_INT_STS_SEQ_CMPT_SHIFT)
580 
581 /*
582  * SEQ_CVC (RW1C)
583  *
584  * one conversion complete in seq_queue if related seq_int_en is set
585  */
586 #define ADC12_INT_STS_SEQ_CVC_MASK (0x800000UL)
587 #define ADC12_INT_STS_SEQ_CVC_SHIFT (23U)
588 #define ADC12_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_CVC_SHIFT) & ADC12_INT_STS_SEQ_CVC_MASK)
589 #define ADC12_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CVC_MASK) >> ADC12_INT_STS_SEQ_CVC_SHIFT)
590 
591 /*
592  * DMA_FIFO_FULL (RW1C)
593  *
594  */
595 #define ADC12_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL)
596 #define ADC12_INT_STS_DMA_FIFO_FULL_SHIFT (22U)
597 #define ADC12_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC12_INT_STS_DMA_FIFO_FULL_MASK)
598 #define ADC12_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) >> ADC12_INT_STS_DMA_FIFO_FULL_SHIFT)
599 
600 /*
601  * AHB_ERR (RW1C)
602  *
603  * set if got hresp=1
604  */
605 #define ADC12_INT_STS_AHB_ERR_MASK (0x200000UL)
606 #define ADC12_INT_STS_AHB_ERR_SHIFT (21U)
607 #define ADC12_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC12_INT_STS_AHB_ERR_SHIFT) & ADC12_INT_STS_AHB_ERR_MASK)
608 #define ADC12_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_STS_AHB_ERR_MASK) >> ADC12_INT_STS_AHB_ERR_SHIFT)
609 
610 /*
611  * WDOG (RW1C)
612  *
613  * set if one chanel watch dog event triggered
614  */
615 #define ADC12_INT_STS_WDOG_MASK (0x7FFFFUL)
616 #define ADC12_INT_STS_WDOG_SHIFT (0U)
617 #define ADC12_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC12_INT_STS_WDOG_SHIFT) & ADC12_INT_STS_WDOG_MASK)
618 #define ADC12_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC12_INT_STS_WDOG_MASK) >> ADC12_INT_STS_WDOG_SHIFT)
619 
620 /* Bitfield definition for register: INT_EN */
621 /*
622  * TRIG_CMPT (RW)
623  *
624  * interrupt for one trigger conversion complete if enabled
625  */
626 #define ADC12_INT_EN_TRIG_CMPT_MASK (0x80000000UL)
627 #define ADC12_INT_EN_TRIG_CMPT_SHIFT (31U)
628 #define ADC12_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_CMPT_SHIFT) & ADC12_INT_EN_TRIG_CMPT_MASK)
629 #define ADC12_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_CMPT_MASK) >> ADC12_INT_EN_TRIG_CMPT_SHIFT)
630 
631 /*
632  * TRIG_SW_CFLCT (RW)
633  *
634  */
635 #define ADC12_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL)
636 #define ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT (30U)
637 #define ADC12_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC12_INT_EN_TRIG_SW_CFLCT_MASK)
638 #define ADC12_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT)
639 
640 /*
641  * TRIG_HW_CFLCT (RW)
642  *
643  */
644 #define ADC12_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL)
645 #define ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT (29U)
646 #define ADC12_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK)
647 #define ADC12_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT)
648 
649 /*
650  * READ_CFLCT (RW)
651  *
652  * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel
653  */
654 #define ADC12_INT_EN_READ_CFLCT_MASK (0x10000000UL)
655 #define ADC12_INT_EN_READ_CFLCT_SHIFT (28U)
656 #define ADC12_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_READ_CFLCT_SHIFT) & ADC12_INT_EN_READ_CFLCT_MASK)
657 #define ADC12_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_READ_CFLCT_MASK) >> ADC12_INT_EN_READ_CFLCT_SHIFT)
658 
659 /*
660  * SEQ_SW_CFLCT (RW)
661  *
662  * sequence queue conflict interrupt, set if HW or SW trigger received during conversion
663  */
664 #define ADC12_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL)
665 #define ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT (27U)
666 #define ADC12_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC12_INT_EN_SEQ_SW_CFLCT_MASK)
667 #define ADC12_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT)
668 
669 /*
670  * SEQ_HW_CFLCT (RW)
671  *
672  */
673 #define ADC12_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL)
674 #define ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT (26U)
675 #define ADC12_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK)
676 #define ADC12_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT)
677 
678 /*
679  * SEQ_DMAABT (RW)
680  *
681  * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set
682  */
683 #define ADC12_INT_EN_SEQ_DMAABT_MASK (0x2000000UL)
684 #define ADC12_INT_EN_SEQ_DMAABT_SHIFT (25U)
685 #define ADC12_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_DMAABT_SHIFT) & ADC12_INT_EN_SEQ_DMAABT_MASK)
686 #define ADC12_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_DMAABT_MASK) >> ADC12_INT_EN_SEQ_DMAABT_SHIFT)
687 
688 /*
689  * SEQ_CMPT (RW)
690  *
691  * the whole sequence complete interrupt
692  */
693 #define ADC12_INT_EN_SEQ_CMPT_MASK (0x1000000UL)
694 #define ADC12_INT_EN_SEQ_CMPT_SHIFT (24U)
695 #define ADC12_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_CMPT_SHIFT) & ADC12_INT_EN_SEQ_CMPT_MASK)
696 #define ADC12_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CMPT_MASK) >> ADC12_INT_EN_SEQ_CMPT_SHIFT)
697 
698 /*
699  * SEQ_CVC (RW)
700  *
701  * one conversion complete in seq_queue if related seq_int_en is set
702  */
703 #define ADC12_INT_EN_SEQ_CVC_MASK (0x800000UL)
704 #define ADC12_INT_EN_SEQ_CVC_SHIFT (23U)
705 #define ADC12_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_CVC_SHIFT) & ADC12_INT_EN_SEQ_CVC_MASK)
706 #define ADC12_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CVC_MASK) >> ADC12_INT_EN_SEQ_CVC_SHIFT)
707 
708 /*
709  * DMA_FIFO_FULL (RW)
710  *
711  * DMA fifo full interrupt, user need to check clock frequency if it's set.
712  */
713 #define ADC12_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL)
714 #define ADC12_INT_EN_DMA_FIFO_FULL_SHIFT (22U)
715 #define ADC12_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC12_INT_EN_DMA_FIFO_FULL_MASK)
716 #define ADC12_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) >> ADC12_INT_EN_DMA_FIFO_FULL_SHIFT)
717 
718 /*
719  * AHB_ERR (RW)
720  *
721  * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr
722  */
723 #define ADC12_INT_EN_AHB_ERR_MASK (0x200000UL)
724 #define ADC12_INT_EN_AHB_ERR_SHIFT (21U)
725 #define ADC12_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC12_INT_EN_AHB_ERR_SHIFT) & ADC12_INT_EN_AHB_ERR_MASK)
726 #define ADC12_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_EN_AHB_ERR_MASK) >> ADC12_INT_EN_AHB_ERR_SHIFT)
727 
728 /*
729  * WDOG (RW)
730  *
731  * set if one chanel watch dog event triggered
732  */
733 #define ADC12_INT_EN_WDOG_MASK (0x7FFFFUL)
734 #define ADC12_INT_EN_WDOG_SHIFT (0U)
735 #define ADC12_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC12_INT_EN_WDOG_SHIFT) & ADC12_INT_EN_WDOG_MASK)
736 #define ADC12_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC12_INT_EN_WDOG_MASK) >> ADC12_INT_EN_WDOG_SHIFT)
737 
738 /* Bitfield definition for register: ANA_CTRL0 */
739 /*
740  * CAL_VAL_DIFF (RW)
741  *
742  * calibration value for differential mode
743  */
744 #define ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK (0x7F000000UL)
745 #define ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT (24U)
746 #define ADC12_ANA_CTRL0_CAL_VAL_DIFF_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT) & ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK)
747 #define ADC12_ANA_CTRL0_CAL_VAL_DIFF_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) >> ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT)
748 
749 /*
750  * CAL_VAL_SE (RW)
751  *
752  * calibration value for single-end mode
753  */
754 #define ADC12_ANA_CTRL0_CAL_VAL_SE_MASK (0x7F0000UL)
755 #define ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT (16U)
756 #define ADC12_ANA_CTRL0_CAL_VAL_SE_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT) & ADC12_ANA_CTRL0_CAL_VAL_SE_MASK)
757 #define ADC12_ANA_CTRL0_CAL_VAL_SE_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) >> ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT)
758 
759 /*
760  * REARM_EN (RW)
761  *
762  * set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number
763  */
764 #define ADC12_ANA_CTRL0_REARM_EN_MASK (0x4000U)
765 #define ADC12_ANA_CTRL0_REARM_EN_SHIFT (14U)
766 #define ADC12_ANA_CTRL0_REARM_EN_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_REARM_EN_SHIFT) & ADC12_ANA_CTRL0_REARM_EN_MASK)
767 #define ADC12_ANA_CTRL0_REARM_EN_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_REARM_EN_MASK) >> ADC12_ANA_CTRL0_REARM_EN_SHIFT)
768 
769 /*
770  * SELRANGE_LDO (RW)
771  *
772  * Defines the range for the LDO reference (vdd_soc)
773  * selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99]
774  * selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21]
775  */
776 #define ADC12_ANA_CTRL0_SELRANGE_LDO_MASK (0x800U)
777 #define ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT (11U)
778 #define ADC12_ANA_CTRL0_SELRANGE_LDO_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT) & ADC12_ANA_CTRL0_SELRANGE_LDO_MASK)
779 #define ADC12_ANA_CTRL0_SELRANGE_LDO_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_SELRANGE_LDO_MASK) >> ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT)
780 
781 /*
782  * ENLDO (RW)
783  *
784  * set to enable adc LDO, need at least 20us for LDO to be stable.
785  */
786 #define ADC12_ANA_CTRL0_ENLDO_MASK (0x40U)
787 #define ADC12_ANA_CTRL0_ENLDO_SHIFT (6U)
788 #define ADC12_ANA_CTRL0_ENLDO_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_ENLDO_SHIFT) & ADC12_ANA_CTRL0_ENLDO_MASK)
789 #define ADC12_ANA_CTRL0_ENLDO_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_ENLDO_MASK) >> ADC12_ANA_CTRL0_ENLDO_SHIFT)
790 
791 /*
792  * ENADC (RW)
793  *
794  * set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit.
795  */
796 #define ADC12_ANA_CTRL0_ENADC_MASK (0x20U)
797 #define ADC12_ANA_CTRL0_ENADC_SHIFT (5U)
798 #define ADC12_ANA_CTRL0_ENADC_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_ENADC_SHIFT) & ADC12_ANA_CTRL0_ENADC_MASK)
799 #define ADC12_ANA_CTRL0_ENADC_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_ENADC_MASK) >> ADC12_ANA_CTRL0_ENADC_SHIFT)
800 
801 /*
802  * RESETADC (RW)
803  *
804  * set to 1 to reset adc analog; default high.
805  */
806 #define ADC12_ANA_CTRL0_RESETADC_MASK (0x10U)
807 #define ADC12_ANA_CTRL0_RESETADC_SHIFT (4U)
808 #define ADC12_ANA_CTRL0_RESETADC_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_RESETADC_SHIFT) & ADC12_ANA_CTRL0_RESETADC_MASK)
809 #define ADC12_ANA_CTRL0_RESETADC_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_RESETADC_MASK) >> ADC12_ANA_CTRL0_RESETADC_SHIFT)
810 
811 /*
812  * RESETCAL (RW)
813  *
814  * set to 1 to reset calibration logic; default high.
815  */
816 #define ADC12_ANA_CTRL0_RESETCAL_MASK (0x8U)
817 #define ADC12_ANA_CTRL0_RESETCAL_SHIFT (3U)
818 #define ADC12_ANA_CTRL0_RESETCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_RESETCAL_SHIFT) & ADC12_ANA_CTRL0_RESETCAL_MASK)
819 #define ADC12_ANA_CTRL0_RESETCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_RESETCAL_MASK) >> ADC12_ANA_CTRL0_RESETCAL_SHIFT)
820 
821 /*
822  * STARTCAL (RW)
823  *
824  * set to start the offset calibration cycle (Active H). user need to clear it after setting it.
825  */
826 #define ADC12_ANA_CTRL0_STARTCAL_MASK (0x4U)
827 #define ADC12_ANA_CTRL0_STARTCAL_SHIFT (2U)
828 #define ADC12_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_STARTCAL_SHIFT) & ADC12_ANA_CTRL0_STARTCAL_MASK)
829 #define ADC12_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_STARTCAL_MASK) >> ADC12_ANA_CTRL0_STARTCAL_SHIFT)
830 
831 /*
832  * LOADCAL (RW)
833  *
834  * Signal that loads the offset calibration word into the internal registers (Active H)
835  */
836 #define ADC12_ANA_CTRL0_LOADCAL_MASK (0x2U)
837 #define ADC12_ANA_CTRL0_LOADCAL_SHIFT (1U)
838 #define ADC12_ANA_CTRL0_LOADCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_LOADCAL_SHIFT) & ADC12_ANA_CTRL0_LOADCAL_MASK)
839 #define ADC12_ANA_CTRL0_LOADCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_LOADCAL_MASK) >> ADC12_ANA_CTRL0_LOADCAL_SHIFT)
840 
841 /* Bitfield definition for register: ANA_CTRL1 */
842 /*
843  * SELRES (RW)
844  *
845  * 11-12bit
846  * 10-10bit
847  * 01-8bit
848  * 00-6bit
849  */
850 #define ADC12_ANA_CTRL1_SELRES_MASK (0xC0U)
851 #define ADC12_ANA_CTRL1_SELRES_SHIFT (6U)
852 #define ADC12_ANA_CTRL1_SELRES_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL1_SELRES_SHIFT) & ADC12_ANA_CTRL1_SELRES_MASK)
853 #define ADC12_ANA_CTRL1_SELRES_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL1_SELRES_MASK) >> ADC12_ANA_CTRL1_SELRES_SHIFT)
854 
855 /* Bitfield definition for register: ANA_STATUS */
856 /*
857  * CALON (RW)
858  *
859  * Indicates if the ADC is in calibration mode (Active H).
860  */
861 #define ADC12_ANA_STATUS_CALON_MASK (0x80U)
862 #define ADC12_ANA_STATUS_CALON_SHIFT (7U)
863 #define ADC12_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC12_ANA_STATUS_CALON_SHIFT) & ADC12_ANA_STATUS_CALON_MASK)
864 #define ADC12_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC12_ANA_STATUS_CALON_MASK) >> ADC12_ANA_STATUS_CALON_SHIFT)
865 
866 /*
867  * CAL_OUT (RW)
868  *
869  */
870 #define ADC12_ANA_STATUS_CAL_OUT_MASK (0x7FU)
871 #define ADC12_ANA_STATUS_CAL_OUT_SHIFT (0U)
872 #define ADC12_ANA_STATUS_CAL_OUT_SET(x) (((uint32_t)(x) << ADC12_ANA_STATUS_CAL_OUT_SHIFT) & ADC12_ANA_STATUS_CAL_OUT_MASK)
873 #define ADC12_ANA_STATUS_CAL_OUT_GET(x) (((uint32_t)(x) & ADC12_ANA_STATUS_CAL_OUT_MASK) >> ADC12_ANA_STATUS_CAL_OUT_SHIFT)
874 
875 
876 
877 /* CONFIG register group index macro definition */
878 #define ADC12_CONFIG_TRG0A (0UL)
879 #define ADC12_CONFIG_TRG0B (1UL)
880 #define ADC12_CONFIG_TRG0C (2UL)
881 #define ADC12_CONFIG_TRG1A (3UL)
882 #define ADC12_CONFIG_TRG1B (4UL)
883 #define ADC12_CONFIG_TRG1C (5UL)
884 #define ADC12_CONFIG_TRG2A (6UL)
885 #define ADC12_CONFIG_TRG2B (7UL)
886 #define ADC12_CONFIG_TRG2C (8UL)
887 #define ADC12_CONFIG_TRG3A (9UL)
888 #define ADC12_CONFIG_TRG3B (10UL)
889 #define ADC12_CONFIG_TRG3C (11UL)
890 
891 /* BUS_RESULT register group index macro definition */
892 #define ADC12_BUS_RESULT_CHN0 (0UL)
893 #define ADC12_BUS_RESULT_CHN1 (1UL)
894 #define ADC12_BUS_RESULT_CHN2 (2UL)
895 #define ADC12_BUS_RESULT_CHN3 (3UL)
896 #define ADC12_BUS_RESULT_CHN4 (4UL)
897 #define ADC12_BUS_RESULT_CHN5 (5UL)
898 #define ADC12_BUS_RESULT_CHN6 (6UL)
899 #define ADC12_BUS_RESULT_CHN7 (7UL)
900 #define ADC12_BUS_RESULT_CHN8 (8UL)
901 #define ADC12_BUS_RESULT_CHN9 (9UL)
902 #define ADC12_BUS_RESULT_CHN10 (10UL)
903 #define ADC12_BUS_RESULT_CHN11 (11UL)
904 #define ADC12_BUS_RESULT_CHN12 (12UL)
905 #define ADC12_BUS_RESULT_CHN13 (13UL)
906 #define ADC12_BUS_RESULT_CHN14 (14UL)
907 #define ADC12_BUS_RESULT_CHN15 (15UL)
908 #define ADC12_BUS_RESULT_CHN16 (16UL)
909 #define ADC12_BUS_RESULT_CHN17 (17UL)
910 #define ADC12_BUS_RESULT_CHN18 (18UL)
911 
912 /* SEQ_QUE register group index macro definition */
913 #define ADC12_SEQ_QUE_CFG0 (0UL)
914 #define ADC12_SEQ_QUE_CFG1 (1UL)
915 #define ADC12_SEQ_QUE_CFG2 (2UL)
916 #define ADC12_SEQ_QUE_CFG3 (3UL)
917 #define ADC12_SEQ_QUE_CFG4 (4UL)
918 #define ADC12_SEQ_QUE_CFG5 (5UL)
919 #define ADC12_SEQ_QUE_CFG6 (6UL)
920 #define ADC12_SEQ_QUE_CFG7 (7UL)
921 #define ADC12_SEQ_QUE_CFG8 (8UL)
922 #define ADC12_SEQ_QUE_CFG9 (9UL)
923 #define ADC12_SEQ_QUE_CFG10 (10UL)
924 #define ADC12_SEQ_QUE_CFG11 (11UL)
925 #define ADC12_SEQ_QUE_CFG12 (12UL)
926 #define ADC12_SEQ_QUE_CFG13 (13UL)
927 #define ADC12_SEQ_QUE_CFG14 (14UL)
928 #define ADC12_SEQ_QUE_CFG15 (15UL)
929 
930 /* PRD_CFG register group index macro definition */
931 #define ADC12_PRD_CFG_CHN0 (0UL)
932 #define ADC12_PRD_CFG_CHN1 (1UL)
933 #define ADC12_PRD_CFG_CHN2 (2UL)
934 #define ADC12_PRD_CFG_CHN3 (3UL)
935 #define ADC12_PRD_CFG_CHN4 (4UL)
936 #define ADC12_PRD_CFG_CHN5 (5UL)
937 #define ADC12_PRD_CFG_CHN6 (6UL)
938 #define ADC12_PRD_CFG_CHN7 (7UL)
939 #define ADC12_PRD_CFG_CHN8 (8UL)
940 #define ADC12_PRD_CFG_CHN9 (9UL)
941 #define ADC12_PRD_CFG_CHN10 (10UL)
942 #define ADC12_PRD_CFG_CHN11 (11UL)
943 #define ADC12_PRD_CFG_CHN12 (12UL)
944 #define ADC12_PRD_CFG_CHN13 (13UL)
945 #define ADC12_PRD_CFG_CHN14 (14UL)
946 #define ADC12_PRD_CFG_CHN15 (15UL)
947 #define ADC12_PRD_CFG_CHN16 (16UL)
948 #define ADC12_PRD_CFG_CHN17 (17UL)
949 #define ADC12_PRD_CFG_CHN18 (18UL)
950 
951 /* SAMPLE_CFG register group index macro definition */
952 #define ADC12_SAMPLE_CFG_CHN0 (0UL)
953 #define ADC12_SAMPLE_CFG_CHN1 (1UL)
954 #define ADC12_SAMPLE_CFG_CHN2 (2UL)
955 #define ADC12_SAMPLE_CFG_CHN3 (3UL)
956 #define ADC12_SAMPLE_CFG_CHN4 (4UL)
957 #define ADC12_SAMPLE_CFG_CHN5 (5UL)
958 #define ADC12_SAMPLE_CFG_CHN6 (6UL)
959 #define ADC12_SAMPLE_CFG_CHN7 (7UL)
960 #define ADC12_SAMPLE_CFG_CHN8 (8UL)
961 #define ADC12_SAMPLE_CFG_CHN9 (9UL)
962 #define ADC12_SAMPLE_CFG_CHN10 (10UL)
963 #define ADC12_SAMPLE_CFG_CHN11 (11UL)
964 #define ADC12_SAMPLE_CFG_CHN12 (12UL)
965 #define ADC12_SAMPLE_CFG_CHN13 (13UL)
966 #define ADC12_SAMPLE_CFG_CHN14 (14UL)
967 #define ADC12_SAMPLE_CFG_CHN15 (15UL)
968 #define ADC12_SAMPLE_CFG_CHN16 (16UL)
969 #define ADC12_SAMPLE_CFG_CHN17 (17UL)
970 #define ADC12_SAMPLE_CFG_CHN18 (18UL)
971 
972 
973 #endif /* HPM_ADC12_H */
ADC12_Type
Definition: hpm_adc12_regs.h:12