hpm_conctl_regs.h File Reference

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Data Structures
struct	CONCTL_Type

Macros
#define	CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK   (0xF8000UL)
#define	CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT   (15U)
#define	CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK)
#define	CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT)
#define	CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK   (0x7C00U)
#define	CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT   (10U)
#define	CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK)
#define	CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT)
#define	CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK   (0x3E0U)
#define	CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT   (5U)
#define	CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK)
#define	CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT)
#define	CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK   (0x1FU)
#define	CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT   (0U)
#define	CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK)
#define	CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT)
#define	CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK   (0x20000000UL)
#define	CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT   (29U)
#define	CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK)
#define	CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT)
#define	CONCTL_CTRL2_ENET0_REFCLK_OE_MASK   (0x80000UL)
#define	CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT   (19U)
#define	CONCTL_CTRL2_ENET0_REFCLK_OE_SET(x)   (((uint32_t)(x) << CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK)
#define	CONCTL_CTRL2_ENET0_REFCLK_OE_GET(x)   (((uint32_t)(x) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) >> CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT)
#define	CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK   (0xE000U)
#define	CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT   (13U)
#define	CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK)
#define	CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) >> CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT)
#define	CONCTL_CTRL2_ENET0_FLOWCTRL_MASK   (0x1000U)
#define	CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT   (12U)
#define	CONCTL_CTRL2_ENET0_FLOWCTRL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK)
#define	CONCTL_CTRL2_ENET0_FLOWCTRL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) >> CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT)
#define	CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK   (0x400U)
#define	CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT   (10U)
#define	CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK)
#define	CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT)
#define	CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK   (0x20000000UL)
#define	CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT   (29U)
#define	CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK)
#define	CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) >> CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT)
#define	CONCTL_CTRL3_ENET1_REFCLK_OE_MASK   (0x80000UL)
#define	CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT   (19U)
#define	CONCTL_CTRL3_ENET1_REFCLK_OE_SET(x)   (((uint32_t)(x) << CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK)
#define	CONCTL_CTRL3_ENET1_REFCLK_OE_GET(x)   (((uint32_t)(x) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) >> CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT)
#define	CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK   (0xE000U)
#define	CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT   (13U)
#define	CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK)
#define	CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) >> CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT)
#define	CONCTL_CTRL3_ENET1_FLOWCTRL_MASK   (0x1000U)
#define	CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT   (12U)
#define	CONCTL_CTRL3_ENET1_FLOWCTRL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK)
#define	CONCTL_CTRL3_ENET1_FLOWCTRL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) >> CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT)
#define	CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK   (0x400U)
#define	CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT   (10U)
#define	CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK)
#define	CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT)
#define	CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK   (0x80000000UL)
#define	CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT   (31U)
#define	CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK)
#define	CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT)
#define	CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK   (0x40000000UL)
#define	CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT   (30U)
#define	CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK)
#define	CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT)
#define	CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK   (0x10000000UL)
#define	CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT   (28U)
#define	CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK)
#define	CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK   (0xF800000UL)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT   (23U)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK   (0x7C0000UL)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT   (18U)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK)
#define	CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT)
#define	CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK   (0x20000UL)
#define	CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT   (17U)
#define	CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK)
#define	CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK   (0x1F000UL)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT   (12U)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK   (0x800U)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT   (11U)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET(x)   (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK)
#define	CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET(x)   (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)
#define	CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK   (0x80000000UL)
#define	CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT   (31U)
#define	CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK)
#define	CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT)
#define	CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK   (0x40000000UL)
#define	CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT   (30U)
#define	CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK)
#define	CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT)
#define	CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK   (0x10000000UL)
#define	CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT   (28U)
#define	CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK)
#define	CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK   (0xF800000UL)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT   (23U)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK   (0x7C0000UL)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT   (18U)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK)
#define	CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT)
#define	CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK   (0x20000UL)
#define	CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT   (17U)
#define	CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK)
#define	CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK   (0x1F000UL)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT   (12U)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK   (0x800U)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT   (11U)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET(x)   (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK)
#define	CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET(x)   (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)

Macro Definition Documentation

CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET

#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT)

CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK

#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK   (0x3E0U)

CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET

#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK)

CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT

#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT   (5U)

CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET

#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT)

CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK

#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK   (0x1FU)

CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET

#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK)

CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT

#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT   (0U)

CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET

#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT)

CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK

#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK   (0xF8000UL)

CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET

#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK)

CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT

#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT   (15U)

CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET

#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT)

CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK

#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK   (0x7C00U)

CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET

#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK)

CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT

#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT   (10U)

CONCTL_CTRL2_ENET0_FLOWCTRL_GET

#define CONCTL_CTRL2_ENET0_FLOWCTRL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) >> CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT)

CONCTL_CTRL2_ENET0_FLOWCTRL_MASK

#define CONCTL_CTRL2_ENET0_FLOWCTRL_MASK   (0x1000U)

CONCTL_CTRL2_ENET0_FLOWCTRL_SET

#define CONCTL_CTRL2_ENET0_FLOWCTRL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK)

CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT

#define CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT   (12U)

CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET

#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT)

CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK

#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK   (0x20000000UL)

CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET

#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK)

CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT

#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT   (29U)

CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET

#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) >> CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT)

CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK

#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK   (0xE000U)

CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET

#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK)

CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT

#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT   (13U)

CONCTL_CTRL2_ENET0_REFCLK_OE_GET

#define CONCTL_CTRL2_ENET0_REFCLK_OE_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) >> CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT)

CONCTL_CTRL2_ENET0_REFCLK_OE_MASK

#define CONCTL_CTRL2_ENET0_REFCLK_OE_MASK   (0x80000UL)

CONCTL_CTRL2_ENET0_REFCLK_OE_SET

#define CONCTL_CTRL2_ENET0_REFCLK_OE_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK)

CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT

#define CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT   (19U)

CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET

#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT)

CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK

#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK   (0x400U)

CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET

#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK)

CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT

#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT   (10U)

CONCTL_CTRL3_ENET1_FLOWCTRL_GET

#define CONCTL_CTRL3_ENET1_FLOWCTRL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) >> CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT)

CONCTL_CTRL3_ENET1_FLOWCTRL_MASK

#define CONCTL_CTRL3_ENET1_FLOWCTRL_MASK   (0x1000U)

CONCTL_CTRL3_ENET1_FLOWCTRL_SET

#define CONCTL_CTRL3_ENET1_FLOWCTRL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK)

CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT

#define CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT   (12U)

CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET

#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) >> CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT)

CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK

#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK   (0x20000000UL)

CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET

#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK)

CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT

#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT   (29U)

CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET

#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) >> CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT)

CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK

#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK   (0xE000U)

CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET

#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK)

CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT

#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT   (13U)

CONCTL_CTRL3_ENET1_REFCLK_OE_GET

#define CONCTL_CTRL3_ENET1_REFCLK_OE_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) >> CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT)

CONCTL_CTRL3_ENET1_REFCLK_OE_MASK

#define CONCTL_CTRL3_ENET1_REFCLK_OE_MASK   (0x80000UL)

CONCTL_CTRL3_ENET1_REFCLK_OE_SET

#define CONCTL_CTRL3_ENET1_REFCLK_OE_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK)

CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT

#define CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT   (19U)

CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET

#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT)

CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK

#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK   (0x400U)

CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET

#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK)

CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT

#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT   (10U)

CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET

#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT)

CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK

#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK   (0x10000000UL)

CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET

#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK)

CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT

#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT   (28U)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK   (0x800U)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT   (11U)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK   (0x1F000UL)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK)

CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT

#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT   (12U)

CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET

#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT)

CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK

#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK   (0x20000UL)

CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET

#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK)

CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT

#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT   (17U)

CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT)

CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK   (0xF800000UL)

CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK)

CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT   (23U)

CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT)

CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK   (0x7C0000UL)

CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK)

CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT

#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT   (18U)

CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET

#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT)

CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK

#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK   (0x80000000UL)

CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET

#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK)

CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT

#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT   (31U)

CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET

#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT)

CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK

#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK   (0x40000000UL)

CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET

#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK)

CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT

#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT   (30U)

CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET

#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT)

CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK

#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK   (0x10000000UL)

CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET

#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK)

CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT

#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT   (28U)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK   (0x800U)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT   (11U)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK   (0x1F000UL)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK)

CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT

#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT   (12U)

CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET

#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT)

CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK

#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK   (0x20000UL)

CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET

#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK)

CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT

#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT   (17U)

CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT)

CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK   (0xF800000UL)

CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK)

CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT   (23U)

CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT)

CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK   (0x7C0000UL)

CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK)

CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT

#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT   (18U)

CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET

#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT)

CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK

#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK   (0x80000000UL)

CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET

#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK)

CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT

#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT   (31U)

CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET

#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET

(

x

)

(((uint32_t)(x) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT)

CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK

#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK   (0x40000000UL)

CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET

#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET

(

x

)

(((uint32_t)(x) << CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK)

CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT

#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT   (30U)