HPM SDK
HPMicro Software Development Kit
hpm_dp83848_regs.h
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1 /*
2  * Copyright (c) 2021-2022 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DP83848_REGS_H
10 #define HPM_DP83848_REGS_H
11 
12 typedef enum {
13  DP83848_BMCR = 0, /* 0x0: Basic Mode Control Register */
14  DP83848_BMSR = 1, /* 0x1: Basic Mode Status Register */
15  DP83848_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */
16  DP83848_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */
17  DP83848_ANAR = 4, /* 0x4: Auto-Negotiation Advertisement Register */
18  DP83848_ANLPAR_BP = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */
19  DP83848_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */
20  DP83848_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */
21  DP83848_PHYSTS = 16, /* 0x10: PHY Status Register */
22  DP83848_FCSCR = 20, /* 0x14: False Carrier Sense Counter Register */
23  DP83848_RECR = 21, /* 0x15: Receiver Error Counter Register */
24  DP83848_PCSR = 22, /* 0x16: 100 Mb/s PCS Configuration and Status Register */
25  DP83848_RBR = 23, /* 0x17: RMII and Bypass Register */
26  DP83848_LEDCR = 24, /* 0x18: LED Direct Control Register */
27  DP83848_PHYCR = 25, /* 0x19: PHY Control Register */
28  DP83848_10BTSCR = 26, /* 0x1A: 10BASE-T Status/Control Register */
29  DP83848_CDCTRL1 = 27, /* 0x1B: CD Test and BIST Extensions Register */
30  DP83848_EDCR = 29, /* 0x1D: Energy Detect Control */
31 } DP83848_REG_Type;
32 
33 
34 /* Bitfield definition for register: BMCR */
35 /*
36  * RESET (RW/SC)
37  *
38  * Reset:
39  * 1 = Initiate software Reset / Reset in Process.
40  * 0 = Normal operation.
41  * This bit, which is self-clearing, returns a value of one until the reset process is complete. The
42  * configuration is re-strapped.
43  */
44 #define DP83848_BMCR_RESET_MASK (0x8000U)
45 #define DP83848_BMCR_RESET_SHIFT (15U)
46 #define DP83848_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK)
47 #define DP83848_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT)
48 
49 /*
50  * LOOPBACK (RW)
51  *
52  * Loopback:
53  * 1 = Loopback enabled.
54  * 0 = Normal operation.
55  * The loopback function enables MII transmit data to be routed to the MII receive data path.
56  * Setting this bit may cause the descrambler to lose synchronization and produce a 500 µs “dead
57  * time” before any valid data will appear at the MII receive outputs.
58  */
59 #define DP83848_BMCR_LOOPBACK_MASK (0x4000U)
60 #define DP83848_BMCR_LOOPBACK_SHIFT (14U)
61 #define DP83848_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK)
62 #define DP83848_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT)
63 
64 /*
65  * SPEED0 (RW)
66  *
67  * Speed Select:
68  * When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
69  * 1 = 100 Mb/s.
70  * 0 = 10 Mb/s.
71  */
72 #define DP83848_BMCR_SPEED0_MASK (0x2000U)
73 #define DP83848_BMCR_SPEED0_SHIFT (13U)
74 #define DP83848_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK)
75 #define DP83848_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT)
76 
77 /*
78  * ANE (RW)
79  *
80  * Auto-Negotiation Enable:
81  * Strap controls initial value at reset.
82  * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set.
83  * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode.
84  */
85 #define DP83848_BMCR_ANE_MASK (0x1000U)
86 #define DP83848_BMCR_ANE_SHIFT (12U)
87 #define DP83848_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK)
88 #define DP83848_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT)
89 
90 /*
91  * PWD (RW)
92  *
93  * Power Down:
94  * 1 = Power down.
95  * 0 = Normal operation.
96  * Setting this bit powers down the PHY. Only the register block is enabled during a power-down
97  * condition.
98  */
99 #define DP83848_BMCR_PWD_MASK (0x800U)
100 #define DP83848_BMCR_PWD_SHIFT (11U)
101 #define DP83848_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK)
102 #define DP83848_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT)
103 
104 /*
105  * ISOLATE (RW)
106  *
107  * Isolate:
108  * 1 = Isolates the Port from the MII with the exception of the serial management.
109  * 0 = Normal operation.
110  */
111 #define DP83848_BMCR_ISOLATE_MASK (0x400U)
112 #define DP83848_BMCR_ISOLATE_SHIFT (10U)
113 #define DP83848_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK)
114 #define DP83848_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT)
115 
116 /*
117  * RESTART_AN (RW/SC)
118  *
119  * Restart Auto-Negotiation:
120  * 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is
121  * disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until
122  * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation
123  * process is not affected by the management entity clearing this bit.
124  * 0 = Normal operation.
125  */
126 #define DP83848_BMCR_RESTART_AN_MASK (0x200U)
127 #define DP83848_BMCR_RESTART_AN_SHIFT (9U)
128 #define DP83848_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK)
129 #define DP83848_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT)
130 
131 /*
132  * DUPLEX (RW)
133  *
134  * Duplex Mode:
135  * When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be
136  * selected.
137  * 1 = Full Duplex operation.
138  * 0 = Half Duplex operation.
139  */
140 #define DP83848_BMCR_DUPLEX_MASK (0x100U)
141 #define DP83848_BMCR_DUPLEX_SHIFT (8U)
142 #define DP83848_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK)
143 #define DP83848_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT)
144 
145 /*
146  * COLLISION_TEST (RW)
147  *
148  * Collision Test:
149  * 1 = Collision test enabled.
150  * 0 = Normal operation.
151  * When set, this bit will cause the COL signal to be asserted in response to the assertion of
152  * TX_EN within 512-bit times. The COL signal will be deasserted within 4-bit times in response to
153  * the deassertion of TX_EN.
154  */
155 #define DP83848_BMCR_COLLISION_TEST_MASK (0x80U)
156 #define DP83848_BMCR_COLLISION_TEST_SHIFT (7U)
157 #define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK)
158 #define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT)
159 
160 /* Bitfield definition for register: BMSR */
161 /*
162  * 100BASE_TX_FULL_DUPLEX (RO)
163  *
164  * 100BASE-TX Full Duplex Capable:
165  * 1 = Device able to perform 100BASE-TX in full duplex mode.
166  */
167 #define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U)
168 #define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U)
169 #define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT)
170 
171 /*
172  * 100BASE_TX_HALF (RO)
173  *
174  * 100BASE-TX Half Duplex Capable:
175  * 1 = Device able to perform 100BASE-TX in half duplex mode.
176  */
177 #define DP83848_BMSR_100BASE_TX_HALF_MASK (0x2000U)
178 #define DP83848_BMSR_100BASE_TX_HALF_SHIFT (13U)
179 #define DP83848_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_HALF_MASK) >> DP83848_BMSR_100BASE_TX_HALF_SHIFT)
180 
181 /*
182  * 10BASE_T_FULL_DUPLEX (RO)
183  *
184  * 10BASE-T Full Duplex Capable:
185  * 1 = Device able to perform 10BASE-T in full duplex mode.
186  */
187 #define DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK (0x1000U)
188 #define DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT (12U)
189 #define DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT)
190 
191 /*
192  * 10BASE_T_HALF_DUPLEX (RO)
193  *
194  * 10BASE-T Half Duplex Capable:
195  * 1 = Device able to perform 10BASE-T in half duplex mode.
196  */
197 #define DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK (0x800U)
198 #define DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT (11U)
199 #define DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT)
200 
201 /*
202  * MF_PREAMBLE_SUPPRESSION (RO)
203  *
204  * Preamble suppression Capable:
205  * 1 = Device able to perform management transaction with preamble suppressed, 32-bits of
206  * preamble needed only once after reset, invalid opcode or invalid turnaround.
207  * 0 = Normal management operation.
208  */
209 #define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U)
210 #define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U)
211 #define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT)
212 
213 /*
214  * AUTO_NEGOTIATION_COMPLETE (RO)
215  *
216  * Auto-Negotiation Complete:
217  * 1 = Auto-Negotiation process complete.
218  * 0 = Auto-Negotiation process not complete.
219  */
220 #define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U)
221 #define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U)
222 #define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT)
223 
224 /*
225  * REMOTE_FAULT (RO)
226  *
227  * Remote Fault:
228  * 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Notification from
229  * Link Partner of Remote Fault.
230  * 0 = No remote fault condition detected.
231  */
232 #define DP83848_BMSR_REMOTE_FAULT_MASK (0x10U)
233 #define DP83848_BMSR_REMOTE_FAULT_SHIFT (4U)
234 #define DP83848_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_BMSR_REMOTE_FAULT_MASK) >> DP83848_BMSR_REMOTE_FAULT_SHIFT)
235 
236 /*
237  * AUTO_NEGOTIATION_ABILITY (RO)
238  *
239  * Auto Negotiation Ability:
240  * 1 = Device is able to perform Auto-Negotiation.
241  * 0 = Device is not able to perform Auto-Negotiation.
242  */
243 #define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U)
244 #define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U)
245 #define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT)
246 
247 /*
248  * LINK_STATUS (RO)
249  *
250  * Link Status:
251  * 1 = Valid link established (for either 10 or 100 Mb/s operation).
252  * 0 = Link not established.
253  * The criteria for link validity is implementation specific. The occurrence of a link failure condition
254  * will causes the Link Status bit to clear. Once cleared, this bit may only be set by establishing a
255  * good link condition and a read through the management interface.
256  */
257 #define DP83848_BMSR_LINK_STATUS_MASK (0x4U)
258 #define DP83848_BMSR_LINK_STATUS_SHIFT (2U)
259 #define DP83848_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_BMSR_LINK_STATUS_MASK) >> DP83848_BMSR_LINK_STATUS_SHIFT)
260 
261 /*
262  * JABBER_DETECT (RO)
263  *
264  * Jabber Detect: This bit only has meaning in 10 Mb/s mode.
265  * 1 = Jabber condition detected.
266  * 0 = No Jabber.
267  * This bit is implemented with a latching function, such that the occurrence of a jabber condition
268  * causes it to set until it is cleared by a read to this register by the management interface or by a
269  * reset.
270  */
271 #define DP83848_BMSR_JABBER_DETECT_MASK (0x2U)
272 #define DP83848_BMSR_JABBER_DETECT_SHIFT (1U)
273 #define DP83848_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_BMSR_JABBER_DETECT_MASK) >> DP83848_BMSR_JABBER_DETECT_SHIFT)
274 
275 /*
276  * EXTENDED_CAPABILITY (RO)
277  *
278  * Extended Capability:
279  * 1 = Extended register capabilities.
280  * 0 = Basic register set capabilities only.
281  */
282 #define DP83848_BMSR_EXTENDED_CAPABILITY_MASK (0x1U)
283 #define DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT (0U)
284 #define DP83848_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT)
285 
286 /* Bitfield definition for register: PHYIDR1 */
287 /*
288  * OUI_MSB (RO)
289  *
290  * OUI Most Significant Bits:
291  * Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most
292  * significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and
293  * 2).
294  */
295 #define DP83848_PHYIDR1_OUI_MSB_MASK (0xFFFFU)
296 #define DP83848_PHYIDR1_OUI_MSB_SHIFT (0U)
297 #define DP83848_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR1_OUI_MSB_MASK) >> DP83848_PHYIDR1_OUI_MSB_SHIFT)
298 
299 /* Bitfield definition for register: PHYIDR2 */
300 /*
301  * OUI_LSB (RO)
302  *
303  * OUI Least Significant Bits:
304  * Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register
305  * respectively.
306  */
307 #define DP83848_PHYIDR2_OUI_LSB_MASK (0xFC00U)
308 #define DP83848_PHYIDR2_OUI_LSB_SHIFT (10U)
309 #define DP83848_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_OUI_LSB_MASK) >> DP83848_PHYIDR2_OUI_LSB_SHIFT)
310 
311 /*
312  * VNDR_MDL (RO)
313  *
314  * Vendor Model Number:
315  * The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit
316  * 9).
317  */
318 #define DP83848_PHYIDR2_VNDR_MDL_MASK (0x3F0U)
319 #define DP83848_PHYIDR2_VNDR_MDL_SHIFT (4U)
320 #define DP83848_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_VNDR_MDL_MASK) >> DP83848_PHYIDR2_VNDR_MDL_SHIFT)
321 
322 /*
323  * MDL_REV (RO)
324  *
325  * Model Revision Number:
326  * Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant
327  * bit to bit 3). This field will be incremented for all major device changes.
328  */
329 #define DP83848_PHYIDR2_MDL_REV_MASK (0xFU)
330 #define DP83848_PHYIDR2_MDL_REV_SHIFT (0U)
331 #define DP83848_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_MDL_REV_MASK) >> DP83848_PHYIDR2_MDL_REV_SHIFT)
332 
333 /* Bitfield definition for register: ANAR */
334 /*
335  * NP (RW)
336  *
337  * Next Page Indication:
338  * 0 = Next Page Transfer not desired.
339  * 1 = Next Page Transfer desired.
340  */
341 #define DP83848_ANAR_NP_MASK (0x8000U)
342 #define DP83848_ANAR_NP_SHIFT (15U)
343 #define DP83848_ANAR_NP_SET(x) (((uint16_t)(x) << DP83848_ANAR_NP_SHIFT) & DP83848_ANAR_NP_MASK)
344 #define DP83848_ANAR_NP_GET(x) (((uint16_t)(x) & DP83848_ANAR_NP_MASK) >> DP83848_ANAR_NP_SHIFT)
345 
346 /*
347  * RF (RW)
348  *
349  * Remote Fault:
350  * 1 = Advertises that this device has detected a Remote Fault.
351  * 0 = No Remote Fault detected.
352  */
353 #define DP83848_ANAR_RF_MASK (0x2000U)
354 #define DP83848_ANAR_RF_SHIFT (13U)
355 #define DP83848_ANAR_RF_SET(x) (((uint16_t)(x) << DP83848_ANAR_RF_SHIFT) & DP83848_ANAR_RF_MASK)
356 #define DP83848_ANAR_RF_GET(x) (((uint16_t)(x) & DP83848_ANAR_RF_MASK) >> DP83848_ANAR_RF_SHIFT)
357 
358 /*
359  * ASM_DIR (RW)
360  *
361  * Asymmetric PAUSE Support for Full Duplex Links:
362  * The ASM_DIR bit indicates that asymmetric PAUSE is supported.
363  * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and
364  * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
365  * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer
366  * and the pause function as specified in clause 31 and annex 31B of 802.3.
367  * 0= No MAC based full duplex flow control.
368  */
369 #define DP83848_ANAR_ASM_DIR_MASK (0x800U)
370 #define DP83848_ANAR_ASM_DIR_SHIFT (11U)
371 #define DP83848_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83848_ANAR_ASM_DIR_SHIFT) & DP83848_ANAR_ASM_DIR_MASK)
372 #define DP83848_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANAR_ASM_DIR_MASK) >> DP83848_ANAR_ASM_DIR_SHIFT)
373 
374 /*
375  * PAUSE (RW)
376  *
377  * PAUSE Support for Full Duplex Links:
378  * The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE
379  * functions as defined in Annex 31B.
380  * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and
381  * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
382  * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer
383  * and the pause function as specified in clause 31 and annex 31B of 802.3.
384  * 0= No MAC based full duplex flow control.
385  */
386 #define DP83848_ANAR_PAUSE_MASK (0x400U)
387 #define DP83848_ANAR_PAUSE_SHIFT (10U)
388 #define DP83848_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83848_ANAR_PAUSE_SHIFT) & DP83848_ANAR_PAUSE_MASK)
389 #define DP83848_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANAR_PAUSE_MASK) >> DP83848_ANAR_PAUSE_SHIFT)
390 
391 /*
392  * T4 (RO)
393  *
394  * 100BASE-T4 Support:
395  * 1= 100BASE-T4 is supported by the local device.
396  * 0 = 100BASE-T4 not supported.
397  */
398 #define DP83848_ANAR_T4_MASK (0x200U)
399 #define DP83848_ANAR_T4_SHIFT (9U)
400 #define DP83848_ANAR_T4_GET(x) (((uint16_t)(x) & DP83848_ANAR_T4_MASK) >> DP83848_ANAR_T4_SHIFT)
401 
402 /*
403  * TX_FD (RW)
404  *
405  * 100BASE-TX Full Duplex Support:
406  * 1 = 100BASE-TX Full Duplex is supported by the local device.
407  * 0 = 100BASE-TX Full Duplex not supported.
408  */
409 #define DP83848_ANAR_TX_FD_MASK (0x100U)
410 #define DP83848_ANAR_TX_FD_SHIFT (8U)
411 #define DP83848_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_FD_SHIFT) & DP83848_ANAR_TX_FD_MASK)
412 #define DP83848_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_FD_MASK) >> DP83848_ANAR_TX_FD_SHIFT)
413 
414 /*
415  * TX (RW)
416  *
417  * 100BASE-TX Support:
418  * 1 = 100BASE-TX is supported by the local device.
419  * 0 = 100BASE-TX not supported.
420  */
421 #define DP83848_ANAR_TX_MASK (0x80U)
422 #define DP83848_ANAR_TX_SHIFT (7U)
423 #define DP83848_ANAR_TX_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_SHIFT) & DP83848_ANAR_TX_MASK)
424 #define DP83848_ANAR_TX_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_MASK) >> DP83848_ANAR_TX_SHIFT)
425 
426 /*
427  * 10_FD (RW)
428  *
429  * 10BASE-T Full Duplex Support:
430  * 1 = 10BASE-T Full Duplex is supported by the local device.
431  * 0 = 10BASE-T Full Duplex not supported.
432  */
433 #define DP83848_ANAR_10_FD_MASK (0x40U)
434 #define DP83848_ANAR_10_FD_SHIFT (6U)
435 #define DP83848_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_FD_SHIFT) & DP83848_ANAR_10_FD_MASK)
436 #define DP83848_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_FD_MASK) >> DP83848_ANAR_10_FD_SHIFT)
437 
438 /*
439  * 10 (RW)
440  *
441  * 10BASE-T Support:
442  * 1 = 10BASE-T is supported by the local device.
443  * 0 = 10BASE-T not supported.
444  */
445 #define DP83848_ANAR_10_MASK (0x20U)
446 #define DP83848_ANAR_10_SHIFT (5U)
447 #define DP83848_ANAR_10_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_SHIFT) & DP83848_ANAR_10_MASK)
448 #define DP83848_ANAR_10_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_MASK) >> DP83848_ANAR_10_SHIFT)
449 
450 /*
451  * SELECTOR (RW)
452  *
453  * Protocol Selection Bits:
454  * These bits contain the binary encoded protocol selector supported by this port. <00001>
455  * indicates that this device supports IEEE 802.3.
456  */
457 #define DP83848_ANAR_SELECTOR_MASK (0x1FU)
458 #define DP83848_ANAR_SELECTOR_SHIFT (0U)
459 #define DP83848_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83848_ANAR_SELECTOR_SHIFT) & DP83848_ANAR_SELECTOR_MASK)
460 #define DP83848_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANAR_SELECTOR_MASK) >> DP83848_ANAR_SELECTOR_SHIFT)
461 
462 /* Bitfield definition for register: ANLPAR_BP */
463 /*
464  * NP (RO)
465  *
466  * Next Page Indication:
467  * 0 = Link Partner does not desire Next Page Transfer.
468  * 1 = Link Partner desires Next Page Transfer.
469  */
470 #define DP83848_ANLPAR_BP_NP_MASK (0x8000U)
471 #define DP83848_ANLPAR_BP_NP_SHIFT (15U)
472 #define DP83848_ANLPAR_BP_NP_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_NP_MASK) >> DP83848_ANLPAR_BP_NP_SHIFT)
473 
474 /*
475  * ACK (RO)
476  *
477  * Acknowledge:
478  * 1 = Link Partner acknowledges reception of the ability data word.
479  * 0 = Not acknowledged.
480  * The Auto-Negotiation state machine will automatically control the this bit based on the incoming
481  * FLP bursts.
482  */
483 #define DP83848_ANLPAR_BP_ACK_MASK (0x4000U)
484 #define DP83848_ANLPAR_BP_ACK_SHIFT (14U)
485 #define DP83848_ANLPAR_BP_ACK_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ACK_MASK) >> DP83848_ANLPAR_BP_ACK_SHIFT)
486 
487 /*
488  * RF (RO)
489  *
490  * Remote Fault:
491  * 1 = Remote Fault indicated by Link Partner.
492  * 0 = No Remote Fault indicated by Link Partner.
493  */
494 #define DP83848_ANLPAR_BP_RF_MASK (0x2000U)
495 #define DP83848_ANLPAR_BP_RF_SHIFT (13U)
496 #define DP83848_ANLPAR_BP_RF_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_RF_MASK) >> DP83848_ANLPAR_BP_RF_SHIFT)
497 
498 /*
499  * ASM_DIR (RO)
500  *
501  * ASYMMETRIC PAUSE:
502  * 1 = Asymmetric pause is supported by the Link Partner.
503  * 0 = Asymmetric pause is not supported by the Link Partner.
504  */
505 #define DP83848_ANLPAR_BP_ASM_DIR_MASK (0x800U)
506 #define DP83848_ANLPAR_BP_ASM_DIR_SHIFT (11U)
507 #define DP83848_ANLPAR_BP_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ASM_DIR_MASK) >> DP83848_ANLPAR_BP_ASM_DIR_SHIFT)
508 
509 /*
510  * PAUSE (RO)
511  *
512  * PAUSE:
513  * 1 = Pause function is supported by the Link Partner.
514  * 0 = Pause function is not supported by the Link Partner.
515  */
516 #define DP83848_ANLPAR_BP_PAUSE_MASK (0x400U)
517 #define DP83848_ANLPAR_BP_PAUSE_SHIFT (10U)
518 #define DP83848_ANLPAR_BP_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_PAUSE_MASK) >> DP83848_ANLPAR_BP_PAUSE_SHIFT)
519 
520 /*
521  * T4 (RO)
522  *
523  * 100BASE-T4 Support:
524  * 1 = 100BASE-T4 is supported by the Link Partner.
525  * 0 = 100BASE-T4 not supported by the Link Partner.
526  */
527 #define DP83848_ANLPAR_BP_T4_MASK (0x200U)
528 #define DP83848_ANLPAR_BP_T4_SHIFT (9U)
529 #define DP83848_ANLPAR_BP_T4_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_T4_MASK) >> DP83848_ANLPAR_BP_T4_SHIFT)
530 
531 /*
532  * TX_FD (RO)
533  *
534  * 100BASE-TX Full Duplex Support:
535  * 1 = 100BASE-TX Full Duplex is supported by the Link Partner.
536  * 0 = 100BASE-TX Full Duplex not supported by the Link Partner.
537  */
538 #define DP83848_ANLPAR_BP_TX_FD_MASK (0x100U)
539 #define DP83848_ANLPAR_BP_TX_FD_SHIFT (8U)
540 #define DP83848_ANLPAR_BP_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_FD_MASK) >> DP83848_ANLPAR_BP_TX_FD_SHIFT)
541 
542 /*
543  * TX (RO)
544  *
545  * 100BASE-TX Support:
546  * 1 = 100BASE-TX is supported by the Link Partner.
547  * 0 = 100BASE-TX not supported by the Link Partner.
548  */
549 #define DP83848_ANLPAR_BP_TX_MASK (0x80U)
550 #define DP83848_ANLPAR_BP_TX_SHIFT (7U)
551 #define DP83848_ANLPAR_BP_TX_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_MASK) >> DP83848_ANLPAR_BP_TX_SHIFT)
552 
553 /*
554  * 10_FD (RO)
555  *
556  * 10BASE-T Full Duplex Support:
557  * 1 = 10BASE-T Full Duplex is supported by the Link Partner.
558  * 0 = 10BASE-T Full Duplex not supported by the Link Partner.
559  */
560 #define DP83848_ANLPAR_BP_10_FD_MASK (0x40U)
561 #define DP83848_ANLPAR_BP_10_FD_SHIFT (6U)
562 #define DP83848_ANLPAR_BP_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_FD_MASK) >> DP83848_ANLPAR_BP_10_FD_SHIFT)
563 
564 /*
565  * 10 (RO)
566  *
567  * 10BASE-T Support:
568  * 1 = 10BASE-T is supported by the Link Partner.
569  * 0 = 10BASE-T not supported by the Link Partner.
570  */
571 #define DP83848_ANLPAR_BP_10_MASK (0x20U)
572 #define DP83848_ANLPAR_BP_10_SHIFT (5U)
573 #define DP83848_ANLPAR_BP_10_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_MASK) >> DP83848_ANLPAR_BP_10_SHIFT)
574 
575 /*
576  * SELECTOR (RO)
577  *
578  * Protocol Selection Bits:
579  * Link Partner’s binary encoded protocol selector.
580  */
581 #define DP83848_ANLPAR_BP_SELECTOR_MASK (0x1FU)
582 #define DP83848_ANLPAR_BP_SELECTOR_SHIFT (0U)
583 #define DP83848_ANLPAR_BP_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_SELECTOR_MASK) >> DP83848_ANLPAR_BP_SELECTOR_SHIFT)
584 
585 /* Bitfield definition for register: ANER */
586 /*
587  * PDF (RO)
588  *
589  * Parallel Detection Fault:
590  * 1 = A fault has been detected through the Parallel Detection function.
591  * 0 = A fault has not been detected.
592  */
593 #define DP83848_ANER_PDF_MASK (0x10U)
594 #define DP83848_ANER_PDF_SHIFT (4U)
595 #define DP83848_ANER_PDF_GET(x) (((uint16_t)(x) & DP83848_ANER_PDF_MASK) >> DP83848_ANER_PDF_SHIFT)
596 
597 /*
598  * LP_NP_ABLE (RO)
599  *
600  * Link Partner Next Page Able:
601  * 1 = Link Partner does support Next Page.
602  * 0 = Link Partner does not support Next Page.
603  */
604 #define DP83848_ANER_LP_NP_ABLE_MASK (0x8U)
605 #define DP83848_ANER_LP_NP_ABLE_SHIFT (3U)
606 #define DP83848_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_NP_ABLE_MASK) >> DP83848_ANER_LP_NP_ABLE_SHIFT)
607 
608 /*
609  * NP_ABLE (RO)
610  *
611  * Next Page Able:
612  * 1 = Indicates local device is able to send additional “Next Pages”.
613  */
614 #define DP83848_ANER_NP_ABLE_MASK (0x4U)
615 #define DP83848_ANER_NP_ABLE_SHIFT (2U)
616 #define DP83848_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_NP_ABLE_MASK) >> DP83848_ANER_NP_ABLE_SHIFT)
617 
618 /*
619  * PAGE_RX (RO)
620  *
621  * Link Code Word Page Received:
622  * 1 = Link Code Word has been received, cleared on a read.
623  * 0 = Link Code Word has not been received.
624  */
625 #define DP83848_ANER_PAGE_RX_MASK (0x2U)
626 #define DP83848_ANER_PAGE_RX_SHIFT (1U)
627 #define DP83848_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83848_ANER_PAGE_RX_MASK) >> DP83848_ANER_PAGE_RX_SHIFT)
628 
629 /*
630  * LP_AN_ABLE (RO)
631  *
632  * Link Partner Auto-Negotiation Able:
633  * 1 = indicates that the Link Partner supports Auto-Negotiation.
634  * 0 = indicates that the Link Partner does not support Auto-Negotiation.
635  */
636 #define DP83848_ANER_LP_AN_ABLE_MASK (0x1U)
637 #define DP83848_ANER_LP_AN_ABLE_SHIFT (0U)
638 #define DP83848_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_AN_ABLE_MASK) >> DP83848_ANER_LP_AN_ABLE_SHIFT)
639 
640 /* Bitfield definition for register: ANNPTR */
641 /*
642  * NP (RW)
643  *
644  * Next Page Indication:
645  * 0 = No other Next Page Transfer desired.
646  * 1 = Another Next Page desired.
647  */
648 #define DP83848_ANNPTR_NP_MASK (0x8000U)
649 #define DP83848_ANNPTR_NP_SHIFT (15U)
650 #define DP83848_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_NP_SHIFT) & DP83848_ANNPTR_NP_MASK)
651 #define DP83848_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_NP_MASK) >> DP83848_ANNPTR_NP_SHIFT)
652 
653 /*
654  * MP (RW)
655  *
656  * Message Page:
657  * 1 = Message Page.
658  * 0 = Unformatted Page.
659  */
660 #define DP83848_ANNPTR_MP_MASK (0x2000U)
661 #define DP83848_ANNPTR_MP_SHIFT (13U)
662 #define DP83848_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_MP_SHIFT) & DP83848_ANNPTR_MP_MASK)
663 #define DP83848_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_MP_MASK) >> DP83848_ANNPTR_MP_SHIFT)
664 
665 /*
666  * ACK2 (RW)
667  *
668  * Acknowledge2:
669  * 1 = Will comply with message.
670  * 0 = Cannot comply with message.
671  * Acknowledge2 is used by the next page function to indicate that Local Device has the ability
672  * to comply with the message received.
673  */
674 #define DP83848_ANNPTR_ACK2_MASK (0x1000U)
675 #define DP83848_ANNPTR_ACK2_SHIFT (12U)
676 #define DP83848_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_ACK2_SHIFT) & DP83848_ANNPTR_ACK2_MASK)
677 #define DP83848_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_ACK2_MASK) >> DP83848_ANNPTR_ACK2_SHIFT)
678 
679 /*
680  * TOG_TX (RW)
681  *
682  * Toggle:
683  * 1 = Value of toggle bit in previously transmitted Link Code Word was 0.
684  * 0 = Value of toggle bit in previously transmitted Link Code Word was 1.
685  * Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization
686  * with the Link Partner during Next Page exchange. This bit shall always take the opposite
687  * value of the Toggle bit in the previously exchanged Link Code Word.
688  */
689 #define DP83848_ANNPTR_TOG_TX_MASK (0x800U)
690 #define DP83848_ANNPTR_TOG_TX_SHIFT (11U)
691 #define DP83848_ANNPTR_TOG_TX_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_TOG_TX_SHIFT) & DP83848_ANNPTR_TOG_TX_MASK)
692 #define DP83848_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_TOG_TX_MASK) >> DP83848_ANNPTR_TOG_TX_SHIFT)
693 
694 /*
695  * CODE (RW)
696  *
697  * This field represents the code field of the next page transmission. If the MP bit is set (bit 13
698  * of this register), then the code shall be interpreted as a "Message Page”, as defined in annex
699  * 28C of IEEE 802.3. Otherwise, the code shall be interpreted as an "Unformatted Page”, and
700  * the interpretation is application specific.
701  * The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE
702  * 802.3.
703  */
704 #define DP83848_ANNPTR_CODE_MASK (0x400U)
705 #define DP83848_ANNPTR_CODE_SHIFT (10U)
706 #define DP83848_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_CODE_SHIFT) & DP83848_ANNPTR_CODE_MASK)
707 #define DP83848_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_CODE_MASK) >> DP83848_ANNPTR_CODE_SHIFT)
708 
709 /* Bitfield definition for register: PHYSTS */
710 /*
711  * MDI_X_MODE (RO)
712  *
713  * MDI-X mode as reported by the Auto-Negotiation logic:
714  * This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the
715  * PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as
716  * the Auto-MDIX algorithm swaps between MDI and MDI-X configurations.
717  * 1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)
718  * 0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)
719  */
720 #define DP83848_PHYSTS_MDI_X_MODE_MASK (0x4000U)
721 #define DP83848_PHYSTS_MDI_X_MODE_SHIFT (14U)
722 #define DP83848_PHYSTS_MDI_X_MODE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_MDI_X_MODE_MASK) >> DP83848_PHYSTS_MDI_X_MODE_SHIFT)
723 
724 /*
725  * RECEIVE_ERRORLATCH (RO)
726  *
727  * Receive Error Latch:
728  * This bit will be cleared upon a read of the RECR register.
729  * 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0).
730  * 0 = No receive error event has occurred.
731  */
732 #define DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK (0x2000U)
733 #define DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT (13U)
734 #define DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK) >> DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT)
735 
736 /*
737  * POLARITY_STATUS (RO)
738  *
739  * Polarity Status:
740  * This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read
741  * of the 10BTSCR register, but not upon a read of the PHYSTS register.
742  * 1 = Inverted Polarity detected.
743  * 0 = Correct Polarity detected.
744  */
745 #define DP83848_PHYSTS_POLARITY_STATUS_MASK (0x1000U)
746 #define DP83848_PHYSTS_POLARITY_STATUS_SHIFT (12U)
747 #define DP83848_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_POLARITY_STATUS_MASK) >> DP83848_PHYSTS_POLARITY_STATUS_SHIFT)
748 
749 /*
750  * FALSE_CARRIER_SENSE_LATCH (RO)
751  *
752  * False Carrier Sense Latch:
753  * This bit will be cleared upon a read of the FCSR register.
754  * 1 = False Carrier event has occurred since last read of FCSCR (address 0x14).
755  * 0 = No False Carrier event has occurred.
756  */
757 #define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK (0x800U)
758 #define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT (11U)
759 #define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK) >> DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT)
760 
761 /*
762  * SIGNAL_DETECT (RO)
763  *
764  * 100Base-TX unconditional Signal Detect from PMD.
765  */
766 #define DP83848_PHYSTS_SIGNAL_DETECT_MASK (0x400U)
767 #define DP83848_PHYSTS_SIGNAL_DETECT_SHIFT (10U)
768 #define DP83848_PHYSTS_SIGNAL_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SIGNAL_DETECT_MASK) >> DP83848_PHYSTS_SIGNAL_DETECT_SHIFT)
769 
770 /*
771  * DESCRAMBLER_LOCK (RO)
772  *
773  * 100Base-TX Descrambler Lock from PMD.
774  */
775 #define DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK (0x200U)
776 #define DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT (9U)
777 #define DP83848_PHYSTS_DESCRAMBLER_LOCK_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK) >> DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT)
778 
779 /*
780  * PAGE_RECEIVED (RO)
781  *
782  * Link Code Word Page Received:
783  * This is a duplicate of the Page Received bit in the ANER register, but this bit will not be
784  * cleared upon a read of the PHYSTS register.
785  * 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address
786  * 0x06, bit 1).
787  * 0 = Link Code Word Page has not been received.
788  */
789 #define DP83848_PHYSTS_PAGE_RECEIVED_MASK (0x100U)
790 #define DP83848_PHYSTS_PAGE_RECEIVED_SHIFT (8U)
791 #define DP83848_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_PAGE_RECEIVED_MASK) >> DP83848_PHYSTS_PAGE_RECEIVED_SHIFT)
792 
793 /*
794  * REMOTE_FAULT (RO)
795  *
796  * Remote Fault:
797  * 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by
798  * reset). Fault criteria: notification from Link Partner of Remote Fault through Auto-Negotiation.
799  * 0 = No remote fault condition detected.
800  */
801 #define DP83848_PHYSTS_REMOTE_FAULT_MASK (0x40U)
802 #define DP83848_PHYSTS_REMOTE_FAULT_SHIFT (6U)
803 #define DP83848_PHYSTS_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_REMOTE_FAULT_MASK) >> DP83848_PHYSTS_REMOTE_FAULT_SHIFT)
804 
805 /*
806  * JABBER_DETECT (RO)
807  *
808  * Jabber Detect: This bit only has meaning in 10 Mb/s mode
809  * This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not
810  * cleared upon a read of the PHYSTS register.
811  * 1 = Jabber condition detected.
812  * 0 = No Jabber.
813  */
814 #define DP83848_PHYSTS_JABBER_DETECT_MASK (0x20U)
815 #define DP83848_PHYSTS_JABBER_DETECT_SHIFT (5U)
816 #define DP83848_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_JABBER_DETECT_MASK) >> DP83848_PHYSTS_JABBER_DETECT_SHIFT)
817 
818 /*
819  * AUTO_NEG_COMPLETE (RO)
820  *
821  * Auto-Negotiation Complete:
822  * 1 = Auto-Negotiation complete.
823  * 0 = Auto-Negotiation not complete.
824  */
825 #define DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK (0x10U)
826 #define DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT (4U)
827 #define DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK) >> DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT)
828 
829 /*
830  * LOOPBACK_STATUS (RO)
831  *
832  * Loopback:
833  * 1 = Loopback enabled.
834  * 0 = Normal operation.
835  */
836 #define DP83848_PHYSTS_LOOPBACK_STATUS_MASK (0x8U)
837 #define DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT (3U)
838 #define DP83848_PHYSTS_LOOPBACK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LOOPBACK_STATUS_MASK) >> DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT)
839 
840 /*
841  * DUPLEX_STATUS (RO)
842  *
843  * Duplex:
844  * This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes.
845  * 1 = Full duplex mode.
846  * 0 = Half duplex mode.
847  * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid
848  * link or if Auto-Negotiation is disabled and there is a valid link.
849  */
850 #define DP83848_PHYSTS_DUPLEX_STATUS_MASK (0x4U)
851 #define DP83848_PHYSTS_DUPLEX_STATUS_SHIFT (2U)
852 #define DP83848_PHYSTS_DUPLEX_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DUPLEX_STATUS_MASK) >> DP83848_PHYSTS_DUPLEX_STATUS_SHIFT)
853 
854 /*
855  * SPEED_STATUS (RO)
856  *
857  * Speed10:
858  * This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced
859  * Modes.
860  * 1 = 10 Mb/s mode.
861  * 0 = 100 Mb/s mode.
862  * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid
863  * link or if Auto-Negotiation is disabled and there is a valid link.
864  */
865 #define DP83848_PHYSTS_SPEED_STATUS_MASK (0x2U)
866 #define DP83848_PHYSTS_SPEED_STATUS_SHIFT (1U)
867 #define DP83848_PHYSTS_SPEED_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SPEED_STATUS_MASK) >> DP83848_PHYSTS_SPEED_STATUS_SHIFT)
868 
869 /*
870  * LINK_STATUS (RO)
871  *
872  * Link Status:
873  * This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be
874  * cleared upon a read of the PHYSTS register.
875  * 1 = Valid link established (for either 10 or 100 Mb/s operation)
876  * 0 = Link not established.
877  */
878 #define DP83848_PHYSTS_LINK_STATUS_MASK (0x1U)
879 #define DP83848_PHYSTS_LINK_STATUS_SHIFT (0U)
880 #define DP83848_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LINK_STATUS_MASK) >> DP83848_PHYSTS_LINK_STATUS_SHIFT)
881 
882 /* Bitfield definition for register: FCSCR */
883 /*
884  * FCSCNT_7_0 (RO)
885  *
886  * False Carrier Event Counter:
887  * This 8-bit counter increments on every false carrier event. This counter sticks when it
888  * reaches its max count (FFh).
889  */
890 #define DP83848_FCSCR_FCSCNT_7_0_MASK (0xFFU)
891 #define DP83848_FCSCR_FCSCNT_7_0_SHIFT (0U)
892 #define DP83848_FCSCR_FCSCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_FCSCR_FCSCNT_7_0_MASK) >> DP83848_FCSCR_FCSCNT_7_0_SHIFT)
893 
894 /* Bitfield definition for register: RECR */
895 /*
896  * RXERCNT_7_0 (RO)
897  *
898  * RX_ER Counter:
899  * When a valid carrier is present and there is at least one occurrence of an invalid data
900  * symbol, this 8-bit counter increments for each receive error detected. This event can
901  * increment only once per valid carrier event. If a collision is present, the attribute will not
902  * increment. The counter sticks when it reaches its max count.
903  */
904 #define DP83848_RECR_RXERCNT_7_0_MASK (0xFFU)
905 #define DP83848_RECR_RXERCNT_7_0_SHIFT (0U)
906 #define DP83848_RECR_RXERCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_RECR_RXERCNT_7_0_MASK) >> DP83848_RECR_RXERCNT_7_0_SHIFT)
907 
908 /* Bitfield definition for register: PCSR */
909 /*
910  * TQ_EN (RW)
911  *
912  * 100Mbs True Quiet Mode Enable:
913  * 1 = Transmit True Quiet Mode.
914  * 0 = Normal Transmit Mode.
915  */
916 #define DP83848_PCSR_TQ_EN_MASK (0x400U)
917 #define DP83848_PCSR_TQ_EN_SHIFT (10U)
918 #define DP83848_PCSR_TQ_EN_SET(x) (((uint16_t)(x) << DP83848_PCSR_TQ_EN_SHIFT) & DP83848_PCSR_TQ_EN_MASK)
919 #define DP83848_PCSR_TQ_EN_GET(x) (((uint16_t)(x) & DP83848_PCSR_TQ_EN_MASK) >> DP83848_PCSR_TQ_EN_SHIFT)
920 
921 /*
922  * SD_FORCE_PMA (RW)
923  *
924  * Signal Detect Force PMA:
925  * 1 = Forces Signal Detection in PMA.
926  * 0 = Normal SD operation.
927  */
928 #define DP83848_PCSR_SD_FORCE_PMA_MASK (0x200U)
929 #define DP83848_PCSR_SD_FORCE_PMA_SHIFT (9U)
930 #define DP83848_PCSR_SD_FORCE_PMA_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_FORCE_PMA_SHIFT) & DP83848_PCSR_SD_FORCE_PMA_MASK)
931 #define DP83848_PCSR_SD_FORCE_PMA_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_FORCE_PMA_MASK) >> DP83848_PCSR_SD_FORCE_PMA_SHIFT)
932 
933 /*
934  * SD_OPTION (RW)
935  *
936  * Signal Detect Option:
937  * 1 = Enhanced signal detect algorithm.
938  * 0 = Reduced signal detect algorithm.
939  */
940 #define DP83848_PCSR_SD_OPTION_MASK (0x100U)
941 #define DP83848_PCSR_SD_OPTION_SHIFT (8U)
942 #define DP83848_PCSR_SD_OPTION_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_OPTION_SHIFT) & DP83848_PCSR_SD_OPTION_MASK)
943 #define DP83848_PCSR_SD_OPTION_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_OPTION_MASK) >> DP83848_PCSR_SD_OPTION_SHIFT)
944 
945 /*
946  * DESC_TIME (RW)
947  *
948  * Descrambler Timeout:
949  * Increase the descrambler timeout. When set this should allow the device to receive larger
950  * packets (>9k bytes) without loss of synchronization.
951  * 1 = 2ms
952  * 0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e)
953  */
954 #define DP83848_PCSR_DESC_TIME_MASK (0x80U)
955 #define DP83848_PCSR_DESC_TIME_SHIFT (7U)
956 #define DP83848_PCSR_DESC_TIME_SET(x) (((uint16_t)(x) << DP83848_PCSR_DESC_TIME_SHIFT) & DP83848_PCSR_DESC_TIME_MASK)
957 #define DP83848_PCSR_DESC_TIME_GET(x) (((uint16_t)(x) & DP83848_PCSR_DESC_TIME_MASK) >> DP83848_PCSR_DESC_TIME_SHIFT)
958 
959 /*
960  * FORCE_100_OK (RW)
961  *
962  * Force 100Mb/s Good Link:
963  * 1 = Forces 100Mb/s Good Link.
964  * 0 = Normal 100Mb/s operation.
965  */
966 #define DP83848_PCSR_FORCE_100_OK_MASK (0x20U)
967 #define DP83848_PCSR_FORCE_100_OK_SHIFT (5U)
968 #define DP83848_PCSR_FORCE_100_OK_SET(x) (((uint16_t)(x) << DP83848_PCSR_FORCE_100_OK_SHIFT) & DP83848_PCSR_FORCE_100_OK_MASK)
969 #define DP83848_PCSR_FORCE_100_OK_GET(x) (((uint16_t)(x) & DP83848_PCSR_FORCE_100_OK_MASK) >> DP83848_PCSR_FORCE_100_OK_SHIFT)
970 
971 /*
972  * NRZI_BYPASS (RW)
973  *
974  * NRZI Bypass Enable:
975  * 1 = NRZI Bypass Enabled.
976  * 0 = NRZI Bypass Disabled.
977  */
978 #define DP83848_PCSR_NRZI_BYPASS_MASK (0x4U)
979 #define DP83848_PCSR_NRZI_BYPASS_SHIFT (2U)
980 #define DP83848_PCSR_NRZI_BYPASS_SET(x) (((uint16_t)(x) << DP83848_PCSR_NRZI_BYPASS_SHIFT) & DP83848_PCSR_NRZI_BYPASS_MASK)
981 #define DP83848_PCSR_NRZI_BYPASS_GET(x) (((uint16_t)(x) & DP83848_PCSR_NRZI_BYPASS_MASK) >> DP83848_PCSR_NRZI_BYPASS_SHIFT)
982 
983 /* Bitfield definition for register: RBR */
984 /*
985  * RMII_MODE (RW)
986  *
987  * Reduced MII Mode:
988  * 0 = Standard MII Mode
989  * 1 = Reduced MII Mode
990  */
991 #define DP83848_RBR_RMII_MODE_MASK (0x20U)
992 #define DP83848_RBR_RMII_MODE_SHIFT (5U)
993 #define DP83848_RBR_RMII_MODE_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_MODE_SHIFT) & DP83848_RBR_RMII_MODE_MASK)
994 #define DP83848_RBR_RMII_MODE_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_MODE_MASK) >> DP83848_RBR_RMII_MODE_SHIFT)
995 
996 /*
997  * RMII_REV1_0 (RW)
998  *
999  * Reduce MII Revision 1.0:
1000  * 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of
1001  * CRS.
1002  * 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV
1003  * will not toggle at the end of a packet.
1004  */
1005 #define DP83848_RBR_RMII_REV1_0_MASK (0x10U)
1006 #define DP83848_RBR_RMII_REV1_0_SHIFT (4U)
1007 #define DP83848_RBR_RMII_REV1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_REV1_0_SHIFT) & DP83848_RBR_RMII_REV1_0_MASK)
1008 #define DP83848_RBR_RMII_REV1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_REV1_0_MASK) >> DP83848_RBR_RMII_REV1_0_SHIFT)
1009 
1010 /*
1011  * RX_OVF_STS (RO)
1012  *
1013  * RX FIFO Over Flow Status:
1014  * 0 = Normal
1015  * 1 = Overflow detected
1016  */
1017 #define DP83848_RBR_RX_OVF_STS_MASK (0x8U)
1018 #define DP83848_RBR_RX_OVF_STS_SHIFT (3U)
1019 #define DP83848_RBR_RX_OVF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_OVF_STS_MASK) >> DP83848_RBR_RX_OVF_STS_SHIFT)
1020 
1021 /*
1022  * RX_UNF_STS (RO)
1023  *
1024  * RX FIFO Under Flow Status:
1025  * 0 = Normal
1026  * 1 = Underflow detected
1027  */
1028 #define DP83848_RBR_RX_UNF_STS_MASK (0x4U)
1029 #define DP83848_RBR_RX_UNF_STS_SHIFT (2U)
1030 #define DP83848_RBR_RX_UNF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_UNF_STS_MASK) >> DP83848_RBR_RX_UNF_STS_SHIFT)
1031 
1032 /*
1033  * ELAST_BUF_1_0 (RW)
1034  *
1035  * Receive Elasticity Buffer. This field controls the Receive Elasticity Buffer which allows for
1036  * frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The
1037  * following value indicate the tolerance in bits for a single packet. The minimum setting allows
1038  * for standard Ethernet frame sizes at ±50 ppm accuracy for both RMII and Receive clocks. For
1039  * greater frequency tolerance the packet lengths may be scaled (that is, for ±100 ppm, the
1040  * packet lengths need to be divided by 2).
1041  * 00 = 14 bit tolerance (up to 16800 byte packets)
1042  * 01 = 2 bit tolerance (up to 2400 byte packets)
1043  * 10 = 6 bit tolerance (up to 7200 byte packets)
1044  * 11 = 10 bit tolerance (up to 12000 byte packets)
1045  */
1046 #define DP83848_RBR_ELAST_BUF_1_0_MASK (0x3U)
1047 #define DP83848_RBR_ELAST_BUF_1_0_SHIFT (0U)
1048 #define DP83848_RBR_ELAST_BUF_1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_ELAST_BUF_1_0_SHIFT) & DP83848_RBR_ELAST_BUF_1_0_MASK)
1049 #define DP83848_RBR_ELAST_BUF_1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_ELAST_BUF_1_0_MASK) >> DP83848_RBR_ELAST_BUF_1_0_SHIFT)
1050 
1051 /* Bitfield definition for register: LEDCR */
1052 /*
1053  * DRV_SPDLED (RW)
1054  *
1055  * 1 = Drive value of SPDLED bit onto LED_SPEED output
1056  * 0 = Normal operation
1057  */
1058 #define DP83848_LEDCR_DRV_SPDLED_MASK (0x20U)
1059 #define DP83848_LEDCR_DRV_SPDLED_SHIFT (5U)
1060 #define DP83848_LEDCR_DRV_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_SPDLED_SHIFT) & DP83848_LEDCR_DRV_SPDLED_MASK)
1061 #define DP83848_LEDCR_DRV_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_SPDLED_MASK) >> DP83848_LEDCR_DRV_SPDLED_SHIFT)
1062 
1063 /*
1064  * DRV_LNKLED (RW)
1065  *
1066  * 1 = Drive value of LNKLED bit onto LED_LINK output
1067  * 0 = Normal operation
1068  */
1069 #define DP83848_LEDCR_DRV_LNKLED_MASK (0x10U)
1070 #define DP83848_LEDCR_DRV_LNKLED_SHIFT (4U)
1071 #define DP83848_LEDCR_DRV_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_LNKLED_SHIFT) & DP83848_LEDCR_DRV_LNKLED_MASK)
1072 #define DP83848_LEDCR_DRV_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_LNKLED_MASK) >> DP83848_LEDCR_DRV_LNKLED_SHIFT)
1073 
1074 /*
1075  * SPDLED (RW)
1076  *
1077  * Value to force on LED_SPEED output
1078  */
1079 #define DP83848_LEDCR_SPDLED_MASK (0x4U)
1080 #define DP83848_LEDCR_SPDLED_SHIFT (2U)
1081 #define DP83848_LEDCR_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_SPDLED_SHIFT) & DP83848_LEDCR_SPDLED_MASK)
1082 #define DP83848_LEDCR_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_SPDLED_MASK) >> DP83848_LEDCR_SPDLED_SHIFT)
1083 
1084 /*
1085  * LNKLED (RW)
1086  *
1087  * Value to force on LED_LINK output
1088  */
1089 #define DP83848_LEDCR_LNKLED_MASK (0x2U)
1090 #define DP83848_LEDCR_LNKLED_SHIFT (1U)
1091 #define DP83848_LEDCR_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_LNKLED_SHIFT) & DP83848_LEDCR_LNKLED_MASK)
1092 #define DP83848_LEDCR_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_LNKLED_MASK) >> DP83848_LEDCR_LNKLED_SHIFT)
1093 
1094 /* Bitfield definition for register: PHYCR */
1095 /*
1096  * MDIX_EN (RW)
1097  *
1098  * Auto-MDIX Enable:
1099  * 1 = Enable Auto-neg Auto-MDIX capability.
1100  * 0 = Disable Auto-neg Auto-MDIX capability.
1101  * The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register
1102  * to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well.
1103  */
1104 #define DP83848_PHYCR_MDIX_EN_MASK (0x8000U)
1105 #define DP83848_PHYCR_MDIX_EN_SHIFT (15U)
1106 #define DP83848_PHYCR_MDIX_EN_SET(x) (((uint16_t)(x) << DP83848_PHYCR_MDIX_EN_SHIFT) & DP83848_PHYCR_MDIX_EN_MASK)
1107 #define DP83848_PHYCR_MDIX_EN_GET(x) (((uint16_t)(x) & DP83848_PHYCR_MDIX_EN_MASK) >> DP83848_PHYCR_MDIX_EN_SHIFT)
1108 
1109 /*
1110  * FORCE_MDIX (RW)
1111  *
1112  * Force MDIX:
1113  * 1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair)
1114  * 0 = Normal operation.
1115  */
1116 #define DP83848_PHYCR_FORCE_MDIX_MASK (0x4000U)
1117 #define DP83848_PHYCR_FORCE_MDIX_SHIFT (14U)
1118 #define DP83848_PHYCR_FORCE_MDIX_SET(x) (((uint16_t)(x) << DP83848_PHYCR_FORCE_MDIX_SHIFT) & DP83848_PHYCR_FORCE_MDIX_MASK)
1119 #define DP83848_PHYCR_FORCE_MDIX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_FORCE_MDIX_MASK) >> DP83848_PHYCR_FORCE_MDIX_SHIFT)
1120 
1121 /*
1122  * PAUSE_RX (RO)
1123  *
1124  * Pause Receive Negotiated:
1125  * Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and
1126  * ANLPAR[11:10] settings.
1127  * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
1128  * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex
1129  * technology.
1130  */
1131 #define DP83848_PHYCR_PAUSE_RX_MASK (0x2000U)
1132 #define DP83848_PHYCR_PAUSE_RX_SHIFT (13U)
1133 #define DP83848_PHYCR_PAUSE_RX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_RX_MASK) >> DP83848_PHYCR_PAUSE_RX_SHIFT)
1134 
1135 /*
1136  * PAUSE_TX (RO)
1137  *
1138  * Pause Transmit Negotiated:
1139  * Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and
1140  * ANLPAR[11:10] settings.
1141  * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
1142  * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex
1143  * technology.
1144  */
1145 #define DP83848_PHYCR_PAUSE_TX_MASK (0x1000U)
1146 #define DP83848_PHYCR_PAUSE_TX_SHIFT (12U)
1147 #define DP83848_PHYCR_PAUSE_TX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_TX_MASK) >> DP83848_PHYCR_PAUSE_TX_SHIFT)
1148 
1149 /*
1150  * BIST_FE (RW)
1151  *
1152  * BIST Force Error:
1153  * 1 = Force BIST Error.
1154  * 0 = Normal operation.
1155  * This bit forces a single error, and is self clearing.
1156  */
1157 #define DP83848_PHYCR_BIST_FE_MASK (0x800U)
1158 #define DP83848_PHYCR_BIST_FE_SHIFT (11U)
1159 #define DP83848_PHYCR_BIST_FE_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_FE_SHIFT) & DP83848_PHYCR_BIST_FE_MASK)
1160 #define DP83848_PHYCR_BIST_FE_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_FE_MASK) >> DP83848_PHYCR_BIST_FE_SHIFT)
1161 
1162 /*
1163  * PSR_15 (RW)
1164  *
1165  * BIST Sequence select:
1166  * 1 = PSR15 selected.
1167  * 0 = PSR9 selected.
1168  */
1169 #define DP83848_PHYCR_PSR_15_MASK (0x400U)
1170 #define DP83848_PHYCR_PSR_15_SHIFT (10U)
1171 #define DP83848_PHYCR_PSR_15_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PSR_15_SHIFT) & DP83848_PHYCR_PSR_15_MASK)
1172 #define DP83848_PHYCR_PSR_15_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PSR_15_MASK) >> DP83848_PHYCR_PSR_15_SHIFT)
1173 
1174 /*
1175  * BIST_STATUS (RO)
1176  *
1177  * BIST Test Status:
1178  * 1 = BIST pass.
1179  * 0 = BIST fail. Latched, cleared when BIST is stopped.
1180  * For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register.
1181  */
1182 #define DP83848_PHYCR_BIST_STATUS_MASK (0x200U)
1183 #define DP83848_PHYCR_BIST_STATUS_SHIFT (9U)
1184 #define DP83848_PHYCR_BIST_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_STATUS_MASK) >> DP83848_PHYCR_BIST_STATUS_SHIFT)
1185 
1186 /*
1187  * BIST_START (RW)
1188  *
1189  * BIST Start:
1190  * 1 = BIST start.
1191  * 0 = BIST stop.
1192  */
1193 #define DP83848_PHYCR_BIST_START_MASK (0x100U)
1194 #define DP83848_PHYCR_BIST_START_SHIFT (8U)
1195 #define DP83848_PHYCR_BIST_START_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_START_SHIFT) & DP83848_PHYCR_BIST_START_MASK)
1196 #define DP83848_PHYCR_BIST_START_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_START_MASK) >> DP83848_PHYCR_BIST_START_SHIFT)
1197 
1198 /*
1199  * BP_STRETCH (RW)
1200  *
1201  * Bypass LED Stretching:
1202  * This will bypass the LED stretching and the LEDs will reflect the internal value.
1203  * 1 = Bypass LED stretching.
1204  * 0 = Normal operation.
1205  */
1206 #define DP83848_PHYCR_BP_STRETCH_MASK (0x80U)
1207 #define DP83848_PHYCR_BP_STRETCH_SHIFT (7U)
1208 #define DP83848_PHYCR_BP_STRETCH_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BP_STRETCH_SHIFT) & DP83848_PHYCR_BP_STRETCH_MASK)
1209 #define DP83848_PHYCR_BP_STRETCH_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BP_STRETCH_MASK) >> DP83848_PHYCR_BP_STRETCH_SHIFT)
1210 
1211 /*
1212  * LED_CNFG_0 (RW)
1213  *
1214  * LED Configuration
1215  * LED_ CNFG[0] Mode Description
1216  * 1 Mode 1
1217  * 0 Mode2
1218  * In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link
1219  * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s
1220  * In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity
1221  * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s
1222  */
1223 #define DP83848_PHYCR_LED_CNFG_0_MASK (0x20U)
1224 #define DP83848_PHYCR_LED_CNFG_0_SHIFT (5U)
1225 #define DP83848_PHYCR_LED_CNFG_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_LED_CNFG_0_SHIFT) & DP83848_PHYCR_LED_CNFG_0_MASK)
1226 #define DP83848_PHYCR_LED_CNFG_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_LED_CNFG_0_MASK) >> DP83848_PHYCR_LED_CNFG_0_SHIFT)
1227 
1228 /*
1229  * PHYADDR_4_0 (RW)
1230  *
1231  * PHY Address: PHY address for port.
1232  */
1233 #define DP83848_PHYCR_PHYADDR_4_0_MASK (0x1FU)
1234 #define DP83848_PHYCR_PHYADDR_4_0_SHIFT (0U)
1235 #define DP83848_PHYCR_PHYADDR_4_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PHYADDR_4_0_SHIFT) & DP83848_PHYCR_PHYADDR_4_0_MASK)
1236 #define DP83848_PHYCR_PHYADDR_4_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PHYADDR_4_0_MASK) >> DP83848_PHYCR_PHYADDR_4_0_SHIFT)
1237 
1238 /* Bitfield definition for register: 10BTSCR */
1239 /*
1240  * SQUELCH (RW)
1241  *
1242  * Squelch Configuration:
1243  * Used to set the Squelch ‘ON’ threshold for the receiver.
1244  * Default Squelch ON is 330-mV peak.
1245  */
1246 #define DP83848_10BTSCR_SQUELCH_MASK (0xE00U)
1247 #define DP83848_10BTSCR_SQUELCH_SHIFT (9U)
1248 #define DP83848_10BTSCR_SQUELCH_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_SQUELCH_SHIFT) & DP83848_10BTSCR_SQUELCH_MASK)
1249 #define DP83848_10BTSCR_SQUELCH_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_SQUELCH_MASK) >> DP83848_10BTSCR_SQUELCH_SHIFT)
1250 
1251 /*
1252  * LOOPBACK_10_DIS (RW)
1253  *
1254  * In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data
1255  * in addition to transmitting the data on the physical medium. This is for consistency with
1256  * earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting
1257  * this bit disables the loopback function.
1258  * This bit does not affect loopback due to setting BMCR[14].
1259  */
1260 #define DP83848_10BTSCR_LOOPBACK_10_DIS_MASK (0x100U)
1261 #define DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT (8U)
1262 #define DP83848_10BTSCR_LOOPBACK_10_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK)
1263 #define DP83848_10BTSCR_LOOPBACK_10_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) >> DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT)
1264 
1265 /*
1266  * LP_DIS (RW)
1267  *
1268  * Normal Link Pulse Disable:
1269  * 1 = Transmission of NLPs is disabled.
1270  * 0 = Transmission of NLPs is enabled.
1271  */
1272 #define DP83848_10BTSCR_LP_DIS_MASK (0x80U)
1273 #define DP83848_10BTSCR_LP_DIS_SHIFT (7U)
1274 #define DP83848_10BTSCR_LP_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LP_DIS_SHIFT) & DP83848_10BTSCR_LP_DIS_MASK)
1275 #define DP83848_10BTSCR_LP_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LP_DIS_MASK) >> DP83848_10BTSCR_LP_DIS_SHIFT)
1276 
1277 /*
1278  * FORCE_LINK_10 (RW)
1279  *
1280  * Force 10Mb Good Link:
1281  * 1 = Forced Good 10 Mb Link.
1282  * 0 = Normal Link Status.
1283  */
1284 #define DP83848_10BTSCR_FORCE_LINK_10_MASK (0x40U)
1285 #define DP83848_10BTSCR_FORCE_LINK_10_SHIFT (6U)
1286 #define DP83848_10BTSCR_FORCE_LINK_10_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_FORCE_LINK_10_SHIFT) & DP83848_10BTSCR_FORCE_LINK_10_MASK)
1287 #define DP83848_10BTSCR_FORCE_LINK_10_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_FORCE_LINK_10_MASK) >> DP83848_10BTSCR_FORCE_LINK_10_SHIFT)
1288 
1289 /*
1290  * POLARITY (RO)
1291  *
1292  * 10Mb Polarity Status:
1293  * This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a
1294  * read of 10BTSCR register, but not upon a read of the PHYSTS register.
1295  * 1 = Inverted Polarity detected.
1296  * 0 = Correct Polarity detected.
1297  */
1298 #define DP83848_10BTSCR_POLARITY_MASK (0x10U)
1299 #define DP83848_10BTSCR_POLARITY_SHIFT (4U)
1300 #define DP83848_10BTSCR_POLARITY_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_POLARITY_MASK) >> DP83848_10BTSCR_POLARITY_SHIFT)
1301 
1302 /*
1303  * HEARTBEAT_DIS (RW)
1304  *
1305  * Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode.
1306  * 1 = Heartbeat function disabled.
1307  * 0 = Heartbeat function enabled.
1308  * When the device is operating at 100 Mb or configured for full duplex operation, this
1309  * bit will be ignored - the heartbeat function is disabled.
1310  */
1311 #define DP83848_10BTSCR_HEARTBEAT_DIS_MASK (0x2U)
1312 #define DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT (1U)
1313 #define DP83848_10BTSCR_HEARTBEAT_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK)
1314 #define DP83848_10BTSCR_HEARTBEAT_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) >> DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT)
1315 
1316 /*
1317  * JABBER_DIS (RW)
1318  *
1319  * Jabber Disable:
1320  * Applicable only in 10BASE-T.
1321  * 1 = Jabber function disabled.
1322  * 0 = Jabber function enabled.
1323  */
1324 #define DP83848_10BTSCR_JABBER_DIS_MASK (0x1U)
1325 #define DP83848_10BTSCR_JABBER_DIS_SHIFT (0U)
1326 #define DP83848_10BTSCR_JABBER_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_JABBER_DIS_SHIFT) & DP83848_10BTSCR_JABBER_DIS_MASK)
1327 #define DP83848_10BTSCR_JABBER_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_JABBER_DIS_MASK) >> DP83848_10BTSCR_JABBER_DIS_SHIFT)
1328 
1329 /* Bitfield definition for register: CDCTRL1 */
1330 /*
1331  * BIST_ERROR_COUNT (RO)
1332  *
1333  * BIST ERROR Counter:
1334  * Counts number of errored data nibbles during Packet BIST. This value will reset when
1335  * Packet BIST is restarted. The counter sticks when it reaches its max count.
1336  */
1337 #define DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK (0xFF00U)
1338 #define DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT (8U)
1339 #define DP83848_CDCTRL1_BIST_ERROR_COUNT_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK) >> DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT)
1340 
1341 /*
1342  * BIST_CONT_MODE (RW)
1343  *
1344  * Packet BIST Continuous Mode:
1345  * Allows continuous pseudo random data transmission without any break in transmission. This
1346  * can be used for transmit VOD testing. This is used in conjunction with the BIST controls in
1347  * the PHYCR Register (0x19h). For 10 Mb operation, jabber function must be disabled, bit 0 of
1348  * the 10BTSCR (0x1Ah), JABBER_DIS = 1.
1349  */
1350 #define DP83848_CDCTRL1_BIST_CONT_MODE_MASK (0x20U)
1351 #define DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT (5U)
1352 #define DP83848_CDCTRL1_BIST_CONT_MODE_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK)
1353 #define DP83848_CDCTRL1_BIST_CONT_MODE_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) >> DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT)
1354 
1355 /*
1356  * CDPATTEN_10 (RW)
1357  *
1358  * CD Pattern Enable for 10Mb:
1359  * 1 = Enabled.
1360  * 0 = Disabled.
1361  */
1362 #define DP83848_CDCTRL1_CDPATTEN_10_MASK (0x10U)
1363 #define DP83848_CDCTRL1_CDPATTEN_10_SHIFT (4U)
1364 #define DP83848_CDCTRL1_CDPATTEN_10_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTEN_10_SHIFT) & DP83848_CDCTRL1_CDPATTEN_10_MASK)
1365 #define DP83848_CDCTRL1_CDPATTEN_10_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTEN_10_MASK) >> DP83848_CDCTRL1_CDPATTEN_10_SHIFT)
1366 
1367 /*
1368  * 10MEG_PATT_GAP ( RW)
1369  *
1370  * Defines gap between data or NLP test sequences:
1371  * 1 = 15 µs.
1372  * 0 = 10 µs.
1373  */
1374 #define DP83848_CDCTRL1_10MEG_PATT_GAP_MASK (0x4U)
1375 #define DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT (2U)
1376 #define DP83848_CDCTRL1_10MEG_PATT_GAP_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK)
1377 #define DP83848_CDCTRL1_10MEG_PATT_GAP_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) >> DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT)
1378 
1379 /*
1380  * CDPATTSEL_1_0 (RW)
1381  *
1382  * CD Pattern Select[1:0]:
1383  * If CDPATTEN_10 = 1:
1384  * 00 = Data, EOP0 sequence
1385  * 01 = Data, EOP1 sequence
1386  * 10 = NLPs
1387  * 11 = Constant Manchester 1 s (10-MHz sine wave) for harmonic distortion testing.
1388  */
1389 #define DP83848_CDCTRL1_CDPATTSEL_1_0_MASK (0x3U)
1390 #define DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT (0U)
1391 #define DP83848_CDCTRL1_CDPATTSEL_1_0_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK)
1392 #define DP83848_CDCTRL1_CDPATTSEL_1_0_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) >> DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT)
1393 
1394 /* Bitfield definition for register: EDCR */
1395 /*
1396  * ED_EN (RW)
1397  *
1398  * Energy Detect Enable:
1399  * Allow Energy Detect Mode.
1400  * When Energy Detect is enabled and Auto-Negotiation is disabled through the BMCR
1401  * register, Auto-MDIX should be disabled through the PHYCR register.
1402  */
1403 #define DP83848_EDCR_ED_EN_MASK (0x8000U)
1404 #define DP83848_EDCR_ED_EN_SHIFT (15U)
1405 #define DP83848_EDCR_ED_EN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_EN_SHIFT) & DP83848_EDCR_ED_EN_MASK)
1406 #define DP83848_EDCR_ED_EN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_EN_MASK) >> DP83848_EDCR_ED_EN_SHIFT)
1407 
1408 /*
1409  * ED_AUTO_UP (RW)
1410  *
1411  * Energy Detect Automatic Power Up:
1412  * Automatically begin power-up sequence when Energy Detect Data Threshold value
1413  * (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the
1414  * ED_MAN bit (ECDR[12]).
1415  */
1416 #define DP83848_EDCR_ED_AUTO_UP_MASK (0x4000U)
1417 #define DP83848_EDCR_ED_AUTO_UP_SHIFT (14U)
1418 #define DP83848_EDCR_ED_AUTO_UP_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_UP_SHIFT) & DP83848_EDCR_ED_AUTO_UP_MASK)
1419 #define DP83848_EDCR_ED_AUTO_UP_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_UP_MASK) >> DP83848_EDCR_ED_AUTO_UP_SHIFT)
1420 
1421 /*
1422  * ED_AUTO_DOWN (RW)
1423  *
1424  * Energy Detect Automatic Power Down:
1425  * Automatically begin power-down sequence when no energy is detected. Alternatively,
1426  * device could be powered down using the ED_MAN bit (EDCR[12]).
1427  */
1428 #define DP83848_EDCR_ED_AUTO_DOWN_MASK (0x2000U)
1429 #define DP83848_EDCR_ED_AUTO_DOWN_SHIFT (13U)
1430 #define DP83848_EDCR_ED_AUTO_DOWN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_DOWN_SHIFT) & DP83848_EDCR_ED_AUTO_DOWN_MASK)
1431 #define DP83848_EDCR_ED_AUTO_DOWN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_DOWN_MASK) >> DP83848_EDCR_ED_AUTO_DOWN_SHIFT)
1432 
1433 /*
1434  * ED_MAN (RW)
1435  *
1436  * Energy Detect Manual Power Up/Down:
1437  * Begin power-up/down sequence when this bit is asserted. When set, the Energy Detect
1438  * algorithm will initiate a change of Energy Detect state regardless of threshold (error or
1439  * data) and timer values.
1440  */
1441 #define DP83848_EDCR_ED_MAN_MASK (0x1000U)
1442 #define DP83848_EDCR_ED_MAN_SHIFT (12U)
1443 #define DP83848_EDCR_ED_MAN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_MAN_SHIFT) & DP83848_EDCR_ED_MAN_MASK)
1444 #define DP83848_EDCR_ED_MAN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_MAN_MASK) >> DP83848_EDCR_ED_MAN_SHIFT)
1445 
1446 /*
1447  * ED_BURST_DIS (RW)
1448  *
1449  * Energy Detect Bust Disable:
1450  * Disable bursting of energy detect data pulses. By default, Energy Detect (ED) transmits
1451  * a burst of 4 ED data pulses each time the CD is powered up. When bursting is
1452  * disabled, only a single ED data pulse will be send each time the CD is powered up.
1453  */
1454 #define DP83848_EDCR_ED_BURST_DIS_MASK (0x800U)
1455 #define DP83848_EDCR_ED_BURST_DIS_SHIFT (11U)
1456 #define DP83848_EDCR_ED_BURST_DIS_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_BURST_DIS_SHIFT) & DP83848_EDCR_ED_BURST_DIS_MASK)
1457 #define DP83848_EDCR_ED_BURST_DIS_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_BURST_DIS_MASK) >> DP83848_EDCR_ED_BURST_DIS_SHIFT)
1458 
1459 /*
1460  * ED_PWR_STATE (RO)
1461  *
1462  * Energy Detect Power State:
1463  * Indicates current Energy Detect Power state. When set, Energy Detect is in the
1464  * powered up state. When cleared, Energy Detect is in the powered down state. This bit
1465  * is invalid when Energy Detect is not enabled.
1466  */
1467 #define DP83848_EDCR_ED_PWR_STATE_MASK (0x400U)
1468 #define DP83848_EDCR_ED_PWR_STATE_SHIFT (10U)
1469 #define DP83848_EDCR_ED_PWR_STATE_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_PWR_STATE_MASK) >> DP83848_EDCR_ED_PWR_STATE_SHIFT)
1470 
1471 /*
1472  * ED_ERR_MET (RO)
1473  *
1474  * Energy Detect Error Threshold Met:
1475  * No action is automatically taken upon receipt of error events. This bit is informational
1476  * only and would be cleared on a read.
1477  */
1478 #define DP83848_EDCR_ED_ERR_MET_MASK (0x200U)
1479 #define DP83848_EDCR_ED_ERR_MET_SHIFT (9U)
1480 #define DP83848_EDCR_ED_ERR_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_MET_MASK) >> DP83848_EDCR_ED_ERR_MET_SHIFT)
1481 
1482 /*
1483  * ED_DATA_MET (RO)
1484  *
1485  * Energy Detect Data Threshold Met:
1486  * The number of data events that occurred met or surpassed the Energy Detect Data
1487  * Threshold. This bit is cleared on a read.
1488  */
1489 #define DP83848_EDCR_ED_DATA_MET_MASK (0x100U)
1490 #define DP83848_EDCR_ED_DATA_MET_SHIFT (8U)
1491 #define DP83848_EDCR_ED_DATA_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_MET_MASK) >> DP83848_EDCR_ED_DATA_MET_SHIFT)
1492 
1493 /*
1494  * ED_ERR_COUNT (RW)
1495  *
1496  * Energy Detect Error Threshold:
1497  * Threshold to determine the number of energy detect error events that should cause the
1498  * device to take action. Intended to allow averaging of noise that may be on the line.
1499  * Counter will reset after approximately 2 seconds without any energy detect data
1500  * events.
1501  */
1502 #define DP83848_EDCR_ED_ERR_COUNT_MASK (0xF0U)
1503 #define DP83848_EDCR_ED_ERR_COUNT_SHIFT (4U)
1504 #define DP83848_EDCR_ED_ERR_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_ERR_COUNT_SHIFT) & DP83848_EDCR_ED_ERR_COUNT_MASK)
1505 #define DP83848_EDCR_ED_ERR_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_COUNT_MASK) >> DP83848_EDCR_ED_ERR_COUNT_SHIFT)
1506 
1507 /*
1508  * ED_DATA_COUNT (RW)
1509  *
1510  * Energy Detect Data Threshold:
1511  * Threshold to determine the number of energy detect events that should cause the
1512  * device to take actions. Intended to allow averaging of noise that may be on the line.
1513  * Counter will reset after approximately 2 seconds without any energy detect data
1514  * events.
1515  */
1516 #define DP83848_EDCR_ED_DATA_COUNT_MASK (0xFU)
1517 #define DP83848_EDCR_ED_DATA_COUNT_SHIFT (0U)
1518 #define DP83848_EDCR_ED_DATA_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_DATA_COUNT_SHIFT) & DP83848_EDCR_ED_DATA_COUNT_MASK)
1519 #define DP83848_EDCR_ED_DATA_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_COUNT_MASK) >> DP83848_EDCR_ED_DATA_COUNT_SHIFT)
1520 
1521 
1522 
1523 
1524 #endif /* HPM_DP83848_REGS_H */
DP83848_REG_Type
DP83848_REG_Type
Definition: hpm_dp83848_regs.h:12
DP83848_BMCR
@ DP83848_BMCR
Definition: hpm_dp83848_regs.h:13
DP83848_10BTSCR
@ DP83848_10BTSCR
Definition: hpm_dp83848_regs.h:28
DP83848_RBR
@ DP83848_RBR
Definition: hpm_dp83848_regs.h:25
DP83848_ANNPTR
@ DP83848_ANNPTR
Definition: hpm_dp83848_regs.h:20
DP83848_PHYCR
@ DP83848_PHYCR
Definition: hpm_dp83848_regs.h:27
DP83848_ANAR
@ DP83848_ANAR
Definition: hpm_dp83848_regs.h:17
DP83848_ANER
@ DP83848_ANER
Definition: hpm_dp83848_regs.h:19
DP83848_PHYIDR2
@ DP83848_PHYIDR2
Definition: hpm_dp83848_regs.h:16
DP83848_RECR
@ DP83848_RECR
Definition: hpm_dp83848_regs.h:23
DP83848_PHYSTS
@ DP83848_PHYSTS
Definition: hpm_dp83848_regs.h:21
DP83848_BMSR
@ DP83848_BMSR
Definition: hpm_dp83848_regs.h:14
DP83848_FCSCR
@ DP83848_FCSCR
Definition: hpm_dp83848_regs.h:22
DP83848_PCSR
@ DP83848_PCSR
Definition: hpm_dp83848_regs.h:24
DP83848_CDCTRL1
@ DP83848_CDCTRL1
Definition: hpm_dp83848_regs.h:29
DP83848_EDCR
@ DP83848_EDCR
Definition: hpm_dp83848_regs.h:30
DP83848_ANLPAR_BP
@ DP83848_ANLPAR_BP
Definition: hpm_dp83848_regs.h:18
DP83848_PHYIDR1
@ DP83848_PHYIDR1
Definition: hpm_dp83848_regs.h:15
DP83848_LEDCR
@ DP83848_LEDCR
Definition: hpm_dp83848_regs.h:26