HPM SDK
HPMicro Software Development Kit
Macros | Enumerations
hpm_dp83848_regs.h File Reference

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Macros

#define DP83848_BMCR_RESET_MASK   (0x8000U)
 
#define DP83848_BMCR_RESET_SHIFT   (15U)
 
#define DP83848_BMCR_RESET_SET(x)   (((uint16_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK)
 
#define DP83848_BMCR_RESET_GET(x)   (((uint16_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT)
 
#define DP83848_BMCR_LOOPBACK_MASK   (0x4000U)
 
#define DP83848_BMCR_LOOPBACK_SHIFT   (14U)
 
#define DP83848_BMCR_LOOPBACK_SET(x)   (((uint16_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK)
 
#define DP83848_BMCR_LOOPBACK_GET(x)   (((uint16_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT)
 
#define DP83848_BMCR_SPEED0_MASK   (0x2000U)
 
#define DP83848_BMCR_SPEED0_SHIFT   (13U)
 
#define DP83848_BMCR_SPEED0_SET(x)   (((uint16_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK)
 
#define DP83848_BMCR_SPEED0_GET(x)   (((uint16_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT)
 
#define DP83848_BMCR_ANE_MASK   (0x1000U)
 
#define DP83848_BMCR_ANE_SHIFT   (12U)
 
#define DP83848_BMCR_ANE_SET(x)   (((uint16_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK)
 
#define DP83848_BMCR_ANE_GET(x)   (((uint16_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT)
 
#define DP83848_BMCR_PWD_MASK   (0x800U)
 
#define DP83848_BMCR_PWD_SHIFT   (11U)
 
#define DP83848_BMCR_PWD_SET(x)   (((uint16_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK)
 
#define DP83848_BMCR_PWD_GET(x)   (((uint16_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT)
 
#define DP83848_BMCR_ISOLATE_MASK   (0x400U)
 
#define DP83848_BMCR_ISOLATE_SHIFT   (10U)
 
#define DP83848_BMCR_ISOLATE_SET(x)   (((uint16_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK)
 
#define DP83848_BMCR_ISOLATE_GET(x)   (((uint16_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT)
 
#define DP83848_BMCR_RESTART_AN_MASK   (0x200U)
 
#define DP83848_BMCR_RESTART_AN_SHIFT   (9U)
 
#define DP83848_BMCR_RESTART_AN_SET(x)   (((uint16_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK)
 
#define DP83848_BMCR_RESTART_AN_GET(x)   (((uint16_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT)
 
#define DP83848_BMCR_DUPLEX_MASK   (0x100U)
 
#define DP83848_BMCR_DUPLEX_SHIFT   (8U)
 
#define DP83848_BMCR_DUPLEX_SET(x)   (((uint16_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK)
 
#define DP83848_BMCR_DUPLEX_GET(x)   (((uint16_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT)
 
#define DP83848_BMCR_COLLISION_TEST_MASK   (0x80U)
 
#define DP83848_BMCR_COLLISION_TEST_SHIFT   (7U)
 
#define DP83848_BMCR_COLLISION_TEST_SET(x)   (((uint16_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK)
 
#define DP83848_BMCR_COLLISION_TEST_GET(x)   (((uint16_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT)
 
#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK   (0x4000U)
 
#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT   (14U)
 
#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET(x)   (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT)
 
#define DP83848_BMSR_100BASE_TX_HALF_MASK   (0x2000U)
 
#define DP83848_BMSR_100BASE_TX_HALF_SHIFT   (13U)
 
#define DP83848_BMSR_100BASE_TX_HALF_GET(x)   (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_HALF_MASK) >> DP83848_BMSR_100BASE_TX_HALF_SHIFT)
 
#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK   (0x1000U)
 
#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT   (12U)
 
#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET(x)   (((uint16_t)(x) & DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT)
 
#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK   (0x800U)
 
#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT   (11U)
 
#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET(x)   (((uint16_t)(x) & DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT)
 
#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK   (0x40U)
 
#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT   (6U)
 
#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x)   (((uint16_t)(x) & DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT)
 
#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK   (0x20U)
 
#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT   (5U)
 
#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x)   (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT)
 
#define DP83848_BMSR_REMOTE_FAULT_MASK   (0x10U)
 
#define DP83848_BMSR_REMOTE_FAULT_SHIFT   (4U)
 
#define DP83848_BMSR_REMOTE_FAULT_GET(x)   (((uint16_t)(x) & DP83848_BMSR_REMOTE_FAULT_MASK) >> DP83848_BMSR_REMOTE_FAULT_SHIFT)
 
#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK   (0x8U)
 
#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT   (3U)
 
#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x)   (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT)
 
#define DP83848_BMSR_LINK_STATUS_MASK   (0x4U)
 
#define DP83848_BMSR_LINK_STATUS_SHIFT   (2U)
 
#define DP83848_BMSR_LINK_STATUS_GET(x)   (((uint16_t)(x) & DP83848_BMSR_LINK_STATUS_MASK) >> DP83848_BMSR_LINK_STATUS_SHIFT)
 
#define DP83848_BMSR_JABBER_DETECT_MASK   (0x2U)
 
#define DP83848_BMSR_JABBER_DETECT_SHIFT   (1U)
 
#define DP83848_BMSR_JABBER_DETECT_GET(x)   (((uint16_t)(x) & DP83848_BMSR_JABBER_DETECT_MASK) >> DP83848_BMSR_JABBER_DETECT_SHIFT)
 
#define DP83848_BMSR_EXTENDED_CAPABILITY_MASK   (0x1U)
 
#define DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT   (0U)
 
#define DP83848_BMSR_EXTENDED_CAPABILITY_GET(x)   (((uint16_t)(x) & DP83848_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT)
 
#define DP83848_PHYIDR1_OUI_MSB_MASK   (0xFFFFU)
 
#define DP83848_PHYIDR1_OUI_MSB_SHIFT   (0U)
 
#define DP83848_PHYIDR1_OUI_MSB_GET(x)   (((uint16_t)(x) & DP83848_PHYIDR1_OUI_MSB_MASK) >> DP83848_PHYIDR1_OUI_MSB_SHIFT)
 
#define DP83848_PHYIDR2_OUI_LSB_MASK   (0xFC00U)
 
#define DP83848_PHYIDR2_OUI_LSB_SHIFT   (10U)
 
#define DP83848_PHYIDR2_OUI_LSB_GET(x)   (((uint16_t)(x) & DP83848_PHYIDR2_OUI_LSB_MASK) >> DP83848_PHYIDR2_OUI_LSB_SHIFT)
 
#define DP83848_PHYIDR2_VNDR_MDL_MASK   (0x3F0U)
 
#define DP83848_PHYIDR2_VNDR_MDL_SHIFT   (4U)
 
#define DP83848_PHYIDR2_VNDR_MDL_GET(x)   (((uint16_t)(x) & DP83848_PHYIDR2_VNDR_MDL_MASK) >> DP83848_PHYIDR2_VNDR_MDL_SHIFT)
 
#define DP83848_PHYIDR2_MDL_REV_MASK   (0xFU)
 
#define DP83848_PHYIDR2_MDL_REV_SHIFT   (0U)
 
#define DP83848_PHYIDR2_MDL_REV_GET(x)   (((uint16_t)(x) & DP83848_PHYIDR2_MDL_REV_MASK) >> DP83848_PHYIDR2_MDL_REV_SHIFT)
 
#define DP83848_ANAR_NP_MASK   (0x8000U)
 
#define DP83848_ANAR_NP_SHIFT   (15U)
 
#define DP83848_ANAR_NP_SET(x)   (((uint16_t)(x) << DP83848_ANAR_NP_SHIFT) & DP83848_ANAR_NP_MASK)
 
#define DP83848_ANAR_NP_GET(x)   (((uint16_t)(x) & DP83848_ANAR_NP_MASK) >> DP83848_ANAR_NP_SHIFT)
 
#define DP83848_ANAR_RF_MASK   (0x2000U)
 
#define DP83848_ANAR_RF_SHIFT   (13U)
 
#define DP83848_ANAR_RF_SET(x)   (((uint16_t)(x) << DP83848_ANAR_RF_SHIFT) & DP83848_ANAR_RF_MASK)
 
#define DP83848_ANAR_RF_GET(x)   (((uint16_t)(x) & DP83848_ANAR_RF_MASK) >> DP83848_ANAR_RF_SHIFT)
 
#define DP83848_ANAR_ASM_DIR_MASK   (0x800U)
 
#define DP83848_ANAR_ASM_DIR_SHIFT   (11U)
 
#define DP83848_ANAR_ASM_DIR_SET(x)   (((uint16_t)(x) << DP83848_ANAR_ASM_DIR_SHIFT) & DP83848_ANAR_ASM_DIR_MASK)
 
#define DP83848_ANAR_ASM_DIR_GET(x)   (((uint16_t)(x) & DP83848_ANAR_ASM_DIR_MASK) >> DP83848_ANAR_ASM_DIR_SHIFT)
 
#define DP83848_ANAR_PAUSE_MASK   (0x400U)
 
#define DP83848_ANAR_PAUSE_SHIFT   (10U)
 
#define DP83848_ANAR_PAUSE_SET(x)   (((uint16_t)(x) << DP83848_ANAR_PAUSE_SHIFT) & DP83848_ANAR_PAUSE_MASK)
 
#define DP83848_ANAR_PAUSE_GET(x)   (((uint16_t)(x) & DP83848_ANAR_PAUSE_MASK) >> DP83848_ANAR_PAUSE_SHIFT)
 
#define DP83848_ANAR_T4_MASK   (0x200U)
 
#define DP83848_ANAR_T4_SHIFT   (9U)
 
#define DP83848_ANAR_T4_GET(x)   (((uint16_t)(x) & DP83848_ANAR_T4_MASK) >> DP83848_ANAR_T4_SHIFT)
 
#define DP83848_ANAR_TX_FD_MASK   (0x100U)
 
#define DP83848_ANAR_TX_FD_SHIFT   (8U)
 
#define DP83848_ANAR_TX_FD_SET(x)   (((uint16_t)(x) << DP83848_ANAR_TX_FD_SHIFT) & DP83848_ANAR_TX_FD_MASK)
 
#define DP83848_ANAR_TX_FD_GET(x)   (((uint16_t)(x) & DP83848_ANAR_TX_FD_MASK) >> DP83848_ANAR_TX_FD_SHIFT)
 
#define DP83848_ANAR_TX_MASK   (0x80U)
 
#define DP83848_ANAR_TX_SHIFT   (7U)
 
#define DP83848_ANAR_TX_SET(x)   (((uint16_t)(x) << DP83848_ANAR_TX_SHIFT) & DP83848_ANAR_TX_MASK)
 
#define DP83848_ANAR_TX_GET(x)   (((uint16_t)(x) & DP83848_ANAR_TX_MASK) >> DP83848_ANAR_TX_SHIFT)
 
#define DP83848_ANAR_10_FD_MASK   (0x40U)
 
#define DP83848_ANAR_10_FD_SHIFT   (6U)
 
#define DP83848_ANAR_10_FD_SET(x)   (((uint16_t)(x) << DP83848_ANAR_10_FD_SHIFT) & DP83848_ANAR_10_FD_MASK)
 
#define DP83848_ANAR_10_FD_GET(x)   (((uint16_t)(x) & DP83848_ANAR_10_FD_MASK) >> DP83848_ANAR_10_FD_SHIFT)
 
#define DP83848_ANAR_10_MASK   (0x20U)
 
#define DP83848_ANAR_10_SHIFT   (5U)
 
#define DP83848_ANAR_10_SET(x)   (((uint16_t)(x) << DP83848_ANAR_10_SHIFT) & DP83848_ANAR_10_MASK)
 
#define DP83848_ANAR_10_GET(x)   (((uint16_t)(x) & DP83848_ANAR_10_MASK) >> DP83848_ANAR_10_SHIFT)
 
#define DP83848_ANAR_SELECTOR_MASK   (0x1FU)
 
#define DP83848_ANAR_SELECTOR_SHIFT   (0U)
 
#define DP83848_ANAR_SELECTOR_SET(x)   (((uint16_t)(x) << DP83848_ANAR_SELECTOR_SHIFT) & DP83848_ANAR_SELECTOR_MASK)
 
#define DP83848_ANAR_SELECTOR_GET(x)   (((uint16_t)(x) & DP83848_ANAR_SELECTOR_MASK) >> DP83848_ANAR_SELECTOR_SHIFT)
 
#define DP83848_ANLPAR_BP_NP_MASK   (0x8000U)
 
#define DP83848_ANLPAR_BP_NP_SHIFT   (15U)
 
#define DP83848_ANLPAR_BP_NP_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_NP_MASK) >> DP83848_ANLPAR_BP_NP_SHIFT)
 
#define DP83848_ANLPAR_BP_ACK_MASK   (0x4000U)
 
#define DP83848_ANLPAR_BP_ACK_SHIFT   (14U)
 
#define DP83848_ANLPAR_BP_ACK_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_ACK_MASK) >> DP83848_ANLPAR_BP_ACK_SHIFT)
 
#define DP83848_ANLPAR_BP_RF_MASK   (0x2000U)
 
#define DP83848_ANLPAR_BP_RF_SHIFT   (13U)
 
#define DP83848_ANLPAR_BP_RF_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_RF_MASK) >> DP83848_ANLPAR_BP_RF_SHIFT)
 
#define DP83848_ANLPAR_BP_ASM_DIR_MASK   (0x800U)
 
#define DP83848_ANLPAR_BP_ASM_DIR_SHIFT   (11U)
 
#define DP83848_ANLPAR_BP_ASM_DIR_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_ASM_DIR_MASK) >> DP83848_ANLPAR_BP_ASM_DIR_SHIFT)
 
#define DP83848_ANLPAR_BP_PAUSE_MASK   (0x400U)
 
#define DP83848_ANLPAR_BP_PAUSE_SHIFT   (10U)
 
#define DP83848_ANLPAR_BP_PAUSE_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_PAUSE_MASK) >> DP83848_ANLPAR_BP_PAUSE_SHIFT)
 
#define DP83848_ANLPAR_BP_T4_MASK   (0x200U)
 
#define DP83848_ANLPAR_BP_T4_SHIFT   (9U)
 
#define DP83848_ANLPAR_BP_T4_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_T4_MASK) >> DP83848_ANLPAR_BP_T4_SHIFT)
 
#define DP83848_ANLPAR_BP_TX_FD_MASK   (0x100U)
 
#define DP83848_ANLPAR_BP_TX_FD_SHIFT   (8U)
 
#define DP83848_ANLPAR_BP_TX_FD_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_FD_MASK) >> DP83848_ANLPAR_BP_TX_FD_SHIFT)
 
#define DP83848_ANLPAR_BP_TX_MASK   (0x80U)
 
#define DP83848_ANLPAR_BP_TX_SHIFT   (7U)
 
#define DP83848_ANLPAR_BP_TX_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_MASK) >> DP83848_ANLPAR_BP_TX_SHIFT)
 
#define DP83848_ANLPAR_BP_10_FD_MASK   (0x40U)
 
#define DP83848_ANLPAR_BP_10_FD_SHIFT   (6U)
 
#define DP83848_ANLPAR_BP_10_FD_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_10_FD_MASK) >> DP83848_ANLPAR_BP_10_FD_SHIFT)
 
#define DP83848_ANLPAR_BP_10_MASK   (0x20U)
 
#define DP83848_ANLPAR_BP_10_SHIFT   (5U)
 
#define DP83848_ANLPAR_BP_10_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_10_MASK) >> DP83848_ANLPAR_BP_10_SHIFT)
 
#define DP83848_ANLPAR_BP_SELECTOR_MASK   (0x1FU)
 
#define DP83848_ANLPAR_BP_SELECTOR_SHIFT   (0U)
 
#define DP83848_ANLPAR_BP_SELECTOR_GET(x)   (((uint16_t)(x) & DP83848_ANLPAR_BP_SELECTOR_MASK) >> DP83848_ANLPAR_BP_SELECTOR_SHIFT)
 
#define DP83848_ANER_PDF_MASK   (0x10U)
 
#define DP83848_ANER_PDF_SHIFT   (4U)
 
#define DP83848_ANER_PDF_GET(x)   (((uint16_t)(x) & DP83848_ANER_PDF_MASK) >> DP83848_ANER_PDF_SHIFT)
 
#define DP83848_ANER_LP_NP_ABLE_MASK   (0x8U)
 
#define DP83848_ANER_LP_NP_ABLE_SHIFT   (3U)
 
#define DP83848_ANER_LP_NP_ABLE_GET(x)   (((uint16_t)(x) & DP83848_ANER_LP_NP_ABLE_MASK) >> DP83848_ANER_LP_NP_ABLE_SHIFT)
 
#define DP83848_ANER_NP_ABLE_MASK   (0x4U)
 
#define DP83848_ANER_NP_ABLE_SHIFT   (2U)
 
#define DP83848_ANER_NP_ABLE_GET(x)   (((uint16_t)(x) & DP83848_ANER_NP_ABLE_MASK) >> DP83848_ANER_NP_ABLE_SHIFT)
 
#define DP83848_ANER_PAGE_RX_MASK   (0x2U)
 
#define DP83848_ANER_PAGE_RX_SHIFT   (1U)
 
#define DP83848_ANER_PAGE_RX_GET(x)   (((uint16_t)(x) & DP83848_ANER_PAGE_RX_MASK) >> DP83848_ANER_PAGE_RX_SHIFT)
 
#define DP83848_ANER_LP_AN_ABLE_MASK   (0x1U)
 
#define DP83848_ANER_LP_AN_ABLE_SHIFT   (0U)
 
#define DP83848_ANER_LP_AN_ABLE_GET(x)   (((uint16_t)(x) & DP83848_ANER_LP_AN_ABLE_MASK) >> DP83848_ANER_LP_AN_ABLE_SHIFT)
 
#define DP83848_ANNPTR_NP_MASK   (0x8000U)
 
#define DP83848_ANNPTR_NP_SHIFT   (15U)
 
#define DP83848_ANNPTR_NP_SET(x)   (((uint16_t)(x) << DP83848_ANNPTR_NP_SHIFT) & DP83848_ANNPTR_NP_MASK)
 
#define DP83848_ANNPTR_NP_GET(x)   (((uint16_t)(x) & DP83848_ANNPTR_NP_MASK) >> DP83848_ANNPTR_NP_SHIFT)
 
#define DP83848_ANNPTR_MP_MASK   (0x2000U)
 
#define DP83848_ANNPTR_MP_SHIFT   (13U)
 
#define DP83848_ANNPTR_MP_SET(x)   (((uint16_t)(x) << DP83848_ANNPTR_MP_SHIFT) & DP83848_ANNPTR_MP_MASK)
 
#define DP83848_ANNPTR_MP_GET(x)   (((uint16_t)(x) & DP83848_ANNPTR_MP_MASK) >> DP83848_ANNPTR_MP_SHIFT)
 
#define DP83848_ANNPTR_ACK2_MASK   (0x1000U)
 
#define DP83848_ANNPTR_ACK2_SHIFT   (12U)
 
#define DP83848_ANNPTR_ACK2_SET(x)   (((uint16_t)(x) << DP83848_ANNPTR_ACK2_SHIFT) & DP83848_ANNPTR_ACK2_MASK)
 
#define DP83848_ANNPTR_ACK2_GET(x)   (((uint16_t)(x) & DP83848_ANNPTR_ACK2_MASK) >> DP83848_ANNPTR_ACK2_SHIFT)
 
#define DP83848_ANNPTR_TOG_TX_MASK   (0x800U)
 
#define DP83848_ANNPTR_TOG_TX_SHIFT   (11U)
 
#define DP83848_ANNPTR_TOG_TX_SET(x)   (((uint16_t)(x) << DP83848_ANNPTR_TOG_TX_SHIFT) & DP83848_ANNPTR_TOG_TX_MASK)
 
#define DP83848_ANNPTR_TOG_TX_GET(x)   (((uint16_t)(x) & DP83848_ANNPTR_TOG_TX_MASK) >> DP83848_ANNPTR_TOG_TX_SHIFT)
 
#define DP83848_ANNPTR_CODE_MASK   (0x400U)
 
#define DP83848_ANNPTR_CODE_SHIFT   (10U)
 
#define DP83848_ANNPTR_CODE_SET(x)   (((uint16_t)(x) << DP83848_ANNPTR_CODE_SHIFT) & DP83848_ANNPTR_CODE_MASK)
 
#define DP83848_ANNPTR_CODE_GET(x)   (((uint16_t)(x) & DP83848_ANNPTR_CODE_MASK) >> DP83848_ANNPTR_CODE_SHIFT)
 
#define DP83848_PHYSTS_MDI_X_MODE_MASK   (0x4000U)
 
#define DP83848_PHYSTS_MDI_X_MODE_SHIFT   (14U)
 
#define DP83848_PHYSTS_MDI_X_MODE_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_MDI_X_MODE_MASK) >> DP83848_PHYSTS_MDI_X_MODE_SHIFT)
 
#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK   (0x2000U)
 
#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT   (13U)
 
#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK) >> DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT)
 
#define DP83848_PHYSTS_POLARITY_STATUS_MASK   (0x1000U)
 
#define DP83848_PHYSTS_POLARITY_STATUS_SHIFT   (12U)
 
#define DP83848_PHYSTS_POLARITY_STATUS_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_POLARITY_STATUS_MASK) >> DP83848_PHYSTS_POLARITY_STATUS_SHIFT)
 
#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK   (0x800U)
 
#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT   (11U)
 
#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK) >> DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT)
 
#define DP83848_PHYSTS_SIGNAL_DETECT_MASK   (0x400U)
 
#define DP83848_PHYSTS_SIGNAL_DETECT_SHIFT   (10U)
 
#define DP83848_PHYSTS_SIGNAL_DETECT_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_SIGNAL_DETECT_MASK) >> DP83848_PHYSTS_SIGNAL_DETECT_SHIFT)
 
#define DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK   (0x200U)
 
#define DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT   (9U)
 
#define DP83848_PHYSTS_DESCRAMBLER_LOCK_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK) >> DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT)
 
#define DP83848_PHYSTS_PAGE_RECEIVED_MASK   (0x100U)
 
#define DP83848_PHYSTS_PAGE_RECEIVED_SHIFT   (8U)
 
#define DP83848_PHYSTS_PAGE_RECEIVED_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_PAGE_RECEIVED_MASK) >> DP83848_PHYSTS_PAGE_RECEIVED_SHIFT)
 
#define DP83848_PHYSTS_REMOTE_FAULT_MASK   (0x40U)
 
#define DP83848_PHYSTS_REMOTE_FAULT_SHIFT   (6U)
 
#define DP83848_PHYSTS_REMOTE_FAULT_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_REMOTE_FAULT_MASK) >> DP83848_PHYSTS_REMOTE_FAULT_SHIFT)
 
#define DP83848_PHYSTS_JABBER_DETECT_MASK   (0x20U)
 
#define DP83848_PHYSTS_JABBER_DETECT_SHIFT   (5U)
 
#define DP83848_PHYSTS_JABBER_DETECT_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_JABBER_DETECT_MASK) >> DP83848_PHYSTS_JABBER_DETECT_SHIFT)
 
#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK   (0x10U)
 
#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT   (4U)
 
#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK) >> DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT)
 
#define DP83848_PHYSTS_LOOPBACK_STATUS_MASK   (0x8U)
 
#define DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT   (3U)
 
#define DP83848_PHYSTS_LOOPBACK_STATUS_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_LOOPBACK_STATUS_MASK) >> DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT)
 
#define DP83848_PHYSTS_DUPLEX_STATUS_MASK   (0x4U)
 
#define DP83848_PHYSTS_DUPLEX_STATUS_SHIFT   (2U)
 
#define DP83848_PHYSTS_DUPLEX_STATUS_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_DUPLEX_STATUS_MASK) >> DP83848_PHYSTS_DUPLEX_STATUS_SHIFT)
 
#define DP83848_PHYSTS_SPEED_STATUS_MASK   (0x2U)
 
#define DP83848_PHYSTS_SPEED_STATUS_SHIFT   (1U)
 
#define DP83848_PHYSTS_SPEED_STATUS_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_SPEED_STATUS_MASK) >> DP83848_PHYSTS_SPEED_STATUS_SHIFT)
 
#define DP83848_PHYSTS_LINK_STATUS_MASK   (0x1U)
 
#define DP83848_PHYSTS_LINK_STATUS_SHIFT   (0U)
 
#define DP83848_PHYSTS_LINK_STATUS_GET(x)   (((uint16_t)(x) & DP83848_PHYSTS_LINK_STATUS_MASK) >> DP83848_PHYSTS_LINK_STATUS_SHIFT)
 
#define DP83848_FCSCR_FCSCNT_7_0_MASK   (0xFFU)
 
#define DP83848_FCSCR_FCSCNT_7_0_SHIFT   (0U)
 
#define DP83848_FCSCR_FCSCNT_7_0_GET(x)   (((uint16_t)(x) & DP83848_FCSCR_FCSCNT_7_0_MASK) >> DP83848_FCSCR_FCSCNT_7_0_SHIFT)
 
#define DP83848_RECR_RXERCNT_7_0_MASK   (0xFFU)
 
#define DP83848_RECR_RXERCNT_7_0_SHIFT   (0U)
 
#define DP83848_RECR_RXERCNT_7_0_GET(x)   (((uint16_t)(x) & DP83848_RECR_RXERCNT_7_0_MASK) >> DP83848_RECR_RXERCNT_7_0_SHIFT)
 
#define DP83848_PCSR_TQ_EN_MASK   (0x400U)
 
#define DP83848_PCSR_TQ_EN_SHIFT   (10U)
 
#define DP83848_PCSR_TQ_EN_SET(x)   (((uint16_t)(x) << DP83848_PCSR_TQ_EN_SHIFT) & DP83848_PCSR_TQ_EN_MASK)
 
#define DP83848_PCSR_TQ_EN_GET(x)   (((uint16_t)(x) & DP83848_PCSR_TQ_EN_MASK) >> DP83848_PCSR_TQ_EN_SHIFT)
 
#define DP83848_PCSR_SD_FORCE_PMA_MASK   (0x200U)
 
#define DP83848_PCSR_SD_FORCE_PMA_SHIFT   (9U)
 
#define DP83848_PCSR_SD_FORCE_PMA_SET(x)   (((uint16_t)(x) << DP83848_PCSR_SD_FORCE_PMA_SHIFT) & DP83848_PCSR_SD_FORCE_PMA_MASK)
 
#define DP83848_PCSR_SD_FORCE_PMA_GET(x)   (((uint16_t)(x) & DP83848_PCSR_SD_FORCE_PMA_MASK) >> DP83848_PCSR_SD_FORCE_PMA_SHIFT)
 
#define DP83848_PCSR_SD_OPTION_MASK   (0x100U)
 
#define DP83848_PCSR_SD_OPTION_SHIFT   (8U)
 
#define DP83848_PCSR_SD_OPTION_SET(x)   (((uint16_t)(x) << DP83848_PCSR_SD_OPTION_SHIFT) & DP83848_PCSR_SD_OPTION_MASK)
 
#define DP83848_PCSR_SD_OPTION_GET(x)   (((uint16_t)(x) & DP83848_PCSR_SD_OPTION_MASK) >> DP83848_PCSR_SD_OPTION_SHIFT)
 
#define DP83848_PCSR_DESC_TIME_MASK   (0x80U)
 
#define DP83848_PCSR_DESC_TIME_SHIFT   (7U)
 
#define DP83848_PCSR_DESC_TIME_SET(x)   (((uint16_t)(x) << DP83848_PCSR_DESC_TIME_SHIFT) & DP83848_PCSR_DESC_TIME_MASK)
 
#define DP83848_PCSR_DESC_TIME_GET(x)   (((uint16_t)(x) & DP83848_PCSR_DESC_TIME_MASK) >> DP83848_PCSR_DESC_TIME_SHIFT)
 
#define DP83848_PCSR_FORCE_100_OK_MASK   (0x20U)
 
#define DP83848_PCSR_FORCE_100_OK_SHIFT   (5U)
 
#define DP83848_PCSR_FORCE_100_OK_SET(x)   (((uint16_t)(x) << DP83848_PCSR_FORCE_100_OK_SHIFT) & DP83848_PCSR_FORCE_100_OK_MASK)
 
#define DP83848_PCSR_FORCE_100_OK_GET(x)   (((uint16_t)(x) & DP83848_PCSR_FORCE_100_OK_MASK) >> DP83848_PCSR_FORCE_100_OK_SHIFT)
 
#define DP83848_PCSR_NRZI_BYPASS_MASK   (0x4U)
 
#define DP83848_PCSR_NRZI_BYPASS_SHIFT   (2U)
 
#define DP83848_PCSR_NRZI_BYPASS_SET(x)   (((uint16_t)(x) << DP83848_PCSR_NRZI_BYPASS_SHIFT) & DP83848_PCSR_NRZI_BYPASS_MASK)
 
#define DP83848_PCSR_NRZI_BYPASS_GET(x)   (((uint16_t)(x) & DP83848_PCSR_NRZI_BYPASS_MASK) >> DP83848_PCSR_NRZI_BYPASS_SHIFT)
 
#define DP83848_RBR_RMII_MODE_MASK   (0x20U)
 
#define DP83848_RBR_RMII_MODE_SHIFT   (5U)
 
#define DP83848_RBR_RMII_MODE_SET(x)   (((uint16_t)(x) << DP83848_RBR_RMII_MODE_SHIFT) & DP83848_RBR_RMII_MODE_MASK)
 
#define DP83848_RBR_RMII_MODE_GET(x)   (((uint16_t)(x) & DP83848_RBR_RMII_MODE_MASK) >> DP83848_RBR_RMII_MODE_SHIFT)
 
#define DP83848_RBR_RMII_REV1_0_MASK   (0x10U)
 
#define DP83848_RBR_RMII_REV1_0_SHIFT   (4U)
 
#define DP83848_RBR_RMII_REV1_0_SET(x)   (((uint16_t)(x) << DP83848_RBR_RMII_REV1_0_SHIFT) & DP83848_RBR_RMII_REV1_0_MASK)
 
#define DP83848_RBR_RMII_REV1_0_GET(x)   (((uint16_t)(x) & DP83848_RBR_RMII_REV1_0_MASK) >> DP83848_RBR_RMII_REV1_0_SHIFT)
 
#define DP83848_RBR_RX_OVF_STS_MASK   (0x8U)
 
#define DP83848_RBR_RX_OVF_STS_SHIFT   (3U)
 
#define DP83848_RBR_RX_OVF_STS_GET(x)   (((uint16_t)(x) & DP83848_RBR_RX_OVF_STS_MASK) >> DP83848_RBR_RX_OVF_STS_SHIFT)
 
#define DP83848_RBR_RX_UNF_STS_MASK   (0x4U)
 
#define DP83848_RBR_RX_UNF_STS_SHIFT   (2U)
 
#define DP83848_RBR_RX_UNF_STS_GET(x)   (((uint16_t)(x) & DP83848_RBR_RX_UNF_STS_MASK) >> DP83848_RBR_RX_UNF_STS_SHIFT)
 
#define DP83848_RBR_ELAST_BUF_1_0_MASK   (0x3U)
 
#define DP83848_RBR_ELAST_BUF_1_0_SHIFT   (0U)
 
#define DP83848_RBR_ELAST_BUF_1_0_SET(x)   (((uint16_t)(x) << DP83848_RBR_ELAST_BUF_1_0_SHIFT) & DP83848_RBR_ELAST_BUF_1_0_MASK)
 
#define DP83848_RBR_ELAST_BUF_1_0_GET(x)   (((uint16_t)(x) & DP83848_RBR_ELAST_BUF_1_0_MASK) >> DP83848_RBR_ELAST_BUF_1_0_SHIFT)
 
#define DP83848_LEDCR_DRV_SPDLED_MASK   (0x20U)
 
#define DP83848_LEDCR_DRV_SPDLED_SHIFT   (5U)
 
#define DP83848_LEDCR_DRV_SPDLED_SET(x)   (((uint16_t)(x) << DP83848_LEDCR_DRV_SPDLED_SHIFT) & DP83848_LEDCR_DRV_SPDLED_MASK)
 
#define DP83848_LEDCR_DRV_SPDLED_GET(x)   (((uint16_t)(x) & DP83848_LEDCR_DRV_SPDLED_MASK) >> DP83848_LEDCR_DRV_SPDLED_SHIFT)
 
#define DP83848_LEDCR_DRV_LNKLED_MASK   (0x10U)
 
#define DP83848_LEDCR_DRV_LNKLED_SHIFT   (4U)
 
#define DP83848_LEDCR_DRV_LNKLED_SET(x)   (((uint16_t)(x) << DP83848_LEDCR_DRV_LNKLED_SHIFT) & DP83848_LEDCR_DRV_LNKLED_MASK)
 
#define DP83848_LEDCR_DRV_LNKLED_GET(x)   (((uint16_t)(x) & DP83848_LEDCR_DRV_LNKLED_MASK) >> DP83848_LEDCR_DRV_LNKLED_SHIFT)
 
#define DP83848_LEDCR_SPDLED_MASK   (0x4U)
 
#define DP83848_LEDCR_SPDLED_SHIFT   (2U)
 
#define DP83848_LEDCR_SPDLED_SET(x)   (((uint16_t)(x) << DP83848_LEDCR_SPDLED_SHIFT) & DP83848_LEDCR_SPDLED_MASK)
 
#define DP83848_LEDCR_SPDLED_GET(x)   (((uint16_t)(x) & DP83848_LEDCR_SPDLED_MASK) >> DP83848_LEDCR_SPDLED_SHIFT)
 
#define DP83848_LEDCR_LNKLED_MASK   (0x2U)
 
#define DP83848_LEDCR_LNKLED_SHIFT   (1U)
 
#define DP83848_LEDCR_LNKLED_SET(x)   (((uint16_t)(x) << DP83848_LEDCR_LNKLED_SHIFT) & DP83848_LEDCR_LNKLED_MASK)
 
#define DP83848_LEDCR_LNKLED_GET(x)   (((uint16_t)(x) & DP83848_LEDCR_LNKLED_MASK) >> DP83848_LEDCR_LNKLED_SHIFT)
 
#define DP83848_PHYCR_MDIX_EN_MASK   (0x8000U)
 
#define DP83848_PHYCR_MDIX_EN_SHIFT   (15U)
 
#define DP83848_PHYCR_MDIX_EN_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_MDIX_EN_SHIFT) & DP83848_PHYCR_MDIX_EN_MASK)
 
#define DP83848_PHYCR_MDIX_EN_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_MDIX_EN_MASK) >> DP83848_PHYCR_MDIX_EN_SHIFT)
 
#define DP83848_PHYCR_FORCE_MDIX_MASK   (0x4000U)
 
#define DP83848_PHYCR_FORCE_MDIX_SHIFT   (14U)
 
#define DP83848_PHYCR_FORCE_MDIX_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_FORCE_MDIX_SHIFT) & DP83848_PHYCR_FORCE_MDIX_MASK)
 
#define DP83848_PHYCR_FORCE_MDIX_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_FORCE_MDIX_MASK) >> DP83848_PHYCR_FORCE_MDIX_SHIFT)
 
#define DP83848_PHYCR_PAUSE_RX_MASK   (0x2000U)
 
#define DP83848_PHYCR_PAUSE_RX_SHIFT   (13U)
 
#define DP83848_PHYCR_PAUSE_RX_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_PAUSE_RX_MASK) >> DP83848_PHYCR_PAUSE_RX_SHIFT)
 
#define DP83848_PHYCR_PAUSE_TX_MASK   (0x1000U)
 
#define DP83848_PHYCR_PAUSE_TX_SHIFT   (12U)
 
#define DP83848_PHYCR_PAUSE_TX_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_PAUSE_TX_MASK) >> DP83848_PHYCR_PAUSE_TX_SHIFT)
 
#define DP83848_PHYCR_BIST_FE_MASK   (0x800U)
 
#define DP83848_PHYCR_BIST_FE_SHIFT   (11U)
 
#define DP83848_PHYCR_BIST_FE_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_BIST_FE_SHIFT) & DP83848_PHYCR_BIST_FE_MASK)
 
#define DP83848_PHYCR_BIST_FE_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_BIST_FE_MASK) >> DP83848_PHYCR_BIST_FE_SHIFT)
 
#define DP83848_PHYCR_PSR_15_MASK   (0x400U)
 
#define DP83848_PHYCR_PSR_15_SHIFT   (10U)
 
#define DP83848_PHYCR_PSR_15_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_PSR_15_SHIFT) & DP83848_PHYCR_PSR_15_MASK)
 
#define DP83848_PHYCR_PSR_15_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_PSR_15_MASK) >> DP83848_PHYCR_PSR_15_SHIFT)
 
#define DP83848_PHYCR_BIST_STATUS_MASK   (0x200U)
 
#define DP83848_PHYCR_BIST_STATUS_SHIFT   (9U)
 
#define DP83848_PHYCR_BIST_STATUS_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_BIST_STATUS_MASK) >> DP83848_PHYCR_BIST_STATUS_SHIFT)
 
#define DP83848_PHYCR_BIST_START_MASK   (0x100U)
 
#define DP83848_PHYCR_BIST_START_SHIFT   (8U)
 
#define DP83848_PHYCR_BIST_START_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_BIST_START_SHIFT) & DP83848_PHYCR_BIST_START_MASK)
 
#define DP83848_PHYCR_BIST_START_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_BIST_START_MASK) >> DP83848_PHYCR_BIST_START_SHIFT)
 
#define DP83848_PHYCR_BP_STRETCH_MASK   (0x80U)
 
#define DP83848_PHYCR_BP_STRETCH_SHIFT   (7U)
 
#define DP83848_PHYCR_BP_STRETCH_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_BP_STRETCH_SHIFT) & DP83848_PHYCR_BP_STRETCH_MASK)
 
#define DP83848_PHYCR_BP_STRETCH_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_BP_STRETCH_MASK) >> DP83848_PHYCR_BP_STRETCH_SHIFT)
 
#define DP83848_PHYCR_LED_CNFG_0_MASK   (0x20U)
 
#define DP83848_PHYCR_LED_CNFG_0_SHIFT   (5U)
 
#define DP83848_PHYCR_LED_CNFG_0_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_LED_CNFG_0_SHIFT) & DP83848_PHYCR_LED_CNFG_0_MASK)
 
#define DP83848_PHYCR_LED_CNFG_0_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_LED_CNFG_0_MASK) >> DP83848_PHYCR_LED_CNFG_0_SHIFT)
 
#define DP83848_PHYCR_PHYADDR_4_0_MASK   (0x1FU)
 
#define DP83848_PHYCR_PHYADDR_4_0_SHIFT   (0U)
 
#define DP83848_PHYCR_PHYADDR_4_0_SET(x)   (((uint16_t)(x) << DP83848_PHYCR_PHYADDR_4_0_SHIFT) & DP83848_PHYCR_PHYADDR_4_0_MASK)
 
#define DP83848_PHYCR_PHYADDR_4_0_GET(x)   (((uint16_t)(x) & DP83848_PHYCR_PHYADDR_4_0_MASK) >> DP83848_PHYCR_PHYADDR_4_0_SHIFT)
 
#define DP83848_10BTSCR_SQUELCH_MASK   (0xE00U)
 
#define DP83848_10BTSCR_SQUELCH_SHIFT   (9U)
 
#define DP83848_10BTSCR_SQUELCH_SET(x)   (((uint16_t)(x) << DP83848_10BTSCR_SQUELCH_SHIFT) & DP83848_10BTSCR_SQUELCH_MASK)
 
#define DP83848_10BTSCR_SQUELCH_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_SQUELCH_MASK) >> DP83848_10BTSCR_SQUELCH_SHIFT)
 
#define DP83848_10BTSCR_LOOPBACK_10_DIS_MASK   (0x100U)
 
#define DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT   (8U)
 
#define DP83848_10BTSCR_LOOPBACK_10_DIS_SET(x)   (((uint16_t)(x) << DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK)
 
#define DP83848_10BTSCR_LOOPBACK_10_DIS_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) >> DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT)
 
#define DP83848_10BTSCR_LP_DIS_MASK   (0x80U)
 
#define DP83848_10BTSCR_LP_DIS_SHIFT   (7U)
 
#define DP83848_10BTSCR_LP_DIS_SET(x)   (((uint16_t)(x) << DP83848_10BTSCR_LP_DIS_SHIFT) & DP83848_10BTSCR_LP_DIS_MASK)
 
#define DP83848_10BTSCR_LP_DIS_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_LP_DIS_MASK) >> DP83848_10BTSCR_LP_DIS_SHIFT)
 
#define DP83848_10BTSCR_FORCE_LINK_10_MASK   (0x40U)
 
#define DP83848_10BTSCR_FORCE_LINK_10_SHIFT   (6U)
 
#define DP83848_10BTSCR_FORCE_LINK_10_SET(x)   (((uint16_t)(x) << DP83848_10BTSCR_FORCE_LINK_10_SHIFT) & DP83848_10BTSCR_FORCE_LINK_10_MASK)
 
#define DP83848_10BTSCR_FORCE_LINK_10_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_FORCE_LINK_10_MASK) >> DP83848_10BTSCR_FORCE_LINK_10_SHIFT)
 
#define DP83848_10BTSCR_POLARITY_MASK   (0x10U)
 
#define DP83848_10BTSCR_POLARITY_SHIFT   (4U)
 
#define DP83848_10BTSCR_POLARITY_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_POLARITY_MASK) >> DP83848_10BTSCR_POLARITY_SHIFT)
 
#define DP83848_10BTSCR_HEARTBEAT_DIS_MASK   (0x2U)
 
#define DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT   (1U)
 
#define DP83848_10BTSCR_HEARTBEAT_DIS_SET(x)   (((uint16_t)(x) << DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK)
 
#define DP83848_10BTSCR_HEARTBEAT_DIS_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) >> DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT)
 
#define DP83848_10BTSCR_JABBER_DIS_MASK   (0x1U)
 
#define DP83848_10BTSCR_JABBER_DIS_SHIFT   (0U)
 
#define DP83848_10BTSCR_JABBER_DIS_SET(x)   (((uint16_t)(x) << DP83848_10BTSCR_JABBER_DIS_SHIFT) & DP83848_10BTSCR_JABBER_DIS_MASK)
 
#define DP83848_10BTSCR_JABBER_DIS_GET(x)   (((uint16_t)(x) & DP83848_10BTSCR_JABBER_DIS_MASK) >> DP83848_10BTSCR_JABBER_DIS_SHIFT)
 
#define DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK   (0xFF00U)
 
#define DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT   (8U)
 
#define DP83848_CDCTRL1_BIST_ERROR_COUNT_GET(x)   (((uint16_t)(x) & DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK) >> DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT)
 
#define DP83848_CDCTRL1_BIST_CONT_MODE_MASK   (0x20U)
 
#define DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT   (5U)
 
#define DP83848_CDCTRL1_BIST_CONT_MODE_SET(x)   (((uint16_t)(x) << DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK)
 
#define DP83848_CDCTRL1_BIST_CONT_MODE_GET(x)   (((uint16_t)(x) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) >> DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT)
 
#define DP83848_CDCTRL1_CDPATTEN_10_MASK   (0x10U)
 
#define DP83848_CDCTRL1_CDPATTEN_10_SHIFT   (4U)
 
#define DP83848_CDCTRL1_CDPATTEN_10_SET(x)   (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTEN_10_SHIFT) & DP83848_CDCTRL1_CDPATTEN_10_MASK)
 
#define DP83848_CDCTRL1_CDPATTEN_10_GET(x)   (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTEN_10_MASK) >> DP83848_CDCTRL1_CDPATTEN_10_SHIFT)
 
#define DP83848_CDCTRL1_10MEG_PATT_GAP_MASK   (0x4U)
 
#define DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT   (2U)
 
#define DP83848_CDCTRL1_10MEG_PATT_GAP_SET(x)   (((uint16_t)(x) << DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK)
 
#define DP83848_CDCTRL1_10MEG_PATT_GAP_GET(x)   (((uint16_t)(x) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) >> DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT)
 
#define DP83848_CDCTRL1_CDPATTSEL_1_0_MASK   (0x3U)
 
#define DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT   (0U)
 
#define DP83848_CDCTRL1_CDPATTSEL_1_0_SET(x)   (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK)
 
#define DP83848_CDCTRL1_CDPATTSEL_1_0_GET(x)   (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) >> DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT)
 
#define DP83848_EDCR_ED_EN_MASK   (0x8000U)
 
#define DP83848_EDCR_ED_EN_SHIFT   (15U)
 
#define DP83848_EDCR_ED_EN_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_EN_SHIFT) & DP83848_EDCR_ED_EN_MASK)
 
#define DP83848_EDCR_ED_EN_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_EN_MASK) >> DP83848_EDCR_ED_EN_SHIFT)
 
#define DP83848_EDCR_ED_AUTO_UP_MASK   (0x4000U)
 
#define DP83848_EDCR_ED_AUTO_UP_SHIFT   (14U)
 
#define DP83848_EDCR_ED_AUTO_UP_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_UP_SHIFT) & DP83848_EDCR_ED_AUTO_UP_MASK)
 
#define DP83848_EDCR_ED_AUTO_UP_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_UP_MASK) >> DP83848_EDCR_ED_AUTO_UP_SHIFT)
 
#define DP83848_EDCR_ED_AUTO_DOWN_MASK   (0x2000U)
 
#define DP83848_EDCR_ED_AUTO_DOWN_SHIFT   (13U)
 
#define DP83848_EDCR_ED_AUTO_DOWN_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_DOWN_SHIFT) & DP83848_EDCR_ED_AUTO_DOWN_MASK)
 
#define DP83848_EDCR_ED_AUTO_DOWN_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_DOWN_MASK) >> DP83848_EDCR_ED_AUTO_DOWN_SHIFT)
 
#define DP83848_EDCR_ED_MAN_MASK   (0x1000U)
 
#define DP83848_EDCR_ED_MAN_SHIFT   (12U)
 
#define DP83848_EDCR_ED_MAN_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_MAN_SHIFT) & DP83848_EDCR_ED_MAN_MASK)
 
#define DP83848_EDCR_ED_MAN_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_MAN_MASK) >> DP83848_EDCR_ED_MAN_SHIFT)
 
#define DP83848_EDCR_ED_BURST_DIS_MASK   (0x800U)
 
#define DP83848_EDCR_ED_BURST_DIS_SHIFT   (11U)
 
#define DP83848_EDCR_ED_BURST_DIS_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_BURST_DIS_SHIFT) & DP83848_EDCR_ED_BURST_DIS_MASK)
 
#define DP83848_EDCR_ED_BURST_DIS_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_BURST_DIS_MASK) >> DP83848_EDCR_ED_BURST_DIS_SHIFT)
 
#define DP83848_EDCR_ED_PWR_STATE_MASK   (0x400U)
 
#define DP83848_EDCR_ED_PWR_STATE_SHIFT   (10U)
 
#define DP83848_EDCR_ED_PWR_STATE_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_PWR_STATE_MASK) >> DP83848_EDCR_ED_PWR_STATE_SHIFT)
 
#define DP83848_EDCR_ED_ERR_MET_MASK   (0x200U)
 
#define DP83848_EDCR_ED_ERR_MET_SHIFT   (9U)
 
#define DP83848_EDCR_ED_ERR_MET_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_ERR_MET_MASK) >> DP83848_EDCR_ED_ERR_MET_SHIFT)
 
#define DP83848_EDCR_ED_DATA_MET_MASK   (0x100U)
 
#define DP83848_EDCR_ED_DATA_MET_SHIFT   (8U)
 
#define DP83848_EDCR_ED_DATA_MET_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_DATA_MET_MASK) >> DP83848_EDCR_ED_DATA_MET_SHIFT)
 
#define DP83848_EDCR_ED_ERR_COUNT_MASK   (0xF0U)
 
#define DP83848_EDCR_ED_ERR_COUNT_SHIFT   (4U)
 
#define DP83848_EDCR_ED_ERR_COUNT_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_ERR_COUNT_SHIFT) & DP83848_EDCR_ED_ERR_COUNT_MASK)
 
#define DP83848_EDCR_ED_ERR_COUNT_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_ERR_COUNT_MASK) >> DP83848_EDCR_ED_ERR_COUNT_SHIFT)
 
#define DP83848_EDCR_ED_DATA_COUNT_MASK   (0xFU)
 
#define DP83848_EDCR_ED_DATA_COUNT_SHIFT   (0U)
 
#define DP83848_EDCR_ED_DATA_COUNT_SET(x)   (((uint16_t)(x) << DP83848_EDCR_ED_DATA_COUNT_SHIFT) & DP83848_EDCR_ED_DATA_COUNT_MASK)
 
#define DP83848_EDCR_ED_DATA_COUNT_GET(x)   (((uint16_t)(x) & DP83848_EDCR_ED_DATA_COUNT_MASK) >> DP83848_EDCR_ED_DATA_COUNT_SHIFT)
 

Enumerations

enum  DP83848_REG_Type {
  DP83848_BMCR = 0 , DP83848_BMSR = 1 , DP83848_PHYIDR1 = 2 , DP83848_PHYIDR2 = 3 ,
  DP83848_ANAR = 4 , DP83848_ANLPAR_BP = 5 , DP83848_ANER = 6 , DP83848_ANNPTR = 7 ,
  DP83848_PHYSTS = 16 , DP83848_FCSCR = 20 , DP83848_RECR = 21 , DP83848_PCSR = 22 ,
  DP83848_RBR = 23 , DP83848_LEDCR = 24 , DP83848_PHYCR = 25 , DP83848_10BTSCR = 26 ,
  DP83848_CDCTRL1 = 27 , DP83848_EDCR = 29
}
 

Macro Definition Documentation

◆ DP83848_10BTSCR_FORCE_LINK_10_GET

#define DP83848_10BTSCR_FORCE_LINK_10_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_FORCE_LINK_10_MASK) >> DP83848_10BTSCR_FORCE_LINK_10_SHIFT)

◆ DP83848_10BTSCR_FORCE_LINK_10_MASK

#define DP83848_10BTSCR_FORCE_LINK_10_MASK   (0x40U)

◆ DP83848_10BTSCR_FORCE_LINK_10_SET

#define DP83848_10BTSCR_FORCE_LINK_10_SET (   x)    (((uint16_t)(x) << DP83848_10BTSCR_FORCE_LINK_10_SHIFT) & DP83848_10BTSCR_FORCE_LINK_10_MASK)

◆ DP83848_10BTSCR_FORCE_LINK_10_SHIFT

#define DP83848_10BTSCR_FORCE_LINK_10_SHIFT   (6U)

◆ DP83848_10BTSCR_HEARTBEAT_DIS_GET

#define DP83848_10BTSCR_HEARTBEAT_DIS_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) >> DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT)

◆ DP83848_10BTSCR_HEARTBEAT_DIS_MASK

#define DP83848_10BTSCR_HEARTBEAT_DIS_MASK   (0x2U)

◆ DP83848_10BTSCR_HEARTBEAT_DIS_SET

#define DP83848_10BTSCR_HEARTBEAT_DIS_SET (   x)    (((uint16_t)(x) << DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK)

◆ DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT

#define DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT   (1U)

◆ DP83848_10BTSCR_JABBER_DIS_GET

#define DP83848_10BTSCR_JABBER_DIS_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_JABBER_DIS_MASK) >> DP83848_10BTSCR_JABBER_DIS_SHIFT)

◆ DP83848_10BTSCR_JABBER_DIS_MASK

#define DP83848_10BTSCR_JABBER_DIS_MASK   (0x1U)

◆ DP83848_10BTSCR_JABBER_DIS_SET

#define DP83848_10BTSCR_JABBER_DIS_SET (   x)    (((uint16_t)(x) << DP83848_10BTSCR_JABBER_DIS_SHIFT) & DP83848_10BTSCR_JABBER_DIS_MASK)

◆ DP83848_10BTSCR_JABBER_DIS_SHIFT

#define DP83848_10BTSCR_JABBER_DIS_SHIFT   (0U)

◆ DP83848_10BTSCR_LOOPBACK_10_DIS_GET

#define DP83848_10BTSCR_LOOPBACK_10_DIS_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) >> DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT)

◆ DP83848_10BTSCR_LOOPBACK_10_DIS_MASK

#define DP83848_10BTSCR_LOOPBACK_10_DIS_MASK   (0x100U)

◆ DP83848_10BTSCR_LOOPBACK_10_DIS_SET

#define DP83848_10BTSCR_LOOPBACK_10_DIS_SET (   x)    (((uint16_t)(x) << DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK)

◆ DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT

#define DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT   (8U)

◆ DP83848_10BTSCR_LP_DIS_GET

#define DP83848_10BTSCR_LP_DIS_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_LP_DIS_MASK) >> DP83848_10BTSCR_LP_DIS_SHIFT)

◆ DP83848_10BTSCR_LP_DIS_MASK

#define DP83848_10BTSCR_LP_DIS_MASK   (0x80U)

◆ DP83848_10BTSCR_LP_DIS_SET

#define DP83848_10BTSCR_LP_DIS_SET (   x)    (((uint16_t)(x) << DP83848_10BTSCR_LP_DIS_SHIFT) & DP83848_10BTSCR_LP_DIS_MASK)

◆ DP83848_10BTSCR_LP_DIS_SHIFT

#define DP83848_10BTSCR_LP_DIS_SHIFT   (7U)

◆ DP83848_10BTSCR_POLARITY_GET

#define DP83848_10BTSCR_POLARITY_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_POLARITY_MASK) >> DP83848_10BTSCR_POLARITY_SHIFT)

◆ DP83848_10BTSCR_POLARITY_MASK

#define DP83848_10BTSCR_POLARITY_MASK   (0x10U)

◆ DP83848_10BTSCR_POLARITY_SHIFT

#define DP83848_10BTSCR_POLARITY_SHIFT   (4U)

◆ DP83848_10BTSCR_SQUELCH_GET

#define DP83848_10BTSCR_SQUELCH_GET (   x)    (((uint16_t)(x) & DP83848_10BTSCR_SQUELCH_MASK) >> DP83848_10BTSCR_SQUELCH_SHIFT)

◆ DP83848_10BTSCR_SQUELCH_MASK

#define DP83848_10BTSCR_SQUELCH_MASK   (0xE00U)

◆ DP83848_10BTSCR_SQUELCH_SET

#define DP83848_10BTSCR_SQUELCH_SET (   x)    (((uint16_t)(x) << DP83848_10BTSCR_SQUELCH_SHIFT) & DP83848_10BTSCR_SQUELCH_MASK)

◆ DP83848_10BTSCR_SQUELCH_SHIFT

#define DP83848_10BTSCR_SQUELCH_SHIFT   (9U)

◆ DP83848_ANAR_10_FD_GET

#define DP83848_ANAR_10_FD_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_10_FD_MASK) >> DP83848_ANAR_10_FD_SHIFT)

◆ DP83848_ANAR_10_FD_MASK

#define DP83848_ANAR_10_FD_MASK   (0x40U)

◆ DP83848_ANAR_10_FD_SET

#define DP83848_ANAR_10_FD_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_10_FD_SHIFT) & DP83848_ANAR_10_FD_MASK)

◆ DP83848_ANAR_10_FD_SHIFT

#define DP83848_ANAR_10_FD_SHIFT   (6U)

◆ DP83848_ANAR_10_GET

#define DP83848_ANAR_10_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_10_MASK) >> DP83848_ANAR_10_SHIFT)

◆ DP83848_ANAR_10_MASK

#define DP83848_ANAR_10_MASK   (0x20U)

◆ DP83848_ANAR_10_SET

#define DP83848_ANAR_10_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_10_SHIFT) & DP83848_ANAR_10_MASK)

◆ DP83848_ANAR_10_SHIFT

#define DP83848_ANAR_10_SHIFT   (5U)

◆ DP83848_ANAR_ASM_DIR_GET

#define DP83848_ANAR_ASM_DIR_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_ASM_DIR_MASK) >> DP83848_ANAR_ASM_DIR_SHIFT)

◆ DP83848_ANAR_ASM_DIR_MASK

#define DP83848_ANAR_ASM_DIR_MASK   (0x800U)

◆ DP83848_ANAR_ASM_DIR_SET

#define DP83848_ANAR_ASM_DIR_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_ASM_DIR_SHIFT) & DP83848_ANAR_ASM_DIR_MASK)

◆ DP83848_ANAR_ASM_DIR_SHIFT

#define DP83848_ANAR_ASM_DIR_SHIFT   (11U)

◆ DP83848_ANAR_NP_GET

#define DP83848_ANAR_NP_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_NP_MASK) >> DP83848_ANAR_NP_SHIFT)

◆ DP83848_ANAR_NP_MASK

#define DP83848_ANAR_NP_MASK   (0x8000U)

◆ DP83848_ANAR_NP_SET

#define DP83848_ANAR_NP_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_NP_SHIFT) & DP83848_ANAR_NP_MASK)

◆ DP83848_ANAR_NP_SHIFT

#define DP83848_ANAR_NP_SHIFT   (15U)

◆ DP83848_ANAR_PAUSE_GET

#define DP83848_ANAR_PAUSE_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_PAUSE_MASK) >> DP83848_ANAR_PAUSE_SHIFT)

◆ DP83848_ANAR_PAUSE_MASK

#define DP83848_ANAR_PAUSE_MASK   (0x400U)

◆ DP83848_ANAR_PAUSE_SET

#define DP83848_ANAR_PAUSE_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_PAUSE_SHIFT) & DP83848_ANAR_PAUSE_MASK)

◆ DP83848_ANAR_PAUSE_SHIFT

#define DP83848_ANAR_PAUSE_SHIFT   (10U)

◆ DP83848_ANAR_RF_GET

#define DP83848_ANAR_RF_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_RF_MASK) >> DP83848_ANAR_RF_SHIFT)

◆ DP83848_ANAR_RF_MASK

#define DP83848_ANAR_RF_MASK   (0x2000U)

◆ DP83848_ANAR_RF_SET

#define DP83848_ANAR_RF_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_RF_SHIFT) & DP83848_ANAR_RF_MASK)

◆ DP83848_ANAR_RF_SHIFT

#define DP83848_ANAR_RF_SHIFT   (13U)

◆ DP83848_ANAR_SELECTOR_GET

#define DP83848_ANAR_SELECTOR_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_SELECTOR_MASK) >> DP83848_ANAR_SELECTOR_SHIFT)

◆ DP83848_ANAR_SELECTOR_MASK

#define DP83848_ANAR_SELECTOR_MASK   (0x1FU)

◆ DP83848_ANAR_SELECTOR_SET

#define DP83848_ANAR_SELECTOR_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_SELECTOR_SHIFT) & DP83848_ANAR_SELECTOR_MASK)

◆ DP83848_ANAR_SELECTOR_SHIFT

#define DP83848_ANAR_SELECTOR_SHIFT   (0U)

◆ DP83848_ANAR_T4_GET

#define DP83848_ANAR_T4_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_T4_MASK) >> DP83848_ANAR_T4_SHIFT)

◆ DP83848_ANAR_T4_MASK

#define DP83848_ANAR_T4_MASK   (0x200U)

◆ DP83848_ANAR_T4_SHIFT

#define DP83848_ANAR_T4_SHIFT   (9U)

◆ DP83848_ANAR_TX_FD_GET

#define DP83848_ANAR_TX_FD_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_TX_FD_MASK) >> DP83848_ANAR_TX_FD_SHIFT)

◆ DP83848_ANAR_TX_FD_MASK

#define DP83848_ANAR_TX_FD_MASK   (0x100U)

◆ DP83848_ANAR_TX_FD_SET

#define DP83848_ANAR_TX_FD_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_TX_FD_SHIFT) & DP83848_ANAR_TX_FD_MASK)

◆ DP83848_ANAR_TX_FD_SHIFT

#define DP83848_ANAR_TX_FD_SHIFT   (8U)

◆ DP83848_ANAR_TX_GET

#define DP83848_ANAR_TX_GET (   x)    (((uint16_t)(x) & DP83848_ANAR_TX_MASK) >> DP83848_ANAR_TX_SHIFT)

◆ DP83848_ANAR_TX_MASK

#define DP83848_ANAR_TX_MASK   (0x80U)

◆ DP83848_ANAR_TX_SET

#define DP83848_ANAR_TX_SET (   x)    (((uint16_t)(x) << DP83848_ANAR_TX_SHIFT) & DP83848_ANAR_TX_MASK)

◆ DP83848_ANAR_TX_SHIFT

#define DP83848_ANAR_TX_SHIFT   (7U)

◆ DP83848_ANER_LP_AN_ABLE_GET

#define DP83848_ANER_LP_AN_ABLE_GET (   x)    (((uint16_t)(x) & DP83848_ANER_LP_AN_ABLE_MASK) >> DP83848_ANER_LP_AN_ABLE_SHIFT)

◆ DP83848_ANER_LP_AN_ABLE_MASK

#define DP83848_ANER_LP_AN_ABLE_MASK   (0x1U)

◆ DP83848_ANER_LP_AN_ABLE_SHIFT

#define DP83848_ANER_LP_AN_ABLE_SHIFT   (0U)

◆ DP83848_ANER_LP_NP_ABLE_GET

#define DP83848_ANER_LP_NP_ABLE_GET (   x)    (((uint16_t)(x) & DP83848_ANER_LP_NP_ABLE_MASK) >> DP83848_ANER_LP_NP_ABLE_SHIFT)

◆ DP83848_ANER_LP_NP_ABLE_MASK

#define DP83848_ANER_LP_NP_ABLE_MASK   (0x8U)

◆ DP83848_ANER_LP_NP_ABLE_SHIFT

#define DP83848_ANER_LP_NP_ABLE_SHIFT   (3U)

◆ DP83848_ANER_NP_ABLE_GET

#define DP83848_ANER_NP_ABLE_GET (   x)    (((uint16_t)(x) & DP83848_ANER_NP_ABLE_MASK) >> DP83848_ANER_NP_ABLE_SHIFT)

◆ DP83848_ANER_NP_ABLE_MASK

#define DP83848_ANER_NP_ABLE_MASK   (0x4U)

◆ DP83848_ANER_NP_ABLE_SHIFT

#define DP83848_ANER_NP_ABLE_SHIFT   (2U)

◆ DP83848_ANER_PAGE_RX_GET

#define DP83848_ANER_PAGE_RX_GET (   x)    (((uint16_t)(x) & DP83848_ANER_PAGE_RX_MASK) >> DP83848_ANER_PAGE_RX_SHIFT)

◆ DP83848_ANER_PAGE_RX_MASK

#define DP83848_ANER_PAGE_RX_MASK   (0x2U)

◆ DP83848_ANER_PAGE_RX_SHIFT

#define DP83848_ANER_PAGE_RX_SHIFT   (1U)

◆ DP83848_ANER_PDF_GET

#define DP83848_ANER_PDF_GET (   x)    (((uint16_t)(x) & DP83848_ANER_PDF_MASK) >> DP83848_ANER_PDF_SHIFT)

◆ DP83848_ANER_PDF_MASK

#define DP83848_ANER_PDF_MASK   (0x10U)

◆ DP83848_ANER_PDF_SHIFT

#define DP83848_ANER_PDF_SHIFT   (4U)

◆ DP83848_ANLPAR_BP_10_FD_GET

#define DP83848_ANLPAR_BP_10_FD_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_10_FD_MASK) >> DP83848_ANLPAR_BP_10_FD_SHIFT)

◆ DP83848_ANLPAR_BP_10_FD_MASK

#define DP83848_ANLPAR_BP_10_FD_MASK   (0x40U)

◆ DP83848_ANLPAR_BP_10_FD_SHIFT

#define DP83848_ANLPAR_BP_10_FD_SHIFT   (6U)

◆ DP83848_ANLPAR_BP_10_GET

#define DP83848_ANLPAR_BP_10_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_10_MASK) >> DP83848_ANLPAR_BP_10_SHIFT)

◆ DP83848_ANLPAR_BP_10_MASK

#define DP83848_ANLPAR_BP_10_MASK   (0x20U)

◆ DP83848_ANLPAR_BP_10_SHIFT

#define DP83848_ANLPAR_BP_10_SHIFT   (5U)

◆ DP83848_ANLPAR_BP_ACK_GET

#define DP83848_ANLPAR_BP_ACK_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_ACK_MASK) >> DP83848_ANLPAR_BP_ACK_SHIFT)

◆ DP83848_ANLPAR_BP_ACK_MASK

#define DP83848_ANLPAR_BP_ACK_MASK   (0x4000U)

◆ DP83848_ANLPAR_BP_ACK_SHIFT

#define DP83848_ANLPAR_BP_ACK_SHIFT   (14U)

◆ DP83848_ANLPAR_BP_ASM_DIR_GET

#define DP83848_ANLPAR_BP_ASM_DIR_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_ASM_DIR_MASK) >> DP83848_ANLPAR_BP_ASM_DIR_SHIFT)

◆ DP83848_ANLPAR_BP_ASM_DIR_MASK

#define DP83848_ANLPAR_BP_ASM_DIR_MASK   (0x800U)

◆ DP83848_ANLPAR_BP_ASM_DIR_SHIFT

#define DP83848_ANLPAR_BP_ASM_DIR_SHIFT   (11U)

◆ DP83848_ANLPAR_BP_NP_GET

#define DP83848_ANLPAR_BP_NP_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_NP_MASK) >> DP83848_ANLPAR_BP_NP_SHIFT)

◆ DP83848_ANLPAR_BP_NP_MASK

#define DP83848_ANLPAR_BP_NP_MASK   (0x8000U)

◆ DP83848_ANLPAR_BP_NP_SHIFT

#define DP83848_ANLPAR_BP_NP_SHIFT   (15U)

◆ DP83848_ANLPAR_BP_PAUSE_GET

#define DP83848_ANLPAR_BP_PAUSE_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_PAUSE_MASK) >> DP83848_ANLPAR_BP_PAUSE_SHIFT)

◆ DP83848_ANLPAR_BP_PAUSE_MASK

#define DP83848_ANLPAR_BP_PAUSE_MASK   (0x400U)

◆ DP83848_ANLPAR_BP_PAUSE_SHIFT

#define DP83848_ANLPAR_BP_PAUSE_SHIFT   (10U)

◆ DP83848_ANLPAR_BP_RF_GET

#define DP83848_ANLPAR_BP_RF_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_RF_MASK) >> DP83848_ANLPAR_BP_RF_SHIFT)

◆ DP83848_ANLPAR_BP_RF_MASK

#define DP83848_ANLPAR_BP_RF_MASK   (0x2000U)

◆ DP83848_ANLPAR_BP_RF_SHIFT

#define DP83848_ANLPAR_BP_RF_SHIFT   (13U)

◆ DP83848_ANLPAR_BP_SELECTOR_GET

#define DP83848_ANLPAR_BP_SELECTOR_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_SELECTOR_MASK) >> DP83848_ANLPAR_BP_SELECTOR_SHIFT)

◆ DP83848_ANLPAR_BP_SELECTOR_MASK

#define DP83848_ANLPAR_BP_SELECTOR_MASK   (0x1FU)

◆ DP83848_ANLPAR_BP_SELECTOR_SHIFT

#define DP83848_ANLPAR_BP_SELECTOR_SHIFT   (0U)

◆ DP83848_ANLPAR_BP_T4_GET

#define DP83848_ANLPAR_BP_T4_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_T4_MASK) >> DP83848_ANLPAR_BP_T4_SHIFT)

◆ DP83848_ANLPAR_BP_T4_MASK

#define DP83848_ANLPAR_BP_T4_MASK   (0x200U)

◆ DP83848_ANLPAR_BP_T4_SHIFT

#define DP83848_ANLPAR_BP_T4_SHIFT   (9U)

◆ DP83848_ANLPAR_BP_TX_FD_GET

#define DP83848_ANLPAR_BP_TX_FD_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_FD_MASK) >> DP83848_ANLPAR_BP_TX_FD_SHIFT)

◆ DP83848_ANLPAR_BP_TX_FD_MASK

#define DP83848_ANLPAR_BP_TX_FD_MASK   (0x100U)

◆ DP83848_ANLPAR_BP_TX_FD_SHIFT

#define DP83848_ANLPAR_BP_TX_FD_SHIFT   (8U)

◆ DP83848_ANLPAR_BP_TX_GET

#define DP83848_ANLPAR_BP_TX_GET (   x)    (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_MASK) >> DP83848_ANLPAR_BP_TX_SHIFT)

◆ DP83848_ANLPAR_BP_TX_MASK

#define DP83848_ANLPAR_BP_TX_MASK   (0x80U)

◆ DP83848_ANLPAR_BP_TX_SHIFT

#define DP83848_ANLPAR_BP_TX_SHIFT   (7U)

◆ DP83848_ANNPTR_ACK2_GET

#define DP83848_ANNPTR_ACK2_GET (   x)    (((uint16_t)(x) & DP83848_ANNPTR_ACK2_MASK) >> DP83848_ANNPTR_ACK2_SHIFT)

◆ DP83848_ANNPTR_ACK2_MASK

#define DP83848_ANNPTR_ACK2_MASK   (0x1000U)

◆ DP83848_ANNPTR_ACK2_SET

#define DP83848_ANNPTR_ACK2_SET (   x)    (((uint16_t)(x) << DP83848_ANNPTR_ACK2_SHIFT) & DP83848_ANNPTR_ACK2_MASK)

◆ DP83848_ANNPTR_ACK2_SHIFT

#define DP83848_ANNPTR_ACK2_SHIFT   (12U)

◆ DP83848_ANNPTR_CODE_GET

#define DP83848_ANNPTR_CODE_GET (   x)    (((uint16_t)(x) & DP83848_ANNPTR_CODE_MASK) >> DP83848_ANNPTR_CODE_SHIFT)

◆ DP83848_ANNPTR_CODE_MASK

#define DP83848_ANNPTR_CODE_MASK   (0x400U)

◆ DP83848_ANNPTR_CODE_SET

#define DP83848_ANNPTR_CODE_SET (   x)    (((uint16_t)(x) << DP83848_ANNPTR_CODE_SHIFT) & DP83848_ANNPTR_CODE_MASK)

◆ DP83848_ANNPTR_CODE_SHIFT

#define DP83848_ANNPTR_CODE_SHIFT   (10U)

◆ DP83848_ANNPTR_MP_GET

#define DP83848_ANNPTR_MP_GET (   x)    (((uint16_t)(x) & DP83848_ANNPTR_MP_MASK) >> DP83848_ANNPTR_MP_SHIFT)

◆ DP83848_ANNPTR_MP_MASK

#define DP83848_ANNPTR_MP_MASK   (0x2000U)

◆ DP83848_ANNPTR_MP_SET

#define DP83848_ANNPTR_MP_SET (   x)    (((uint16_t)(x) << DP83848_ANNPTR_MP_SHIFT) & DP83848_ANNPTR_MP_MASK)

◆ DP83848_ANNPTR_MP_SHIFT

#define DP83848_ANNPTR_MP_SHIFT   (13U)

◆ DP83848_ANNPTR_NP_GET

#define DP83848_ANNPTR_NP_GET (   x)    (((uint16_t)(x) & DP83848_ANNPTR_NP_MASK) >> DP83848_ANNPTR_NP_SHIFT)

◆ DP83848_ANNPTR_NP_MASK

#define DP83848_ANNPTR_NP_MASK   (0x8000U)

◆ DP83848_ANNPTR_NP_SET

#define DP83848_ANNPTR_NP_SET (   x)    (((uint16_t)(x) << DP83848_ANNPTR_NP_SHIFT) & DP83848_ANNPTR_NP_MASK)

◆ DP83848_ANNPTR_NP_SHIFT

#define DP83848_ANNPTR_NP_SHIFT   (15U)

◆ DP83848_ANNPTR_TOG_TX_GET

#define DP83848_ANNPTR_TOG_TX_GET (   x)    (((uint16_t)(x) & DP83848_ANNPTR_TOG_TX_MASK) >> DP83848_ANNPTR_TOG_TX_SHIFT)

◆ DP83848_ANNPTR_TOG_TX_MASK

#define DP83848_ANNPTR_TOG_TX_MASK   (0x800U)

◆ DP83848_ANNPTR_TOG_TX_SET

#define DP83848_ANNPTR_TOG_TX_SET (   x)    (((uint16_t)(x) << DP83848_ANNPTR_TOG_TX_SHIFT) & DP83848_ANNPTR_TOG_TX_MASK)

◆ DP83848_ANNPTR_TOG_TX_SHIFT

#define DP83848_ANNPTR_TOG_TX_SHIFT   (11U)

◆ DP83848_BMCR_ANE_GET

#define DP83848_BMCR_ANE_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT)

◆ DP83848_BMCR_ANE_MASK

#define DP83848_BMCR_ANE_MASK   (0x1000U)

◆ DP83848_BMCR_ANE_SET

#define DP83848_BMCR_ANE_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK)

◆ DP83848_BMCR_ANE_SHIFT

#define DP83848_BMCR_ANE_SHIFT   (12U)

◆ DP83848_BMCR_COLLISION_TEST_GET

#define DP83848_BMCR_COLLISION_TEST_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT)

◆ DP83848_BMCR_COLLISION_TEST_MASK

#define DP83848_BMCR_COLLISION_TEST_MASK   (0x80U)

◆ DP83848_BMCR_COLLISION_TEST_SET

#define DP83848_BMCR_COLLISION_TEST_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK)

◆ DP83848_BMCR_COLLISION_TEST_SHIFT

#define DP83848_BMCR_COLLISION_TEST_SHIFT   (7U)

◆ DP83848_BMCR_DUPLEX_GET

#define DP83848_BMCR_DUPLEX_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT)

◆ DP83848_BMCR_DUPLEX_MASK

#define DP83848_BMCR_DUPLEX_MASK   (0x100U)

◆ DP83848_BMCR_DUPLEX_SET

#define DP83848_BMCR_DUPLEX_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK)

◆ DP83848_BMCR_DUPLEX_SHIFT

#define DP83848_BMCR_DUPLEX_SHIFT   (8U)

◆ DP83848_BMCR_ISOLATE_GET

#define DP83848_BMCR_ISOLATE_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT)

◆ DP83848_BMCR_ISOLATE_MASK

#define DP83848_BMCR_ISOLATE_MASK   (0x400U)

◆ DP83848_BMCR_ISOLATE_SET

#define DP83848_BMCR_ISOLATE_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK)

◆ DP83848_BMCR_ISOLATE_SHIFT

#define DP83848_BMCR_ISOLATE_SHIFT   (10U)

◆ DP83848_BMCR_LOOPBACK_GET

#define DP83848_BMCR_LOOPBACK_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT)

◆ DP83848_BMCR_LOOPBACK_MASK

#define DP83848_BMCR_LOOPBACK_MASK   (0x4000U)

◆ DP83848_BMCR_LOOPBACK_SET

#define DP83848_BMCR_LOOPBACK_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK)

◆ DP83848_BMCR_LOOPBACK_SHIFT

#define DP83848_BMCR_LOOPBACK_SHIFT   (14U)

◆ DP83848_BMCR_PWD_GET

#define DP83848_BMCR_PWD_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT)

◆ DP83848_BMCR_PWD_MASK

#define DP83848_BMCR_PWD_MASK   (0x800U)

◆ DP83848_BMCR_PWD_SET

#define DP83848_BMCR_PWD_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK)

◆ DP83848_BMCR_PWD_SHIFT

#define DP83848_BMCR_PWD_SHIFT   (11U)

◆ DP83848_BMCR_RESET_GET

#define DP83848_BMCR_RESET_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT)

◆ DP83848_BMCR_RESET_MASK

#define DP83848_BMCR_RESET_MASK   (0x8000U)

◆ DP83848_BMCR_RESET_SET

#define DP83848_BMCR_RESET_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK)

◆ DP83848_BMCR_RESET_SHIFT

#define DP83848_BMCR_RESET_SHIFT   (15U)

◆ DP83848_BMCR_RESTART_AN_GET

#define DP83848_BMCR_RESTART_AN_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT)

◆ DP83848_BMCR_RESTART_AN_MASK

#define DP83848_BMCR_RESTART_AN_MASK   (0x200U)

◆ DP83848_BMCR_RESTART_AN_SET

#define DP83848_BMCR_RESTART_AN_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK)

◆ DP83848_BMCR_RESTART_AN_SHIFT

#define DP83848_BMCR_RESTART_AN_SHIFT   (9U)

◆ DP83848_BMCR_SPEED0_GET

#define DP83848_BMCR_SPEED0_GET (   x)    (((uint16_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT)

◆ DP83848_BMCR_SPEED0_MASK

#define DP83848_BMCR_SPEED0_MASK   (0x2000U)

◆ DP83848_BMCR_SPEED0_SET

#define DP83848_BMCR_SPEED0_SET (   x)    (((uint16_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK)

◆ DP83848_BMCR_SPEED0_SHIFT

#define DP83848_BMCR_SPEED0_SHIFT   (13U)

◆ DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET

#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT)

◆ DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK

#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK   (0x4000U)

◆ DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT

#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT   (14U)

◆ DP83848_BMSR_100BASE_TX_HALF_GET

#define DP83848_BMSR_100BASE_TX_HALF_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_HALF_MASK) >> DP83848_BMSR_100BASE_TX_HALF_SHIFT)

◆ DP83848_BMSR_100BASE_TX_HALF_MASK

#define DP83848_BMSR_100BASE_TX_HALF_MASK   (0x2000U)

◆ DP83848_BMSR_100BASE_TX_HALF_SHIFT

#define DP83848_BMSR_100BASE_TX_HALF_SHIFT   (13U)

◆ DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET

#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT)

◆ DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK

#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK   (0x1000U)

◆ DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT

#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT   (12U)

◆ DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET

#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT)

◆ DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK

#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK   (0x800U)

◆ DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT

#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT   (11U)

◆ DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET

#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT)

◆ DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK

#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK   (0x8U)

◆ DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT

#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT   (3U)

◆ DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET

#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT)

◆ DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK

#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK   (0x20U)

◆ DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT

#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT   (5U)

◆ DP83848_BMSR_EXTENDED_CAPABILITY_GET

#define DP83848_BMSR_EXTENDED_CAPABILITY_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT)

◆ DP83848_BMSR_EXTENDED_CAPABILITY_MASK

#define DP83848_BMSR_EXTENDED_CAPABILITY_MASK   (0x1U)

◆ DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT

#define DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT   (0U)

◆ DP83848_BMSR_JABBER_DETECT_GET

#define DP83848_BMSR_JABBER_DETECT_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_JABBER_DETECT_MASK) >> DP83848_BMSR_JABBER_DETECT_SHIFT)

◆ DP83848_BMSR_JABBER_DETECT_MASK

#define DP83848_BMSR_JABBER_DETECT_MASK   (0x2U)

◆ DP83848_BMSR_JABBER_DETECT_SHIFT

#define DP83848_BMSR_JABBER_DETECT_SHIFT   (1U)

◆ DP83848_BMSR_LINK_STATUS_GET

#define DP83848_BMSR_LINK_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_LINK_STATUS_MASK) >> DP83848_BMSR_LINK_STATUS_SHIFT)

◆ DP83848_BMSR_LINK_STATUS_MASK

#define DP83848_BMSR_LINK_STATUS_MASK   (0x4U)

◆ DP83848_BMSR_LINK_STATUS_SHIFT

#define DP83848_BMSR_LINK_STATUS_SHIFT   (2U)

◆ DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET

#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT)

◆ DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK

#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK   (0x40U)

◆ DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT

#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT   (6U)

◆ DP83848_BMSR_REMOTE_FAULT_GET

#define DP83848_BMSR_REMOTE_FAULT_GET (   x)    (((uint16_t)(x) & DP83848_BMSR_REMOTE_FAULT_MASK) >> DP83848_BMSR_REMOTE_FAULT_SHIFT)

◆ DP83848_BMSR_REMOTE_FAULT_MASK

#define DP83848_BMSR_REMOTE_FAULT_MASK   (0x10U)

◆ DP83848_BMSR_REMOTE_FAULT_SHIFT

#define DP83848_BMSR_REMOTE_FAULT_SHIFT   (4U)

◆ DP83848_CDCTRL1_10MEG_PATT_GAP_GET

#define DP83848_CDCTRL1_10MEG_PATT_GAP_GET (   x)    (((uint16_t)(x) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) >> DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT)

◆ DP83848_CDCTRL1_10MEG_PATT_GAP_MASK

#define DP83848_CDCTRL1_10MEG_PATT_GAP_MASK   (0x4U)

◆ DP83848_CDCTRL1_10MEG_PATT_GAP_SET

#define DP83848_CDCTRL1_10MEG_PATT_GAP_SET (   x)    (((uint16_t)(x) << DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK)

◆ DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT

#define DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT   (2U)

◆ DP83848_CDCTRL1_BIST_CONT_MODE_GET

#define DP83848_CDCTRL1_BIST_CONT_MODE_GET (   x)    (((uint16_t)(x) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) >> DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT)

◆ DP83848_CDCTRL1_BIST_CONT_MODE_MASK

#define DP83848_CDCTRL1_BIST_CONT_MODE_MASK   (0x20U)

◆ DP83848_CDCTRL1_BIST_CONT_MODE_SET

#define DP83848_CDCTRL1_BIST_CONT_MODE_SET (   x)    (((uint16_t)(x) << DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK)

◆ DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT

#define DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT   (5U)

◆ DP83848_CDCTRL1_BIST_ERROR_COUNT_GET

#define DP83848_CDCTRL1_BIST_ERROR_COUNT_GET (   x)    (((uint16_t)(x) & DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK) >> DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT)

◆ DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK

#define DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK   (0xFF00U)

◆ DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT

#define DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT   (8U)

◆ DP83848_CDCTRL1_CDPATTEN_10_GET

#define DP83848_CDCTRL1_CDPATTEN_10_GET (   x)    (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTEN_10_MASK) >> DP83848_CDCTRL1_CDPATTEN_10_SHIFT)

◆ DP83848_CDCTRL1_CDPATTEN_10_MASK

#define DP83848_CDCTRL1_CDPATTEN_10_MASK   (0x10U)

◆ DP83848_CDCTRL1_CDPATTEN_10_SET

#define DP83848_CDCTRL1_CDPATTEN_10_SET (   x)    (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTEN_10_SHIFT) & DP83848_CDCTRL1_CDPATTEN_10_MASK)

◆ DP83848_CDCTRL1_CDPATTEN_10_SHIFT

#define DP83848_CDCTRL1_CDPATTEN_10_SHIFT   (4U)

◆ DP83848_CDCTRL1_CDPATTSEL_1_0_GET

#define DP83848_CDCTRL1_CDPATTSEL_1_0_GET (   x)    (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) >> DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT)

◆ DP83848_CDCTRL1_CDPATTSEL_1_0_MASK

#define DP83848_CDCTRL1_CDPATTSEL_1_0_MASK   (0x3U)

◆ DP83848_CDCTRL1_CDPATTSEL_1_0_SET

#define DP83848_CDCTRL1_CDPATTSEL_1_0_SET (   x)    (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK)

◆ DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT

#define DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT   (0U)

◆ DP83848_EDCR_ED_AUTO_DOWN_GET

#define DP83848_EDCR_ED_AUTO_DOWN_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_DOWN_MASK) >> DP83848_EDCR_ED_AUTO_DOWN_SHIFT)

◆ DP83848_EDCR_ED_AUTO_DOWN_MASK

#define DP83848_EDCR_ED_AUTO_DOWN_MASK   (0x2000U)

◆ DP83848_EDCR_ED_AUTO_DOWN_SET

#define DP83848_EDCR_ED_AUTO_DOWN_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_DOWN_SHIFT) & DP83848_EDCR_ED_AUTO_DOWN_MASK)

◆ DP83848_EDCR_ED_AUTO_DOWN_SHIFT

#define DP83848_EDCR_ED_AUTO_DOWN_SHIFT   (13U)

◆ DP83848_EDCR_ED_AUTO_UP_GET

#define DP83848_EDCR_ED_AUTO_UP_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_UP_MASK) >> DP83848_EDCR_ED_AUTO_UP_SHIFT)

◆ DP83848_EDCR_ED_AUTO_UP_MASK

#define DP83848_EDCR_ED_AUTO_UP_MASK   (0x4000U)

◆ DP83848_EDCR_ED_AUTO_UP_SET

#define DP83848_EDCR_ED_AUTO_UP_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_UP_SHIFT) & DP83848_EDCR_ED_AUTO_UP_MASK)

◆ DP83848_EDCR_ED_AUTO_UP_SHIFT

#define DP83848_EDCR_ED_AUTO_UP_SHIFT   (14U)

◆ DP83848_EDCR_ED_BURST_DIS_GET

#define DP83848_EDCR_ED_BURST_DIS_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_BURST_DIS_MASK) >> DP83848_EDCR_ED_BURST_DIS_SHIFT)

◆ DP83848_EDCR_ED_BURST_DIS_MASK

#define DP83848_EDCR_ED_BURST_DIS_MASK   (0x800U)

◆ DP83848_EDCR_ED_BURST_DIS_SET

#define DP83848_EDCR_ED_BURST_DIS_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_BURST_DIS_SHIFT) & DP83848_EDCR_ED_BURST_DIS_MASK)

◆ DP83848_EDCR_ED_BURST_DIS_SHIFT

#define DP83848_EDCR_ED_BURST_DIS_SHIFT   (11U)

◆ DP83848_EDCR_ED_DATA_COUNT_GET

#define DP83848_EDCR_ED_DATA_COUNT_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_DATA_COUNT_MASK) >> DP83848_EDCR_ED_DATA_COUNT_SHIFT)

◆ DP83848_EDCR_ED_DATA_COUNT_MASK

#define DP83848_EDCR_ED_DATA_COUNT_MASK   (0xFU)

◆ DP83848_EDCR_ED_DATA_COUNT_SET

#define DP83848_EDCR_ED_DATA_COUNT_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_DATA_COUNT_SHIFT) & DP83848_EDCR_ED_DATA_COUNT_MASK)

◆ DP83848_EDCR_ED_DATA_COUNT_SHIFT

#define DP83848_EDCR_ED_DATA_COUNT_SHIFT   (0U)

◆ DP83848_EDCR_ED_DATA_MET_GET

#define DP83848_EDCR_ED_DATA_MET_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_DATA_MET_MASK) >> DP83848_EDCR_ED_DATA_MET_SHIFT)

◆ DP83848_EDCR_ED_DATA_MET_MASK

#define DP83848_EDCR_ED_DATA_MET_MASK   (0x100U)

◆ DP83848_EDCR_ED_DATA_MET_SHIFT

#define DP83848_EDCR_ED_DATA_MET_SHIFT   (8U)

◆ DP83848_EDCR_ED_EN_GET

#define DP83848_EDCR_ED_EN_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_EN_MASK) >> DP83848_EDCR_ED_EN_SHIFT)

◆ DP83848_EDCR_ED_EN_MASK

#define DP83848_EDCR_ED_EN_MASK   (0x8000U)

◆ DP83848_EDCR_ED_EN_SET

#define DP83848_EDCR_ED_EN_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_EN_SHIFT) & DP83848_EDCR_ED_EN_MASK)

◆ DP83848_EDCR_ED_EN_SHIFT

#define DP83848_EDCR_ED_EN_SHIFT   (15U)

◆ DP83848_EDCR_ED_ERR_COUNT_GET

#define DP83848_EDCR_ED_ERR_COUNT_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_ERR_COUNT_MASK) >> DP83848_EDCR_ED_ERR_COUNT_SHIFT)

◆ DP83848_EDCR_ED_ERR_COUNT_MASK

#define DP83848_EDCR_ED_ERR_COUNT_MASK   (0xF0U)

◆ DP83848_EDCR_ED_ERR_COUNT_SET

#define DP83848_EDCR_ED_ERR_COUNT_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_ERR_COUNT_SHIFT) & DP83848_EDCR_ED_ERR_COUNT_MASK)

◆ DP83848_EDCR_ED_ERR_COUNT_SHIFT

#define DP83848_EDCR_ED_ERR_COUNT_SHIFT   (4U)

◆ DP83848_EDCR_ED_ERR_MET_GET

#define DP83848_EDCR_ED_ERR_MET_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_ERR_MET_MASK) >> DP83848_EDCR_ED_ERR_MET_SHIFT)

◆ DP83848_EDCR_ED_ERR_MET_MASK

#define DP83848_EDCR_ED_ERR_MET_MASK   (0x200U)

◆ DP83848_EDCR_ED_ERR_MET_SHIFT

#define DP83848_EDCR_ED_ERR_MET_SHIFT   (9U)

◆ DP83848_EDCR_ED_MAN_GET

#define DP83848_EDCR_ED_MAN_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_MAN_MASK) >> DP83848_EDCR_ED_MAN_SHIFT)

◆ DP83848_EDCR_ED_MAN_MASK

#define DP83848_EDCR_ED_MAN_MASK   (0x1000U)

◆ DP83848_EDCR_ED_MAN_SET

#define DP83848_EDCR_ED_MAN_SET (   x)    (((uint16_t)(x) << DP83848_EDCR_ED_MAN_SHIFT) & DP83848_EDCR_ED_MAN_MASK)

◆ DP83848_EDCR_ED_MAN_SHIFT

#define DP83848_EDCR_ED_MAN_SHIFT   (12U)

◆ DP83848_EDCR_ED_PWR_STATE_GET

#define DP83848_EDCR_ED_PWR_STATE_GET (   x)    (((uint16_t)(x) & DP83848_EDCR_ED_PWR_STATE_MASK) >> DP83848_EDCR_ED_PWR_STATE_SHIFT)

◆ DP83848_EDCR_ED_PWR_STATE_MASK

#define DP83848_EDCR_ED_PWR_STATE_MASK   (0x400U)

◆ DP83848_EDCR_ED_PWR_STATE_SHIFT

#define DP83848_EDCR_ED_PWR_STATE_SHIFT   (10U)

◆ DP83848_FCSCR_FCSCNT_7_0_GET

#define DP83848_FCSCR_FCSCNT_7_0_GET (   x)    (((uint16_t)(x) & DP83848_FCSCR_FCSCNT_7_0_MASK) >> DP83848_FCSCR_FCSCNT_7_0_SHIFT)

◆ DP83848_FCSCR_FCSCNT_7_0_MASK

#define DP83848_FCSCR_FCSCNT_7_0_MASK   (0xFFU)

◆ DP83848_FCSCR_FCSCNT_7_0_SHIFT

#define DP83848_FCSCR_FCSCNT_7_0_SHIFT   (0U)

◆ DP83848_LEDCR_DRV_LNKLED_GET

#define DP83848_LEDCR_DRV_LNKLED_GET (   x)    (((uint16_t)(x) & DP83848_LEDCR_DRV_LNKLED_MASK) >> DP83848_LEDCR_DRV_LNKLED_SHIFT)

◆ DP83848_LEDCR_DRV_LNKLED_MASK

#define DP83848_LEDCR_DRV_LNKLED_MASK   (0x10U)

◆ DP83848_LEDCR_DRV_LNKLED_SET

#define DP83848_LEDCR_DRV_LNKLED_SET (   x)    (((uint16_t)(x) << DP83848_LEDCR_DRV_LNKLED_SHIFT) & DP83848_LEDCR_DRV_LNKLED_MASK)

◆ DP83848_LEDCR_DRV_LNKLED_SHIFT

#define DP83848_LEDCR_DRV_LNKLED_SHIFT   (4U)

◆ DP83848_LEDCR_DRV_SPDLED_GET

#define DP83848_LEDCR_DRV_SPDLED_GET (   x)    (((uint16_t)(x) & DP83848_LEDCR_DRV_SPDLED_MASK) >> DP83848_LEDCR_DRV_SPDLED_SHIFT)

◆ DP83848_LEDCR_DRV_SPDLED_MASK

#define DP83848_LEDCR_DRV_SPDLED_MASK   (0x20U)

◆ DP83848_LEDCR_DRV_SPDLED_SET

#define DP83848_LEDCR_DRV_SPDLED_SET (   x)    (((uint16_t)(x) << DP83848_LEDCR_DRV_SPDLED_SHIFT) & DP83848_LEDCR_DRV_SPDLED_MASK)

◆ DP83848_LEDCR_DRV_SPDLED_SHIFT

#define DP83848_LEDCR_DRV_SPDLED_SHIFT   (5U)

◆ DP83848_LEDCR_LNKLED_GET

#define DP83848_LEDCR_LNKLED_GET (   x)    (((uint16_t)(x) & DP83848_LEDCR_LNKLED_MASK) >> DP83848_LEDCR_LNKLED_SHIFT)

◆ DP83848_LEDCR_LNKLED_MASK

#define DP83848_LEDCR_LNKLED_MASK   (0x2U)

◆ DP83848_LEDCR_LNKLED_SET

#define DP83848_LEDCR_LNKLED_SET (   x)    (((uint16_t)(x) << DP83848_LEDCR_LNKLED_SHIFT) & DP83848_LEDCR_LNKLED_MASK)

◆ DP83848_LEDCR_LNKLED_SHIFT

#define DP83848_LEDCR_LNKLED_SHIFT   (1U)

◆ DP83848_LEDCR_SPDLED_GET

#define DP83848_LEDCR_SPDLED_GET (   x)    (((uint16_t)(x) & DP83848_LEDCR_SPDLED_MASK) >> DP83848_LEDCR_SPDLED_SHIFT)

◆ DP83848_LEDCR_SPDLED_MASK

#define DP83848_LEDCR_SPDLED_MASK   (0x4U)

◆ DP83848_LEDCR_SPDLED_SET

#define DP83848_LEDCR_SPDLED_SET (   x)    (((uint16_t)(x) << DP83848_LEDCR_SPDLED_SHIFT) & DP83848_LEDCR_SPDLED_MASK)

◆ DP83848_LEDCR_SPDLED_SHIFT

#define DP83848_LEDCR_SPDLED_SHIFT   (2U)

◆ DP83848_PCSR_DESC_TIME_GET

#define DP83848_PCSR_DESC_TIME_GET (   x)    (((uint16_t)(x) & DP83848_PCSR_DESC_TIME_MASK) >> DP83848_PCSR_DESC_TIME_SHIFT)

◆ DP83848_PCSR_DESC_TIME_MASK

#define DP83848_PCSR_DESC_TIME_MASK   (0x80U)

◆ DP83848_PCSR_DESC_TIME_SET

#define DP83848_PCSR_DESC_TIME_SET (   x)    (((uint16_t)(x) << DP83848_PCSR_DESC_TIME_SHIFT) & DP83848_PCSR_DESC_TIME_MASK)

◆ DP83848_PCSR_DESC_TIME_SHIFT

#define DP83848_PCSR_DESC_TIME_SHIFT   (7U)

◆ DP83848_PCSR_FORCE_100_OK_GET

#define DP83848_PCSR_FORCE_100_OK_GET (   x)    (((uint16_t)(x) & DP83848_PCSR_FORCE_100_OK_MASK) >> DP83848_PCSR_FORCE_100_OK_SHIFT)

◆ DP83848_PCSR_FORCE_100_OK_MASK

#define DP83848_PCSR_FORCE_100_OK_MASK   (0x20U)

◆ DP83848_PCSR_FORCE_100_OK_SET

#define DP83848_PCSR_FORCE_100_OK_SET (   x)    (((uint16_t)(x) << DP83848_PCSR_FORCE_100_OK_SHIFT) & DP83848_PCSR_FORCE_100_OK_MASK)

◆ DP83848_PCSR_FORCE_100_OK_SHIFT

#define DP83848_PCSR_FORCE_100_OK_SHIFT   (5U)

◆ DP83848_PCSR_NRZI_BYPASS_GET

#define DP83848_PCSR_NRZI_BYPASS_GET (   x)    (((uint16_t)(x) & DP83848_PCSR_NRZI_BYPASS_MASK) >> DP83848_PCSR_NRZI_BYPASS_SHIFT)

◆ DP83848_PCSR_NRZI_BYPASS_MASK

#define DP83848_PCSR_NRZI_BYPASS_MASK   (0x4U)

◆ DP83848_PCSR_NRZI_BYPASS_SET

#define DP83848_PCSR_NRZI_BYPASS_SET (   x)    (((uint16_t)(x) << DP83848_PCSR_NRZI_BYPASS_SHIFT) & DP83848_PCSR_NRZI_BYPASS_MASK)

◆ DP83848_PCSR_NRZI_BYPASS_SHIFT

#define DP83848_PCSR_NRZI_BYPASS_SHIFT   (2U)

◆ DP83848_PCSR_SD_FORCE_PMA_GET

#define DP83848_PCSR_SD_FORCE_PMA_GET (   x)    (((uint16_t)(x) & DP83848_PCSR_SD_FORCE_PMA_MASK) >> DP83848_PCSR_SD_FORCE_PMA_SHIFT)

◆ DP83848_PCSR_SD_FORCE_PMA_MASK

#define DP83848_PCSR_SD_FORCE_PMA_MASK   (0x200U)

◆ DP83848_PCSR_SD_FORCE_PMA_SET

#define DP83848_PCSR_SD_FORCE_PMA_SET (   x)    (((uint16_t)(x) << DP83848_PCSR_SD_FORCE_PMA_SHIFT) & DP83848_PCSR_SD_FORCE_PMA_MASK)

◆ DP83848_PCSR_SD_FORCE_PMA_SHIFT

#define DP83848_PCSR_SD_FORCE_PMA_SHIFT   (9U)

◆ DP83848_PCSR_SD_OPTION_GET

#define DP83848_PCSR_SD_OPTION_GET (   x)    (((uint16_t)(x) & DP83848_PCSR_SD_OPTION_MASK) >> DP83848_PCSR_SD_OPTION_SHIFT)

◆ DP83848_PCSR_SD_OPTION_MASK

#define DP83848_PCSR_SD_OPTION_MASK   (0x100U)

◆ DP83848_PCSR_SD_OPTION_SET

#define DP83848_PCSR_SD_OPTION_SET (   x)    (((uint16_t)(x) << DP83848_PCSR_SD_OPTION_SHIFT) & DP83848_PCSR_SD_OPTION_MASK)

◆ DP83848_PCSR_SD_OPTION_SHIFT

#define DP83848_PCSR_SD_OPTION_SHIFT   (8U)

◆ DP83848_PCSR_TQ_EN_GET

#define DP83848_PCSR_TQ_EN_GET (   x)    (((uint16_t)(x) & DP83848_PCSR_TQ_EN_MASK) >> DP83848_PCSR_TQ_EN_SHIFT)

◆ DP83848_PCSR_TQ_EN_MASK

#define DP83848_PCSR_TQ_EN_MASK   (0x400U)

◆ DP83848_PCSR_TQ_EN_SET

#define DP83848_PCSR_TQ_EN_SET (   x)    (((uint16_t)(x) << DP83848_PCSR_TQ_EN_SHIFT) & DP83848_PCSR_TQ_EN_MASK)

◆ DP83848_PCSR_TQ_EN_SHIFT

#define DP83848_PCSR_TQ_EN_SHIFT   (10U)

◆ DP83848_PHYCR_BIST_FE_GET

#define DP83848_PHYCR_BIST_FE_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_BIST_FE_MASK) >> DP83848_PHYCR_BIST_FE_SHIFT)

◆ DP83848_PHYCR_BIST_FE_MASK

#define DP83848_PHYCR_BIST_FE_MASK   (0x800U)

◆ DP83848_PHYCR_BIST_FE_SET

#define DP83848_PHYCR_BIST_FE_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_BIST_FE_SHIFT) & DP83848_PHYCR_BIST_FE_MASK)

◆ DP83848_PHYCR_BIST_FE_SHIFT

#define DP83848_PHYCR_BIST_FE_SHIFT   (11U)

◆ DP83848_PHYCR_BIST_START_GET

#define DP83848_PHYCR_BIST_START_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_BIST_START_MASK) >> DP83848_PHYCR_BIST_START_SHIFT)

◆ DP83848_PHYCR_BIST_START_MASK

#define DP83848_PHYCR_BIST_START_MASK   (0x100U)

◆ DP83848_PHYCR_BIST_START_SET

#define DP83848_PHYCR_BIST_START_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_BIST_START_SHIFT) & DP83848_PHYCR_BIST_START_MASK)

◆ DP83848_PHYCR_BIST_START_SHIFT

#define DP83848_PHYCR_BIST_START_SHIFT   (8U)

◆ DP83848_PHYCR_BIST_STATUS_GET

#define DP83848_PHYCR_BIST_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_BIST_STATUS_MASK) >> DP83848_PHYCR_BIST_STATUS_SHIFT)

◆ DP83848_PHYCR_BIST_STATUS_MASK

#define DP83848_PHYCR_BIST_STATUS_MASK   (0x200U)

◆ DP83848_PHYCR_BIST_STATUS_SHIFT

#define DP83848_PHYCR_BIST_STATUS_SHIFT   (9U)

◆ DP83848_PHYCR_BP_STRETCH_GET

#define DP83848_PHYCR_BP_STRETCH_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_BP_STRETCH_MASK) >> DP83848_PHYCR_BP_STRETCH_SHIFT)

◆ DP83848_PHYCR_BP_STRETCH_MASK

#define DP83848_PHYCR_BP_STRETCH_MASK   (0x80U)

◆ DP83848_PHYCR_BP_STRETCH_SET

#define DP83848_PHYCR_BP_STRETCH_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_BP_STRETCH_SHIFT) & DP83848_PHYCR_BP_STRETCH_MASK)

◆ DP83848_PHYCR_BP_STRETCH_SHIFT

#define DP83848_PHYCR_BP_STRETCH_SHIFT   (7U)

◆ DP83848_PHYCR_FORCE_MDIX_GET

#define DP83848_PHYCR_FORCE_MDIX_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_FORCE_MDIX_MASK) >> DP83848_PHYCR_FORCE_MDIX_SHIFT)

◆ DP83848_PHYCR_FORCE_MDIX_MASK

#define DP83848_PHYCR_FORCE_MDIX_MASK   (0x4000U)

◆ DP83848_PHYCR_FORCE_MDIX_SET

#define DP83848_PHYCR_FORCE_MDIX_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_FORCE_MDIX_SHIFT) & DP83848_PHYCR_FORCE_MDIX_MASK)

◆ DP83848_PHYCR_FORCE_MDIX_SHIFT

#define DP83848_PHYCR_FORCE_MDIX_SHIFT   (14U)

◆ DP83848_PHYCR_LED_CNFG_0_GET

#define DP83848_PHYCR_LED_CNFG_0_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_LED_CNFG_0_MASK) >> DP83848_PHYCR_LED_CNFG_0_SHIFT)

◆ DP83848_PHYCR_LED_CNFG_0_MASK

#define DP83848_PHYCR_LED_CNFG_0_MASK   (0x20U)

◆ DP83848_PHYCR_LED_CNFG_0_SET

#define DP83848_PHYCR_LED_CNFG_0_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_LED_CNFG_0_SHIFT) & DP83848_PHYCR_LED_CNFG_0_MASK)

◆ DP83848_PHYCR_LED_CNFG_0_SHIFT

#define DP83848_PHYCR_LED_CNFG_0_SHIFT   (5U)

◆ DP83848_PHYCR_MDIX_EN_GET

#define DP83848_PHYCR_MDIX_EN_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_MDIX_EN_MASK) >> DP83848_PHYCR_MDIX_EN_SHIFT)

◆ DP83848_PHYCR_MDIX_EN_MASK

#define DP83848_PHYCR_MDIX_EN_MASK   (0x8000U)

◆ DP83848_PHYCR_MDIX_EN_SET

#define DP83848_PHYCR_MDIX_EN_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_MDIX_EN_SHIFT) & DP83848_PHYCR_MDIX_EN_MASK)

◆ DP83848_PHYCR_MDIX_EN_SHIFT

#define DP83848_PHYCR_MDIX_EN_SHIFT   (15U)

◆ DP83848_PHYCR_PAUSE_RX_GET

#define DP83848_PHYCR_PAUSE_RX_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_PAUSE_RX_MASK) >> DP83848_PHYCR_PAUSE_RX_SHIFT)

◆ DP83848_PHYCR_PAUSE_RX_MASK

#define DP83848_PHYCR_PAUSE_RX_MASK   (0x2000U)

◆ DP83848_PHYCR_PAUSE_RX_SHIFT

#define DP83848_PHYCR_PAUSE_RX_SHIFT   (13U)

◆ DP83848_PHYCR_PAUSE_TX_GET

#define DP83848_PHYCR_PAUSE_TX_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_PAUSE_TX_MASK) >> DP83848_PHYCR_PAUSE_TX_SHIFT)

◆ DP83848_PHYCR_PAUSE_TX_MASK

#define DP83848_PHYCR_PAUSE_TX_MASK   (0x1000U)

◆ DP83848_PHYCR_PAUSE_TX_SHIFT

#define DP83848_PHYCR_PAUSE_TX_SHIFT   (12U)

◆ DP83848_PHYCR_PHYADDR_4_0_GET

#define DP83848_PHYCR_PHYADDR_4_0_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_PHYADDR_4_0_MASK) >> DP83848_PHYCR_PHYADDR_4_0_SHIFT)

◆ DP83848_PHYCR_PHYADDR_4_0_MASK

#define DP83848_PHYCR_PHYADDR_4_0_MASK   (0x1FU)

◆ DP83848_PHYCR_PHYADDR_4_0_SET

#define DP83848_PHYCR_PHYADDR_4_0_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_PHYADDR_4_0_SHIFT) & DP83848_PHYCR_PHYADDR_4_0_MASK)

◆ DP83848_PHYCR_PHYADDR_4_0_SHIFT

#define DP83848_PHYCR_PHYADDR_4_0_SHIFT   (0U)

◆ DP83848_PHYCR_PSR_15_GET

#define DP83848_PHYCR_PSR_15_GET (   x)    (((uint16_t)(x) & DP83848_PHYCR_PSR_15_MASK) >> DP83848_PHYCR_PSR_15_SHIFT)

◆ DP83848_PHYCR_PSR_15_MASK

#define DP83848_PHYCR_PSR_15_MASK   (0x400U)

◆ DP83848_PHYCR_PSR_15_SET

#define DP83848_PHYCR_PSR_15_SET (   x)    (((uint16_t)(x) << DP83848_PHYCR_PSR_15_SHIFT) & DP83848_PHYCR_PSR_15_MASK)

◆ DP83848_PHYCR_PSR_15_SHIFT

#define DP83848_PHYCR_PSR_15_SHIFT   (10U)

◆ DP83848_PHYIDR1_OUI_MSB_GET

#define DP83848_PHYIDR1_OUI_MSB_GET (   x)    (((uint16_t)(x) & DP83848_PHYIDR1_OUI_MSB_MASK) >> DP83848_PHYIDR1_OUI_MSB_SHIFT)

◆ DP83848_PHYIDR1_OUI_MSB_MASK

#define DP83848_PHYIDR1_OUI_MSB_MASK   (0xFFFFU)

◆ DP83848_PHYIDR1_OUI_MSB_SHIFT

#define DP83848_PHYIDR1_OUI_MSB_SHIFT   (0U)

◆ DP83848_PHYIDR2_MDL_REV_GET

#define DP83848_PHYIDR2_MDL_REV_GET (   x)    (((uint16_t)(x) & DP83848_PHYIDR2_MDL_REV_MASK) >> DP83848_PHYIDR2_MDL_REV_SHIFT)

◆ DP83848_PHYIDR2_MDL_REV_MASK

#define DP83848_PHYIDR2_MDL_REV_MASK   (0xFU)

◆ DP83848_PHYIDR2_MDL_REV_SHIFT

#define DP83848_PHYIDR2_MDL_REV_SHIFT   (0U)

◆ DP83848_PHYIDR2_OUI_LSB_GET

#define DP83848_PHYIDR2_OUI_LSB_GET (   x)    (((uint16_t)(x) & DP83848_PHYIDR2_OUI_LSB_MASK) >> DP83848_PHYIDR2_OUI_LSB_SHIFT)

◆ DP83848_PHYIDR2_OUI_LSB_MASK

#define DP83848_PHYIDR2_OUI_LSB_MASK   (0xFC00U)

◆ DP83848_PHYIDR2_OUI_LSB_SHIFT

#define DP83848_PHYIDR2_OUI_LSB_SHIFT   (10U)

◆ DP83848_PHYIDR2_VNDR_MDL_GET

#define DP83848_PHYIDR2_VNDR_MDL_GET (   x)    (((uint16_t)(x) & DP83848_PHYIDR2_VNDR_MDL_MASK) >> DP83848_PHYIDR2_VNDR_MDL_SHIFT)

◆ DP83848_PHYIDR2_VNDR_MDL_MASK

#define DP83848_PHYIDR2_VNDR_MDL_MASK   (0x3F0U)

◆ DP83848_PHYIDR2_VNDR_MDL_SHIFT

#define DP83848_PHYIDR2_VNDR_MDL_SHIFT   (4U)

◆ DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET

#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK) >> DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT)

◆ DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK

#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK   (0x10U)

◆ DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT

#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT   (4U)

◆ DP83848_PHYSTS_DESCRAMBLER_LOCK_GET

#define DP83848_PHYSTS_DESCRAMBLER_LOCK_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK) >> DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT)

◆ DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK

#define DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK   (0x200U)

◆ DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT

#define DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT   (9U)

◆ DP83848_PHYSTS_DUPLEX_STATUS_GET

#define DP83848_PHYSTS_DUPLEX_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_DUPLEX_STATUS_MASK) >> DP83848_PHYSTS_DUPLEX_STATUS_SHIFT)

◆ DP83848_PHYSTS_DUPLEX_STATUS_MASK

#define DP83848_PHYSTS_DUPLEX_STATUS_MASK   (0x4U)

◆ DP83848_PHYSTS_DUPLEX_STATUS_SHIFT

#define DP83848_PHYSTS_DUPLEX_STATUS_SHIFT   (2U)

◆ DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET

#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK) >> DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT)

◆ DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK

#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK   (0x800U)

◆ DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT

#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT   (11U)

◆ DP83848_PHYSTS_JABBER_DETECT_GET

#define DP83848_PHYSTS_JABBER_DETECT_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_JABBER_DETECT_MASK) >> DP83848_PHYSTS_JABBER_DETECT_SHIFT)

◆ DP83848_PHYSTS_JABBER_DETECT_MASK

#define DP83848_PHYSTS_JABBER_DETECT_MASK   (0x20U)

◆ DP83848_PHYSTS_JABBER_DETECT_SHIFT

#define DP83848_PHYSTS_JABBER_DETECT_SHIFT   (5U)

◆ DP83848_PHYSTS_LINK_STATUS_GET

#define DP83848_PHYSTS_LINK_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_LINK_STATUS_MASK) >> DP83848_PHYSTS_LINK_STATUS_SHIFT)

◆ DP83848_PHYSTS_LINK_STATUS_MASK

#define DP83848_PHYSTS_LINK_STATUS_MASK   (0x1U)

◆ DP83848_PHYSTS_LINK_STATUS_SHIFT

#define DP83848_PHYSTS_LINK_STATUS_SHIFT   (0U)

◆ DP83848_PHYSTS_LOOPBACK_STATUS_GET

#define DP83848_PHYSTS_LOOPBACK_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_LOOPBACK_STATUS_MASK) >> DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT)

◆ DP83848_PHYSTS_LOOPBACK_STATUS_MASK

#define DP83848_PHYSTS_LOOPBACK_STATUS_MASK   (0x8U)

◆ DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT

#define DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT   (3U)

◆ DP83848_PHYSTS_MDI_X_MODE_GET

#define DP83848_PHYSTS_MDI_X_MODE_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_MDI_X_MODE_MASK) >> DP83848_PHYSTS_MDI_X_MODE_SHIFT)

◆ DP83848_PHYSTS_MDI_X_MODE_MASK

#define DP83848_PHYSTS_MDI_X_MODE_MASK   (0x4000U)

◆ DP83848_PHYSTS_MDI_X_MODE_SHIFT

#define DP83848_PHYSTS_MDI_X_MODE_SHIFT   (14U)

◆ DP83848_PHYSTS_PAGE_RECEIVED_GET

#define DP83848_PHYSTS_PAGE_RECEIVED_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_PAGE_RECEIVED_MASK) >> DP83848_PHYSTS_PAGE_RECEIVED_SHIFT)

◆ DP83848_PHYSTS_PAGE_RECEIVED_MASK

#define DP83848_PHYSTS_PAGE_RECEIVED_MASK   (0x100U)

◆ DP83848_PHYSTS_PAGE_RECEIVED_SHIFT

#define DP83848_PHYSTS_PAGE_RECEIVED_SHIFT   (8U)

◆ DP83848_PHYSTS_POLARITY_STATUS_GET

#define DP83848_PHYSTS_POLARITY_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_POLARITY_STATUS_MASK) >> DP83848_PHYSTS_POLARITY_STATUS_SHIFT)

◆ DP83848_PHYSTS_POLARITY_STATUS_MASK

#define DP83848_PHYSTS_POLARITY_STATUS_MASK   (0x1000U)

◆ DP83848_PHYSTS_POLARITY_STATUS_SHIFT

#define DP83848_PHYSTS_POLARITY_STATUS_SHIFT   (12U)

◆ DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET

#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK) >> DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT)

◆ DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK

#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK   (0x2000U)

◆ DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT

#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT   (13U)

◆ DP83848_PHYSTS_REMOTE_FAULT_GET

#define DP83848_PHYSTS_REMOTE_FAULT_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_REMOTE_FAULT_MASK) >> DP83848_PHYSTS_REMOTE_FAULT_SHIFT)

◆ DP83848_PHYSTS_REMOTE_FAULT_MASK

#define DP83848_PHYSTS_REMOTE_FAULT_MASK   (0x40U)

◆ DP83848_PHYSTS_REMOTE_FAULT_SHIFT

#define DP83848_PHYSTS_REMOTE_FAULT_SHIFT   (6U)

◆ DP83848_PHYSTS_SIGNAL_DETECT_GET

#define DP83848_PHYSTS_SIGNAL_DETECT_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_SIGNAL_DETECT_MASK) >> DP83848_PHYSTS_SIGNAL_DETECT_SHIFT)

◆ DP83848_PHYSTS_SIGNAL_DETECT_MASK

#define DP83848_PHYSTS_SIGNAL_DETECT_MASK   (0x400U)

◆ DP83848_PHYSTS_SIGNAL_DETECT_SHIFT

#define DP83848_PHYSTS_SIGNAL_DETECT_SHIFT   (10U)

◆ DP83848_PHYSTS_SPEED_STATUS_GET

#define DP83848_PHYSTS_SPEED_STATUS_GET (   x)    (((uint16_t)(x) & DP83848_PHYSTS_SPEED_STATUS_MASK) >> DP83848_PHYSTS_SPEED_STATUS_SHIFT)

◆ DP83848_PHYSTS_SPEED_STATUS_MASK

#define DP83848_PHYSTS_SPEED_STATUS_MASK   (0x2U)

◆ DP83848_PHYSTS_SPEED_STATUS_SHIFT

#define DP83848_PHYSTS_SPEED_STATUS_SHIFT   (1U)

◆ DP83848_RBR_ELAST_BUF_1_0_GET

#define DP83848_RBR_ELAST_BUF_1_0_GET (   x)    (((uint16_t)(x) & DP83848_RBR_ELAST_BUF_1_0_MASK) >> DP83848_RBR_ELAST_BUF_1_0_SHIFT)

◆ DP83848_RBR_ELAST_BUF_1_0_MASK

#define DP83848_RBR_ELAST_BUF_1_0_MASK   (0x3U)

◆ DP83848_RBR_ELAST_BUF_1_0_SET

#define DP83848_RBR_ELAST_BUF_1_0_SET (   x)    (((uint16_t)(x) << DP83848_RBR_ELAST_BUF_1_0_SHIFT) & DP83848_RBR_ELAST_BUF_1_0_MASK)

◆ DP83848_RBR_ELAST_BUF_1_0_SHIFT

#define DP83848_RBR_ELAST_BUF_1_0_SHIFT   (0U)

◆ DP83848_RBR_RMII_MODE_GET

#define DP83848_RBR_RMII_MODE_GET (   x)    (((uint16_t)(x) & DP83848_RBR_RMII_MODE_MASK) >> DP83848_RBR_RMII_MODE_SHIFT)

◆ DP83848_RBR_RMII_MODE_MASK

#define DP83848_RBR_RMII_MODE_MASK   (0x20U)

◆ DP83848_RBR_RMII_MODE_SET

#define DP83848_RBR_RMII_MODE_SET (   x)    (((uint16_t)(x) << DP83848_RBR_RMII_MODE_SHIFT) & DP83848_RBR_RMII_MODE_MASK)

◆ DP83848_RBR_RMII_MODE_SHIFT

#define DP83848_RBR_RMII_MODE_SHIFT   (5U)

◆ DP83848_RBR_RMII_REV1_0_GET

#define DP83848_RBR_RMII_REV1_0_GET (   x)    (((uint16_t)(x) & DP83848_RBR_RMII_REV1_0_MASK) >> DP83848_RBR_RMII_REV1_0_SHIFT)

◆ DP83848_RBR_RMII_REV1_0_MASK

#define DP83848_RBR_RMII_REV1_0_MASK   (0x10U)

◆ DP83848_RBR_RMII_REV1_0_SET

#define DP83848_RBR_RMII_REV1_0_SET (   x)    (((uint16_t)(x) << DP83848_RBR_RMII_REV1_0_SHIFT) & DP83848_RBR_RMII_REV1_0_MASK)

◆ DP83848_RBR_RMII_REV1_0_SHIFT

#define DP83848_RBR_RMII_REV1_0_SHIFT   (4U)

◆ DP83848_RBR_RX_OVF_STS_GET

#define DP83848_RBR_RX_OVF_STS_GET (   x)    (((uint16_t)(x) & DP83848_RBR_RX_OVF_STS_MASK) >> DP83848_RBR_RX_OVF_STS_SHIFT)

◆ DP83848_RBR_RX_OVF_STS_MASK

#define DP83848_RBR_RX_OVF_STS_MASK   (0x8U)

◆ DP83848_RBR_RX_OVF_STS_SHIFT

#define DP83848_RBR_RX_OVF_STS_SHIFT   (3U)

◆ DP83848_RBR_RX_UNF_STS_GET

#define DP83848_RBR_RX_UNF_STS_GET (   x)    (((uint16_t)(x) & DP83848_RBR_RX_UNF_STS_MASK) >> DP83848_RBR_RX_UNF_STS_SHIFT)

◆ DP83848_RBR_RX_UNF_STS_MASK

#define DP83848_RBR_RX_UNF_STS_MASK   (0x4U)

◆ DP83848_RBR_RX_UNF_STS_SHIFT

#define DP83848_RBR_RX_UNF_STS_SHIFT   (2U)

◆ DP83848_RECR_RXERCNT_7_0_GET

#define DP83848_RECR_RXERCNT_7_0_GET (   x)    (((uint16_t)(x) & DP83848_RECR_RXERCNT_7_0_MASK) >> DP83848_RECR_RXERCNT_7_0_SHIFT)

◆ DP83848_RECR_RXERCNT_7_0_MASK

#define DP83848_RECR_RXERCNT_7_0_MASK   (0xFFU)

◆ DP83848_RECR_RXERCNT_7_0_SHIFT

#define DP83848_RECR_RXERCNT_7_0_SHIFT   (0U)

Enumeration Type Documentation

◆ DP83848_REG_Type

enum DP83848_REG_Type
Enumerator
DP83848_BMCR 
DP83848_BMSR 
DP83848_PHYIDR1 
DP83848_PHYIDR2 
DP83848_ANAR 
DP83848_ANLPAR_BP 
DP83848_ANER 
DP83848_ANNPTR 
DP83848_PHYSTS 
DP83848_FCSCR 
DP83848_RECR 
DP83848_PCSR 
DP83848_RBR 
DP83848_LEDCR 
DP83848_PHYCR 
DP83848_10BTSCR 
DP83848_CDCTRL1 
DP83848_EDCR