HPM SDK
HPMicro Software Development Kit
hpm_gwc_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_GWC_H
10 #define HPM_GWC_H
11 
12 typedef struct {
13  __RW uint32_t GLB_CTRL; /* 0x0: control reg */
14  __RW uint32_t IRQ_MASK; /* 0x4: interrupt enable */
15  __RW uint32_t IRQ_STS; /* 0x8: interrupt status */
16  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
17  struct {
18  __RW uint32_t CFG0; /* 0x10: config reg 0 */
19  __RW uint32_t CFG1; /* 0x14: config reg 1 */
20  __RW uint32_t REFCRC; /* 0x18: reference CRC */
21  __RW uint32_t CALCRC; /* 0x1C: calculated CRC */
22  } CHANNEL[16];
23 } GWC_Type;
24 
25 
26 /* Bitfield definition for register: GLB_CTRL */
27 /*
28  * CLK_POL (RW)
29  *
30  * graphic clock polarity.
31  * set to invert input graphic clock
32  */
33 #define GWC_GLB_CTRL_CLK_POL_MASK (0x80U)
34 #define GWC_GLB_CTRL_CLK_POL_SHIFT (7U)
35 #define GWC_GLB_CTRL_CLK_POL_SET(x) (((uint32_t)(x) << GWC_GLB_CTRL_CLK_POL_SHIFT) & GWC_GLB_CTRL_CLK_POL_MASK)
36 #define GWC_GLB_CTRL_CLK_POL_GET(x) (((uint32_t)(x) & GWC_GLB_CTRL_CLK_POL_MASK) >> GWC_GLB_CTRL_CLK_POL_SHIFT)
37 
38 /*
39  * GWC_EN (RW)
40  *
41  * graphic window check enable.
42  * set to enable the whole block
43  */
44 #define GWC_GLB_CTRL_GWC_EN_MASK (0x1U)
45 #define GWC_GLB_CTRL_GWC_EN_SHIFT (0U)
46 #define GWC_GLB_CTRL_GWC_EN_SET(x) (((uint32_t)(x) << GWC_GLB_CTRL_GWC_EN_SHIFT) & GWC_GLB_CTRL_GWC_EN_MASK)
47 #define GWC_GLB_CTRL_GWC_EN_GET(x) (((uint32_t)(x) & GWC_GLB_CTRL_GWC_EN_MASK) >> GWC_GLB_CTRL_GWC_EN_SHIFT)
48 
49 /* Bitfield definition for register: IRQ_MASK */
50 /*
51  * MASK_RREEZ (RW)
52  *
53  * freeze mask, set to disable changing ERR_MASK and FUNC_MASK.
54  * can only be cleared by system reset
55  */
56 #define GWC_IRQ_MASK_MASK_RREEZ_MASK (0x8U)
57 #define GWC_IRQ_MASK_MASK_RREEZ_SHIFT (3U)
58 #define GWC_IRQ_MASK_MASK_RREEZ_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_MASK_RREEZ_SHIFT) & GWC_IRQ_MASK_MASK_RREEZ_MASK)
59 #define GWC_IRQ_MASK_MASK_RREEZ_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_MASK_RREEZ_MASK) >> GWC_IRQ_MASK_MASK_RREEZ_SHIFT)
60 
61 /*
62  * FUNC_MASK (RW)
63  *
64  * function interrupt mask
65  */
66 #define GWC_IRQ_MASK_FUNC_MASK_MASK (0x2U)
67 #define GWC_IRQ_MASK_FUNC_MASK_SHIFT (1U)
68 #define GWC_IRQ_MASK_FUNC_MASK_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_FUNC_MASK_SHIFT) & GWC_IRQ_MASK_FUNC_MASK_MASK)
69 #define GWC_IRQ_MASK_FUNC_MASK_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_FUNC_MASK_MASK) >> GWC_IRQ_MASK_FUNC_MASK_SHIFT)
70 
71 /*
72  * ERR_MASK (RW)
73  *
74  * error interrupt mask
75  */
76 #define GWC_IRQ_MASK_ERR_MASK_MASK (0x1U)
77 #define GWC_IRQ_MASK_ERR_MASK_SHIFT (0U)
78 #define GWC_IRQ_MASK_ERR_MASK_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_ERR_MASK_SHIFT) & GWC_IRQ_MASK_ERR_MASK_MASK)
79 #define GWC_IRQ_MASK_ERR_MASK_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_ERR_MASK_MASK) >> GWC_IRQ_MASK_ERR_MASK_SHIFT)
80 
81 /* Bitfield definition for register: IRQ_STS */
82 /*
83  * FUNC_STS (W1C)
84  *
85  * function interrupt status.
86  * it's set when detect two VSYNC signals after the block is enabled(GWC_EN is set)
87  * software write 1 to clear.
88  */
89 #define GWC_IRQ_STS_FUNC_STS_MASK (0x20000UL)
90 #define GWC_IRQ_STS_FUNC_STS_SHIFT (17U)
91 #define GWC_IRQ_STS_FUNC_STS_SET(x) (((uint32_t)(x) << GWC_IRQ_STS_FUNC_STS_SHIFT) & GWC_IRQ_STS_FUNC_STS_MASK)
92 #define GWC_IRQ_STS_FUNC_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_FUNC_STS_MASK) >> GWC_IRQ_STS_FUNC_STS_SHIFT)
93 
94 /*
95  * ERR_STS (RO)
96  *
97  * error status, it's OR of GWC_FAIL_STS[15:0]
98  */
99 #define GWC_IRQ_STS_ERR_STS_MASK (0x10000UL)
100 #define GWC_IRQ_STS_ERR_STS_SHIFT (16U)
101 #define GWC_IRQ_STS_ERR_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_ERR_STS_MASK) >> GWC_IRQ_STS_ERR_STS_SHIFT)
102 
103 /*
104  * GWC_FAIL_STS (W1C)
105  *
106  * graphic window check fail interrupt status.
107  * will be set if the calculated CRC not equal reference CRC.
108  * one bit for each channel.
109  * software write 1 to clear.
110  */
111 #define GWC_IRQ_STS_GWC_FAIL_STS_MASK (0xFFFFU)
112 #define GWC_IRQ_STS_GWC_FAIL_STS_SHIFT (0U)
113 #define GWC_IRQ_STS_GWC_FAIL_STS_SET(x) (((uint32_t)(x) << GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) & GWC_IRQ_STS_GWC_FAIL_STS_MASK)
114 #define GWC_IRQ_STS_GWC_FAIL_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) >> GWC_IRQ_STS_GWC_FAIL_STS_SHIFT)
115 
116 /* Bitfield definition for register of struct array CHANNEL: CFG0 */
117 /*
118  * ENABLE (RW)
119  *
120  * channel enable
121  */
122 #define GWC_CHANNEL_CFG0_ENABLE_MASK (0x80000000UL)
123 #define GWC_CHANNEL_CFG0_ENABLE_SHIFT (31U)
124 #define GWC_CHANNEL_CFG0_ENABLE_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_ENABLE_SHIFT) & GWC_CHANNEL_CFG0_ENABLE_MASK)
125 #define GWC_CHANNEL_CFG0_ENABLE_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_ENABLE_MASK) >> GWC_CHANNEL_CFG0_ENABLE_SHIFT)
126 
127 /*
128  * FREEZE (RW)
129  *
130  * freeze config. set to freeze all other config registers for current channel.
131  * can only be cleared by system reset
132  */
133 #define GWC_CHANNEL_CFG0_FREEZE_MASK (0x40000000UL)
134 #define GWC_CHANNEL_CFG0_FREEZE_SHIFT (30U)
135 #define GWC_CHANNEL_CFG0_FREEZE_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_FREEZE_SHIFT) & GWC_CHANNEL_CFG0_FREEZE_MASK)
136 #define GWC_CHANNEL_CFG0_FREEZE_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_FREEZE_MASK) >> GWC_CHANNEL_CFG0_FREEZE_SHIFT)
137 
138 /*
139  * START_ROW (RW)
140  *
141  * define the window start row number
142  */
143 #define GWC_CHANNEL_CFG0_START_ROW_MASK (0xFFF0000UL)
144 #define GWC_CHANNEL_CFG0_START_ROW_SHIFT (16U)
145 #define GWC_CHANNEL_CFG0_START_ROW_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_ROW_SHIFT) & GWC_CHANNEL_CFG0_START_ROW_MASK)
146 #define GWC_CHANNEL_CFG0_START_ROW_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_ROW_MASK) >> GWC_CHANNEL_CFG0_START_ROW_SHIFT)
147 
148 /*
149  * START_COL (RW)
150  *
151  * define the window start column number
152  */
153 #define GWC_CHANNEL_CFG0_START_COL_MASK (0x1FFFU)
154 #define GWC_CHANNEL_CFG0_START_COL_SHIFT (0U)
155 #define GWC_CHANNEL_CFG0_START_COL_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_COL_SHIFT) & GWC_CHANNEL_CFG0_START_COL_MASK)
156 #define GWC_CHANNEL_CFG0_START_COL_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_COL_MASK) >> GWC_CHANNEL_CFG0_START_COL_SHIFT)
157 
158 /* Bitfield definition for register of struct array CHANNEL: CFG1 */
159 /*
160  * END_ROW (RW)
161  *
162  * define the window end row number
163  */
164 #define GWC_CHANNEL_CFG1_END_ROW_MASK (0xFFF0000UL)
165 #define GWC_CHANNEL_CFG1_END_ROW_SHIFT (16U)
166 #define GWC_CHANNEL_CFG1_END_ROW_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_ROW_SHIFT) & GWC_CHANNEL_CFG1_END_ROW_MASK)
167 #define GWC_CHANNEL_CFG1_END_ROW_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_ROW_MASK) >> GWC_CHANNEL_CFG1_END_ROW_SHIFT)
168 
169 /*
170  * END_COL (RW)
171  *
172  * define the window end column number
173  */
174 #define GWC_CHANNEL_CFG1_END_COL_MASK (0x1FFFU)
175 #define GWC_CHANNEL_CFG1_END_COL_SHIFT (0U)
176 #define GWC_CHANNEL_CFG1_END_COL_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_COL_SHIFT) & GWC_CHANNEL_CFG1_END_COL_MASK)
177 #define GWC_CHANNEL_CFG1_END_COL_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_COL_MASK) >> GWC_CHANNEL_CFG1_END_COL_SHIFT)
178 
179 /* Bitfield definition for register of struct array CHANNEL: REFCRC */
180 /*
181  * REF_CRC (RW)
182  *
183  * reference CRC
184  * polynomial function: 0x104C11DB7
185  */
186 #define GWC_CHANNEL_REFCRC_REF_CRC_MASK (0xFFFFFFFFUL)
187 #define GWC_CHANNEL_REFCRC_REF_CRC_SHIFT (0U)
188 #define GWC_CHANNEL_REFCRC_REF_CRC_SET(x) (((uint32_t)(x) << GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) & GWC_CHANNEL_REFCRC_REF_CRC_MASK)
189 #define GWC_CHANNEL_REFCRC_REF_CRC_GET(x) (((uint32_t)(x) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) >> GWC_CHANNEL_REFCRC_REF_CRC_SHIFT)
190 
191 /* Bitfield definition for register of struct array CHANNEL: CALCRC */
192 /*
193  * CAL_CRC (RW)
194  *
195  * calculated CRC for last frame
196  */
197 #define GWC_CHANNEL_CALCRC_CAL_CRC_MASK (0xFFFFFFFFUL)
198 #define GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT (0U)
199 #define GWC_CHANNEL_CALCRC_CAL_CRC_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK)
200 #define GWC_CHANNEL_CALCRC_CAL_CRC_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) >> GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT)
201 
202 
203 
204 /* CHANNEL register group index macro definition */
205 #define GWC_CHANNEL_CH0 (0UL)
206 #define GWC_CHANNEL_CH15 (15UL)
207 
208 
209 #endif /* HPM_GWC_H */
GWC_Type
Definition: hpm_gwc_regs.h:12