hpm_gwc_regs.h File Reference

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Data Structures
struct	GWC_Type

Macros
#define	GWC_GLB_CTRL_CLK_POL_MASK   (0x80U)
#define	GWC_GLB_CTRL_CLK_POL_SHIFT   (7U)
#define	GWC_GLB_CTRL_CLK_POL_SET(x)   (((uint32_t)(x) << GWC_GLB_CTRL_CLK_POL_SHIFT) & GWC_GLB_CTRL_CLK_POL_MASK)
#define	GWC_GLB_CTRL_CLK_POL_GET(x)   (((uint32_t)(x) & GWC_GLB_CTRL_CLK_POL_MASK) >> GWC_GLB_CTRL_CLK_POL_SHIFT)
#define	GWC_GLB_CTRL_GWC_EN_MASK   (0x1U)
#define	GWC_GLB_CTRL_GWC_EN_SHIFT   (0U)
#define	GWC_GLB_CTRL_GWC_EN_SET(x)   (((uint32_t)(x) << GWC_GLB_CTRL_GWC_EN_SHIFT) & GWC_GLB_CTRL_GWC_EN_MASK)
#define	GWC_GLB_CTRL_GWC_EN_GET(x)   (((uint32_t)(x) & GWC_GLB_CTRL_GWC_EN_MASK) >> GWC_GLB_CTRL_GWC_EN_SHIFT)
#define	GWC_IRQ_MASK_MASK_RREEZ_MASK   (0x8U)
#define	GWC_IRQ_MASK_MASK_RREEZ_SHIFT   (3U)
#define	GWC_IRQ_MASK_MASK_RREEZ_SET(x)   (((uint32_t)(x) << GWC_IRQ_MASK_MASK_RREEZ_SHIFT) & GWC_IRQ_MASK_MASK_RREEZ_MASK)
#define	GWC_IRQ_MASK_MASK_RREEZ_GET(x)   (((uint32_t)(x) & GWC_IRQ_MASK_MASK_RREEZ_MASK) >> GWC_IRQ_MASK_MASK_RREEZ_SHIFT)
#define	GWC_IRQ_MASK_FUNC_MASK_MASK   (0x2U)
#define	GWC_IRQ_MASK_FUNC_MASK_SHIFT   (1U)
#define	GWC_IRQ_MASK_FUNC_MASK_SET(x)   (((uint32_t)(x) << GWC_IRQ_MASK_FUNC_MASK_SHIFT) & GWC_IRQ_MASK_FUNC_MASK_MASK)
#define	GWC_IRQ_MASK_FUNC_MASK_GET(x)   (((uint32_t)(x) & GWC_IRQ_MASK_FUNC_MASK_MASK) >> GWC_IRQ_MASK_FUNC_MASK_SHIFT)
#define	GWC_IRQ_MASK_ERR_MASK_MASK   (0x1U)
#define	GWC_IRQ_MASK_ERR_MASK_SHIFT   (0U)
#define	GWC_IRQ_MASK_ERR_MASK_SET(x)   (((uint32_t)(x) << GWC_IRQ_MASK_ERR_MASK_SHIFT) & GWC_IRQ_MASK_ERR_MASK_MASK)
#define	GWC_IRQ_MASK_ERR_MASK_GET(x)   (((uint32_t)(x) & GWC_IRQ_MASK_ERR_MASK_MASK) >> GWC_IRQ_MASK_ERR_MASK_SHIFT)
#define	GWC_IRQ_STS_FUNC_STS_MASK   (0x20000UL)
#define	GWC_IRQ_STS_FUNC_STS_SHIFT   (17U)
#define	GWC_IRQ_STS_FUNC_STS_SET(x)   (((uint32_t)(x) << GWC_IRQ_STS_FUNC_STS_SHIFT) & GWC_IRQ_STS_FUNC_STS_MASK)
#define	GWC_IRQ_STS_FUNC_STS_GET(x)   (((uint32_t)(x) & GWC_IRQ_STS_FUNC_STS_MASK) >> GWC_IRQ_STS_FUNC_STS_SHIFT)
#define	GWC_IRQ_STS_ERR_STS_MASK   (0x10000UL)
#define	GWC_IRQ_STS_ERR_STS_SHIFT   (16U)
#define	GWC_IRQ_STS_ERR_STS_GET(x)   (((uint32_t)(x) & GWC_IRQ_STS_ERR_STS_MASK) >> GWC_IRQ_STS_ERR_STS_SHIFT)
#define	GWC_IRQ_STS_GWC_FAIL_STS_MASK   (0xFFFFU)
#define	GWC_IRQ_STS_GWC_FAIL_STS_SHIFT   (0U)
#define	GWC_IRQ_STS_GWC_FAIL_STS_SET(x)   (((uint32_t)(x) << GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) & GWC_IRQ_STS_GWC_FAIL_STS_MASK)
#define	GWC_IRQ_STS_GWC_FAIL_STS_GET(x)   (((uint32_t)(x) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) >> GWC_IRQ_STS_GWC_FAIL_STS_SHIFT)
#define	GWC_CHANNEL_CFG0_ENABLE_MASK   (0x80000000UL)
#define	GWC_CHANNEL_CFG0_ENABLE_SHIFT   (31U)
#define	GWC_CHANNEL_CFG0_ENABLE_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CFG0_ENABLE_SHIFT) & GWC_CHANNEL_CFG0_ENABLE_MASK)
#define	GWC_CHANNEL_CFG0_ENABLE_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CFG0_ENABLE_MASK) >> GWC_CHANNEL_CFG0_ENABLE_SHIFT)
#define	GWC_CHANNEL_CFG0_FREEZE_MASK   (0x40000000UL)
#define	GWC_CHANNEL_CFG0_FREEZE_SHIFT   (30U)
#define	GWC_CHANNEL_CFG0_FREEZE_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CFG0_FREEZE_SHIFT) & GWC_CHANNEL_CFG0_FREEZE_MASK)
#define	GWC_CHANNEL_CFG0_FREEZE_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CFG0_FREEZE_MASK) >> GWC_CHANNEL_CFG0_FREEZE_SHIFT)
#define	GWC_CHANNEL_CFG0_START_ROW_MASK   (0xFFF0000UL)
#define	GWC_CHANNEL_CFG0_START_ROW_SHIFT   (16U)
#define	GWC_CHANNEL_CFG0_START_ROW_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_ROW_SHIFT) & GWC_CHANNEL_CFG0_START_ROW_MASK)
#define	GWC_CHANNEL_CFG0_START_ROW_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_ROW_MASK) >> GWC_CHANNEL_CFG0_START_ROW_SHIFT)
#define	GWC_CHANNEL_CFG0_START_COL_MASK   (0x1FFFU)
#define	GWC_CHANNEL_CFG0_START_COL_SHIFT   (0U)
#define	GWC_CHANNEL_CFG0_START_COL_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_COL_SHIFT) & GWC_CHANNEL_CFG0_START_COL_MASK)
#define	GWC_CHANNEL_CFG0_START_COL_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_COL_MASK) >> GWC_CHANNEL_CFG0_START_COL_SHIFT)
#define	GWC_CHANNEL_CFG1_END_ROW_MASK   (0xFFF0000UL)
#define	GWC_CHANNEL_CFG1_END_ROW_SHIFT   (16U)
#define	GWC_CHANNEL_CFG1_END_ROW_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_ROW_SHIFT) & GWC_CHANNEL_CFG1_END_ROW_MASK)
#define	GWC_CHANNEL_CFG1_END_ROW_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_ROW_MASK) >> GWC_CHANNEL_CFG1_END_ROW_SHIFT)
#define	GWC_CHANNEL_CFG1_END_COL_MASK   (0x1FFFU)
#define	GWC_CHANNEL_CFG1_END_COL_SHIFT   (0U)
#define	GWC_CHANNEL_CFG1_END_COL_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_COL_SHIFT) & GWC_CHANNEL_CFG1_END_COL_MASK)
#define	GWC_CHANNEL_CFG1_END_COL_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_COL_MASK) >> GWC_CHANNEL_CFG1_END_COL_SHIFT)
#define	GWC_CHANNEL_REFCRC_REF_CRC_MASK   (0xFFFFFFFFUL)
#define	GWC_CHANNEL_REFCRC_REF_CRC_SHIFT   (0U)
#define	GWC_CHANNEL_REFCRC_REF_CRC_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) & GWC_CHANNEL_REFCRC_REF_CRC_MASK)
#define	GWC_CHANNEL_REFCRC_REF_CRC_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) >> GWC_CHANNEL_REFCRC_REF_CRC_SHIFT)
#define	GWC_CHANNEL_CALCRC_CAL_CRC_MASK   (0xFFFFFFFFUL)
#define	GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT   (0U)
#define	GWC_CHANNEL_CALCRC_CAL_CRC_SET(x)   (((uint32_t)(x) << GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK)
#define	GWC_CHANNEL_CALCRC_CAL_CRC_GET(x)   (((uint32_t)(x) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) >> GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT)
#define	GWC_CHANNEL_CH0   (0UL)
#define	GWC_CHANNEL_CH15   (15UL)

Macro Definition Documentation

GWC_CHANNEL_CALCRC_CAL_CRC_GET

#define GWC_CHANNEL_CALCRC_CAL_CRC_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) >> GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT)

GWC_CHANNEL_CALCRC_CAL_CRC_MASK

#define GWC_CHANNEL_CALCRC_CAL_CRC_MASK   (0xFFFFFFFFUL)

GWC_CHANNEL_CALCRC_CAL_CRC_SET

#define GWC_CHANNEL_CALCRC_CAL_CRC_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK)

GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT

#define GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT   (0U)

GWC_CHANNEL_CFG0_ENABLE_GET

#define GWC_CHANNEL_CFG0_ENABLE_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CFG0_ENABLE_MASK) >> GWC_CHANNEL_CFG0_ENABLE_SHIFT)

GWC_CHANNEL_CFG0_ENABLE_MASK

#define GWC_CHANNEL_CFG0_ENABLE_MASK   (0x80000000UL)

GWC_CHANNEL_CFG0_ENABLE_SET

#define GWC_CHANNEL_CFG0_ENABLE_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CFG0_ENABLE_SHIFT) & GWC_CHANNEL_CFG0_ENABLE_MASK)

GWC_CHANNEL_CFG0_ENABLE_SHIFT

#define GWC_CHANNEL_CFG0_ENABLE_SHIFT   (31U)

GWC_CHANNEL_CFG0_FREEZE_GET

#define GWC_CHANNEL_CFG0_FREEZE_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CFG0_FREEZE_MASK) >> GWC_CHANNEL_CFG0_FREEZE_SHIFT)

GWC_CHANNEL_CFG0_FREEZE_MASK

#define GWC_CHANNEL_CFG0_FREEZE_MASK   (0x40000000UL)

GWC_CHANNEL_CFG0_FREEZE_SET

#define GWC_CHANNEL_CFG0_FREEZE_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CFG0_FREEZE_SHIFT) & GWC_CHANNEL_CFG0_FREEZE_MASK)

GWC_CHANNEL_CFG0_FREEZE_SHIFT

#define GWC_CHANNEL_CFG0_FREEZE_SHIFT   (30U)

GWC_CHANNEL_CFG0_START_COL_GET

#define GWC_CHANNEL_CFG0_START_COL_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CFG0_START_COL_MASK) >> GWC_CHANNEL_CFG0_START_COL_SHIFT)

GWC_CHANNEL_CFG0_START_COL_MASK

#define GWC_CHANNEL_CFG0_START_COL_MASK   (0x1FFFU)

GWC_CHANNEL_CFG0_START_COL_SET

#define GWC_CHANNEL_CFG0_START_COL_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CFG0_START_COL_SHIFT) & GWC_CHANNEL_CFG0_START_COL_MASK)

GWC_CHANNEL_CFG0_START_COL_SHIFT

#define GWC_CHANNEL_CFG0_START_COL_SHIFT   (0U)

GWC_CHANNEL_CFG0_START_ROW_GET

#define GWC_CHANNEL_CFG0_START_ROW_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CFG0_START_ROW_MASK) >> GWC_CHANNEL_CFG0_START_ROW_SHIFT)

GWC_CHANNEL_CFG0_START_ROW_MASK

#define GWC_CHANNEL_CFG0_START_ROW_MASK   (0xFFF0000UL)

GWC_CHANNEL_CFG0_START_ROW_SET

#define GWC_CHANNEL_CFG0_START_ROW_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CFG0_START_ROW_SHIFT) & GWC_CHANNEL_CFG0_START_ROW_MASK)

GWC_CHANNEL_CFG0_START_ROW_SHIFT

#define GWC_CHANNEL_CFG0_START_ROW_SHIFT   (16U)

GWC_CHANNEL_CFG1_END_COL_GET

#define GWC_CHANNEL_CFG1_END_COL_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CFG1_END_COL_MASK) >> GWC_CHANNEL_CFG1_END_COL_SHIFT)

GWC_CHANNEL_CFG1_END_COL_MASK

#define GWC_CHANNEL_CFG1_END_COL_MASK   (0x1FFFU)

GWC_CHANNEL_CFG1_END_COL_SET

#define GWC_CHANNEL_CFG1_END_COL_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CFG1_END_COL_SHIFT) & GWC_CHANNEL_CFG1_END_COL_MASK)

GWC_CHANNEL_CFG1_END_COL_SHIFT

#define GWC_CHANNEL_CFG1_END_COL_SHIFT   (0U)

GWC_CHANNEL_CFG1_END_ROW_GET

#define GWC_CHANNEL_CFG1_END_ROW_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_CFG1_END_ROW_MASK) >> GWC_CHANNEL_CFG1_END_ROW_SHIFT)

GWC_CHANNEL_CFG1_END_ROW_MASK

#define GWC_CHANNEL_CFG1_END_ROW_MASK   (0xFFF0000UL)

GWC_CHANNEL_CFG1_END_ROW_SET

#define GWC_CHANNEL_CFG1_END_ROW_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_CFG1_END_ROW_SHIFT) & GWC_CHANNEL_CFG1_END_ROW_MASK)

GWC_CHANNEL_CFG1_END_ROW_SHIFT

#define GWC_CHANNEL_CFG1_END_ROW_SHIFT   (16U)

GWC_CHANNEL_CH0

#define GWC_CHANNEL_CH0   (0UL)

GWC_CHANNEL_CH15

#define GWC_CHANNEL_CH15   (15UL)

GWC_CHANNEL_REFCRC_REF_CRC_GET

#define GWC_CHANNEL_REFCRC_REF_CRC_GET

(

x

)

(((uint32_t)(x) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) >> GWC_CHANNEL_REFCRC_REF_CRC_SHIFT)

GWC_CHANNEL_REFCRC_REF_CRC_MASK

#define GWC_CHANNEL_REFCRC_REF_CRC_MASK   (0xFFFFFFFFUL)

GWC_CHANNEL_REFCRC_REF_CRC_SET

#define GWC_CHANNEL_REFCRC_REF_CRC_SET

(

x

)

(((uint32_t)(x) << GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) & GWC_CHANNEL_REFCRC_REF_CRC_MASK)

GWC_CHANNEL_REFCRC_REF_CRC_SHIFT

#define GWC_CHANNEL_REFCRC_REF_CRC_SHIFT   (0U)

GWC_GLB_CTRL_CLK_POL_GET

#define GWC_GLB_CTRL_CLK_POL_GET

(

x

)

(((uint32_t)(x) & GWC_GLB_CTRL_CLK_POL_MASK) >> GWC_GLB_CTRL_CLK_POL_SHIFT)

GWC_GLB_CTRL_CLK_POL_MASK

#define GWC_GLB_CTRL_CLK_POL_MASK   (0x80U)

GWC_GLB_CTRL_CLK_POL_SET

#define GWC_GLB_CTRL_CLK_POL_SET

(

x

)

(((uint32_t)(x) << GWC_GLB_CTRL_CLK_POL_SHIFT) & GWC_GLB_CTRL_CLK_POL_MASK)

GWC_GLB_CTRL_CLK_POL_SHIFT

#define GWC_GLB_CTRL_CLK_POL_SHIFT   (7U)

GWC_GLB_CTRL_GWC_EN_GET

#define GWC_GLB_CTRL_GWC_EN_GET

(

x

)

(((uint32_t)(x) & GWC_GLB_CTRL_GWC_EN_MASK) >> GWC_GLB_CTRL_GWC_EN_SHIFT)

GWC_GLB_CTRL_GWC_EN_MASK

#define GWC_GLB_CTRL_GWC_EN_MASK   (0x1U)

GWC_GLB_CTRL_GWC_EN_SET

#define GWC_GLB_CTRL_GWC_EN_SET

(

x

)

(((uint32_t)(x) << GWC_GLB_CTRL_GWC_EN_SHIFT) & GWC_GLB_CTRL_GWC_EN_MASK)

GWC_GLB_CTRL_GWC_EN_SHIFT

#define GWC_GLB_CTRL_GWC_EN_SHIFT   (0U)

GWC_IRQ_MASK_ERR_MASK_GET

#define GWC_IRQ_MASK_ERR_MASK_GET

(

x

)

(((uint32_t)(x) & GWC_IRQ_MASK_ERR_MASK_MASK) >> GWC_IRQ_MASK_ERR_MASK_SHIFT)

GWC_IRQ_MASK_ERR_MASK_MASK

#define GWC_IRQ_MASK_ERR_MASK_MASK   (0x1U)

GWC_IRQ_MASK_ERR_MASK_SET

#define GWC_IRQ_MASK_ERR_MASK_SET

(

x

)

(((uint32_t)(x) << GWC_IRQ_MASK_ERR_MASK_SHIFT) & GWC_IRQ_MASK_ERR_MASK_MASK)

GWC_IRQ_MASK_ERR_MASK_SHIFT

#define GWC_IRQ_MASK_ERR_MASK_SHIFT   (0U)

GWC_IRQ_MASK_FUNC_MASK_GET

#define GWC_IRQ_MASK_FUNC_MASK_GET

(

x

)

(((uint32_t)(x) & GWC_IRQ_MASK_FUNC_MASK_MASK) >> GWC_IRQ_MASK_FUNC_MASK_SHIFT)

GWC_IRQ_MASK_FUNC_MASK_MASK

#define GWC_IRQ_MASK_FUNC_MASK_MASK   (0x2U)

GWC_IRQ_MASK_FUNC_MASK_SET

#define GWC_IRQ_MASK_FUNC_MASK_SET

(

x

)

(((uint32_t)(x) << GWC_IRQ_MASK_FUNC_MASK_SHIFT) & GWC_IRQ_MASK_FUNC_MASK_MASK)

GWC_IRQ_MASK_FUNC_MASK_SHIFT

#define GWC_IRQ_MASK_FUNC_MASK_SHIFT   (1U)

GWC_IRQ_MASK_MASK_RREEZ_GET

#define GWC_IRQ_MASK_MASK_RREEZ_GET

(

x

)

(((uint32_t)(x) & GWC_IRQ_MASK_MASK_RREEZ_MASK) >> GWC_IRQ_MASK_MASK_RREEZ_SHIFT)

GWC_IRQ_MASK_MASK_RREEZ_MASK

#define GWC_IRQ_MASK_MASK_RREEZ_MASK   (0x8U)

GWC_IRQ_MASK_MASK_RREEZ_SET

#define GWC_IRQ_MASK_MASK_RREEZ_SET

(

x

)

(((uint32_t)(x) << GWC_IRQ_MASK_MASK_RREEZ_SHIFT) & GWC_IRQ_MASK_MASK_RREEZ_MASK)

GWC_IRQ_MASK_MASK_RREEZ_SHIFT

#define GWC_IRQ_MASK_MASK_RREEZ_SHIFT   (3U)

GWC_IRQ_STS_ERR_STS_GET

#define GWC_IRQ_STS_ERR_STS_GET

(

x

)

(((uint32_t)(x) & GWC_IRQ_STS_ERR_STS_MASK) >> GWC_IRQ_STS_ERR_STS_SHIFT)

GWC_IRQ_STS_ERR_STS_MASK

#define GWC_IRQ_STS_ERR_STS_MASK   (0x10000UL)

GWC_IRQ_STS_ERR_STS_SHIFT

#define GWC_IRQ_STS_ERR_STS_SHIFT   (16U)

GWC_IRQ_STS_FUNC_STS_GET

#define GWC_IRQ_STS_FUNC_STS_GET

(

x

)

(((uint32_t)(x) & GWC_IRQ_STS_FUNC_STS_MASK) >> GWC_IRQ_STS_FUNC_STS_SHIFT)

GWC_IRQ_STS_FUNC_STS_MASK

#define GWC_IRQ_STS_FUNC_STS_MASK   (0x20000UL)

GWC_IRQ_STS_FUNC_STS_SET

#define GWC_IRQ_STS_FUNC_STS_SET

(

x

)

(((uint32_t)(x) << GWC_IRQ_STS_FUNC_STS_SHIFT) & GWC_IRQ_STS_FUNC_STS_MASK)

GWC_IRQ_STS_FUNC_STS_SHIFT

#define GWC_IRQ_STS_FUNC_STS_SHIFT   (17U)

GWC_IRQ_STS_GWC_FAIL_STS_GET

#define GWC_IRQ_STS_GWC_FAIL_STS_GET

(

x

)

(((uint32_t)(x) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) >> GWC_IRQ_STS_GWC_FAIL_STS_SHIFT)

GWC_IRQ_STS_GWC_FAIL_STS_MASK

#define GWC_IRQ_STS_GWC_FAIL_STS_MASK   (0xFFFFU)

GWC_IRQ_STS_GWC_FAIL_STS_SET

#define GWC_IRQ_STS_GWC_FAIL_STS_SET

(

x

)

(((uint32_t)(x) << GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) & GWC_IRQ_STS_GWC_FAIL_STS_MASK)

GWC_IRQ_STS_GWC_FAIL_STS_SHIFT

#define GWC_IRQ_STS_GWC_FAIL_STS_SHIFT   (0U)