HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_mipi_dsi_phy_regs.h File Reference

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Data Structures

struct  MIPI_DSI_PHY_Type
 

Macros

#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK   (0xFFFFU)
 
#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT   (16U)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT   (8U)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT   (16U)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT   (8U)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK   (0xFFFFU)
 
#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK   (0xFF000000UL)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT   (24U)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT   (16U)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT   (8U)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT   (16U)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT   (8U)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK)
 
#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK   (0xFFFFU)
 
#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK   (0xFF000000UL)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT   (24U)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT   (16U)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT   (8U)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK)
 
#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK   (0xFFFFU)
 
#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK   (0xFF000000UL)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT   (24U)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT   (16U)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT   (8U)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK)
 
#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK   (0xFFFFU)
 
#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK   (0xFF000000UL)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT   (24U)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK   (0xFF0000UL)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT   (16U)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT   (8U)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT)
 
#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT   (0U)
 
#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK)
 
#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT)
 
#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT   (0U)
 
#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK)
 
#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) >> MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK   (0x80U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT   (7U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK   (0x40U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT   (6U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK   (0x20U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT   (5U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK   (0x10U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT   (4U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK   (0x8U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT   (3U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK   (0x4U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT   (2U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK   (0x2U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT   (1U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT)
 
#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK   (0x1U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK)
 
#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK   (0x8000000UL)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT   (27U)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK   (0x7000000UL)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT   (24U)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK   (0xF80000UL)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT   (19U)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK   (0x7FFF0UL)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT   (4U)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK   (0xFU)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT   (0U)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK)
 
#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK   (0x2000U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT   (13U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK   (0x1E00U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT   (9U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK   (0x1FEU)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT   (1U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK   (0x1U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT   (0U)
 
#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT)
 
#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK   (0x3800U)
 
#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT   (11U)
 
#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK)
 
#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK   (0x700U)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT   (8U)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK   (0xF0U)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT   (4U)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK   (0xFU)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT   (0U)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK)
 
#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK   (0x7E0000UL)
 
#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT   (17U)
 
#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK   (0x1F000UL)
 
#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT   (12U)
 
#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK   (0xF80U)
 
#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT   (7U)
 
#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK   (0x40U)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT   (6U)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK   (0x30U)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT   (4U)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK   (0x8U)
 
#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT   (3U)
 
#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK   (0x7U)
 
#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT   (0U)
 
#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK   (0xFFFFFC00UL)
 
#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT   (10U)
 
#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK   (0x3C0U)
 
#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT   (6U)
 
#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) >> MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK   (0x20U)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT   (5U)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK   (0x18U)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT   (3U)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK   (0x4U)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT   (2U)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT)
 
#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK   (0x3U)
 
#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT   (0U)
 
#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK)
 
#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT)
 
#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK   (0x780U)
 
#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT   (7U)
 
#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK)
 
#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) >> MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT)
 
#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK   (0x60U)
 
#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT   (5U)
 
#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK)
 
#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) >> MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT)
 
#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK   (0x1FU)
 
#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT   (0U)
 
#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK)
 
#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) >> MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK   (0xFFFFFFFFUL)
 
#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK)
 
#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK   (0xFF00U)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT   (8U)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT   (0U)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK)
 
#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK   (0x10U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT   (4U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK   (0x8U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT   (3U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK   (0x4U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT   (2U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK   (0x2U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT   (1U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK   (0x1U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT   (0U)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK)
 
#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK   (0x100U)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT   (8U)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK   (0xFFU)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT   (0U)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK)
 
#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK   (0x8U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT   (3U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK   (0x4U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT   (2U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK   (0x2U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT   (1U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK   (0x1U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT   (0U)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SET(x)   (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK)
 
#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_GET(x)   (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT)
 

Macro Definition Documentation

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_GET

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK   (0xFFU)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_GET

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK   (0x100U)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SET

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT   (8U)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SET

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK)

◆ MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT

#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT   (0U)

◆ MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_GET

#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK   (0xFFFFU)

◆ MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SET

#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT   (0U)

◆ MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_GET

#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SET

#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT   (0U)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_GET

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK   (0xFFU)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT   (0U)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_GET

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT   (16U)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_GET

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT   (8U)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_GET

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT   (16U)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_GET

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT   (8U)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_GET

#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK   (0xFFU)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SET

#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT   (0U)

◆ MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_GET

#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT)

◆ MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK

#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SET

#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK)

◆ MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT

#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT   (0U)

◆ MIPI_DSI_PHY_COMMON_PARA0_T_LPX_GET

#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) >> MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT)

◆ MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK

#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK   (0xFFU)

◆ MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SET

#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK)

◆ MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT

#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT   (0U)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_GET

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK   (0x10U)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SET

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT   (4U)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_GET

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK   (0x20U)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SET

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT   (5U)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_GET

#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK   (0x40U)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SET

#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT   (6U)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_GET

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK   (0x2U)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SET

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT   (1U)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_GET

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK   (0x4U)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SET

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT   (2U)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_GET

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK   (0x8U)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SET

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT   (3U)

◆ MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_GET

#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK   (0x1U)

◆ MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SET

#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK)

◆ MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT   (0U)

◆ MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_GET

#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT)

◆ MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK

#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK   (0x80U)

◆ MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT

#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT   (7U)

◆ MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK   (0xFFFFU)

◆ MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK   (0xFFU)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK   (0xFF000000UL)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT   (24U)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT   (8U)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT   (16U)

◆ MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK   (0xFFU)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT   (16U)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_GET

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK)

◆ MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT

#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT   (8U)

◆ MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK   (0xFFFFU)

◆ MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK   (0xFFU)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK   (0xFF000000UL)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT   (24U)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT   (8U)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT   (16U)

◆ MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_GET

#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT)

◆ MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK

#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SET

#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK)

◆ MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT

#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK   (0xFFFFU)

◆ MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK   (0xFFU)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK   (0xFF000000UL)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT   (24U)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT   (8U)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT   (16U)

◆ MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_GET

#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT)

◆ MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK

#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SET

#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK)

◆ MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT

#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK   (0xFFFFU)

◆ MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK   (0xFFU)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT   (0U)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK   (0xFF000000UL)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT   (24U)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT   (8U)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK   (0xFF0000UL)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT   (16U)

◆ MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_GET

#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT)

◆ MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK

#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK   (0xFFFFFFFFUL)

◆ MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SET

#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK)

◆ MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT

#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT   (0U)

◆ MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_GET

#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT)

◆ MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK

#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK   (0xFFU)

◆ MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SET

#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK)

◆ MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT

#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT   (0U)

◆ MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_GET

#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT)

◆ MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK

#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK   (0xFF00U)

◆ MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SET

#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK)

◆ MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT

#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT   (8U)

◆ MIPI_DSI_PHY_MISC_PARA_DLL_SEL_GET

#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) >> MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT)

◆ MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK

#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK   (0x780U)

◆ MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SET

#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK)

◆ MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT

#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT   (7U)

◆ MIPI_DSI_PHY_MISC_PARA_LANE_NUM_GET

#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) >> MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT)

◆ MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK

#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK   (0x60U)

◆ MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET

#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK)

◆ MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT

#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT   (5U)

◆ MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_GET

#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) >> MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT)

◆ MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK

#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK   (0x1FU)

◆ MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SET

#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK)

◆ MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT

#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT   (0U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_GET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK   (0x10U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT   (4U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_GET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK   (0x4U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT   (2U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_GET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK   (0x8U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT   (3U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_GET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK   (0x1U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT   (0U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_GET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK   (0x2U)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SET

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK)

◆ MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT

#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT   (1U)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_GET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK   (0xFU)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT   (0U)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_GET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK   (0x7FFF0UL)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT   (4U)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_GET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK   (0x8000000UL)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT   (27U)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_GET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK   (0x7000000UL)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT   (24U)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_GET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK   (0xF80000UL)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK)

◆ MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT

#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT   (19U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_GET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK   (0x1U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT   (0U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_GET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK   (0x2U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT   (1U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_GET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK   (0x4U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT   (2U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_GET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK   (0x8U)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SET

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK)

◆ MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT

#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT   (3U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_GET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK   (0x1FEU)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT   (1U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_GET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK   (0x1U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT   (0U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_GET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK   (0x2000U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT   (13U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_GET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK   (0x1E00U)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SET

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK)

◆ MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT

#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT   (9U)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_GET

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK   (0x40U)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SET

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT   (6U)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_GET

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK   (0x30U)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SET

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK)

◆ MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT   (4U)

◆ MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_GET

#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK

#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK   (0x1F000UL)

◆ MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT   (12U)

◆ MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_GET

#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK

#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK   (0xF80U)

◆ MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT   (7U)

◆ MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_GET

#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK

#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK   (0x7E0000UL)

◆ MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT   (17U)

◆ MIPI_DSI_PHY_TEST_PARA0_FSET_EN_GET

#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK

#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK   (0x8U)

◆ MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SET

#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK)

◆ MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT   (3U)

◆ MIPI_DSI_PHY_TEST_PARA0_FT_SEL_GET

#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK

#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK   (0x7U)

◆ MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SET

#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK)

◆ MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT

#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT   (0U)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_GET

#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK

#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK   (0x20U)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SET

#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT

#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT   (5U)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_EN_GET

#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK

#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK   (0x18U)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SET

#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT

#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT   (3U)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_GET

#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK

#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK   (0x4U)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SET

#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK)

◆ MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT

#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT   (2U)

◆ MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_GET

#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK

#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK   (0xFFFFFC00UL)

◆ MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SET

#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK)

◆ MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT

#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT   (10U)

◆ MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_GET

#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) >> MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK

#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK   (0x3C0U)

◆ MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SET

#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK)

◆ MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT

#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT   (6U)

◆ MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_GET

#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT)

◆ MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK

#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK   (0x3U)

◆ MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SET

#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK)

◆ MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT

#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT   (0U)

◆ MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_GET

#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT)

◆ MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK

#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK   (0x3800U)

◆ MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SET

#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK)

◆ MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT

#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT   (11U)

◆ MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_GET

#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT)

◆ MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK

#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK   (0xFU)

◆ MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SET

#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK)

◆ MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT

#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT   (0U)

◆ MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_GET

#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT)

◆ MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK

#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK   (0xF0U)

◆ MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SET

#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK)

◆ MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT

#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT   (4U)

◆ MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_GET

#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_GET (   x)    (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT)

◆ MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK

#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK   (0x700U)

◆ MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SET

#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SET (   x)    (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK)

◆ MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT

#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT   (8U)