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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
|
Go to the source code of this file.
Data Structures | |
| struct | MTG_Type |
| #define MTG_CMD_0 (0UL) |
| #define MTG_CMD_1 (1UL) |
| #define MTG_CMD_2 (2UL) |
| #define MTG_CMD_3 (3UL) |
| #define MTG_EVENT_0 (0UL) |
| #define MTG_EVENT_1 (1UL) |
| #define MTG_EVENT_2 (2UL) |
| #define MTG_EVENT_3 (3UL) |
| #define MTG_EVENT_CONTROL_DIR_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_DIR_MASK) >> MTG_EVENT_CONTROL_DIR_SHIFT) |
| #define MTG_EVENT_CONTROL_DIR_MASK (0x60000UL) |
| #define MTG_EVENT_CONTROL_DIR_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_DIR_MODE_MASK) >> MTG_EVENT_CONTROL_DIR_MODE_SHIFT) |
| #define MTG_EVENT_CONTROL_DIR_MODE_MASK (0x10000UL) |
| #define MTG_EVENT_CONTROL_DIR_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_DIR_MODE_SHIFT) & MTG_EVENT_CONTROL_DIR_MODE_MASK) |
| #define MTG_EVENT_CONTROL_DIR_MODE_SHIFT (16U) |
| #define MTG_EVENT_CONTROL_DIR_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_DIR_SHIFT) & MTG_EVENT_CONTROL_DIR_MASK) |
| #define MTG_EVENT_CONTROL_DIR_SHIFT (17U) |
| #define MTG_EVENT_CONTROL_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_ENABLE_MASK) >> MTG_EVENT_CONTROL_ENABLE_SHIFT) |
| #define MTG_EVENT_CONTROL_ENABLE_MASK (0x80000000UL) |
| #define MTG_EVENT_CONTROL_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_ENABLE_SHIFT) & MTG_EVENT_CONTROL_ENABLE_MASK) |
| #define MTG_EVENT_CONTROL_ENABLE_SHIFT (31U) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK) >> MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK (0x4U) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT) & MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT (2U) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_IRQ_MASK) >> MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_MASK (0x1U) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT) & MTG_EVENT_CONTROL_EVENT_IRQ_MASK) |
| #define MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT (0U) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK) >> MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK (0x8U) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT (3U) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK) >> MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK (0x2U) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK) |
| #define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT (1U) |
| #define MTG_EVENT_CONTROL_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_MODE_MASK) >> MTG_EVENT_CONTROL_MODE_SHIFT) |
| #define MTG_EVENT_CONTROL_MODE_MASK (0x780000UL) |
| #define MTG_EVENT_CONTROL_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_MODE_SHIFT) & MTG_EVENT_CONTROL_MODE_MASK) |
| #define MTG_EVENT_CONTROL_MODE_SHIFT (19U) |
| #define MTG_EVENT_CONTROL_OBJECT_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_OBJECT_MASK) >> MTG_EVENT_CONTROL_OBJECT_SHIFT) |
| #define MTG_EVENT_CONTROL_OBJECT_MASK (0x7800000UL) |
| #define MTG_EVENT_CONTROL_OBJECT_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_OBJECT_SHIFT) & MTG_EVENT_CONTROL_OBJECT_MASK) |
| #define MTG_EVENT_CONTROL_OBJECT_SHIFT (23U) |
| #define MTG_EVENT_CONTROL_OVER_MODE_CMP_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK) >> MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT) |
| #define MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK (0x8000U) |
| #define MTG_EVENT_CONTROL_OVER_MODE_CMP_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT) & MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK) |
| #define MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT (15U) |
| #define MTG_EVENT_CONTROL_SOURCE_MUX_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_SOURCE_MUX_MASK) >> MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT) |
| #define MTG_EVENT_CONTROL_SOURCE_MUX_MASK (0x78000000UL) |
| #define MTG_EVENT_CONTROL_SOURCE_MUX_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT) & MTG_EVENT_CONTROL_SOURCE_MUX_MASK) |
| #define MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT (27U) |
| #define MTG_EVENT_CONTROL_TRIG_NUM_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_CONTROL_TRIG_NUM_MASK) >> MTG_EVENT_CONTROL_TRIG_NUM_SHIFT) |
| #define MTG_EVENT_CONTROL_TRIG_NUM_MASK (0x4000U) |
| #define MTG_EVENT_CONTROL_TRIG_NUM_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_CONTROL_TRIG_NUM_SHIFT) & MTG_EVENT_CONTROL_TRIG_NUM_MASK) |
| #define MTG_EVENT_CONTROL_TRIG_NUM_SHIFT (14U) |
| #define MTG_EVENT_PRESET_0_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_PRESET_0_PRESET_MASK) >> MTG_EVENT_PRESET_0_PRESET_SHIFT) |
| #define MTG_EVENT_PRESET_0_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_EVENT_PRESET_0_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_PRESET_0_PRESET_SHIFT) & MTG_EVENT_PRESET_0_PRESET_MASK) |
| #define MTG_EVENT_PRESET_0_PRESET_SHIFT (0U) |
| #define MTG_EVENT_PRESET_1_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_PRESET_1_PRESET_MASK) >> MTG_EVENT_PRESET_1_PRESET_SHIFT) |
| #define MTG_EVENT_PRESET_1_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_EVENT_PRESET_1_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_PRESET_1_PRESET_SHIFT) & MTG_EVENT_PRESET_1_PRESET_MASK) |
| #define MTG_EVENT_PRESET_1_PRESET_SHIFT (0U) |
| #define MTG_EVENT_PRESET_2_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_PRESET_2_PRESET_MASK) >> MTG_EVENT_PRESET_2_PRESET_SHIFT) |
| #define MTG_EVENT_PRESET_2_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_EVENT_PRESET_2_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_PRESET_2_PRESET_SHIFT) & MTG_EVENT_PRESET_2_PRESET_MASK) |
| #define MTG_EVENT_PRESET_2_PRESET_SHIFT (0U) |
| #define MTG_EVENT_PRESET_3_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_PRESET_3_PRESET_MASK) >> MTG_EVENT_PRESET_3_PRESET_SHIFT) |
| #define MTG_EVENT_PRESET_3_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_EVENT_PRESET_3_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_EVENT_PRESET_3_PRESET_SHIFT) & MTG_EVENT_PRESET_3_PRESET_MASK) |
| #define MTG_EVENT_PRESET_3_PRESET_SHIFT (0U) |
| #define MTG_EVENT_TIMESTAMP_TIMESTAMP_GET | ( | x | ) | (((uint32_t)(x) & MTG_EVENT_TIMESTAMP_TIMESTAMP_MASK) >> MTG_EVENT_TIMESTAMP_TIMESTAMP_SHIFT) |
| #define MTG_EVENT_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) |
| #define MTG_EVENT_TIMESTAMP_TIMESTAMP_SHIFT (0U) |
| #define MTG_FILTER_ACC_LOCK_ACC_STATUS_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ACC_LOCK_ACC_STATUS_MASK) >> MTG_FILTER_ACC_LOCK_ACC_STATUS_SHIFT) |
| #define MTG_FILTER_ACC_LOCK_ACC_STATUS_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_ACC_LOCK_ACC_STATUS_SHIFT (0U) |
| #define MTG_FILTER_ACC_VALUE_VALUE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ACC_VALUE_VALUE_MASK) >> MTG_FILTER_ACC_VALUE_VALUE_SHIFT) |
| #define MTG_FILTER_ACC_VALUE_VALUE_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_ACC_VALUE_VALUE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ACC_VALUE_VALUE_SHIFT) & MTG_FILTER_ACC_VALUE_VALUE_MASK) |
| #define MTG_FILTER_ACC_VALUE_VALUE_SHIFT (0U) |
| #define MTG_FILTER_CONTROL_A_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_A_EN_MASK) >> MTG_FILTER_CONTROL_A_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_A_EN_MASK (0x40U) |
| #define MTG_FILTER_CONTROL_A_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_A_EN_SHIFT) & MTG_FILTER_CONTROL_A_EN_MASK) |
| #define MTG_FILTER_CONTROL_A_EN_SHIFT (6U) |
| #define MTG_FILTER_CONTROL_EN_TIME0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_EN_TIME0_MASK) >> MTG_FILTER_CONTROL_EN_TIME0_SHIFT) |
| #define MTG_FILTER_CONTROL_EN_TIME0_MASK (0x100U) |
| #define MTG_FILTER_CONTROL_EN_TIME0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_EN_TIME0_SHIFT) & MTG_FILTER_CONTROL_EN_TIME0_MASK) |
| #define MTG_FILTER_CONTROL_EN_TIME0_SHIFT (8U) |
| #define MTG_FILTER_CONTROL_EN_TIME1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_EN_TIME1_MASK) >> MTG_FILTER_CONTROL_EN_TIME1_SHIFT) |
| #define MTG_FILTER_CONTROL_EN_TIME1_MASK (0x200U) |
| #define MTG_FILTER_CONTROL_EN_TIME1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_EN_TIME1_SHIFT) & MTG_FILTER_CONTROL_EN_TIME1_MASK) |
| #define MTG_FILTER_CONTROL_EN_TIME1_SHIFT (9U) |
| #define MTG_FILTER_CONTROL_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_ENABLE_MASK) >> MTG_FILTER_CONTROL_ENABLE_SHIFT) |
| #define MTG_FILTER_CONTROL_ENABLE_MASK (0x1U) |
| #define MTG_FILTER_CONTROL_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_ENABLE_SHIFT) & MTG_FILTER_CONTROL_ENABLE_MASK) |
| #define MTG_FILTER_CONTROL_ENABLE_SHIFT (0U) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK (0x10U) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT (4U) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK (0x400000UL) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT (22U) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK (0x200000UL) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT (21U) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_SHIFT) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_MASK (0x800000UL) |
| #define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_SHIFT (23U) |
| #define MTG_FILTER_CONTROL_ERR_INI_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_INI_MASK) >> MTG_FILTER_CONTROL_ERR_INI_SHIFT) |
| #define MTG_FILTER_CONTROL_ERR_INI_MASK (0x20U) |
| #define MTG_FILTER_CONTROL_ERR_INI_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_INI_SHIFT) & MTG_FILTER_CONTROL_ERR_INI_MASK) |
| #define MTG_FILTER_CONTROL_ERR_INI_SHIFT (5U) |
| #define MTG_FILTER_CONTROL_FF_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_FF_EN_MASK) >> MTG_FILTER_CONTROL_FF_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_FF_EN_MASK (0x4U) |
| #define MTG_FILTER_CONTROL_FF_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_FF_EN_SHIFT) & MTG_FILTER_CONTROL_FF_EN_MASK) |
| #define MTG_FILTER_CONTROL_FF_EN_SHIFT (2U) |
| #define MTG_FILTER_CONTROL_FF_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_FF_MODE_MASK) >> MTG_FILTER_CONTROL_FF_MODE_SHIFT) |
| #define MTG_FILTER_CONTROL_FF_MODE_MASK (0x8U) |
| #define MTG_FILTER_CONTROL_FF_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_FF_MODE_SHIFT) & MTG_FILTER_CONTROL_FF_MODE_MASK) |
| #define MTG_FILTER_CONTROL_FF_MODE_SHIFT (3U) |
| #define MTG_FILTER_CONTROL_INIT_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_INIT_EN_MASK) >> MTG_FILTER_CONTROL_INIT_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_INIT_EN_MASK (0x2U) |
| #define MTG_FILTER_CONTROL_INIT_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_INIT_EN_SHIFT) & MTG_FILTER_CONTROL_INIT_EN_MASK) |
| #define MTG_FILTER_CONTROL_INIT_EN_SHIFT (1U) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK (0x80000000UL) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT (31U) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK (0x40000000UL) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT (30U) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK (0x20000000UL) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK) |
| #define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT (29U) |
| #define MTG_FILTER_CONTROL_REV_INI_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_REV_INI_MODE_MASK) >> MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT) |
| #define MTG_FILTER_CONTROL_REV_INI_MODE_MASK (0x20000UL) |
| #define MTG_FILTER_CONTROL_REV_INI_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT) & MTG_FILTER_CONTROL_REV_INI_MODE_MASK) |
| #define MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT (17U) |
| #define MTG_FILTER_CONTROL_SEL_TIME0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_SEL_TIME0_MASK) >> MTG_FILTER_CONTROL_SEL_TIME0_SHIFT) |
| #define MTG_FILTER_CONTROL_SEL_TIME0_MASK (0xC00U) |
| #define MTG_FILTER_CONTROL_SEL_TIME0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_SEL_TIME0_SHIFT) & MTG_FILTER_CONTROL_SEL_TIME0_MASK) |
| #define MTG_FILTER_CONTROL_SEL_TIME0_SHIFT (10U) |
| #define MTG_FILTER_CONTROL_SEL_TIME1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_SEL_TIME1_MASK) >> MTG_FILTER_CONTROL_SEL_TIME1_SHIFT) |
| #define MTG_FILTER_CONTROL_SEL_TIME1_MASK (0x3000U) |
| #define MTG_FILTER_CONTROL_SEL_TIME1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_SEL_TIME1_SHIFT) & MTG_FILTER_CONTROL_SEL_TIME1_MASK) |
| #define MTG_FILTER_CONTROL_SEL_TIME1_SHIFT (12U) |
| #define MTG_FILTER_CONTROL_SW_LOCK_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_SW_LOCK_MASK) >> MTG_FILTER_CONTROL_SW_LOCK_SHIFT) |
| #define MTG_FILTER_CONTROL_SW_LOCK_MASK (0x100000UL) |
| #define MTG_FILTER_CONTROL_SW_LOCK_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_SW_LOCK_SHIFT) & MTG_FILTER_CONTROL_SW_LOCK_MASK) |
| #define MTG_FILTER_CONTROL_SW_LOCK_SHIFT (20U) |
| #define MTG_FILTER_CONTROL_TIMEOUT_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_CONTROL_TIMEOUT_EN_MASK) >> MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT) |
| #define MTG_FILTER_CONTROL_TIMEOUT_EN_MASK (0x80000UL) |
| #define MTG_FILTER_CONTROL_TIMEOUT_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT) & MTG_FILTER_CONTROL_TIMEOUT_EN_MASK) |
| #define MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT (19U) |
| #define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK) >> MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT) |
| #define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT) & MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK) |
| #define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT (0U) |
| #define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK) >> MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT) |
| #define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT) & MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK) |
| #define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT (0U) |
| #define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT) |
| #define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK (0xF00U) |
| #define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK) |
| #define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT (8U) |
| #define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT) |
| #define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK (0xFU) |
| #define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK) |
| #define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT (0U) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK (0xF000U) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT (12U) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK (0xF0U) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK) |
| #define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT (4U) |
| #define MTG_FILTER_GAIN_GAIN_T0_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_GAIN_GAIN_T0_EN_MASK) >> MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT) |
| #define MTG_FILTER_GAIN_GAIN_T0_EN_MASK (0x80000000UL) |
| #define MTG_FILTER_GAIN_GAIN_T0_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT) & MTG_FILTER_GAIN_GAIN_T0_EN_MASK) |
| #define MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT (31U) |
| #define MTG_FILTER_GAIN_GAIN_T1_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_GAIN_GAIN_T1_EN_MASK) >> MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT) |
| #define MTG_FILTER_GAIN_GAIN_T1_EN_MASK (0x40000000UL) |
| #define MTG_FILTER_GAIN_GAIN_T1_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT) & MTG_FILTER_GAIN_GAIN_T1_EN_MASK) |
| #define MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT (30U) |
| #define MTG_FILTER_GAIN_K_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_GAIN_K_MASK) >> MTG_FILTER_GAIN_K_SHIFT) |
| #define MTG_FILTER_GAIN_K_MASK (0xFFFFFFUL) |
| #define MTG_FILTER_GAIN_K_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_GAIN_K_SHIFT) & MTG_FILTER_GAIN_K_MASK) |
| #define MTG_FILTER_GAIN_K_SHIFT (0U) |
| #define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK) >> MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT) |
| #define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK (0x3FU) |
| #define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT) & MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK) |
| #define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT (0U) |
| #define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK) >> MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT) |
| #define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK (0x3F00U) |
| #define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT) & MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK) |
| #define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT (8U) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK) >> MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK (0x3F0000UL) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT) & MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT (16U) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK) >> MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK (0x3F000000UL) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT) & MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK) |
| #define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT (24U) |
| #define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK) >> MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK (0xF0000000UL) |
| #define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT) & MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT (28U) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK (0xF00000UL) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT (20U) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK (0xF0000UL) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT (16U) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK (0xF000U) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT (12U) |
| #define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK (0xF00U) |
| #define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT (8U) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK (0xF0U) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT (4U) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK (0xFU) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT (0U) |
| #define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK) >> MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT) |
| #define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK (0xF000000UL) |
| #define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT) & MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK) |
| #define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT (24U) |
| #define MTG_FILTER_POS_LOCK_POS_STATUS_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_POS_LOCK_POS_STATUS_MASK) >> MTG_FILTER_POS_LOCK_POS_STATUS_SHIFT) |
| #define MTG_FILTER_POS_LOCK_POS_STATUS_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_POS_LOCK_POS_STATUS_SHIFT (0U) |
| #define MTG_FILTER_POS_VALUE_VALUE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_POS_VALUE_VALUE_MASK) >> MTG_FILTER_POS_VALUE_VALUE_SHIFT) |
| #define MTG_FILTER_POS_VALUE_VALUE_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_POS_VALUE_VALUE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_POS_VALUE_VALUE_SHIFT) & MTG_FILTER_POS_VALUE_VALUE_MASK) |
| #define MTG_FILTER_POS_VALUE_VALUE_SHIFT (0U) |
| #define MTG_FILTER_REV_LOCK_REV_STATUS_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_REV_LOCK_REV_STATUS_MASK) >> MTG_FILTER_REV_LOCK_REV_STATUS_SHIFT) |
| #define MTG_FILTER_REV_LOCK_REV_STATUS_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_REV_LOCK_REV_STATUS_SHIFT (0U) |
| #define MTG_FILTER_REV_VALUE_VALUE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_REV_VALUE_VALUE_MASK) >> MTG_FILTER_REV_VALUE_VALUE_SHIFT) |
| #define MTG_FILTER_REV_VALUE_VALUE_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_REV_VALUE_VALUE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_REV_VALUE_VALUE_SHIFT) & MTG_FILTER_REV_VALUE_VALUE_MASK) |
| #define MTG_FILTER_REV_VALUE_VALUE_SHIFT (0U) |
| #define MTG_FILTER_STAGE_SEL_STAGE0_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT) |
| #define MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK (0x1FU) |
| #define MTG_FILTER_STAGE_SEL_STAGE0_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK) |
| #define MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT (0U) |
| #define MTG_FILTER_STAGE_SEL_STAGE1_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT) |
| #define MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK (0x3E0U) |
| #define MTG_FILTER_STAGE_SEL_STAGE1_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK) |
| #define MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT (5U) |
| #define MTG_FILTER_STAGE_SEL_STAGE2_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT) |
| #define MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK (0x7C00U) |
| #define MTG_FILTER_STAGE_SEL_STAGE2_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK) |
| #define MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT (10U) |
| #define MTG_FILTER_STAGE_SEL_STAGE3_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT) |
| #define MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK (0xF8000UL) |
| #define MTG_FILTER_STAGE_SEL_STAGE3_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK) |
| #define MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT (15U) |
| #define MTG_FILTER_STAGE_SEL_STAGE4_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT) |
| #define MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK (0x1F00000UL) |
| #define MTG_FILTER_STAGE_SEL_STAGE4_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK) |
| #define MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT (20U) |
| #define MTG_FILTER_STAGE_SEL_STAGE5_SEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT) |
| #define MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK (0x3E000000UL) |
| #define MTG_FILTER_STAGE_SEL_STAGE5_SEL_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK) |
| #define MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT (25U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK (0xFU) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT (0U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK (0xF0U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT (4U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK (0xF00U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT (8U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK (0xF000U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT (12U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK (0xF0000UL) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT (16U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK (0xF00000UL) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT (20U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK (0xF000000UL) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT (24U) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK (0xF0000000UL) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK) |
| #define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT (28U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK (0xFU) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT (0U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK (0xF0U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT (4U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK (0xF00U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT (8U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK (0xF000U) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK) |
| #define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT (12U) |
| #define MTG_FILTER_TIME0_SW_ADJUST_TIME_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK) >> MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT) |
| #define MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_TIME0_SW_ADJUST_TIME_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT) & MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK) |
| #define MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT (0U) |
| #define MTG_FILTER_TIME1_SW_ADJUST_TIME_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK) >> MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT) |
| #define MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_TIME1_SW_ADJUST_TIME_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT) & MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK) |
| #define MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT (0U) |
| #define MTG_FILTER_TIME_CONSTANT_TP_TP_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TP_TP_MASK) >> MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT) |
| #define MTG_FILTER_TIME_CONSTANT_TP_TP_MASK (0xFFFFFFUL) |
| #define MTG_FILTER_TIME_CONSTANT_TP_TP_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT) & MTG_FILTER_TIME_CONSTANT_TP_TP_MASK) |
| #define MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT (0U) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK) >> MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK (0xFFFFFFUL) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT) & MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT (0U) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_TZ_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK) >> MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK (0xFFFFFFUL) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_TZ_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT) & MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK) |
| #define MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT (0U) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK) >> MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK (0xF0U) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT (4U) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK) >> MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK (0xF000U) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK) |
| #define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT (12U) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK) >> MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK (0xFU) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT (0U) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK) >> MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK (0xF00U) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK) |
| #define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT (8U) |
| #define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK) >> MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT) |
| #define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT) & MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK) |
| #define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT (0U) |
| #define MTG_FILTER_VEL_LOCK_VEL_STATUS_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_VEL_LOCK_VEL_STATUS_MASK) >> MTG_FILTER_VEL_LOCK_VEL_STATUS_SHIFT) |
| #define MTG_FILTER_VEL_LOCK_VEL_STATUS_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_VEL_LOCK_VEL_STATUS_SHIFT (0U) |
| #define MTG_FILTER_VEL_VALUE_VALUE_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_VEL_VALUE_VALUE_MASK) >> MTG_FILTER_VEL_VALUE_VALUE_SHIFT) |
| #define MTG_FILTER_VEL_VALUE_VALUE_MASK (0xFFFFFFFFUL) |
| #define MTG_FILTER_VEL_VALUE_VALUE_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_VEL_VALUE_VALUE_SHIFT) & MTG_FILTER_VEL_VALUE_VALUE_MASK) |
| #define MTG_FILTER_VEL_VALUE_VALUE_SHIFT (0U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE0_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK (0x1U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE0_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT (0U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE1_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK (0x2U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE1_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT (1U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE2_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK (0x4U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE2_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT (2U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE3_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK (0x8U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE3_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT (3U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE4_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK (0x10U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE4_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT (4U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE5_GET | ( | x | ) | (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK (0x20U) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE5_SET | ( | x | ) | (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK) |
| #define MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT (5U) |
| #define MTG_SW_EVENT_SW_EVENT_TRIG_GET | ( | x | ) | (((uint32_t)(x) & MTG_SW_EVENT_SW_EVENT_TRIG_MASK) >> MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT) |
| #define MTG_SW_EVENT_SW_EVENT_TRIG_MASK (0x1U) |
| #define MTG_SW_EVENT_SW_EVENT_TRIG_SET | ( | x | ) | (((uint32_t)(x) << MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT) & MTG_SW_EVENT_SW_EVENT_TRIG_MASK) |
| #define MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT (0U) |
| #define MTG_SW_GLB_RESET_SW_GLB_RESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_SW_GLB_RESET_SW_GLB_RESET_MASK) >> MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT) |
| #define MTG_SW_GLB_RESET_SW_GLB_RESET_MASK (0x1U) |
| #define MTG_SW_GLB_RESET_SW_GLB_RESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT) & MTG_SW_GLB_RESET_SW_GLB_RESET_MASK) |
| #define MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT (0U) |
| #define MTG_TRA_0 (0UL) |
| #define MTG_TRA_1 (1UL) |
| #define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK) >> MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT) |
| #define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT) & MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK) |
| #define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT (0U) |
| #define MTG_TRA_CMD_CONTROL_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_MODE_MASK) >> MTG_TRA_CMD_CONTROL_MODE_SHIFT) |
| #define MTG_TRA_CMD_CONTROL_MODE_MASK (0x20000000UL) |
| #define MTG_TRA_CMD_CONTROL_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_MODE_SHIFT) & MTG_TRA_CMD_CONTROL_MODE_MASK) |
| #define MTG_TRA_CMD_CONTROL_MODE_SHIFT (29U) |
| #define MTG_TRA_CMD_CONTROL_OBJECT_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_OBJECT_MASK) >> MTG_TRA_CMD_CONTROL_OBJECT_SHIFT) |
| #define MTG_TRA_CMD_CONTROL_OBJECT_MASK (0x1FU) |
| #define MTG_TRA_CMD_CONTROL_OBJECT_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_OBJECT_SHIFT) & MTG_TRA_CMD_CONTROL_OBJECT_MASK) |
| #define MTG_TRA_CMD_CONTROL_OBJECT_SHIFT (0U) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK) >> MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK (0x40000000UL) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT) & MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT (30U) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK) >> MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK (0x80000000UL) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT) & MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK) |
| #define MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT (31U) |
| #define MTG_TRA_CMD_JER_PRESET_JER_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK) >> MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT) |
| #define MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_CMD_JER_PRESET_JER_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT) & MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK) |
| #define MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT (0U) |
| #define MTG_TRA_CMD_POS_PRESET_POS_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK) >> MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT) |
| #define MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_CMD_POS_PRESET_POS_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT) & MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK) |
| #define MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT (0U) |
| #define MTG_TRA_CMD_REV_PRESET_REV_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK) >> MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT) |
| #define MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_CMD_REV_PRESET_REV_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT) & MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK) |
| #define MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT (0U) |
| #define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_MASK) >> MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_SHIFT) |
| #define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_SHIFT (0U) |
| #define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK) >> MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT) |
| #define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT) & MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK) |
| #define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT (0U) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK) >> MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK (0x20U) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT (5U) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK) >> MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK (0x8U) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK) |
| #define MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT (3U) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK) >> MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK (0x10U) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT) & MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT (4U) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CONTROL_LOCK_IRQ_MASK) >> MTG_TRA_CONTROL_LOCK_IRQ_SHIFT) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_MASK (0x4U) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CONTROL_LOCK_IRQ_SHIFT) & MTG_TRA_CONTROL_LOCK_IRQ_MASK) |
| #define MTG_TRA_CONTROL_LOCK_IRQ_SHIFT (2U) |
| #define MTG_TRA_CONTROL_OVALID_CLEAR_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CONTROL_OVALID_CLEAR_MASK) >> MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT) |
| #define MTG_TRA_CONTROL_OVALID_CLEAR_MASK (0x1U) |
| #define MTG_TRA_CONTROL_OVALID_CLEAR_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT) & MTG_TRA_CONTROL_OVALID_CLEAR_MASK) |
| #define MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT (0U) |
| #define MTG_TRA_CONTROL_SW_LOCK_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_CONTROL_SW_LOCK_MASK) >> MTG_TRA_CONTROL_SW_LOCK_SHIFT) |
| #define MTG_TRA_CONTROL_SW_LOCK_MASK (0x2U) |
| #define MTG_TRA_CONTROL_SW_LOCK_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_CONTROL_SW_LOCK_SHIFT) & MTG_TRA_CONTROL_SW_LOCK_MASK) |
| #define MTG_TRA_CONTROL_SW_LOCK_SHIFT (1U) |
| #define MTG_TRA_LINK_LINK_CFG_0_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_0_MASK) >> MTG_TRA_LINK_LINK_CFG_0_SHIFT) |
| #define MTG_TRA_LINK_LINK_CFG_0_MASK (0x7U) |
| #define MTG_TRA_LINK_LINK_CFG_0_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_0_SHIFT) & MTG_TRA_LINK_LINK_CFG_0_MASK) |
| #define MTG_TRA_LINK_LINK_CFG_0_SHIFT (0U) |
| #define MTG_TRA_LINK_LINK_CFG_1_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_1_MASK) >> MTG_TRA_LINK_LINK_CFG_1_SHIFT) |
| #define MTG_TRA_LINK_LINK_CFG_1_MASK (0x70U) |
| #define MTG_TRA_LINK_LINK_CFG_1_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_1_SHIFT) & MTG_TRA_LINK_LINK_CFG_1_MASK) |
| #define MTG_TRA_LINK_LINK_CFG_1_SHIFT (4U) |
| #define MTG_TRA_LINK_LINK_CFG_2_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_2_MASK) >> MTG_TRA_LINK_LINK_CFG_2_SHIFT) |
| #define MTG_TRA_LINK_LINK_CFG_2_MASK (0x700U) |
| #define MTG_TRA_LINK_LINK_CFG_2_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_2_SHIFT) & MTG_TRA_LINK_LINK_CFG_2_MASK) |
| #define MTG_TRA_LINK_LINK_CFG_2_SHIFT (8U) |
| #define MTG_TRA_LINK_LINK_CFG_3_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_3_MASK) >> MTG_TRA_LINK_LINK_CFG_3_SHIFT) |
| #define MTG_TRA_LINK_LINK_CFG_3_MASK (0x7000U) |
| #define MTG_TRA_LINK_LINK_CFG_3_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_3_SHIFT) & MTG_TRA_LINK_LINK_CFG_3_MASK) |
| #define MTG_TRA_LINK_LINK_CFG_3_SHIFT (12U) |
| #define MTG_TRA_LOCK_ACC_LOCK_ACC_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LOCK_ACC_LOCK_ACC_MASK) >> MTG_TRA_LOCK_ACC_LOCK_ACC_SHIFT) |
| #define MTG_TRA_LOCK_ACC_LOCK_ACC_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_LOCK_ACC_LOCK_ACC_SHIFT (0U) |
| #define MTG_TRA_LOCK_POS_LOCK_POS_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LOCK_POS_LOCK_POS_MASK) >> MTG_TRA_LOCK_POS_LOCK_POS_SHIFT) |
| #define MTG_TRA_LOCK_POS_LOCK_POS_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_LOCK_POS_LOCK_POS_SHIFT (0U) |
| #define MTG_TRA_LOCK_REV_LOCK_REV_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LOCK_REV_LOCK_REV_MASK) >> MTG_TRA_LOCK_REV_LOCK_REV_SHIFT) |
| #define MTG_TRA_LOCK_REV_LOCK_REV_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_LOCK_REV_LOCK_REV_SHIFT (0U) |
| #define MTG_TRA_LOCK_TIME_LOCK_TIME_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LOCK_TIME_LOCK_TIME_MASK) >> MTG_TRA_LOCK_TIME_LOCK_TIME_SHIFT) |
| #define MTG_TRA_LOCK_TIME_LOCK_TIME_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_LOCK_TIME_LOCK_TIME_SHIFT (0U) |
| #define MTG_TRA_LOCK_VEL_LOCK_VEL_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_LOCK_VEL_LOCK_VEL_MASK) >> MTG_TRA_LOCK_VEL_LOCK_VEL_SHIFT) |
| #define MTG_TRA_LOCK_VEL_LOCK_VEL_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_LOCK_VEL_LOCK_VEL_SHIFT (0U) |
| #define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK) >> MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT) |
| #define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT) & MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK) |
| #define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT (0U) |
| #define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK) >> MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT) |
| #define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT) & MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK) |
| #define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT (0U) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK) >> MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK (0x80000000UL) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT) & MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT (31U) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_SHIFT_ACC_SHIFT_MASK) >> MTG_TRA_SHIFT_ACC_SHIFT_SHIFT) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_MASK (0x70U) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_SHIFT_ACC_SHIFT_SHIFT) & MTG_TRA_SHIFT_ACC_SHIFT_MASK) |
| #define MTG_TRA_SHIFT_ACC_SHIFT_SHIFT (4U) |
| #define MTG_TRA_SHIFT_JER_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_SHIFT_JER_SHIFT_MASK) >> MTG_TRA_SHIFT_JER_SHIFT_SHIFT) |
| #define MTG_TRA_SHIFT_JER_SHIFT_MASK (0x700U) |
| #define MTG_TRA_SHIFT_JER_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_SHIFT_JER_SHIFT_SHIFT) & MTG_TRA_SHIFT_JER_SHIFT_MASK) |
| #define MTG_TRA_SHIFT_JER_SHIFT_SHIFT (8U) |
| #define MTG_TRA_SHIFT_SHIFT_FAIL_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK) >> MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT) |
| #define MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK (0x20000000UL) |
| #define MTG_TRA_SHIFT_SHIFT_FAIL_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT) & MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK) |
| #define MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT (29U) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK) >> MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK (0x40000000UL) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT) & MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT (30U) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_SHIFT_VEL_SHIFT_MASK) >> MTG_TRA_SHIFT_VEL_SHIFT_SHIFT) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_MASK (0xFU) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_SHIFT_VEL_SHIFT_SHIFT) & MTG_TRA_SHIFT_VEL_SHIFT_MASK) |
| #define MTG_TRA_SHIFT_VEL_SHIFT_SHIFT (0U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK (0x400U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT (10U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK (0x1000U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT (12U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK (0x800U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT (11U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK (0x100U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT (8U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK (0x200U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT (9U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK (0x2U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT (1U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK (0x4U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT (2U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK (0x1U) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK) |
| #define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT (0U) |
| #define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK) >> MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT) |
| #define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT) & MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK) |
| #define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT (0U) |
| #define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK) >> MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT) |
| #define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT) & MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK) |
| #define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT (0U) |
| #define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK) >> MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT) |
| #define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT) & MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK) |
| #define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT (0U) |
| #define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_GET | ( | x | ) | (((uint32_t)(x) & MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK) >> MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT) |
| #define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK (0xFFFFFFFFUL) |
| #define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SET | ( | x | ) | (((uint32_t)(x) << MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT) & MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK) |
| #define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT (0U) |
1.9.1