hpm_mtgv2_drv.h

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/*
 * Copyright (c) 2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_MMC_DRV_H
#define HPM_MMC_DRV_H
 
#include "hpm_common.h"
#include "hpm_mtgv2_regs.h"
typedef enum mtg_irq_enable {
    irq_filter_mul1_overflow = 1 << 0,
    irq_filter_mul0_overflow = 1 << 1,
    irq_event3_object_sudden_change = 1 << 2,
    irq_event3 = 1 << 3,
    irq_event2_object_sudden_change = 1 << 4,
    irq_event2 = 1 << 5,
    irq_event1_object_sudden_change = 1 << 6,
    irq_event1 = 1 << 7,
    irq_event0_object_sudden_change = 1 << 8,
    irq_event0 = 1 << 9,
    irq_tra1_lock = 1 << 10,
    irq_tra1_vel_shift_issue = 1 << 11,
    irq_tra1_acc_shift_issue = 1 << 12,
    irq_tra1_cmd_conflict = 1 << 13,
    irq_tra1_cmd3 = 1 << 14,
    irq_tra1_cmd2 = 1 << 15,
    irq_tra1_cmd1 = 1 << 16,
    irq_tra1_cmd0 = 1 << 17,
    irq_tra0_lock = 1 << 18,
    irq_tra0_vel_shift_issue = 1 << 19,
    irq_tra0_acc_shift_issue = 1 << 20,
    irq_tra0_cmd_conflict = 1 << 21,
    irq_tra0_cmd3 = 1 << 22,
    irq_tra0_cmd2 = 1 << 23,
    irq_tra0_cmd1 = 1 << 24,
    irq_tra0_cmd0 = 1 << 25,
    irq_f_i_irq = 1 << 26,
    irq_i_f_irq0 = 1 << 27,
 
} mtg_irq_enable_t;
 
typedef struct mtg_result {
    int32_t rev; /* revolution */
    uint32_t pos; /* postion */
    int32_t vel; /* velocity */
    int32_t acc; /* acceleration */
    uint32_t time_stamp; /* time stamp */
} mtg_lock_value_t;
 
typedef enum mtg_evnet_object_postion {
    event_source_before_filter = 1 << 0, /* before filter, also treat as input of mtg */
    event_source_filter_output = 1 << 1, /* after filter, also treat as input of mtg's time compensation module */
    event_source_tra0_output = 1 << 2, /* output of mtg's trajectory predictor0 */
    event_source_tra1_output = 1 << 3, /* output of mtg's trajectory predictor1 */
} mtg_evnet_object_postion_t;
 
typedef enum mtg_event_object {
    event_object_rev_pos = 1, /* location, revolution and position */
    event_object_vel = 2, /* velocity */
    event_object_acc = 4, /* acceleration */
    event_object_pos = 8, /* postion, ignore revolution */
} mtg_event_object_t;
 
typedef enum mtg_event_mode {
    event_mode_across = 1, /* across mode, change from greater than to less than, or opposite */
    event_mode_hold = 2, /* hold mode, maintain within a range for a period of time */
    event_mode_over_protect = 4, /* over protect mode, greater than or less than */
    event_mode_time_match = 8, /* time match mode, when the synt's cnt value is equal to the preset */
} mtg_event_mode_t;
 
typedef enum mtg_event_dir {
    event_dir_negative = 0,
    event_dir_positive = 1,
    event_dir_both = 2,
} mtg_event_dir_t;
 
typedef enum mtg_event_dir_mode {
    event_dir_mode_dy = 0, /* use first derivative of object */
    event_dir_mode_y1_y0 = 1, /* use difference of current and previous */
} mtg_event_dir_mode_t;
 
typedef enum mtg_event_over_mode_cmp {
    event_over_cmp_mode_smaller = 0,
    event_over_cmp_mode_bigger = 1,
} mtg_event_over_mode_cmp_t;
 
typedef enum mtg_event_trig_num {
    event_trig_once = 0, /* event can only be triggered once */
    event_trig_repeat = 1, /* event can be triggered multiple times */
} mtg_event_trig_num_t;
 
typedef struct mtg_event_param {
    bool enable;
    bool irq_en; /* enable or disable the event irq */
    mtg_event_object_t obj;
    mtg_evnet_object_postion_t obj_postion;
    mtg_event_mode_t mode;
    mtg_event_dir_t dir;
    mtg_event_dir_mode_t dir_mode;
    mtg_event_trig_num_t trig_num;
 
    /* union struct of event presets registers, different meaning when different event mode */
    union {
        struct {
            uint32_t cross_value_h; /* the high 32bit of cross_value, only need set when object is ${event_object_rev_pos} */
            uint32_t cross_value_l; /* the low 32bit of cross_value */
        } cross_param;
        struct {
            uint32_t hold_value_h; /* the high 32bit of hold_value, only need set when object is ${event_object_rev_pos} */
            uint32_t hold_value_l; /* the low 32bit of hold_value */
            uint32_t error_limit; /* the range is between ${hold value - error_limit} and ${hold value + error_limit} */
            uint32_t hold_clock_cnt; /* the event will be triggered when match the hold value and error_limit and last for &{hold_clock_cnt} clocks */
        } hold_param;
        struct {
            uint32_t limit_value_h; /* the high 32bit of limit_value */
            uint32_t limit_value_l; /* the low 32bit of limit_value */
        } over_protect_param;
        struct {
            uint32_t clock_count; /* the event will be triggered when synt clock match the value */
        } time_param;
        uint32_t preset[4];
    } preset;
} mtg_event_param_t;
 
/*
 * @brief define the struct of the trajectory predictor limit
 */
typedef struct mtg_tra_limit_param {
    bool vel_step_limit_en; /* velocity step limit enable, when enable, the velocity variation per clock will be limited by vel_step_max and vel_step_min */
    uint32_t vel_step_max; /* velocity step limit value max */
    uint32_t vel_step_min;  /* velocity step limit value min */
    bool pos_step_limit_en; /* postion step limit enable, when enable, the postion variation per clock will be limited by pos_step_max and pos_step_min */
    uint32_t pos_step_max; /* postion step limit value max */
    uint32_t pos_step_min; /* postion step limit value min */
} mtg_tra_limit_param_t;
 
typedef enum mtg_software_force_one_way_mode {
    sw_force_negative = 0,
    sw_force_positive = 1,
} mtg_software_force_one_way_mode_t;
 
typedef enum vel_one_way_mode {
    bigger_or_eq_zero = 0,
    smaller_or_eq_zero = 1,
} vel_one_way_mode_t;
 
typedef struct mtg_hardware_force_one_way_mode {
    uint32_t vel_limit_p;
    uint32_t vel_limit_n;
} mtg_hardware_force_one_way_mode_t;
 
typedef enum mtg_filter_ff_mode {
    mtg_filter_ff_mode_from_register = 0,
    mtg_filter_ff_mode_from_input = 1,
} mtg_filter_ff_mode_t;
 
typedef enum mtg_filter_first_load_mode {
    mtg_filter_first_load_mode_without_acc = 0,
    mtg_filter_first_load_mode_include_acc = 1,
} mtg_filter_first_load_mode_t;
 
typedef enum mtg_filter_err_bypass_mode {
    mtg_filter_err_bypass_mode_hw = 0,
    mtg_filter_err_bypass_mode_sw = 1,
} mtg_filter_err_bypass_mode_t;
 
typedef struct mtg_filter_param {
    bool enable; /* filter enable */
    bool ff_en; /* filter feedforward enable */
    bool init_en; /* filter first value initialization enable */
    bool err_bypass_en; /* filter error bypass enable. when difference between filter input and output beyond the limit, filter output will be bypassed  */
    mtg_filter_err_bypass_mode_t err_bypass_mode;
    bool err_init; /* filter error reset enable. when difference between filter input and output beyond the limit, the filter will reset */
    bool timeout_en; /* filter timeout enable */
    bool err_bypass_i_f_en;
    bool err_bypass_f_i_en;
    bool multi_err_irq_en;
    bool acceleration_en; /* filter acceleration enable. when enable, the filter will output acceleration value */
    mtg_filter_ff_mode_t ff_mode;
    mtg_filter_first_load_mode_t first_load_mode;
    int32_t vel_init_value; /* the initial value of velocity. only used when init_en == true */
    int32_t acc_init_value; /* the initial value of acceleration. only used when init_en == true */
    uint32_t filter_time_constant_tp;
    uint32_t filter_time_constant_tz;
    uint32_t filter_time_constant_tz_1;
    uint32_t filter_gain;
    uint32_t filter_stage_shift[2];
    uint32_t filter_param_shift;
    uint32_t filter_time_shift;
    uint32_t filter_ff_shift;
 
} mtg_filter_param_t;
 
typedef enum mtg_time_input_source {
    mtg_time_input_from_filter = 1, /* the value in the filter will be used */
    mtg_time_input_from_input = 2, /* the value in the input will be used */
} mtg_time_input_source_t;
 
typedef struct mtg_time_init_param {
    bool enable;
    uint32_t adjust_value; /* time compensation clocks */
    uint8_t index;
    mtg_time_input_source_t source;
} mtg_time_init_param_t;
 
typedef struct mtg_timeout_param {
    bool enable;
    uint32_t timeout_clock_count;
} mtg_timeout_param_t;
 
typedef enum mtg_link_cfg {
    link_event0 = 0,
    link_event1 = 1,
    link_event2 = 2,
    link_event3 = 3,
    link_hw_trigger = 4,
    link_sw_trigger = 5,
    link_event_timeout = 6,
} mtg_link_cfg_t;
 
typedef enum {
    cmd_object_rev = 1 << 0,
    cmd_object_pos = 1 << 1,
    cmd_object_vel = 1 << 2,
    cmd_object_acc = 1 << 3,
    cmd_object_jer = 1 << 4,
} mtg_tra_cmd_object_t;
 
typedef enum {
    cmd_mode_new_value = 0, /* when cmd exec, the preset value will replace the old value */
    cmd_mode_old_delta = 1, /* when cmd exec, the preset value will be added to the old value */
} mtg_link_cmd_mode_t;
 
typedef struct mtg_tra_shift {
    uint8_t jerk_shift;
    uint8_t acc_shift;
    uint8_t vel_shift;
} mtg_tra_shift_t;
 
typedef struct mtg_tra_cmd_cfg {
    uint8_t index;
    uint32_t object; /* cmd object, see ${mtg_tra_cmd_object_t} */
    mtg_link_cmd_mode_t mode;
    uint32_t rev_preset;
    uint32_t pos_preset;
    uint32_t vel_preset;
    uint32_t acc_preset;
    uint32_t jer_preset;
} mtg_tra_cmd_cfg_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline uint32_t mtg_get_tra_control_status(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    return base->TRA[tra_index].CONTROL;
}
 
static inline uint32_t mtg_get_tra_cmd_control_status(MTGV2_Type *base, uint8_t tra_index, uint8_t cmd_index)
{
    assert((tra_index < 2) && (cmd_index < 4));
    return base->TRA[tra_index].CMD[cmd_index].CONTROL;
}
 
static inline void mtg_trig_tra_lock(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    base->TRA[tra_index].CONTROL |= MTGV2_TRA_CONTROL_SW_LOCK_SET(1);
}
 
static inline void mtg_clear_tra_lock(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    base->TRA[tra_index].CONTROL &= ~MTGV2_TRA_CONTROL_SW_LOCK_MASK;
}
 
static inline int32_t mtg_get_tra_rev_lock_value(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    return base->TRA[tra_index].LOCK_REV;
}
 
static inline uint32_t mtg_get_tra_pos_lock_value(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    return base->TRA[tra_index].LOCK_POS;
}
 
static inline int32_t mtg_get_tra_vel_lock_value(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    return base->TRA[tra_index].LOCK_VEL;
}
 
static inline int32_t mtg_get_tra_acc_lock_value(MTGV2_Type *base, uint8_t tra_index)
{
    assert(tra_index < 2);
    return base->TRA[tra_index].LOCK_ACC;
}
 
 
static inline void mtg_filter_enable_bypass(MTGV2_Type *base)
{
    base->FILTER_CONTROL |= MTGV2_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SET(1);
    base->FILTER_CONTROL |= MTGV2_FILTER_CONTROL_ERR_BYPASS_EN_SET(1);
}
 
static inline void mtg_filter_disable_bypass(MTGV2_Type *base)
{
    base->FILTER_CONTROL &= ~MTGV2_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK;
    base->FILTER_CONTROL &= ~MTGV2_FILTER_CONTROL_ERR_BYPASS_EN_MASK;
}
 
static inline void mtg_filter_switch_filter_result(MTGV2_Type *base)
{
    base->FILTER_CONTROL |= MTGV2_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SET(1);
}
 
static inline void mtg_filter_stop_auto_switch_filter_result(MTGV2_Type *base)
{
    base->FILTER_CONTROL &= ~MTGV2_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK;
}
 
static inline bool mtg_get_err_bypass_status(MTGV2_Type *base)
{
    return MTGV2_FILTER_CONTROL_ERR_BYPASS_STATUS_GET(base->FILTER_CONTROL) == 0 ? true : false;
}
 
static inline void mtg_set_time0_adjust_value(MTGV2_Type *base, uint32_t value)
{
    base->FILTER_TIME0_SW_ADJUST = value;
}
 
static inline void mtg_set_time1_adjust_value(MTGV2_Type *base, uint32_t value)
{
    base->FILTER_TIME1_SW_ADJUST = value;
}
 
static inline void mtg_tra_set_shift(MTGV2_Type *base, uint8_t index, uint8_t jer_shift, uint8_t acc_shift, uint8_t vel_shift)
{
    assert(index < 2);
    base->TRA[index].SHIFT = MTGV2_TRA_SHIFT_JER_SHIFT_SET(jer_shift) |
                             MTGV2_TRA_SHIFT_ACC_SHIFT_SET(acc_shift) |
                             MTGV2_TRA_SHIFT_VEL_SHIFT_SET(vel_shift);
}
 
static inline void mtg_set_global_reset(MTGV2_Type *base)
{
    base->SW_GLB_RESET = 1;
}
 
static inline void mtg_stop_global_reset(MTGV2_Type *base)
{
    base->SW_GLB_RESET = 0;
}
 
void mtg_get_tra_lock_result(MTGV2_Type *base, uint8_t tra_index, mtg_lock_value_t *para);
 
hpm_stat_t mtg_setup_event(MTGV2_Type *base, uint8_t event_index, mtg_event_param_t *param);
 
hpm_stat_t mtg_setup_tra_limit(MTGV2_Type *base, uint8_t tra_index, mtg_tra_limit_param_t *param);
 
void mtg_setup_tra_software_pos_one_way_mode(MTGV2_Type *base, uint8_t tra_index, mtg_software_force_one_way_mode_t param);
 
void mtg_setup_tra_hardware_pos_one_way_mode(MTGV2_Type *base, uint8_t tra_index, mtg_hardware_force_one_way_mode_t *param);
 
void mtg_disable_tra_pos_one_way_mode(MTGV2_Type *base, uint8_t tra_index);
 
void mtg_setup_tra_vel_one_way(MTGV2_Type *base, uint8_t tra_index, vel_one_way_mode_t mode, bool enable);
 
void mtg_filter_get_default_filter_stage_param(mtg_filter_param_t *param);
 
void mtg_setup_time(MTGV2_Type *base, mtg_time_init_param_t *param);
 
void mtg_setup_filter(MTGV2_Type *base, mtg_filter_param_t *param);
 
void mtg_setup_timeout(MTGV2_Type *base, mtg_timeout_param_t *param);
 
void mtg_setup_link_cfg(MTGV2_Type *base, uint8_t tra_index, mtg_link_cfg_t link_cfg, mtg_tra_cmd_cfg_t *cmd_cfg);
 
void mtg_soft_event_trigger(MTGV2_Type *base);
 
void mtg_get_default_tra_shift(mtg_tra_shift_t *cfg);
 
static inline uint32_t mtg_get_irq_status(MTGV2_Type *ptr)
{
    return ptr->IRQ_STATUS;
}
 
static inline void mtg_enable_irq(MTGV2_Type *ptr, mtg_irq_enable_t irq)
{
    ptr->IRQ_ENABLE |= MTGV2_IRQ_ENABLE_IRQ_ENABLE_SET(irq);
}
 
static inline void mtg_clear_irq_status(MTGV2_Type *ptr, uint32_t irq)
{
    ptr->IRQ_STATUS = irq;
}
 
int32_t mtg_calc_vel_preset(MTGV2_Type *base, clock_name_t clock, uint8_t tra_index, float speed);
 
int32_t mtg_calc_acc_preset(MTGV2_Type *base, clock_name_t clock, uint8_t tra_index, float acc);
 
int32_t mtg_calc_jer_preset(MTGV2_Type *base, clock_name_t clock, uint8_t tra_index, float jer);
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_MTGV2_DRV_H */