hpm_opamp_regs.h File Reference

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Data Structures
struct	OPAMP_Type

Macros
#define	OPAMP_CTRL0_EN_LV_MASK   (0x4000000UL)
#define	OPAMP_CTRL0_EN_LV_SHIFT   (26U)
#define	OPAMP_CTRL0_EN_LV_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_EN_LV_SHIFT) & OPAMP_CTRL0_EN_LV_MASK)
#define	OPAMP_CTRL0_EN_LV_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_EN_LV_MASK) >> OPAMP_CTRL0_EN_LV_SHIFT)
#define	OPAMP_CTRL0_VIM_SEL_MASK   (0x70000UL)
#define	OPAMP_CTRL0_VIM_SEL_SHIFT   (16U)
#define	OPAMP_CTRL0_VIM_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_VIM_SEL_SHIFT) & OPAMP_CTRL0_VIM_SEL_MASK)
#define	OPAMP_CTRL0_VIM_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_VIM_SEL_MASK) >> OPAMP_CTRL0_VIM_SEL_SHIFT)
#define	OPAMP_CTRL0_MODE_MASK   (0xF800U)
#define	OPAMP_CTRL0_MODE_SHIFT   (11U)
#define	OPAMP_CTRL0_MODE_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_MODE_SHIFT) & OPAMP_CTRL0_MODE_MASK)
#define	OPAMP_CTRL0_MODE_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_MODE_MASK) >> OPAMP_CTRL0_MODE_SHIFT)
#define	OPAMP_CTRL0_GAIN_SEL_MASK   (0x700U)
#define	OPAMP_CTRL0_GAIN_SEL_SHIFT   (8U)
#define	OPAMP_CTRL0_GAIN_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_GAIN_SEL_SHIFT) & OPAMP_CTRL0_GAIN_SEL_MASK)
#define	OPAMP_CTRL0_GAIN_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_GAIN_SEL_MASK) >> OPAMP_CTRL0_GAIN_SEL_SHIFT)
#define	OPAMP_CTRL0_DISABLE_PM_CAP_MASK   (0x80U)
#define	OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT   (7U)
#define	OPAMP_CTRL0_DISABLE_PM_CAP_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK)
#define	OPAMP_CTRL0_DISABLE_PM_CAP_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) >> OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT)
#define	OPAMP_CTRL0_MILLER_SEL_MASK   (0x70U)
#define	OPAMP_CTRL0_MILLER_SEL_SHIFT   (4U)
#define	OPAMP_CTRL0_MILLER_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_MILLER_SEL_SHIFT) & OPAMP_CTRL0_MILLER_SEL_MASK)
#define	OPAMP_CTRL0_MILLER_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_MILLER_SEL_MASK) >> OPAMP_CTRL0_MILLER_SEL_SHIFT)
#define	OPAMP_CTRL0_VBYPASS_MASK   (0x8U)
#define	OPAMP_CTRL0_VBYPASS_SHIFT   (3U)
#define	OPAMP_CTRL0_VBYPASS_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_VBYPASS_SHIFT) & OPAMP_CTRL0_VBYPASS_MASK)
#define	OPAMP_CTRL0_VBYPASS_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_VBYPASS_MASK) >> OPAMP_CTRL0_VBYPASS_SHIFT)
#define	OPAMP_CTRL0_VIP_SEL_MASK   (0x7U)
#define	OPAMP_CTRL0_VIP_SEL_SHIFT   (0U)
#define	OPAMP_CTRL0_VIP_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CTRL0_VIP_SEL_SHIFT) & OPAMP_CTRL0_VIP_SEL_MASK)
#define	OPAMP_CTRL0_VIP_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CTRL0_VIP_SEL_MASK) >> OPAMP_CTRL0_VIP_SEL_SHIFT)
#define	OPAMP_STATUS_TRIG_CONFLICT_MASK   (0xFF00000UL)
#define	OPAMP_STATUS_TRIG_CONFLICT_SHIFT   (20U)
#define	OPAMP_STATUS_TRIG_CONFLICT_SET(x)   (((uint32_t)(x) << OPAMP_STATUS_TRIG_CONFLICT_SHIFT) & OPAMP_STATUS_TRIG_CONFLICT_MASK)
#define	OPAMP_STATUS_TRIG_CONFLICT_GET(x)   (((uint32_t)(x) & OPAMP_STATUS_TRIG_CONFLICT_MASK) >> OPAMP_STATUS_TRIG_CONFLICT_SHIFT)
#define	OPAMP_STATUS_PRESET_ACT_MASK   (0x80000UL)
#define	OPAMP_STATUS_PRESET_ACT_SHIFT   (19U)
#define	OPAMP_STATUS_PRESET_ACT_GET(x)   (((uint32_t)(x) & OPAMP_STATUS_PRESET_ACT_MASK) >> OPAMP_STATUS_PRESET_ACT_SHIFT)
#define	OPAMP_STATUS_CUR_PRESET_MASK   (0x70000UL)
#define	OPAMP_STATUS_CUR_PRESET_SHIFT   (16U)
#define	OPAMP_STATUS_CUR_PRESET_GET(x)   (((uint32_t)(x) & OPAMP_STATUS_CUR_PRESET_MASK) >> OPAMP_STATUS_CUR_PRESET_SHIFT)
#define	OPAMP_CTRL1_SW_PRESET_MASK   (0x80000000UL)
#define	OPAMP_CTRL1_SW_PRESET_SHIFT   (31U)
#define	OPAMP_CTRL1_SW_PRESET_SET(x)   (((uint32_t)(x) << OPAMP_CTRL1_SW_PRESET_SHIFT) & OPAMP_CTRL1_SW_PRESET_MASK)
#define	OPAMP_CTRL1_SW_PRESET_GET(x)   (((uint32_t)(x) & OPAMP_CTRL1_SW_PRESET_MASK) >> OPAMP_CTRL1_SW_PRESET_SHIFT)
#define	OPAMP_CTRL1_SW_SEL_MASK   (0x7U)
#define	OPAMP_CTRL1_SW_SEL_SHIFT   (0U)
#define	OPAMP_CTRL1_SW_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CTRL1_SW_SEL_SHIFT) & OPAMP_CTRL1_SW_SEL_MASK)
#define	OPAMP_CTRL1_SW_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CTRL1_SW_SEL_MASK) >> OPAMP_CTRL1_SW_SEL_SHIFT)
#define	OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK   (0x8000000UL)
#define	OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT   (27U)
#define	OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK)
#define	OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) >> OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT)
#define	OPAMP_CFG_CFG0_MILLER_SEL_MASK   (0x7000000UL)
#define	OPAMP_CFG_CFG0_MILLER_SEL_SHIFT   (24U)
#define	OPAMP_CFG_CFG0_MILLER_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) & OPAMP_CFG_CFG0_MILLER_SEL_MASK)
#define	OPAMP_CFG_CFG0_MILLER_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) >> OPAMP_CFG_CFG0_MILLER_SEL_SHIFT)
#define	OPAMP_CFG_CFG0_VIM_SEL_MASK   (0x700U)
#define	OPAMP_CFG_CFG0_VIM_SEL_SHIFT   (8U)
#define	OPAMP_CFG_CFG0_VIM_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG0_VIM_SEL_SHIFT) & OPAMP_CFG_CFG0_VIM_SEL_MASK)
#define	OPAMP_CFG_CFG0_VIM_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG0_VIM_SEL_MASK) >> OPAMP_CFG_CFG0_VIM_SEL_SHIFT)
#define	OPAMP_CFG_CFG0_VIP_SEL_MASK   (0x7U)
#define	OPAMP_CFG_CFG0_VIP_SEL_SHIFT   (0U)
#define	OPAMP_CFG_CFG0_VIP_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG0_VIP_SEL_SHIFT) & OPAMP_CFG_CFG0_VIP_SEL_MASK)
#define	OPAMP_CFG_CFG0_VIP_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG0_VIP_SEL_MASK) >> OPAMP_CFG_CFG0_VIP_SEL_SHIFT)
#define	OPAMP_CFG_CFG1_HW_TRIG_EN_MASK   (0x80000000UL)
#define	OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT   (31U)
#define	OPAMP_CFG_CFG1_HW_TRIG_EN_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK)
#define	OPAMP_CFG_CFG1_HW_TRIG_EN_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) >> OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT)
#define	OPAMP_CFG_CFG1_EN_LV_MASK   (0x40000000UL)
#define	OPAMP_CFG_CFG1_EN_LV_SHIFT   (30U)
#define	OPAMP_CFG_CFG1_EN_LV_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG1_EN_LV_SHIFT) & OPAMP_CFG_CFG1_EN_LV_MASK)
#define	OPAMP_CFG_CFG1_EN_LV_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG1_EN_LV_MASK) >> OPAMP_CFG_CFG1_EN_LV_SHIFT)
#define	OPAMP_CFG_CFG1_VBYPASS_LV_MASK   (0x20000000UL)
#define	OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT   (29U)
#define	OPAMP_CFG_CFG1_VBYPASS_LV_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK)
#define	OPAMP_CFG_CFG1_VBYPASS_LV_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) >> OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT)
#define	OPAMP_CFG_CFG1_MODE_MASK   (0xF8U)
#define	OPAMP_CFG_CFG1_MODE_SHIFT   (3U)
#define	OPAMP_CFG_CFG1_MODE_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG1_MODE_SHIFT) & OPAMP_CFG_CFG1_MODE_MASK)
#define	OPAMP_CFG_CFG1_MODE_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG1_MODE_MASK) >> OPAMP_CFG_CFG1_MODE_SHIFT)
#define	OPAMP_CFG_CFG1_GAIN_SEL_MASK   (0x7U)
#define	OPAMP_CFG_CFG1_GAIN_SEL_SHIFT   (0U)
#define	OPAMP_CFG_CFG1_GAIN_SEL_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) & OPAMP_CFG_CFG1_GAIN_SEL_MASK)
#define	OPAMP_CFG_CFG1_GAIN_SEL_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) >> OPAMP_CFG_CFG1_GAIN_SEL_SHIFT)
#define	OPAMP_CFG_CFG2_CHANNEL_MASK   (0x7000000UL)
#define	OPAMP_CFG_CFG2_CHANNEL_SHIFT   (24U)
#define	OPAMP_CFG_CFG2_CHANNEL_SET(x)   (((uint32_t)(x) << OPAMP_CFG_CFG2_CHANNEL_SHIFT) & OPAMP_CFG_CFG2_CHANNEL_MASK)
#define	OPAMP_CFG_CFG2_CHANNEL_GET(x)   (((uint32_t)(x) & OPAMP_CFG_CFG2_CHANNEL_MASK) >> OPAMP_CFG_CFG2_CHANNEL_SHIFT)
#define	OPAMP_CFG_PRESET0   (0UL)
#define	OPAMP_CFG_PRESET1   (1UL)
#define	OPAMP_CFG_PRESET2   (2UL)
#define	OPAMP_CFG_PRESET3   (4UL)
#define	OPAMP_CFG_PRESET4   (5UL)
#define	OPAMP_CFG_PRESET5   (6UL)
#define	OPAMP_CFG_PRESET6   (8UL)
#define	OPAMP_CFG_PRESET7   (9UL)

Macro Definition Documentation

OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET

#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) >> OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT)

OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK

#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK   (0x8000000UL)

OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET

#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK)

OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT

#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT   (27U)

OPAMP_CFG_CFG0_MILLER_SEL_GET

#define OPAMP_CFG_CFG0_MILLER_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) >> OPAMP_CFG_CFG0_MILLER_SEL_SHIFT)

OPAMP_CFG_CFG0_MILLER_SEL_MASK

#define OPAMP_CFG_CFG0_MILLER_SEL_MASK   (0x7000000UL)

OPAMP_CFG_CFG0_MILLER_SEL_SET

#define OPAMP_CFG_CFG0_MILLER_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) & OPAMP_CFG_CFG0_MILLER_SEL_MASK)

OPAMP_CFG_CFG0_MILLER_SEL_SHIFT

#define OPAMP_CFG_CFG0_MILLER_SEL_SHIFT   (24U)

OPAMP_CFG_CFG0_VIM_SEL_GET

#define OPAMP_CFG_CFG0_VIM_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG0_VIM_SEL_MASK) >> OPAMP_CFG_CFG0_VIM_SEL_SHIFT)

OPAMP_CFG_CFG0_VIM_SEL_MASK

#define OPAMP_CFG_CFG0_VIM_SEL_MASK   (0x700U)

OPAMP_CFG_CFG0_VIM_SEL_SET

#define OPAMP_CFG_CFG0_VIM_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG0_VIM_SEL_SHIFT) & OPAMP_CFG_CFG0_VIM_SEL_MASK)

OPAMP_CFG_CFG0_VIM_SEL_SHIFT

#define OPAMP_CFG_CFG0_VIM_SEL_SHIFT   (8U)

OPAMP_CFG_CFG0_VIP_SEL_GET

#define OPAMP_CFG_CFG0_VIP_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG0_VIP_SEL_MASK) >> OPAMP_CFG_CFG0_VIP_SEL_SHIFT)

OPAMP_CFG_CFG0_VIP_SEL_MASK

#define OPAMP_CFG_CFG0_VIP_SEL_MASK   (0x7U)

OPAMP_CFG_CFG0_VIP_SEL_SET

#define OPAMP_CFG_CFG0_VIP_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG0_VIP_SEL_SHIFT) & OPAMP_CFG_CFG0_VIP_SEL_MASK)

OPAMP_CFG_CFG0_VIP_SEL_SHIFT

#define OPAMP_CFG_CFG0_VIP_SEL_SHIFT   (0U)

OPAMP_CFG_CFG1_EN_LV_GET

#define OPAMP_CFG_CFG1_EN_LV_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG1_EN_LV_MASK) >> OPAMP_CFG_CFG1_EN_LV_SHIFT)

OPAMP_CFG_CFG1_EN_LV_MASK

#define OPAMP_CFG_CFG1_EN_LV_MASK   (0x40000000UL)

OPAMP_CFG_CFG1_EN_LV_SET

#define OPAMP_CFG_CFG1_EN_LV_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG1_EN_LV_SHIFT) & OPAMP_CFG_CFG1_EN_LV_MASK)

OPAMP_CFG_CFG1_EN_LV_SHIFT

#define OPAMP_CFG_CFG1_EN_LV_SHIFT   (30U)

OPAMP_CFG_CFG1_GAIN_SEL_GET

#define OPAMP_CFG_CFG1_GAIN_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) >> OPAMP_CFG_CFG1_GAIN_SEL_SHIFT)

OPAMP_CFG_CFG1_GAIN_SEL_MASK

#define OPAMP_CFG_CFG1_GAIN_SEL_MASK   (0x7U)

OPAMP_CFG_CFG1_GAIN_SEL_SET

#define OPAMP_CFG_CFG1_GAIN_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) & OPAMP_CFG_CFG1_GAIN_SEL_MASK)

OPAMP_CFG_CFG1_GAIN_SEL_SHIFT

#define OPAMP_CFG_CFG1_GAIN_SEL_SHIFT   (0U)

OPAMP_CFG_CFG1_HW_TRIG_EN_GET

#define OPAMP_CFG_CFG1_HW_TRIG_EN_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) >> OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT)

OPAMP_CFG_CFG1_HW_TRIG_EN_MASK

#define OPAMP_CFG_CFG1_HW_TRIG_EN_MASK   (0x80000000UL)

OPAMP_CFG_CFG1_HW_TRIG_EN_SET

#define OPAMP_CFG_CFG1_HW_TRIG_EN_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK)

OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT

#define OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT   (31U)

OPAMP_CFG_CFG1_MODE_GET

#define OPAMP_CFG_CFG1_MODE_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG1_MODE_MASK) >> OPAMP_CFG_CFG1_MODE_SHIFT)

OPAMP_CFG_CFG1_MODE_MASK

#define OPAMP_CFG_CFG1_MODE_MASK   (0xF8U)

OPAMP_CFG_CFG1_MODE_SET

#define OPAMP_CFG_CFG1_MODE_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG1_MODE_SHIFT) & OPAMP_CFG_CFG1_MODE_MASK)

OPAMP_CFG_CFG1_MODE_SHIFT

#define OPAMP_CFG_CFG1_MODE_SHIFT   (3U)

OPAMP_CFG_CFG1_VBYPASS_LV_GET

#define OPAMP_CFG_CFG1_VBYPASS_LV_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) >> OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT)

OPAMP_CFG_CFG1_VBYPASS_LV_MASK

#define OPAMP_CFG_CFG1_VBYPASS_LV_MASK   (0x20000000UL)

OPAMP_CFG_CFG1_VBYPASS_LV_SET

#define OPAMP_CFG_CFG1_VBYPASS_LV_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK)

OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT

#define OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT   (29U)

OPAMP_CFG_CFG2_CHANNEL_GET

#define OPAMP_CFG_CFG2_CHANNEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CFG_CFG2_CHANNEL_MASK) >> OPAMP_CFG_CFG2_CHANNEL_SHIFT)

OPAMP_CFG_CFG2_CHANNEL_MASK

#define OPAMP_CFG_CFG2_CHANNEL_MASK   (0x7000000UL)

OPAMP_CFG_CFG2_CHANNEL_SET

#define OPAMP_CFG_CFG2_CHANNEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CFG_CFG2_CHANNEL_SHIFT) & OPAMP_CFG_CFG2_CHANNEL_MASK)

OPAMP_CFG_CFG2_CHANNEL_SHIFT

#define OPAMP_CFG_CFG2_CHANNEL_SHIFT   (24U)

OPAMP_CFG_PRESET0

#define OPAMP_CFG_PRESET0   (0UL)

OPAMP_CFG_PRESET1

#define OPAMP_CFG_PRESET1   (1UL)

OPAMP_CFG_PRESET2

#define OPAMP_CFG_PRESET2   (2UL)

OPAMP_CFG_PRESET3

#define OPAMP_CFG_PRESET3   (4UL)

OPAMP_CFG_PRESET4

#define OPAMP_CFG_PRESET4   (5UL)

OPAMP_CFG_PRESET5

#define OPAMP_CFG_PRESET5   (6UL)

OPAMP_CFG_PRESET6

#define OPAMP_CFG_PRESET6   (8UL)

OPAMP_CFG_PRESET7

#define OPAMP_CFG_PRESET7   (9UL)

OPAMP_CTRL0_DISABLE_PM_CAP_GET

#define OPAMP_CTRL0_DISABLE_PM_CAP_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) >> OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT)

OPAMP_CTRL0_DISABLE_PM_CAP_MASK

#define OPAMP_CTRL0_DISABLE_PM_CAP_MASK   (0x80U)

OPAMP_CTRL0_DISABLE_PM_CAP_SET

#define OPAMP_CTRL0_DISABLE_PM_CAP_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK)

OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT

#define OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT   (7U)

OPAMP_CTRL0_EN_LV_GET

#define OPAMP_CTRL0_EN_LV_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_EN_LV_MASK) >> OPAMP_CTRL0_EN_LV_SHIFT)

OPAMP_CTRL0_EN_LV_MASK

#define OPAMP_CTRL0_EN_LV_MASK   (0x4000000UL)

OPAMP_CTRL0_EN_LV_SET

#define OPAMP_CTRL0_EN_LV_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_EN_LV_SHIFT) & OPAMP_CTRL0_EN_LV_MASK)

OPAMP_CTRL0_EN_LV_SHIFT

#define OPAMP_CTRL0_EN_LV_SHIFT   (26U)

OPAMP_CTRL0_GAIN_SEL_GET

#define OPAMP_CTRL0_GAIN_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_GAIN_SEL_MASK) >> OPAMP_CTRL0_GAIN_SEL_SHIFT)

OPAMP_CTRL0_GAIN_SEL_MASK

#define OPAMP_CTRL0_GAIN_SEL_MASK   (0x700U)

OPAMP_CTRL0_GAIN_SEL_SET

#define OPAMP_CTRL0_GAIN_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_GAIN_SEL_SHIFT) & OPAMP_CTRL0_GAIN_SEL_MASK)

OPAMP_CTRL0_GAIN_SEL_SHIFT

#define OPAMP_CTRL0_GAIN_SEL_SHIFT   (8U)

OPAMP_CTRL0_MILLER_SEL_GET

#define OPAMP_CTRL0_MILLER_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_MILLER_SEL_MASK) >> OPAMP_CTRL0_MILLER_SEL_SHIFT)

OPAMP_CTRL0_MILLER_SEL_MASK

#define OPAMP_CTRL0_MILLER_SEL_MASK   (0x70U)

OPAMP_CTRL0_MILLER_SEL_SET

#define OPAMP_CTRL0_MILLER_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_MILLER_SEL_SHIFT) & OPAMP_CTRL0_MILLER_SEL_MASK)

OPAMP_CTRL0_MILLER_SEL_SHIFT

#define OPAMP_CTRL0_MILLER_SEL_SHIFT   (4U)

OPAMP_CTRL0_MODE_GET

#define OPAMP_CTRL0_MODE_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_MODE_MASK) >> OPAMP_CTRL0_MODE_SHIFT)

OPAMP_CTRL0_MODE_MASK

#define OPAMP_CTRL0_MODE_MASK   (0xF800U)

OPAMP_CTRL0_MODE_SET

#define OPAMP_CTRL0_MODE_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_MODE_SHIFT) & OPAMP_CTRL0_MODE_MASK)

OPAMP_CTRL0_MODE_SHIFT

#define OPAMP_CTRL0_MODE_SHIFT   (11U)

OPAMP_CTRL0_VBYPASS_GET

#define OPAMP_CTRL0_VBYPASS_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_VBYPASS_MASK) >> OPAMP_CTRL0_VBYPASS_SHIFT)

OPAMP_CTRL0_VBYPASS_MASK

#define OPAMP_CTRL0_VBYPASS_MASK   (0x8U)

OPAMP_CTRL0_VBYPASS_SET

#define OPAMP_CTRL0_VBYPASS_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_VBYPASS_SHIFT) & OPAMP_CTRL0_VBYPASS_MASK)

OPAMP_CTRL0_VBYPASS_SHIFT

#define OPAMP_CTRL0_VBYPASS_SHIFT   (3U)

OPAMP_CTRL0_VIM_SEL_GET

#define OPAMP_CTRL0_VIM_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_VIM_SEL_MASK) >> OPAMP_CTRL0_VIM_SEL_SHIFT)

OPAMP_CTRL0_VIM_SEL_MASK

#define OPAMP_CTRL0_VIM_SEL_MASK   (0x70000UL)

OPAMP_CTRL0_VIM_SEL_SET

#define OPAMP_CTRL0_VIM_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_VIM_SEL_SHIFT) & OPAMP_CTRL0_VIM_SEL_MASK)

OPAMP_CTRL0_VIM_SEL_SHIFT

#define OPAMP_CTRL0_VIM_SEL_SHIFT   (16U)

OPAMP_CTRL0_VIP_SEL_GET

#define OPAMP_CTRL0_VIP_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL0_VIP_SEL_MASK) >> OPAMP_CTRL0_VIP_SEL_SHIFT)

OPAMP_CTRL0_VIP_SEL_MASK

#define OPAMP_CTRL0_VIP_SEL_MASK   (0x7U)

OPAMP_CTRL0_VIP_SEL_SET

#define OPAMP_CTRL0_VIP_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL0_VIP_SEL_SHIFT) & OPAMP_CTRL0_VIP_SEL_MASK)

OPAMP_CTRL0_VIP_SEL_SHIFT

#define OPAMP_CTRL0_VIP_SEL_SHIFT   (0U)

OPAMP_CTRL1_SW_PRESET_GET

#define OPAMP_CTRL1_SW_PRESET_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL1_SW_PRESET_MASK) >> OPAMP_CTRL1_SW_PRESET_SHIFT)

OPAMP_CTRL1_SW_PRESET_MASK

#define OPAMP_CTRL1_SW_PRESET_MASK   (0x80000000UL)

OPAMP_CTRL1_SW_PRESET_SET

#define OPAMP_CTRL1_SW_PRESET_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL1_SW_PRESET_SHIFT) & OPAMP_CTRL1_SW_PRESET_MASK)

OPAMP_CTRL1_SW_PRESET_SHIFT

#define OPAMP_CTRL1_SW_PRESET_SHIFT   (31U)

OPAMP_CTRL1_SW_SEL_GET

#define OPAMP_CTRL1_SW_SEL_GET

(

x

)

(((uint32_t)(x) & OPAMP_CTRL1_SW_SEL_MASK) >> OPAMP_CTRL1_SW_SEL_SHIFT)

OPAMP_CTRL1_SW_SEL_MASK

#define OPAMP_CTRL1_SW_SEL_MASK   (0x7U)

OPAMP_CTRL1_SW_SEL_SET

#define OPAMP_CTRL1_SW_SEL_SET

(

x

)

(((uint32_t)(x) << OPAMP_CTRL1_SW_SEL_SHIFT) & OPAMP_CTRL1_SW_SEL_MASK)

OPAMP_CTRL1_SW_SEL_SHIFT

#define OPAMP_CTRL1_SW_SEL_SHIFT   (0U)

OPAMP_STATUS_CUR_PRESET_GET

#define OPAMP_STATUS_CUR_PRESET_GET

(

x

)

(((uint32_t)(x) & OPAMP_STATUS_CUR_PRESET_MASK) >> OPAMP_STATUS_CUR_PRESET_SHIFT)

OPAMP_STATUS_CUR_PRESET_MASK

#define OPAMP_STATUS_CUR_PRESET_MASK   (0x70000UL)

OPAMP_STATUS_CUR_PRESET_SHIFT

#define OPAMP_STATUS_CUR_PRESET_SHIFT   (16U)

OPAMP_STATUS_PRESET_ACT_GET

#define OPAMP_STATUS_PRESET_ACT_GET

(

x

)

(((uint32_t)(x) & OPAMP_STATUS_PRESET_ACT_MASK) >> OPAMP_STATUS_PRESET_ACT_SHIFT)

OPAMP_STATUS_PRESET_ACT_MASK

#define OPAMP_STATUS_PRESET_ACT_MASK   (0x80000UL)

OPAMP_STATUS_PRESET_ACT_SHIFT

#define OPAMP_STATUS_PRESET_ACT_SHIFT   (19U)

OPAMP_STATUS_TRIG_CONFLICT_GET

#define OPAMP_STATUS_TRIG_CONFLICT_GET

(

x

)

(((uint32_t)(x) & OPAMP_STATUS_TRIG_CONFLICT_MASK) >> OPAMP_STATUS_TRIG_CONFLICT_SHIFT)

OPAMP_STATUS_TRIG_CONFLICT_MASK

#define OPAMP_STATUS_TRIG_CONFLICT_MASK   (0xFF00000UL)

OPAMP_STATUS_TRIG_CONFLICT_SET

#define OPAMP_STATUS_TRIG_CONFLICT_SET

(

x

)

(((uint32_t)(x) << OPAMP_STATUS_TRIG_CONFLICT_SHIFT) & OPAMP_STATUS_TRIG_CONFLICT_MASK)

OPAMP_STATUS_TRIG_CONFLICT_SHIFT

#define OPAMP_STATUS_TRIG_CONFLICT_SHIFT   (20U)