Data Structures
struct	PIXELMUX_Type

Macros
#define	PIXELMUX_PIXMUX_RGB_EN_MASK (0x20000000UL)

#define	PIXELMUX_PIXMUX_RGB_EN_SHIFT (29U)

#define	PIXELMUX_PIXMUX_RGB_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_EN_SHIFT) & PIXELMUX_PIXMUX_RGB_EN_MASK)

#define	PIXELMUX_PIXMUX_RGB_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_EN_MASK) >> PIXELMUX_PIXMUX_RGB_EN_SHIFT)

#define	PIXELMUX_PIXMUX_RGB_SEL_MASK (0x10000000UL)

#define	PIXELMUX_PIXMUX_RGB_SEL_SHIFT (28U)

#define	PIXELMUX_PIXMUX_RGB_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_SEL_SHIFT) & PIXELMUX_PIXMUX_RGB_SEL_MASK)

#define	PIXELMUX_PIXMUX_RGB_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_SEL_MASK) >> PIXELMUX_PIXMUX_RGB_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_GWC1_EN_MASK (0x8000000UL)

#define	PIXELMUX_PIXMUX_GWC1_EN_SHIFT (27U)

#define	PIXELMUX_PIXMUX_GWC1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_EN_SHIFT) & PIXELMUX_PIXMUX_GWC1_EN_MASK)

#define	PIXELMUX_PIXMUX_GWC1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_EN_MASK) >> PIXELMUX_PIXMUX_GWC1_EN_SHIFT)

#define	PIXELMUX_PIXMUX_GWC1_SEL_MASK (0x4000000UL)

#define	PIXELMUX_PIXMUX_GWC1_SEL_SHIFT (26U)

#define	PIXELMUX_PIXMUX_GWC1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC1_SEL_MASK)

#define	PIXELMUX_PIXMUX_GWC1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) >> PIXELMUX_PIXMUX_GWC1_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_GWC0_EN_MASK (0x2000000UL)

#define	PIXELMUX_PIXMUX_GWC0_EN_SHIFT (25U)

#define	PIXELMUX_PIXMUX_GWC0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_EN_SHIFT) & PIXELMUX_PIXMUX_GWC0_EN_MASK)

#define	PIXELMUX_PIXMUX_GWC0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_EN_MASK) >> PIXELMUX_PIXMUX_GWC0_EN_SHIFT)

#define	PIXELMUX_PIXMUX_GWC0_SEL_MASK (0x1000000UL)

#define	PIXELMUX_PIXMUX_GWC0_SEL_SHIFT (24U)

#define	PIXELMUX_PIXMUX_GWC0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC0_SEL_MASK)

#define	PIXELMUX_PIXMUX_GWC0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) >> PIXELMUX_PIXMUX_GWC0_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_LVB_DI1_EN_MASK (0x800000UL)

#define	PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT (23U)

#define	PIXELMUX_PIXMUX_LVB_DI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK)

#define	PIXELMUX_PIXMUX_LVB_DI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT)

#define	PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK (0x400000UL)

#define	PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT (22U)

#define	PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK)

#define	PIXELMUX_PIXMUX_LVB_DI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_LVB_DI0_EN_MASK (0x200000UL)

#define	PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT (21U)

#define	PIXELMUX_PIXMUX_LVB_DI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK)

#define	PIXELMUX_PIXMUX_LVB_DI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT)

#define	PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK (0x100000UL)

#define	PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT (20U)

#define	PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK)

#define	PIXELMUX_PIXMUX_LVB_DI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_DSI1_EN_MASK (0x80000UL)

#define	PIXELMUX_PIXMUX_DSI1_EN_SHIFT (19U)

#define	PIXELMUX_PIXMUX_DSI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_EN_SHIFT) & PIXELMUX_PIXMUX_DSI1_EN_MASK)

#define	PIXELMUX_PIXMUX_DSI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_EN_MASK) >> PIXELMUX_PIXMUX_DSI1_EN_SHIFT)

#define	PIXELMUX_PIXMUX_DSI1_SEL_MASK (0x40000UL)

#define	PIXELMUX_PIXMUX_DSI1_SEL_SHIFT (18U)

#define	PIXELMUX_PIXMUX_DSI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI1_SEL_MASK)

#define	PIXELMUX_PIXMUX_DSI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) >> PIXELMUX_PIXMUX_DSI1_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_DSI0_EN_MASK (0x20000UL)

#define	PIXELMUX_PIXMUX_DSI0_EN_SHIFT (17U)

#define	PIXELMUX_PIXMUX_DSI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_EN_SHIFT) & PIXELMUX_PIXMUX_DSI0_EN_MASK)

#define	PIXELMUX_PIXMUX_DSI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_EN_MASK) >> PIXELMUX_PIXMUX_DSI0_EN_SHIFT)

#define	PIXELMUX_PIXMUX_DSI0_SEL_MASK (0x10000UL)

#define	PIXELMUX_PIXMUX_DSI0_SEL_SHIFT (16U)

#define	PIXELMUX_PIXMUX_DSI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI0_SEL_MASK)

#define	PIXELMUX_PIXMUX_DSI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) >> PIXELMUX_PIXMUX_DSI0_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_CAM1_EN_MASK (0x80U)

#define	PIXELMUX_PIXMUX_CAM1_EN_SHIFT (7U)

#define	PIXELMUX_PIXMUX_CAM1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_EN_SHIFT) & PIXELMUX_PIXMUX_CAM1_EN_MASK)

#define	PIXELMUX_PIXMUX_CAM1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_EN_MASK) >> PIXELMUX_PIXMUX_CAM1_EN_SHIFT)

#define	PIXELMUX_PIXMUX_CAM1_SEL_MASK (0x70U)

#define	PIXELMUX_PIXMUX_CAM1_SEL_SHIFT (4U)

#define	PIXELMUX_PIXMUX_CAM1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM1_SEL_MASK)

#define	PIXELMUX_PIXMUX_CAM1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) >> PIXELMUX_PIXMUX_CAM1_SEL_SHIFT)

#define	PIXELMUX_PIXMUX_CAM0_EN_MASK (0x8U)

#define	PIXELMUX_PIXMUX_CAM0_EN_SHIFT (3U)

#define	PIXELMUX_PIXMUX_CAM0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_EN_SHIFT) & PIXELMUX_PIXMUX_CAM0_EN_MASK)

#define	PIXELMUX_PIXMUX_CAM0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_EN_MASK) >> PIXELMUX_PIXMUX_CAM0_EN_SHIFT)

#define	PIXELMUX_PIXMUX_CAM0_SEL_MASK (0x7U)

#define	PIXELMUX_PIXMUX_CAM0_SEL_SHIFT (0U)

#define	PIXELMUX_PIXMUX_CAM0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM0_SEL_MASK)

#define	PIXELMUX_PIXMUX_CAM0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) >> PIXELMUX_PIXMUX_CAM0_SEL_SHIFT)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK (0xFFFF0000UL)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT (16U)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK (0xFU)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT (0U)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK)

#define	PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT)

#define	PIXELMUX_MISC_LVB_DI1_CTL_MASK (0x2U)

#define	PIXELMUX_MISC_LVB_DI1_CTL_SHIFT (1U)

#define	PIXELMUX_MISC_LVB_DI1_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI1_CTL_MASK)

#define	PIXELMUX_MISC_LVB_DI1_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) >> PIXELMUX_MISC_LVB_DI1_CTL_SHIFT)

#define	PIXELMUX_MISC_LVB_DI0_CTL_MASK (0x1U)

#define	PIXELMUX_MISC_LVB_DI0_CTL_SHIFT (0U)

#define	PIXELMUX_MISC_LVB_DI0_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI0_CTL_MASK)

#define	PIXELMUX_MISC_LVB_DI0_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) >> PIXELMUX_MISC_LVB_DI0_CTL_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK (0x7C00000UL)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT (22U)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK (0x200000UL)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT (21U)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK (0x100000UL)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK (0x7C000UL)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT (14U)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK (0x2000U)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT (13U)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK (0x1000U)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT (12U)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK (0x200U)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT (9U)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK (0x100U)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT (8U)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK (0x80U)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT (7U)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK (0x40U)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT (6U)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK (0x20U)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT (5U)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK (0x10U)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT (4U)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK (0x8U)

#define	PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT (3U)

#define	PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT)

#define	PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK (0x4U)

#define	PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT (2U)

#define	PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK)

#define	PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK (0x2U)

#define	PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT (1U)

#define	PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT)

#define	PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK (0x1U)

#define	PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK)

#define	PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT)

#define	PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK (0xF000000UL)

#define	PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT (24U)

#define	PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK (0xF00000UL)

#define	PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK (0xF0000UL)

#define	PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT (16U)

#define	PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK (0xF000U)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT (12U)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK (0xF00U)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT (8U)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK (0xF0U)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT (4U)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK (0xFU)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK (0x20000000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT (29U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK (0x18000000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT (27U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK (0x6000000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT (25U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK (0xF00000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK (0x80000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT (19U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK (0x40000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT (18U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK (0x20000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT (17U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK (0x10000UL)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT (16U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK)

#define	PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT)

#define	PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK (0xFFFFFFFFUL)

#define	PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK (0x80000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT (31U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK (0x40000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT (30U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK (0x20000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT (29U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK (0x10000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT (28U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK (0x8000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT (27U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK (0x4000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT (26U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK (0x2000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT (25U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK (0x1000000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT (24U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK (0x800000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT (23U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK (0x400000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT (22U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK (0x300000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK (0xC0000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT (18U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK (0x30000UL)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT (16U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK (0xC000U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT (14U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK (0x3000U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT (12U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK (0x800U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT (11U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK (0x400U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT (10U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK (0x1FFU)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK)

#define	PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK (0x20000000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT (29U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK (0x18000000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT (27U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK (0x6000000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT (25U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK (0xF00000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT (19U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK (0x40000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT (18U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK (0x20000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT (17U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK (0x10000UL)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT (16U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK (0x7FFFU)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK)

#define	PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT)

#define	PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK (0xFFFFFFFFUL)

#define	PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK)

#define	PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK (0x80000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT (31U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK (0x40000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT (30U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK (0x20000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT (29U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK (0x10000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT (28U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK (0x8000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT (27U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK (0x4000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT (26U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK (0x2000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT (25U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK (0x1000000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT (24U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK (0x800000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT (23U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK (0x400000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT (22U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK (0x300000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK (0xC0000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT (18U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK (0x30000UL)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT (16U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK (0xC000U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT (14U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK (0x3000U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT (12U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK (0x800U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT (11U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK (0x400U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT (10U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK (0x1FFU)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK)

#define	PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK (0x80000000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT (31U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK (0x40000000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT (30U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK (0x30000000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT (28U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK (0xF000000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT (24U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK (0x400000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT (22U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK (0x200000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT (21U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK (0x100000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK (0x80000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT (19U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK (0x40000UL)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT (18U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK (0x3U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK)

#define	PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK (0x80000000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT (31U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK (0x40000000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT (30U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK (0x30000000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT (28U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK (0xF000000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT (24U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK (0x400000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT (22U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK (0x200000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT (21U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK (0x100000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT (20U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK (0x80000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT (19U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK (0x40000UL)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT (18U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK (0x3U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT (0U)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK)

#define	PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT)

#define	PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK (0xFF00U)

#define	PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT (8U)

#define	PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT)

#define	PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK (0xFFU)

#define	PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT)

#define	PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK (0x20000UL)

#define	PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT (17U)

#define	PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK) >> PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT)

#define	PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL)

#define	PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U)

#define	PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT)

#define	PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK (0x1FU)

#define	PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT)

#define	PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK (0x20000UL)

#define	PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT (17U)

#define	PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK) >> PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT)

#define	PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL)

#define	PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U)

#define	PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT)

#define	PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK (0x1FU)

#define	PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK (0xFF00U)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT (8U)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK (0xF0U)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT (4U)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK (0xFU)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK (0xFF00U)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT (8U)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK (0xF0U)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT (4U)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK (0xFU)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT)

#define	PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK (0xF000U)

#define	PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT (12U)

#define	PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK (0x800U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT (11U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK (0x400U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT (10U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK (0x200U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT (9U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK (0x100U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT (8U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK (0x80U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT (7U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK (0x40U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT (6U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK (0x20U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT (5U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK (0x10U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT (4U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK (0x8U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT (3U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK (0x4U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT (2U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK (0x2U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT (1U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK (0x1U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK (0xF000U)

#define	PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT (12U)

#define	PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK (0x800U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT (11U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK (0x400U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT (10U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK (0x200U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT (9U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK (0x100U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT (8U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK (0x80U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT (7U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK (0x40U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT (6U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK (0x20U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT (5U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK (0x10U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT (4U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK (0x8U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT (3U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK (0x4U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT (2U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK (0x2U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT (1U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK (0x1U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK (0x40U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT (6U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK (0x20U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT (5U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK (0x10U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT (4U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK (0x8U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT (3U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK (0x4U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT (2U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK (0x2U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT (1U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK (0x1U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK (0x40U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT (6U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK (0x20U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT (5U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK (0x10U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT (4U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK (0x8U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT (3U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK (0x4U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT (2U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK (0x2U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT (1U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK (0x1U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT (0U)

#define	PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT)

#define	PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK (0xFFFFFFFFUL)

#define	PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT (0U)

#define	PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK)

#define	PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) >> PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT)

#define	PIXELMUX_DSI_SETTING_DSI0_CFG (0UL)

#define	PIXELMUX_DSI_SETTING_DSI1_CFG (1UL)

Macro Definition Documentation

◆ PIXELMUX_DSI_SETTING_DSI0_CFG

#define PIXELMUX_DSI_SETTING_DSI0_CFG (0UL)

◆ PIXELMUX_DSI_SETTING_DSI1_CFG

#define PIXELMUX_DSI_SETTING_DSI1_CFG (1UL)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET

#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET ( x ) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK

#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK (0xFFFF0000UL)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET

#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET ( x ) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT

#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT (16U)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET

#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET ( x ) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK

#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK (0xFU)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET

#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET ( x ) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK)

◆ PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT

#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET

#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT)

◆ PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK

#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK (0xFFU)

◆ PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT

#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET

#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT)

◆ PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK

#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK (0xFF00U)

◆ PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT

#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT (8U)

◆ PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET

#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT)

◆ PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK

#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL)

◆ PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT

#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U)

◆ PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET

#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT)

◆ PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK

#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK (0x1FU)

◆ PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT

#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET

#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK) >> PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT)

◆ PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK

#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK (0x20000UL)

◆ PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT

#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT (17U)

◆ PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET

#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT)

◆ PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK

#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL)

◆ PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT

#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U)

◆ PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET

#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT)

◆ PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK

#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK (0x1FU)

◆ PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT

#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET

#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK) >> PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT)

◆ PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK

#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK (0x20000UL)

◆ PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT

#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT (17U)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK (0xFU)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK (0xF0U)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT (4U)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK (0xFF00U)

◆ PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT

#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT (8U)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK (0xFU)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK (0xF0U)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT (4U)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK (0xFF00U)

◆ PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT

#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT (8U)

◆ PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET

#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT)

◆ PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK

#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK (0xF000U)

◆ PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT

#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT (12U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK (0x20U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT (5U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK (0x1U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK (0x40U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT (6U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK (0x2U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT (1U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK (0x80U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT (7U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK (0x4U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT (2U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK (0x100U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT (8U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK (0x8U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT (3U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK (0x200U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK (0x800U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT (11U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT (9U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK (0x400U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT (10U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK (0x10U)

◆ PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT (4U)

◆ PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET

#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT)

◆ PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK

#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK (0xF000U)

◆ PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT

#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT (12U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK (0x20U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT (5U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK (0x1U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK (0x40U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT (6U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK (0x2U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT (1U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK (0x80U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT (7U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK (0x4U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT (2U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK (0x100U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT (8U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK (0x8U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT (3U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK (0x200U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK (0x800U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT (11U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT (9U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK (0x400U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT (10U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK (0x10U)

◆ PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT (4U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK (0x1U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK (0x2U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT (1U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK (0x40U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT (6U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK (0x10U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT (4U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK (0x4U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT (2U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK (0x20U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT (5U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK (0x8U)

◆ PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT (3U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK (0x1U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT (0U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK (0x2U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT (1U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK (0x40U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT (6U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK (0x10U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT (4U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK (0x4U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT (2U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK (0x20U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT (5U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK (0x8U)

◆ PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT

#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT (3U)

◆ PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET

#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) >> PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT)

◆ PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK

#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK (0xFFFFFFFFUL)

◆ PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET

#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK)

◆ PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT

#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK (0x7C000UL)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT (14U)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK (0x2000U)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT (13U)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK (0x1000U)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT (12U)

◆ PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET

#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK

#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK (0x4U)

◆ PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET

#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT (2U)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK (0x7C00000UL)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT (22U)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK (0x200000UL)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT (21U)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK (0x100000UL)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET

#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT)

◆ PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK

#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK (0x8U)

◆ PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET

#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK)

◆ PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT

#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT (3U)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET

#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK

#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK (0x20U)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET

#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT (5U)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET

#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK

#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK (0x10U)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET

#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT (4U)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET

#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK

#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK (0x40U)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET

#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT (6U)

◆ PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET

#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK

#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK (0x1U)

◆ PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET

#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET

#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK

#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK (0x100U)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET

#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT (8U)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET

#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK

#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK (0x80U)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET

#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT (7U)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET

#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK

#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK (0x200U)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET

#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT (9U)

◆ PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET

#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT)

◆ PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK

#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK (0x2U)

◆ PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET

#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK)

◆ PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT

#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT (1U)

◆ PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET

#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK (0xF000000UL)

◆ PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET

#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT (24U)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET

#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK (0xFU)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET

#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET

#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK (0xF0U)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET

#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT (4U)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET

#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK (0xF00U)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET

#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT (8U)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET

#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK (0xF000U)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET

#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT (12U)

◆ PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET

#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK (0xF0000UL)

◆ PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET

#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT (16U)

◆ PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET

#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK

#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK (0xF00000UL)

◆ PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET

#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK (0x10000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT (16U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK (0x80000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT (19U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK (0x6000000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT (25U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK (0x20000000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT (29U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK (0x18000000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT (27U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK (0xF00000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK (0x40000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT (18U)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK

#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK (0x20000UL)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET

#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK)

◆ PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT

#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT (17U)

◆ PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET

#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK

#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK (0xFFFFFFFFUL)

◆ PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET

#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK (0x1FFU)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK (0x800U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT (11U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK (0x400U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT (10U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK (0x8000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT (27U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK (0x400000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT (22U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK (0x3000U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT (12U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK (0x10000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT (28U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK (0x800000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT (23U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK (0xC000U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT (14U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK (0x20000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT (29U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK (0x1000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT (24U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK (0x30000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT (16U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK (0x40000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT (30U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK (0x2000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT (25U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK (0xC0000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT (18U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK (0x80000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT (31U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK (0x4000000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT (26U)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK (0x300000UL)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK (0x10000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT (16U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT (19U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK (0x6000000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT (25U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK (0x7FFFU)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK (0x20000000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT (29U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK (0x18000000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT (27U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK (0xF00000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK (0x40000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT (18U)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK

#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK (0x20000UL)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET

#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK)

◆ PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT

#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT (17U)

◆ PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET

#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT)

◆ PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK

#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK (0xFFFFFFFFUL)

◆ PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET

#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK)

◆ PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT

#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK (0x1FFU)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK (0x800U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT (11U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK (0x400U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT (10U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK (0x8000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT (27U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK (0x400000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT (22U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK (0x3000U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT (12U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK (0x10000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT (28U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK (0x800000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT (23U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK (0xC000U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT (14U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK (0x20000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT (29U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK (0x1000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT (24U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK (0x30000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT (16U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK (0x40000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT (30U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK (0x2000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT (25U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK (0xC0000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT (18U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK (0x80000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT (31U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK (0x4000000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT (26U)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK (0x300000UL)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK)

◆ PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT

#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK (0x40000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT (18U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK (0x80000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK (0x100000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT (19U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK (0xF000000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT (24U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK (0x200000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT (21U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK (0x80000000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT (31U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK (0x40000000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT (30U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK (0x30000000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT (28U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK (0x3U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK (0x400000UL)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET

#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT (22U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK (0x40000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT (18U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK (0x80000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK (0x100000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT (20U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT (19U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK (0xF000000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT (24U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK (0x200000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT (21U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK (0x80000000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT (31U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK (0x40000000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT (30U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK (0x30000000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT (28U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK (0x3U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT (0U)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK

#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK (0x400000UL)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET

#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK)

◆ PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT

#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT (22U)

◆ PIXELMUX_MISC_LVB_DI0_CTL_GET

#define PIXELMUX_MISC_LVB_DI0_CTL_GET ( x ) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) >> PIXELMUX_MISC_LVB_DI0_CTL_SHIFT)

◆ PIXELMUX_MISC_LVB_DI0_CTL_MASK

#define PIXELMUX_MISC_LVB_DI0_CTL_MASK (0x1U)

◆ PIXELMUX_MISC_LVB_DI0_CTL_SET

#define PIXELMUX_MISC_LVB_DI0_CTL_SET ( x ) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI0_CTL_MASK)

◆ PIXELMUX_MISC_LVB_DI0_CTL_SHIFT

#define PIXELMUX_MISC_LVB_DI0_CTL_SHIFT (0U)

◆ PIXELMUX_MISC_LVB_DI1_CTL_GET

#define PIXELMUX_MISC_LVB_DI1_CTL_GET ( x ) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) >> PIXELMUX_MISC_LVB_DI1_CTL_SHIFT)

◆ PIXELMUX_MISC_LVB_DI1_CTL_MASK

#define PIXELMUX_MISC_LVB_DI1_CTL_MASK (0x2U)

◆ PIXELMUX_MISC_LVB_DI1_CTL_SET

#define PIXELMUX_MISC_LVB_DI1_CTL_SET ( x ) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI1_CTL_MASK)

◆ PIXELMUX_MISC_LVB_DI1_CTL_SHIFT

#define PIXELMUX_MISC_LVB_DI1_CTL_SHIFT (1U)

◆ PIXELMUX_PIXMUX_CAM0_EN_GET

#define PIXELMUX_PIXMUX_CAM0_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_EN_MASK) >> PIXELMUX_PIXMUX_CAM0_EN_SHIFT)

◆ PIXELMUX_PIXMUX_CAM0_EN_MASK

#define PIXELMUX_PIXMUX_CAM0_EN_MASK (0x8U)

◆ PIXELMUX_PIXMUX_CAM0_EN_SET

#define PIXELMUX_PIXMUX_CAM0_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_EN_SHIFT) & PIXELMUX_PIXMUX_CAM0_EN_MASK)

◆ PIXELMUX_PIXMUX_CAM0_EN_SHIFT

#define PIXELMUX_PIXMUX_CAM0_EN_SHIFT (3U)

◆ PIXELMUX_PIXMUX_CAM0_SEL_GET

#define PIXELMUX_PIXMUX_CAM0_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) >> PIXELMUX_PIXMUX_CAM0_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_CAM0_SEL_MASK

#define PIXELMUX_PIXMUX_CAM0_SEL_MASK (0x7U)

◆ PIXELMUX_PIXMUX_CAM0_SEL_SET

#define PIXELMUX_PIXMUX_CAM0_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM0_SEL_MASK)

◆ PIXELMUX_PIXMUX_CAM0_SEL_SHIFT

#define PIXELMUX_PIXMUX_CAM0_SEL_SHIFT (0U)

◆ PIXELMUX_PIXMUX_CAM1_EN_GET

#define PIXELMUX_PIXMUX_CAM1_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_EN_MASK) >> PIXELMUX_PIXMUX_CAM1_EN_SHIFT)

◆ PIXELMUX_PIXMUX_CAM1_EN_MASK

#define PIXELMUX_PIXMUX_CAM1_EN_MASK (0x80U)

◆ PIXELMUX_PIXMUX_CAM1_EN_SET

#define PIXELMUX_PIXMUX_CAM1_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_EN_SHIFT) & PIXELMUX_PIXMUX_CAM1_EN_MASK)

◆ PIXELMUX_PIXMUX_CAM1_EN_SHIFT

#define PIXELMUX_PIXMUX_CAM1_EN_SHIFT (7U)

◆ PIXELMUX_PIXMUX_CAM1_SEL_GET

#define PIXELMUX_PIXMUX_CAM1_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) >> PIXELMUX_PIXMUX_CAM1_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_CAM1_SEL_MASK

#define PIXELMUX_PIXMUX_CAM1_SEL_MASK (0x70U)

◆ PIXELMUX_PIXMUX_CAM1_SEL_SET

#define PIXELMUX_PIXMUX_CAM1_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM1_SEL_MASK)

◆ PIXELMUX_PIXMUX_CAM1_SEL_SHIFT

#define PIXELMUX_PIXMUX_CAM1_SEL_SHIFT (4U)

◆ PIXELMUX_PIXMUX_DSI0_EN_GET

#define PIXELMUX_PIXMUX_DSI0_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_EN_MASK) >> PIXELMUX_PIXMUX_DSI0_EN_SHIFT)

◆ PIXELMUX_PIXMUX_DSI0_EN_MASK

#define PIXELMUX_PIXMUX_DSI0_EN_MASK (0x20000UL)

◆ PIXELMUX_PIXMUX_DSI0_EN_SET

#define PIXELMUX_PIXMUX_DSI0_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_EN_SHIFT) & PIXELMUX_PIXMUX_DSI0_EN_MASK)

◆ PIXELMUX_PIXMUX_DSI0_EN_SHIFT

#define PIXELMUX_PIXMUX_DSI0_EN_SHIFT (17U)

◆ PIXELMUX_PIXMUX_DSI0_SEL_GET

#define PIXELMUX_PIXMUX_DSI0_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) >> PIXELMUX_PIXMUX_DSI0_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_DSI0_SEL_MASK

#define PIXELMUX_PIXMUX_DSI0_SEL_MASK (0x10000UL)

◆ PIXELMUX_PIXMUX_DSI0_SEL_SET

#define PIXELMUX_PIXMUX_DSI0_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI0_SEL_MASK)

◆ PIXELMUX_PIXMUX_DSI0_SEL_SHIFT

#define PIXELMUX_PIXMUX_DSI0_SEL_SHIFT (16U)

◆ PIXELMUX_PIXMUX_DSI1_EN_GET

#define PIXELMUX_PIXMUX_DSI1_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_EN_MASK) >> PIXELMUX_PIXMUX_DSI1_EN_SHIFT)

◆ PIXELMUX_PIXMUX_DSI1_EN_MASK

#define PIXELMUX_PIXMUX_DSI1_EN_MASK (0x80000UL)

◆ PIXELMUX_PIXMUX_DSI1_EN_SET

#define PIXELMUX_PIXMUX_DSI1_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_EN_SHIFT) & PIXELMUX_PIXMUX_DSI1_EN_MASK)

◆ PIXELMUX_PIXMUX_DSI1_EN_SHIFT

#define PIXELMUX_PIXMUX_DSI1_EN_SHIFT (19U)

◆ PIXELMUX_PIXMUX_DSI1_SEL_GET

#define PIXELMUX_PIXMUX_DSI1_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) >> PIXELMUX_PIXMUX_DSI1_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_DSI1_SEL_MASK

#define PIXELMUX_PIXMUX_DSI1_SEL_MASK (0x40000UL)

◆ PIXELMUX_PIXMUX_DSI1_SEL_SET

#define PIXELMUX_PIXMUX_DSI1_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI1_SEL_MASK)

◆ PIXELMUX_PIXMUX_DSI1_SEL_SHIFT

#define PIXELMUX_PIXMUX_DSI1_SEL_SHIFT (18U)

◆ PIXELMUX_PIXMUX_GWC0_EN_GET

#define PIXELMUX_PIXMUX_GWC0_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_EN_MASK) >> PIXELMUX_PIXMUX_GWC0_EN_SHIFT)

◆ PIXELMUX_PIXMUX_GWC0_EN_MASK

#define PIXELMUX_PIXMUX_GWC0_EN_MASK (0x2000000UL)

◆ PIXELMUX_PIXMUX_GWC0_EN_SET

#define PIXELMUX_PIXMUX_GWC0_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_EN_SHIFT) & PIXELMUX_PIXMUX_GWC0_EN_MASK)

◆ PIXELMUX_PIXMUX_GWC0_EN_SHIFT

#define PIXELMUX_PIXMUX_GWC0_EN_SHIFT (25U)

◆ PIXELMUX_PIXMUX_GWC0_SEL_GET

#define PIXELMUX_PIXMUX_GWC0_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) >> PIXELMUX_PIXMUX_GWC0_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_GWC0_SEL_MASK

#define PIXELMUX_PIXMUX_GWC0_SEL_MASK (0x1000000UL)

◆ PIXELMUX_PIXMUX_GWC0_SEL_SET

#define PIXELMUX_PIXMUX_GWC0_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC0_SEL_MASK)

◆ PIXELMUX_PIXMUX_GWC0_SEL_SHIFT

#define PIXELMUX_PIXMUX_GWC0_SEL_SHIFT (24U)

◆ PIXELMUX_PIXMUX_GWC1_EN_GET

#define PIXELMUX_PIXMUX_GWC1_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_EN_MASK) >> PIXELMUX_PIXMUX_GWC1_EN_SHIFT)

◆ PIXELMUX_PIXMUX_GWC1_EN_MASK

#define PIXELMUX_PIXMUX_GWC1_EN_MASK (0x8000000UL)

◆ PIXELMUX_PIXMUX_GWC1_EN_SET

#define PIXELMUX_PIXMUX_GWC1_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_EN_SHIFT) & PIXELMUX_PIXMUX_GWC1_EN_MASK)

◆ PIXELMUX_PIXMUX_GWC1_EN_SHIFT

#define PIXELMUX_PIXMUX_GWC1_EN_SHIFT (27U)

◆ PIXELMUX_PIXMUX_GWC1_SEL_GET

#define PIXELMUX_PIXMUX_GWC1_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) >> PIXELMUX_PIXMUX_GWC1_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_GWC1_SEL_MASK

#define PIXELMUX_PIXMUX_GWC1_SEL_MASK (0x4000000UL)

◆ PIXELMUX_PIXMUX_GWC1_SEL_SET

#define PIXELMUX_PIXMUX_GWC1_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC1_SEL_MASK)

◆ PIXELMUX_PIXMUX_GWC1_SEL_SHIFT

#define PIXELMUX_PIXMUX_GWC1_SEL_SHIFT (26U)

◆ PIXELMUX_PIXMUX_LVB_DI0_EN_GET

#define PIXELMUX_PIXMUX_LVB_DI0_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT)

◆ PIXELMUX_PIXMUX_LVB_DI0_EN_MASK

#define PIXELMUX_PIXMUX_LVB_DI0_EN_MASK (0x200000UL)

◆ PIXELMUX_PIXMUX_LVB_DI0_EN_SET

#define PIXELMUX_PIXMUX_LVB_DI0_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK)

◆ PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT

#define PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT (21U)

◆ PIXELMUX_PIXMUX_LVB_DI0_SEL_GET

#define PIXELMUX_PIXMUX_LVB_DI0_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK

#define PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK (0x100000UL)

◆ PIXELMUX_PIXMUX_LVB_DI0_SEL_SET

#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK)

◆ PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT

#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT (20U)

◆ PIXELMUX_PIXMUX_LVB_DI1_EN_GET

#define PIXELMUX_PIXMUX_LVB_DI1_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT)

◆ PIXELMUX_PIXMUX_LVB_DI1_EN_MASK

#define PIXELMUX_PIXMUX_LVB_DI1_EN_MASK (0x800000UL)

◆ PIXELMUX_PIXMUX_LVB_DI1_EN_SET

#define PIXELMUX_PIXMUX_LVB_DI1_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK)

◆ PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT

#define PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT (23U)

◆ PIXELMUX_PIXMUX_LVB_DI1_SEL_GET

#define PIXELMUX_PIXMUX_LVB_DI1_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK

#define PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK (0x400000UL)

◆ PIXELMUX_PIXMUX_LVB_DI1_SEL_SET

#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK)

◆ PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT

#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT (22U)

◆ PIXELMUX_PIXMUX_RGB_EN_GET

#define PIXELMUX_PIXMUX_RGB_EN_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_EN_MASK) >> PIXELMUX_PIXMUX_RGB_EN_SHIFT)

◆ PIXELMUX_PIXMUX_RGB_EN_MASK

#define PIXELMUX_PIXMUX_RGB_EN_MASK (0x20000000UL)

◆ PIXELMUX_PIXMUX_RGB_EN_SET

#define PIXELMUX_PIXMUX_RGB_EN_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_EN_SHIFT) & PIXELMUX_PIXMUX_RGB_EN_MASK)

◆ PIXELMUX_PIXMUX_RGB_EN_SHIFT

#define PIXELMUX_PIXMUX_RGB_EN_SHIFT (29U)

◆ PIXELMUX_PIXMUX_RGB_SEL_GET

#define PIXELMUX_PIXMUX_RGB_SEL_GET ( x ) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_SEL_MASK) >> PIXELMUX_PIXMUX_RGB_SEL_SHIFT)

◆ PIXELMUX_PIXMUX_RGB_SEL_MASK

#define PIXELMUX_PIXMUX_RGB_SEL_MASK (0x10000000UL)

◆ PIXELMUX_PIXMUX_RGB_SEL_SET

#define PIXELMUX_PIXMUX_RGB_SEL_SET ( x ) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_SEL_SHIFT) & PIXELMUX_PIXMUX_RGB_SEL_MASK)

◆ PIXELMUX_PIXMUX_RGB_SEL_SHIFT

#define PIXELMUX_PIXMUX_RGB_SEL_SHIFT (28U)

Data Structures

Macros