#include "hpm_pllctlv2_drv.h"

Macros
#define	PLLCTLV2_PLL_MFN_FACTOR (10U)

#define	PLLCTLV2_PLL_MFD_DEFAULT (240UL * 1000000UL)

#define	PLLCTLV2_PLL_MFI_MIN (16U)

#define	PLLCTLV2_PLL_MFI_MAX (42U)

#define	PLLCTLV2_PLL_XTAL_FREQ (24000000UL)

#define	PLLCTLV2_PLL_FREQ_MIN (PLLCTLV2_PLL_MFI_MIN * PLLCTLV2_PLL_XTAL_FREQ)

#define	PLLCTLV2_PLL_FREQ_MAX ((PLLCTLV2_PLL_MFI_MAX + 1U) * PLLCTLV2_PLL_XTAL_FREQ)

Functions
hpm_stat_t	pllctlv2_set_pll_with_mfi_mfn (PLLCTLV2_Type *ptr, pllctlv2_pll_t pll, uint32_t mfi, uint32_t mfn)
	Set the PLL via the low-level MFI, MFD and MFN PLL frequency = REF CLOCK * (mfi + 1.0 * mfn / mfd) More...

hpm_stat_t	pllctlv2_init_pll_with_freq (PLLCTLV2_Type *ptr, pllctlv2_pll_t pll, uint32_t freq_in_hz)
	Initialize PLL to specified frequency Note: the specified PLL clock needs to be enabled before being configured. More...

void	pllctlv2_enable_spread_spectrum (PLLCTLV2_Type *ptr, pllctlv2_pll_t pll, uint32_t step, uint32_t stop)
	Enable PLL Spread Spectrum feature. More...

void	pllctlv2_set_postdiv (PLLCTLV2_Type *ptr, pllctlv2_pll_t pll, pllctlv2_clk_t clk, pllctlv2_div_t div_value)
	Set PLL Post divider. More...

uint32_t	pllctlv2_get_pll_freq_in_hz (PLLCTLV2_Type *ptr, pllctlv2_pll_t pll)
	Get the specified PLl clock frequency. More...

uint32_t	pllctlv2_get_pll_postdiv_freq_in_hz (PLLCTLV2_Type *ptr, pllctlv2_pll_t pll, pllctlv2_clk_t clk)
	Get the selected PLL post divider frequency. More...

Macro Definition Documentation

◆ PLLCTLV2_PLL_FREQ_MAX

#define PLLCTLV2_PLL_FREQ_MAX ((PLLCTLV2_PLL_MFI_MAX + 1U) * PLLCTLV2_PLL_XTAL_FREQ)

#define PLLCTLV2_PLL_MFD_DEFAULT (240UL * 1000000UL)

PLLCTLV2 PLL Default MFD value

#define PLLCTLV2_PLL_MFI_MAX (42U)

#define PLLCTLV2_PLL_MFI_MIN (16U)

#define PLLCTLV2_PLL_MFN_FACTOR (10U)

PLLCTLV2 PLL MFN Factor

#define PLLCTLV2_PLL_XTAL_FREQ (24000000UL)