HPM SDK
HPMicro Software Development Kit
hpm_qeo_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEO_H
10 #define HPM_QEO_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t MODE; /* 0x0: analog waves mode */
15  __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */
16  __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */
17  __RW uint32_t VD_VQ_INJECT[3]; /* 0x14 - 0x1C: wave0 vd vq inject value */
18  __W uint32_t VD_VQ_LOAD; /* 0x20: load wave0/1/2 vd vq value */
19  __RW uint32_t AMPLITUDE[3]; /* 0x24 - 0x2C: wave0 amplitude */
20  __RW uint32_t MID_POINT[3]; /* 0x30 - 0x38: wave0 output middle point offset */
21  struct {
22  __RW uint32_t MIN; /* 0x3C: wave0 low area limit value */
23  __RW uint32_t MAX; /* 0x40: wave0 high area limit value */
24  } LIMIT[3];
25  __RW uint32_t DEADZONE_SHIFT[3]; /* 0x54 - 0x5C: deadzone_shifter_wave0 */
26  } WAVE;
27  struct {
28  __RW uint32_t MODE; /* 0x60: wave_a/b/z output mode */
29  __RW uint32_t RESOLUTION; /* 0x64: resolution of wave_a/b/z */
30  __RW uint32_t PHASE_SHIFT[3]; /* 0x68 - 0x70: wave_a phase shifter */
31  __RW uint32_t LINE_WIDTH; /* 0x74: Two-phase orthogonality wave 1/4 period */
32  __RW uint32_t WDOG_WIDTH; /* 0x78: wdog width of qeo */
33  __W uint32_t POSTION_SYNC; /* 0x7C: sync abz owned postion */
34  } ABZ;
35  struct {
36  __RW uint32_t MODE; /* 0x80: pwm mode */
37  __RW uint32_t RESOLUTION; /* 0x84: resolution of pwm */
38  __RW uint32_t PHASE_SHIFT[4]; /* 0x88 - 0x94: pwm_a phase shifter */
39  __RW uint32_t PHASE_TABLE[24]; /* 0x98 - 0xF4: pwm_phase_table 0 */
40  } PWM;
41  __RW uint32_t POSTION_SOFTWARE; /* 0xF8: softwave inject postion */
42  __RW uint32_t POSTION_SEL; /* 0xFC: select softwave inject postion */
43  __R uint32_t STATUS; /* 0x100: qeo status */
44  __R uint32_t DEBUG0; /* 0x104: qeo debug 0 */
45  __R uint32_t DEBUG1; /* 0x108: qeo debug 1 */
46  __R uint32_t DEBUG2; /* 0x10C: qeo debug 2 */
47  __R uint32_t DEBUG3; /* 0x110: qeo debug 3 */
48 } QEO_Type;
49 
50 
51 /* Bitfield definition for register of struct WAVE: MODE */
52 /*
53  * WAVE2_ABOVE_MAX_LIMIT (RW)
54  *
55  * wave2 above max limit mode.
56  * 0: output 0xffff.
57  * 1: output 0x0.
58  * 2: output as level_max_limit2.level0_max_limit
59  */
60 #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL)
61 #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U)
62 #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK)
63 #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT)
64 
65 /*
66  * WAVE2_HIGH_AREA1_LIMIT (RW)
67  *
68  * wave2 high area1 limit mode.
69  * 0: output 0xffff.
70  * 1: output as level_max_limit2.level0_max_limit
71  */
72 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL)
73 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U)
74 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK)
75 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT)
76 
77 /*
78  * WAVE2_HIGH_AREA0_LIMIT (RW)
79  *
80  * wave2 high area0 limit mode.
81  * 0: output 0xffff.
82  * 1: output as level_max_limit2.level0_max_limit
83  */
84 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL)
85 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U)
86 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK)
87 #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT)
88 
89 /*
90  * WAVE2_LOW_AREA1_LIMIT (RW)
91  *
92  * wave2 low area1 limit mode.
93  * 0: output 0.
94  * 1: output as level_min_limit2.level1_min_limit
95  */
96 #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL)
97 #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U)
98 #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK)
99 #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT)
100 
101 /*
102  * WAVE2_LOW_AREA0_LIMIT (RW)
103  *
104  * wave2 low area0 limit mode.
105  * 0: output 0.
106  * 1: output as level_min_limit2.level1_min_limit
107  */
108 #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL)
109 #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U)
110 #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK)
111 #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT)
112 
113 /*
114  * WAVE2_BELOW_MIN_LIMIT (RW)
115  *
116  * wave2 below min limit mode.
117  * 0: output 0.
118  * 1: output 0xffff.
119  * 2: output as level_min_limit2.level1_min_limit
120  */
121 #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL)
122 #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U)
123 #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK)
124 #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT)
125 
126 /*
127  * WAVE1_ABOVE_MAX_LIMIT (RW)
128  *
129  * wave1 above max limit mode.
130  * 0: output 0xffff.
131  * 1: output 0x0.
132  * 2: output as level_max_limit1.level0_max_limit
133  */
134 #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL)
135 #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U)
136 #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK)
137 #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT)
138 
139 /*
140  * WAVE1_HIGH_AREA1_LIMIT (RW)
141  *
142  * wave1 high area1 limit mode.
143  * 0: output 0xffff.
144  * 1: output as level_max_limit1.level0_max_limit
145  */
146 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL)
147 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U)
148 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK)
149 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT)
150 
151 /*
152  * WAVE1_HIGH_AREA0_LIMIT (RW)
153  *
154  * wave1 high area0 limit mode.
155  * 0: output 0xffff.
156  * 1: output as level_max_limit1.level0_max_limit
157  */
158 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL)
159 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U)
160 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK)
161 #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT)
162 
163 /*
164  * WAVE1_LOW_AREA1_LIMIT (RW)
165  *
166  * wave1 low area1 limit mode.
167  * 0: output 0.
168  * 1: output as level_min_limit1.level1_min_limit
169  */
170 #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL)
171 #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U)
172 #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK)
173 #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT)
174 
175 /*
176  * WAVE1_LOW_AREA0_LIMIT (RW)
177  *
178  * wave1 low area0 limit mode.
179  * 0: output 0.
180  * 1: output as level_min_limit1.level1_min_limit
181  */
182 #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL)
183 #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U)
184 #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK)
185 #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT)
186 
187 /*
188  * WAVE1_BELOW_MIN_LIMIT (RW)
189  *
190  * wave1 below min limit mode.
191  * 0: output 0.
192  * 1: output 0xffff.
193  * 2: output as level_min_limit1.level1_min_limit
194  */
195 #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL)
196 #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U)
197 #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK)
198 #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT)
199 
200 /*
201  * WAVE0_ABOVE_MAX_LIMIT (RW)
202  *
203  * wave0 above max limit mode.
204  * 0: output 0xffff.
205  * 1: output 0x0.
206  * 2: output as level_max_limit0.level0_max_limit
207  */
208 #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U)
209 #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U)
210 #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK)
211 #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT)
212 
213 /*
214  * WAVE0_HIGH_AREA1_LIMIT (RW)
215  *
216  * wave0 high area1 limit mode.
217  * 0: output 0xffff.
218  * 1: output as level_max_limit0.level0_max_limit
219  */
220 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U)
221 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U)
222 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK)
223 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT)
224 
225 /*
226  * WAVE0_HIGH_AREA0_LIMIT (RW)
227  *
228  * wave0 high area0 limit mode.
229  * 0: output 0xffff.
230  * 1: output as level_max_limit0.level0_max_limit
231  */
232 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U)
233 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U)
234 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK)
235 #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT)
236 
237 /*
238  * WAVE0_LOW_AREA1_LIMIT (RW)
239  *
240  * wave0 low area1 limit mode.
241  * 0: output 0.
242  * 1: output as level_min_limit0.level1_min_limit
243  */
244 #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U)
245 #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U)
246 #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK)
247 #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT)
248 
249 /*
250  * WAVE0_LOW_AREA0_LIMIT (RW)
251  *
252  * wave0 low area0 limit mode.
253  * 0: output 0.
254  * 1: output as level_min_limit0.level1_min_limit
255  */
256 #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U)
257 #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U)
258 #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK)
259 #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT)
260 
261 /*
262  * WAVE0_BELOW_MIN_LIMIT (RW)
263  *
264  * wave0 below min limit mode.
265  * 0: output 0.
266  * 1: output 0xffff.
267  * 2: output as level_min_limit0.level1_min_limit
268  */
269 #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U)
270 #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U)
271 #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK)
272 #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT)
273 
274 /*
275  * SADDLE_TYPE (RW)
276  *
277  * saddle type seclect;
278  * 0:standard saddle.
279  * 1: triple-cos saddle.
280  */
281 #define QEO_WAVE_MODE_SADDLE_TYPE_MASK (0x80U)
282 #define QEO_WAVE_MODE_SADDLE_TYPE_SHIFT (7U)
283 #define QEO_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEO_WAVE_MODE_SADDLE_TYPE_MASK)
284 #define QEO_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) >> QEO_WAVE_MODE_SADDLE_TYPE_SHIFT)
285 
286 /*
287  * EN_WAVE2_VD_VQ_INJECT (RW)
288  *
289  * wave2 VdVq inject enable.
290  * 0: disable VdVq inject.
291  * 1: enable VdVq inject.
292  */
293 #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK (0x40U)
294 #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT (6U)
295 #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK)
296 #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT)
297 
298 /*
299  * EN_WAVE1_VD_VQ_INJECT (RW)
300  *
301  * wave1 VdVq inject enable.
302  * 0: disable VdVq inject.
303  * 1: enable VdVq inject.
304  */
305 #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK (0x20U)
306 #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT (5U)
307 #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK)
308 #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT)
309 
310 /*
311  * EN_WAVE0_VD_VQ_INJECT (RW)
312  *
313  * wave0 VdVq inject enable.
314  * 0: disable VdVq inject.
315  * 1: enable VdVq inject.
316  */
317 #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK (0x10U)
318 #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT (4U)
319 #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK)
320 #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT)
321 
322 /*
323  * WAVES_OUTPUT_TYPE (RW)
324  *
325  * wave0/1/2 output mode.
326  * 0: cosine wave.
327  * 1: saddle wave.
328  * 2. abs cosine wave.
329  * 3. saw wave
330  */
331 #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U)
332 #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U)
333 #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK)
334 #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT)
335 
336 /* Bitfield definition for register of struct WAVE: RESOLUTION */
337 /*
338  * LINES (RW)
339  *
340  * wave0/1/2 resolution
341  */
342 #define QEO_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
343 #define QEO_WAVE_RESOLUTION_LINES_SHIFT (0U)
344 #define QEO_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_WAVE_RESOLUTION_LINES_SHIFT) & QEO_WAVE_RESOLUTION_LINES_MASK)
345 #define QEO_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_WAVE_RESOLUTION_LINES_MASK) >> QEO_WAVE_RESOLUTION_LINES_SHIFT)
346 
347 /* Bitfield definition for register of struct WAVE: WAVE0 */
348 /*
349  * VAL (RW)
350  *
351  * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period
352  */
353 #define QEO_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFU)
354 #define QEO_WAVE_PHASE_SHIFT_VAL_SHIFT (0U)
355 #define QEO_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEO_WAVE_PHASE_SHIFT_VAL_MASK)
356 #define QEO_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) >> QEO_WAVE_PHASE_SHIFT_VAL_SHIFT)
357 
358 /* Bitfield definition for register of struct WAVE: WAVE0 */
359 /*
360  * VQ_VAL (RW)
361  *
362  * Vq inject value
363  */
364 #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK (0xFFFF0000UL)
365 #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT (16U)
366 #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK)
367 #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT)
368 
369 /*
370  * VD_VAL (RW)
371  *
372  * Vd inject value
373  */
374 #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK (0xFFFFU)
375 #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT (0U)
376 #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK)
377 #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT)
378 
379 /* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */
380 /*
381  * LOAD (WO)
382  *
383  * load wave0/1/2 vd vq value. always read 0
384  * 0: vd vq keep previous value.
385  * 1: load wave0/1/2 vd vq value at sametime.
386  */
387 #define QEO_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U)
388 #define QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U)
389 #define QEO_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK)
390 #define QEO_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT)
391 
392 /* Bitfield definition for register of struct WAVE: WAVE0 */
393 /*
394  * EN_SCAL (RW)
395  *
396  * enable wave amplitude scaling. 0: disable; 1: enable
397  */
398 #define QEO_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL)
399 #define QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U)
400 #define QEO_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK)
401 #define QEO_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT)
402 
403 /*
404  * AMP_VAL (RW)
405  *
406  * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value.
407  */
408 #define QEO_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU)
409 #define QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U)
410 #define QEO_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK)
411 #define QEO_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT)
412 
413 /* Bitfield definition for register of struct WAVE: WAVE0 */
414 /*
415  * VAL (RW)
416  *
417  * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value.
418  */
419 #define QEO_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL)
420 #define QEO_WAVE_MID_POINT_VAL_SHIFT (0U)
421 #define QEO_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_MID_POINT_VAL_SHIFT) & QEO_WAVE_MID_POINT_VAL_MASK)
422 #define QEO_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_MID_POINT_VAL_MASK) >> QEO_WAVE_MID_POINT_VAL_SHIFT)
423 
424 /* Bitfield definition for register of struct WAVE: MIN */
425 /*
426  * LIMIT1 (RW)
427  *
428  * low area limit level1
429  */
430 #define QEO_WAVE_LIMIT_MIN_LIMIT1_MASK (0xFFFF0000UL)
431 #define QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT (16U)
432 #define QEO_WAVE_LIMIT_MIN_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK)
433 #define QEO_WAVE_LIMIT_MIN_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT)
434 
435 /*
436  * LIMIT0 (RW)
437  *
438  * low area limit level0
439  */
440 #define QEO_WAVE_LIMIT_MIN_LIMIT0_MASK (0xFFFFU)
441 #define QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT (0U)
442 #define QEO_WAVE_LIMIT_MIN_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK)
443 #define QEO_WAVE_LIMIT_MIN_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT)
444 
445 /* Bitfield definition for register of struct WAVE: MAX */
446 /*
447  * LIMIT1 (RW)
448  *
449  * high area limit level1
450  */
451 #define QEO_WAVE_LIMIT_MAX_LIMIT1_MASK (0xFFFF0000UL)
452 #define QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT (16U)
453 #define QEO_WAVE_LIMIT_MAX_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK)
454 #define QEO_WAVE_LIMIT_MAX_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT)
455 
456 /*
457  * LIMIT0 (RW)
458  *
459  * high area limit level0
460  */
461 #define QEO_WAVE_LIMIT_MAX_LIMIT0_MASK (0xFFFFU)
462 #define QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT (0U)
463 #define QEO_WAVE_LIMIT_MAX_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK)
464 #define QEO_WAVE_LIMIT_MAX_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT)
465 
466 /* Bitfield definition for register of struct WAVE: WAVE0 */
467 /*
468  * VAL (RW)
469  *
470  * wave0 deadzone shifter value
471  */
472 #define QEO_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFU)
473 #define QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U)
474 #define QEO_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK)
475 #define QEO_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT)
476 
477 /* Bitfield definition for register of struct ABZ: MODE */
478 /*
479  * REVERSE_EDGE_TYPE (RW)
480  *
481  * pulse reverse wave，reverse edge point:
482  * 0: between pulse's posedge and negedge, min period dedicated by the num line_width
483  * 1: edge change point flow pulse's negedge.
484  */
485 #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL)
486 #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U)
487 #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK)
488 #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT)
489 
490 /*
491  * EN_WDOG (RW)
492  *
493  * enable abz wdog:
494  * 0: disable abz wdog.
495  * 1: enable abz wdog.
496  */
497 #define QEO_ABZ_MODE_EN_WDOG_MASK (0x1000000UL)
498 #define QEO_ABZ_MODE_EN_WDOG_SHIFT (24U)
499 #define QEO_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_EN_WDOG_SHIFT) & QEO_ABZ_MODE_EN_WDOG_MASK)
500 #define QEO_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_EN_WDOG_MASK) >> QEO_ABZ_MODE_EN_WDOG_SHIFT)
501 
502 /*
503  * Z_POLARITY (RW)
504  *
505  * wave_z polarity.
506  * 0: normal output.
507  * 1: invert normal output
508  */
509 #define QEO_ABZ_MODE_Z_POLARITY_MASK (0x100000UL)
510 #define QEO_ABZ_MODE_Z_POLARITY_SHIFT (20U)
511 #define QEO_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_POLARITY_SHIFT) & QEO_ABZ_MODE_Z_POLARITY_MASK)
512 #define QEO_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_POLARITY_MASK) >> QEO_ABZ_MODE_Z_POLARITY_SHIFT)
513 
514 /*
515  * B_POLARITY (RW)
516  *
517  * wave_b polarity.
518  * 0: normal output.
519  * 1: invert normal output
520  */
521 #define QEO_ABZ_MODE_B_POLARITY_MASK (0x10000UL)
522 #define QEO_ABZ_MODE_B_POLARITY_SHIFT (16U)
523 #define QEO_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_POLARITY_SHIFT) & QEO_ABZ_MODE_B_POLARITY_MASK)
524 #define QEO_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_POLARITY_MASK) >> QEO_ABZ_MODE_B_POLARITY_SHIFT)
525 
526 /*
527  * A_POLARITY (RW)
528  *
529  * wave_a polarity.
530  * 0: normal output.
531  * 1: invert normal output
532  */
533 #define QEO_ABZ_MODE_A_POLARITY_MASK (0x1000U)
534 #define QEO_ABZ_MODE_A_POLARITY_SHIFT (12U)
535 #define QEO_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_POLARITY_SHIFT) & QEO_ABZ_MODE_A_POLARITY_MASK)
536 #define QEO_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_POLARITY_MASK) >> QEO_ABZ_MODE_A_POLARITY_SHIFT)
537 
538 /*
539  * Z_TYPE (RW)
540  *
541  * wave_z type:
542  * 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period.
543  * 1: zero pulse output high about 75% period. start from 0 to 75% period.
544  * 2: zero pulse output high about 100% period.
545  * 3: wave_z output as tree-phase wave same as wave_a/wave_b
546  */
547 #define QEO_ABZ_MODE_Z_TYPE_MASK (0x300U)
548 #define QEO_ABZ_MODE_Z_TYPE_SHIFT (8U)
549 #define QEO_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_TYPE_SHIFT) & QEO_ABZ_MODE_Z_TYPE_MASK)
550 #define QEO_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_TYPE_MASK) >> QEO_ABZ_MODE_Z_TYPE_SHIFT)
551 
552 /*
553  * B_TYPE (RW)
554  *
555  * wave_b type:
556  * 0: Two-phase orthogonality wave_b.
557  * 1: reverse wave of pulse/reverse type.
558  * 2: down wave of up/down type.
559  * 3: Three-phase orthogonality wave_b.
560  */
561 #define QEO_ABZ_MODE_B_TYPE_MASK (0x30U)
562 #define QEO_ABZ_MODE_B_TYPE_SHIFT (4U)
563 #define QEO_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_TYPE_SHIFT) & QEO_ABZ_MODE_B_TYPE_MASK)
564 #define QEO_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_TYPE_MASK) >> QEO_ABZ_MODE_B_TYPE_SHIFT)
565 
566 /*
567  * A_TYPE (RW)
568  *
569  * wave_a type:
570  * 0: Two-phase orthogonality wave_a.
571  * 1: pulse wave of pulse/reverse type.
572  * 2: up wave of up/down type.
573  * 3: Three-phase orthogonality wave_a.
574  */
575 #define QEO_ABZ_MODE_A_TYPE_MASK (0x3U)
576 #define QEO_ABZ_MODE_A_TYPE_SHIFT (0U)
577 #define QEO_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_TYPE_SHIFT) & QEO_ABZ_MODE_A_TYPE_MASK)
578 #define QEO_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_TYPE_MASK) >> QEO_ABZ_MODE_A_TYPE_SHIFT)
579 
580 /* Bitfield definition for register of struct ABZ: RESOLUTION */
581 /*
582  * LINES (RW)
583  *
584  * wave_a/b/z resolution
585  */
586 #define QEO_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
587 #define QEO_ABZ_RESOLUTION_LINES_SHIFT (0U)
588 #define QEO_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_ABZ_RESOLUTION_LINES_SHIFT) & QEO_ABZ_RESOLUTION_LINES_MASK)
589 #define QEO_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_ABZ_RESOLUTION_LINES_MASK) >> QEO_ABZ_RESOLUTION_LINES_SHIFT)
590 
591 /* Bitfield definition for register of struct ABZ: A */
592 /*
593  * VAL (RW)
594  *
595  * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period.
596  */
597 #define QEO_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFU)
598 #define QEO_ABZ_PHASE_SHIFT_VAL_SHIFT (0U)
599 #define QEO_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEO_ABZ_PHASE_SHIFT_VAL_MASK)
600 #define QEO_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) >> QEO_ABZ_PHASE_SHIFT_VAL_SHIFT)
601 
602 /* Bitfield definition for register of struct ABZ: LINE_WIDTH */
603 /*
604  * LINE (RW)
605  *
606  * the num of system clk by 1/4 period when using as Two-phase orthogonality.
607  */
608 #define QEO_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL)
609 #define QEO_ABZ_LINE_WIDTH_LINE_SHIFT (0U)
610 #define QEO_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEO_ABZ_LINE_WIDTH_LINE_SHIFT) & QEO_ABZ_LINE_WIDTH_LINE_MASK)
611 #define QEO_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEO_ABZ_LINE_WIDTH_LINE_MASK) >> QEO_ABZ_LINE_WIDTH_LINE_SHIFT)
612 
613 /* Bitfield definition for register of struct ABZ: WDOG_WIDTH */
614 /*
615  * WIDTH (RW)
616  *
617  * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk.
618  */
619 #define QEO_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL)
620 #define QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U)
621 #define QEO_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK)
622 #define QEO_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT)
623 
624 /* Bitfield definition for register of struct ABZ: POSTION_SYNC */
625 /*
626  * POSTION (WO)
627  *
628  * load next valid postion into abz owned postion. always read 0
629  * 0: sync abz owned postion with next valid postion.
630  * 1: not sync.
631  */
632 #define QEO_ABZ_POSTION_SYNC_POSTION_MASK (0x1U)
633 #define QEO_ABZ_POSTION_SYNC_POSTION_SHIFT (0U)
634 #define QEO_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEO_ABZ_POSTION_SYNC_POSTION_MASK)
635 #define QEO_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) >> QEO_ABZ_POSTION_SYNC_POSTION_SHIFT)
636 
637 /* Bitfield definition for register of struct PWM: MODE */
638 /*
639  * PWM7_SAFETY (RW)
640  *
641  * PWM safety mode phase table
642  */
643 #define QEO_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL)
644 #define QEO_PWM_MODE_PWM7_SAFETY_SHIFT (30U)
645 #define QEO_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM7_SAFETY_SHIFT) & QEO_PWM_MODE_PWM7_SAFETY_MASK)
646 #define QEO_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM7_SAFETY_MASK) >> QEO_PWM_MODE_PWM7_SAFETY_SHIFT)
647 
648 /*
649  * PWM6_SAFETY (RW)
650  *
651  * PWM safety mode phase table
652  */
653 #define QEO_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL)
654 #define QEO_PWM_MODE_PWM6_SAFETY_SHIFT (28U)
655 #define QEO_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM6_SAFETY_SHIFT) & QEO_PWM_MODE_PWM6_SAFETY_MASK)
656 #define QEO_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM6_SAFETY_MASK) >> QEO_PWM_MODE_PWM6_SAFETY_SHIFT)
657 
658 /*
659  * PWM5_SAFETY (RW)
660  *
661  * PWM safety mode phase table
662  */
663 #define QEO_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL)
664 #define QEO_PWM_MODE_PWM5_SAFETY_SHIFT (26U)
665 #define QEO_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM5_SAFETY_SHIFT) & QEO_PWM_MODE_PWM5_SAFETY_MASK)
666 #define QEO_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM5_SAFETY_MASK) >> QEO_PWM_MODE_PWM5_SAFETY_SHIFT)
667 
668 /*
669  * PWM4_SAFETY (RW)
670  *
671  * PWM safety mode phase table
672  */
673 #define QEO_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL)
674 #define QEO_PWM_MODE_PWM4_SAFETY_SHIFT (24U)
675 #define QEO_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM4_SAFETY_SHIFT) & QEO_PWM_MODE_PWM4_SAFETY_MASK)
676 #define QEO_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM4_SAFETY_MASK) >> QEO_PWM_MODE_PWM4_SAFETY_SHIFT)
677 
678 /*
679  * PWM3_SAFETY (RW)
680  *
681  * PWM safety mode phase table
682  */
683 #define QEO_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL)
684 #define QEO_PWM_MODE_PWM3_SAFETY_SHIFT (22U)
685 #define QEO_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM3_SAFETY_SHIFT) & QEO_PWM_MODE_PWM3_SAFETY_MASK)
686 #define QEO_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM3_SAFETY_MASK) >> QEO_PWM_MODE_PWM3_SAFETY_SHIFT)
687 
688 /*
689  * PWM2_SAFETY (RW)
690  *
691  * PWM safety mode phase table
692  */
693 #define QEO_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL)
694 #define QEO_PWM_MODE_PWM2_SAFETY_SHIFT (20U)
695 #define QEO_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM2_SAFETY_SHIFT) & QEO_PWM_MODE_PWM2_SAFETY_MASK)
696 #define QEO_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM2_SAFETY_MASK) >> QEO_PWM_MODE_PWM2_SAFETY_SHIFT)
697 
698 /*
699  * PWM1_SAFETY (RW)
700  *
701  * PWM safety mode phase table
702  */
703 #define QEO_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL)
704 #define QEO_PWM_MODE_PWM1_SAFETY_SHIFT (18U)
705 #define QEO_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM1_SAFETY_SHIFT) & QEO_PWM_MODE_PWM1_SAFETY_MASK)
706 #define QEO_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM1_SAFETY_MASK) >> QEO_PWM_MODE_PWM1_SAFETY_SHIFT)
707 
708 /*
709  * PWM0_SAFETY (RW)
710  *
711  * PWM safety mode phase table
712  */
713 #define QEO_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL)
714 #define QEO_PWM_MODE_PWM0_SAFETY_SHIFT (16U)
715 #define QEO_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM0_SAFETY_SHIFT) & QEO_PWM_MODE_PWM0_SAFETY_MASK)
716 #define QEO_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM0_SAFETY_MASK) >> QEO_PWM_MODE_PWM0_SAFETY_SHIFT)
717 
718 /*
719  * PWM_ENTER_SAFETY_MODE (RW)
720  *
721  * PWM enter safety mode
722  * 0: not enter
723  * 1: enter
724  */
725 #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U)
726 #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U)
727 #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK)
728 #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT)
729 
730 /*
731  * PWM_SAFETY_BYPASS (RW)
732  *
733  * PWM safety mode bypass
734  * 0: not bypass
735  * 1: bypass
736  */
737 #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U)
738 #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U)
739 #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK)
740 #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT)
741 
742 /*
743  * REVISE_UP_DN (RW)
744  *
745  * exchange PWM pairs’ output
746  * 0: not exchange.
747  * 1: exchange.
748  */
749 #define QEO_PWM_MODE_REVISE_UP_DN_MASK (0x10U)
750 #define QEO_PWM_MODE_REVISE_UP_DN_SHIFT (4U)
751 #define QEO_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_REVISE_UP_DN_SHIFT) & QEO_PWM_MODE_REVISE_UP_DN_MASK)
752 #define QEO_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_REVISE_UP_DN_MASK) >> QEO_PWM_MODE_REVISE_UP_DN_SHIFT)
753 
754 /*
755  * PHASE_NUM (RW)
756  *
757  * pwm force phase number.
758  */
759 #define QEO_PWM_MODE_PHASE_NUM_MASK (0xFU)
760 #define QEO_PWM_MODE_PHASE_NUM_SHIFT (0U)
761 #define QEO_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PHASE_NUM_SHIFT) & QEO_PWM_MODE_PHASE_NUM_MASK)
762 #define QEO_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PHASE_NUM_MASK) >> QEO_PWM_MODE_PHASE_NUM_SHIFT)
763 
764 /* Bitfield definition for register of struct PWM: RESOLUTION */
765 /*
766  * LINES (RW)
767  *
768  * pwm resolution
769  */
770 #define QEO_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
771 #define QEO_PWM_RESOLUTION_LINES_SHIFT (0U)
772 #define QEO_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_PWM_RESOLUTION_LINES_SHIFT) & QEO_PWM_RESOLUTION_LINES_MASK)
773 #define QEO_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_PWM_RESOLUTION_LINES_MASK) >> QEO_PWM_RESOLUTION_LINES_SHIFT)
774 
775 /* Bitfield definition for register of struct PWM: A */
776 /*
777  * VAL (RW)
778  *
779  * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period
780  */
781 #define QEO_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFU)
782 #define QEO_PWM_PHASE_SHIFT_VAL_SHIFT (0U)
783 #define QEO_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_SHIFT_VAL_SHIFT) & QEO_PWM_PHASE_SHIFT_VAL_MASK)
784 #define QEO_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_SHIFT_VAL_MASK) >> QEO_PWM_PHASE_SHIFT_VAL_SHIFT)
785 
786 /* Bitfield definition for register of struct PWM: POSEDGE0 */
787 /*
788  * PWM7 (RW)
789  *
790  * pwm phase table value
791  */
792 #define QEO_PWM_PHASE_TABLE_PWM7_MASK (0xC000U)
793 #define QEO_PWM_PHASE_TABLE_PWM7_SHIFT (14U)
794 #define QEO_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM7_SHIFT) & QEO_PWM_PHASE_TABLE_PWM7_MASK)
795 #define QEO_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM7_MASK) >> QEO_PWM_PHASE_TABLE_PWM7_SHIFT)
796 
797 /*
798  * PWM6 (RW)
799  *
800  * pwm phase table value
801  */
802 #define QEO_PWM_PHASE_TABLE_PWM6_MASK (0x3000U)
803 #define QEO_PWM_PHASE_TABLE_PWM6_SHIFT (12U)
804 #define QEO_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM6_SHIFT) & QEO_PWM_PHASE_TABLE_PWM6_MASK)
805 #define QEO_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM6_MASK) >> QEO_PWM_PHASE_TABLE_PWM6_SHIFT)
806 
807 /*
808  * PWM5 (RW)
809  *
810  * pwm phase table value
811  */
812 #define QEO_PWM_PHASE_TABLE_PWM5_MASK (0xC00U)
813 #define QEO_PWM_PHASE_TABLE_PWM5_SHIFT (10U)
814 #define QEO_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM5_SHIFT) & QEO_PWM_PHASE_TABLE_PWM5_MASK)
815 #define QEO_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM5_MASK) >> QEO_PWM_PHASE_TABLE_PWM5_SHIFT)
816 
817 /*
818  * PWM4 (RW)
819  *
820  * pwm phase table value
821  */
822 #define QEO_PWM_PHASE_TABLE_PWM4_MASK (0x300U)
823 #define QEO_PWM_PHASE_TABLE_PWM4_SHIFT (8U)
824 #define QEO_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM4_SHIFT) & QEO_PWM_PHASE_TABLE_PWM4_MASK)
825 #define QEO_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM4_MASK) >> QEO_PWM_PHASE_TABLE_PWM4_SHIFT)
826 
827 /*
828  * PWM3 (RW)
829  *
830  * pwm phase table value
831  */
832 #define QEO_PWM_PHASE_TABLE_PWM3_MASK (0xC0U)
833 #define QEO_PWM_PHASE_TABLE_PWM3_SHIFT (6U)
834 #define QEO_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM3_SHIFT) & QEO_PWM_PHASE_TABLE_PWM3_MASK)
835 #define QEO_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM3_MASK) >> QEO_PWM_PHASE_TABLE_PWM3_SHIFT)
836 
837 /*
838  * PWM2 (RW)
839  *
840  * pwm phase table value
841  */
842 #define QEO_PWM_PHASE_TABLE_PWM2_MASK (0x30U)
843 #define QEO_PWM_PHASE_TABLE_PWM2_SHIFT (4U)
844 #define QEO_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM2_SHIFT) & QEO_PWM_PHASE_TABLE_PWM2_MASK)
845 #define QEO_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM2_MASK) >> QEO_PWM_PHASE_TABLE_PWM2_SHIFT)
846 
847 /*
848  * PWM1 (RW)
849  *
850  * pwm phase table value
851  */
852 #define QEO_PWM_PHASE_TABLE_PWM1_MASK (0xCU)
853 #define QEO_PWM_PHASE_TABLE_PWM1_SHIFT (2U)
854 #define QEO_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM1_SHIFT) & QEO_PWM_PHASE_TABLE_PWM1_MASK)
855 #define QEO_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM1_MASK) >> QEO_PWM_PHASE_TABLE_PWM1_SHIFT)
856 
857 /*
858  * PWM0 (RW)
859  *
860  * pwm phase table value
861  */
862 #define QEO_PWM_PHASE_TABLE_PWM0_MASK (0x3U)
863 #define QEO_PWM_PHASE_TABLE_PWM0_SHIFT (0U)
864 #define QEO_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM0_SHIFT) & QEO_PWM_PHASE_TABLE_PWM0_MASK)
865 #define QEO_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM0_MASK) >> QEO_PWM_PHASE_TABLE_PWM0_SHIFT)
866 
867 /* Bitfield definition for register: POSTION_SOFTWARE */
868 /*
869  * POSTION_SOFTWAVE (RW)
870  *
871  * softwave inject postion
872  */
873 #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL)
874 #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U)
875 #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK)
876 #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT)
877 
878 /* Bitfield definition for register: POSTION_SEL */
879 /*
880  * POSTION_SEL (RW)
881  *
882  * enable softwave inject postion.
883  * 0: disable.
884  * 1: enable.
885  */
886 #define QEO_POSTION_SEL_POSTION_SEL_MASK (0x1U)
887 #define QEO_POSTION_SEL_POSTION_SEL_SHIFT (0U)
888 #define QEO_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEO_POSTION_SEL_POSTION_SEL_SHIFT) & QEO_POSTION_SEL_POSTION_SEL_MASK)
889 #define QEO_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEO_POSTION_SEL_POSTION_SEL_MASK) >> QEO_POSTION_SEL_POSTION_SEL_SHIFT)
890 
891 /* Bitfield definition for register: STATUS */
892 /*
893  * PWM_FOURCE (RO)
894  *
895  * qeo_pwm_force observe
896  */
897 #define QEO_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL)
898 #define QEO_STATUS_PWM_FOURCE_SHIFT (16U)
899 #define QEO_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_FOURCE_MASK) >> QEO_STATUS_PWM_FOURCE_SHIFT)
900 
901 /*
902  * PWM_SAFETY (RO)
903  *
904  * pwm_fault status
905  */
906 #define QEO_STATUS_PWM_SAFETY_MASK (0x1U)
907 #define QEO_STATUS_PWM_SAFETY_SHIFT (0U)
908 #define QEO_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_SAFETY_MASK) >> QEO_STATUS_PWM_SAFETY_SHIFT)
909 
910 /* Bitfield definition for register: DEBUG0 */
911 /*
912  * WAVE1 (RO)
913  *
914  * wave1 observe
915  */
916 #define QEO_DEBUG0_WAVE1_MASK (0xFFFF0000UL)
917 #define QEO_DEBUG0_WAVE1_SHIFT (16U)
918 #define QEO_DEBUG0_WAVE1_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE1_MASK) >> QEO_DEBUG0_WAVE1_SHIFT)
919 
920 /*
921  * WAVE0 (RO)
922  *
923  * wave0 observe
924  */
925 #define QEO_DEBUG0_WAVE0_MASK (0xFFFFU)
926 #define QEO_DEBUG0_WAVE0_SHIFT (0U)
927 #define QEO_DEBUG0_WAVE0_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE0_MASK) >> QEO_DEBUG0_WAVE0_SHIFT)
928 
929 /* Bitfield definition for register: DEBUG1 */
930 /*
931  * QEO_FINISH (RO)
932  *
933  * qeo finish observe
934  */
935 #define QEO_DEBUG1_QEO_FINISH_MASK (0x10000000UL)
936 #define QEO_DEBUG1_QEO_FINISH_SHIFT (28U)
937 #define QEO_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEO_DEBUG1_QEO_FINISH_MASK) >> QEO_DEBUG1_QEO_FINISH_SHIFT)
938 
939 /*
940  * WAVE_Z (RO)
941  *
942  * wave_z observe
943  */
944 #define QEO_DEBUG1_WAVE_Z_MASK (0x1000000UL)
945 #define QEO_DEBUG1_WAVE_Z_SHIFT (24U)
946 #define QEO_DEBUG1_WAVE_Z_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_Z_MASK) >> QEO_DEBUG1_WAVE_Z_SHIFT)
947 
948 /*
949  * WAVE_B (RO)
950  *
951  * wave_b observe
952  */
953 #define QEO_DEBUG1_WAVE_B_MASK (0x100000UL)
954 #define QEO_DEBUG1_WAVE_B_SHIFT (20U)
955 #define QEO_DEBUG1_WAVE_B_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_B_MASK) >> QEO_DEBUG1_WAVE_B_SHIFT)
956 
957 /*
958  * WAVE_A (RO)
959  *
960  * wave_a observe
961  */
962 #define QEO_DEBUG1_WAVE_A_MASK (0x10000UL)
963 #define QEO_DEBUG1_WAVE_A_SHIFT (16U)
964 #define QEO_DEBUG1_WAVE_A_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_A_MASK) >> QEO_DEBUG1_WAVE_A_SHIFT)
965 
966 /*
967  * WAVE2 (RO)
968  *
969  * wave2 observe
970  */
971 #define QEO_DEBUG1_WAVE2_MASK (0xFFFFU)
972 #define QEO_DEBUG1_WAVE2_SHIFT (0U)
973 #define QEO_DEBUG1_WAVE2_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE2_MASK) >> QEO_DEBUG1_WAVE2_SHIFT)
974 
975 /* Bitfield definition for register: DEBUG2 */
976 /*
977  * ABZ_OWN_POSTION (RO)
978  *
979  * abz_own_postion observe
980  */
981 #define QEO_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL)
982 #define QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U)
983 #define QEO_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT)
984 
985 /* Bitfield definition for register: DEBUG3 */
986 /*
987  * ABZ_OWN_POSTION (RO)
988  *
989  * abz_own_postion observe
990  */
991 #define QEO_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL)
992 #define QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U)
993 #define QEO_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT)
994 
995 
996 
997 /* PHASE_SHIFT register group index macro definition */
998 #define QEO_WAVE_PHASE_SHIFT_WAVE0 (0UL)
999 #define QEO_WAVE_PHASE_SHIFT_WAVE1 (1UL)
1000 #define QEO_WAVE_PHASE_SHIFT_WAVE2 (2UL)
1001 
1002 /* VD_VQ_INJECT register group index macro definition */
1003 #define QEO_WAVE_VD_VQ_INJECT_WAVE0 (0UL)
1004 #define QEO_WAVE_VD_VQ_INJECT_WAVE1 (1UL)
1005 #define QEO_WAVE_VD_VQ_INJECT_WAVE2 (2UL)
1006 
1007 /* AMPLITUDE register group index macro definition */
1008 #define QEO_WAVE_AMPLITUDE_WAVE0 (0UL)
1009 #define QEO_WAVE_AMPLITUDE_WAVE1 (1UL)
1010 #define QEO_WAVE_AMPLITUDE_WAVE2 (2UL)
1011 
1012 /* MID_POINT register group index macro definition */
1013 #define QEO_WAVE_MID_POINT_WAVE0 (0UL)
1014 #define QEO_WAVE_MID_POINT_WAVE1 (1UL)
1015 #define QEO_WAVE_MID_POINT_WAVE2 (2UL)
1016 
1017 /* LIMIT register group index macro definition */
1018 #define QEO_LIMIT_WAVE0 (0UL)
1019 #define QEO_LIMIT_WAVE1 (1UL)
1020 #define QEO_LIMIT_WAVE2 (2UL)
1021 
1022 /* DEADZONE_SHIFT register group index macro definition */
1023 #define QEO_WAVE_DEADZONE_SHIFT_WAVE0 (0UL)
1024 #define QEO_WAVE_DEADZONE_SHIFT_WAVE1 (1UL)
1025 #define QEO_WAVE_DEADZONE_SHIFT_WAVE2 (2UL)
1026 
1027 /* PHASE_SHIFT register group index macro definition */
1028 #define QEO_ABZ_PHASE_SHIFT_A (0UL)
1029 #define QEO_ABZ_PHASE_SHIFT_B (1UL)
1030 #define QEO_ABZ_PHASE_SHIFT_Z (2UL)
1031 
1032 /* PHASE_SHIFT register group index macro definition */
1033 #define QEO_PWM_PHASE_SHIFT_A (0UL)
1034 #define QEO_PWM_PHASE_SHIFT_B (1UL)
1035 #define QEO_PWM_PHASE_SHIFT_C (2UL)
1036 #define QEO_PWM_PHASE_SHIFT_D (3UL)
1037 
1038 /* PHASE_TABLE register group index macro definition */
1039 #define QEO_PWM_PHASE_TABLE_POSEDGE0 (0UL)
1040 #define QEO_PWM_PHASE_TABLE_POSEDGE1 (1UL)
1041 #define QEO_PWM_PHASE_TABLE_POSEDGE2 (2UL)
1042 #define QEO_PWM_PHASE_TABLE_POSEDGE3 (3UL)
1043 #define QEO_PWM_PHASE_TABLE_POSEDGE4 (4UL)
1044 #define QEO_PWM_PHASE_TABLE_POSEDGE5 (5UL)
1045 #define QEO_PWM_PHASE_TABLE_POSEDGE6 (6UL)
1046 #define QEO_PWM_PHASE_TABLE_POSEDGE7 (7UL)
1047 #define QEO_PWM_PHASE_TABLE_POSEDGE8 (8UL)
1048 #define QEO_PWM_PHASE_TABLE_POSEDGE9 (9UL)
1049 #define QEO_PWM_PHASE_TABLE_POSEDGE10 (10UL)
1050 #define QEO_PWM_PHASE_TABLE_POSEDGE11 (11UL)
1051 #define QEO_PWM_PHASE_TABLE_NEGEDGE0 (12UL)
1052 #define QEO_PWM_PHASE_TABLE_NEGEDGE1 (13UL)
1053 #define QEO_PWM_PHASE_TABLE_NEGEDGE2 (14UL)
1054 #define QEO_PWM_PHASE_TABLE_NEGEDGE3 (15UL)
1055 #define QEO_PWM_PHASE_TABLE_NEGEDGE4 (16UL)
1056 #define QEO_PWM_PHASE_TABLE_NEGEDGE5 (17UL)
1057 #define QEO_PWM_PHASE_TABLE_NEGEDGE6 (18UL)
1058 #define QEO_PWM_PHASE_TABLE_NEGEDGE7 (19UL)
1059 #define QEO_PWM_PHASE_TABLE_NEGEDGE8 (20UL)
1060 #define QEO_PWM_PHASE_TABLE_NEGEDGE9 (21UL)
1061 #define QEO_PWM_PHASE_TABLE_NEGEDGE10 (22UL)
1062 #define QEO_PWM_PHASE_TABLE_NEGEDGE11 (23UL)
1063 
1064 
1065 #endif /* HPM_QEO_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
QEO_Type
Definition: hpm_qeo_regs.h:12