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Data Structures | |
| struct | QEO_Type |
| #define QEO_ABZ_LINE_WIDTH_LINE_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_LINE_WIDTH_LINE_MASK) >> QEO_ABZ_LINE_WIDTH_LINE_SHIFT) |
| #define QEO_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL) |
| #define QEO_ABZ_LINE_WIDTH_LINE_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_LINE_WIDTH_LINE_SHIFT) & QEO_ABZ_LINE_WIDTH_LINE_MASK) |
| #define QEO_ABZ_LINE_WIDTH_LINE_SHIFT (0U) |
| #define QEO_ABZ_MODE_A_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_A_POLARITY_MASK) >> QEO_ABZ_MODE_A_POLARITY_SHIFT) |
| #define QEO_ABZ_MODE_A_POLARITY_MASK (0x1000U) |
| #define QEO_ABZ_MODE_A_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_A_POLARITY_SHIFT) & QEO_ABZ_MODE_A_POLARITY_MASK) |
| #define QEO_ABZ_MODE_A_POLARITY_SHIFT (12U) |
| #define QEO_ABZ_MODE_A_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_A_TYPE_MASK) >> QEO_ABZ_MODE_A_TYPE_SHIFT) |
| #define QEO_ABZ_MODE_A_TYPE_MASK (0x3U) |
| #define QEO_ABZ_MODE_A_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_A_TYPE_SHIFT) & QEO_ABZ_MODE_A_TYPE_MASK) |
| #define QEO_ABZ_MODE_A_TYPE_SHIFT (0U) |
| #define QEO_ABZ_MODE_B_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_B_POLARITY_MASK) >> QEO_ABZ_MODE_B_POLARITY_SHIFT) |
| #define QEO_ABZ_MODE_B_POLARITY_MASK (0x10000UL) |
| #define QEO_ABZ_MODE_B_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_B_POLARITY_SHIFT) & QEO_ABZ_MODE_B_POLARITY_MASK) |
| #define QEO_ABZ_MODE_B_POLARITY_SHIFT (16U) |
| #define QEO_ABZ_MODE_B_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_B_TYPE_MASK) >> QEO_ABZ_MODE_B_TYPE_SHIFT) |
| #define QEO_ABZ_MODE_B_TYPE_MASK (0x30U) |
| #define QEO_ABZ_MODE_B_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_B_TYPE_SHIFT) & QEO_ABZ_MODE_B_TYPE_MASK) |
| #define QEO_ABZ_MODE_B_TYPE_SHIFT (4U) |
| #define QEO_ABZ_MODE_EN_WDOG_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_EN_WDOG_MASK) >> QEO_ABZ_MODE_EN_WDOG_SHIFT) |
| #define QEO_ABZ_MODE_EN_WDOG_MASK (0x1000000UL) |
| #define QEO_ABZ_MODE_EN_WDOG_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_EN_WDOG_SHIFT) & QEO_ABZ_MODE_EN_WDOG_MASK) |
| #define QEO_ABZ_MODE_EN_WDOG_SHIFT (24U) |
| #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) |
| #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL) |
| #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) |
| #define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U) |
| #define QEO_ABZ_MODE_Z_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_Z_POLARITY_MASK) >> QEO_ABZ_MODE_Z_POLARITY_SHIFT) |
| #define QEO_ABZ_MODE_Z_POLARITY_MASK (0x100000UL) |
| #define QEO_ABZ_MODE_Z_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_Z_POLARITY_SHIFT) & QEO_ABZ_MODE_Z_POLARITY_MASK) |
| #define QEO_ABZ_MODE_Z_POLARITY_SHIFT (20U) |
| #define QEO_ABZ_MODE_Z_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_MODE_Z_TYPE_MASK) >> QEO_ABZ_MODE_Z_TYPE_SHIFT) |
| #define QEO_ABZ_MODE_Z_TYPE_MASK (0x300U) |
| #define QEO_ABZ_MODE_Z_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_MODE_Z_TYPE_SHIFT) & QEO_ABZ_MODE_Z_TYPE_MASK) |
| #define QEO_ABZ_MODE_Z_TYPE_SHIFT (8U) |
| #define QEO_ABZ_PHASE_SHIFT_A (0UL) |
| #define QEO_ABZ_PHASE_SHIFT_B (1UL) |
| #define QEO_ABZ_PHASE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) >> QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) |
| #define QEO_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFU) |
| #define QEO_ABZ_PHASE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) |
| #define QEO_ABZ_PHASE_SHIFT_VAL_SHIFT (0U) |
| #define QEO_ABZ_PHASE_SHIFT_Z (2UL) |
| #define QEO_ABZ_POSTION_SYNC_POSTION_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) >> QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) |
| #define QEO_ABZ_POSTION_SYNC_POSTION_MASK (0x1U) |
| #define QEO_ABZ_POSTION_SYNC_POSTION_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) |
| #define QEO_ABZ_POSTION_SYNC_POSTION_SHIFT (0U) |
| #define QEO_ABZ_RESOLUTION_LINES_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_RESOLUTION_LINES_MASK) >> QEO_ABZ_RESOLUTION_LINES_SHIFT) |
| #define QEO_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) |
| #define QEO_ABZ_RESOLUTION_LINES_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_RESOLUTION_LINES_SHIFT) & QEO_ABZ_RESOLUTION_LINES_MASK) |
| #define QEO_ABZ_RESOLUTION_LINES_SHIFT (0U) |
| #define QEO_ABZ_WDOG_WIDTH_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) |
| #define QEO_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL) |
| #define QEO_ABZ_WDOG_WIDTH_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) |
| #define QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U) |
| #define QEO_DEBUG0_WAVE0_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG0_WAVE0_MASK) >> QEO_DEBUG0_WAVE0_SHIFT) |
| #define QEO_DEBUG0_WAVE0_MASK (0xFFFFU) |
| #define QEO_DEBUG0_WAVE0_SHIFT (0U) |
| #define QEO_DEBUG0_WAVE1_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG0_WAVE1_MASK) >> QEO_DEBUG0_WAVE1_SHIFT) |
| #define QEO_DEBUG0_WAVE1_MASK (0xFFFF0000UL) |
| #define QEO_DEBUG0_WAVE1_SHIFT (16U) |
| #define QEO_DEBUG1_QEO_FINISH_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG1_QEO_FINISH_MASK) >> QEO_DEBUG1_QEO_FINISH_SHIFT) |
| #define QEO_DEBUG1_QEO_FINISH_MASK (0x10000000UL) |
| #define QEO_DEBUG1_QEO_FINISH_SHIFT (28U) |
| #define QEO_DEBUG1_WAVE2_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG1_WAVE2_MASK) >> QEO_DEBUG1_WAVE2_SHIFT) |
| #define QEO_DEBUG1_WAVE2_MASK (0xFFFFU) |
| #define QEO_DEBUG1_WAVE2_SHIFT (0U) |
| #define QEO_DEBUG1_WAVE_A_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG1_WAVE_A_MASK) >> QEO_DEBUG1_WAVE_A_SHIFT) |
| #define QEO_DEBUG1_WAVE_A_MASK (0x10000UL) |
| #define QEO_DEBUG1_WAVE_A_SHIFT (16U) |
| #define QEO_DEBUG1_WAVE_B_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG1_WAVE_B_MASK) >> QEO_DEBUG1_WAVE_B_SHIFT) |
| #define QEO_DEBUG1_WAVE_B_MASK (0x100000UL) |
| #define QEO_DEBUG1_WAVE_B_SHIFT (20U) |
| #define QEO_DEBUG1_WAVE_Z_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG1_WAVE_Z_MASK) >> QEO_DEBUG1_WAVE_Z_SHIFT) |
| #define QEO_DEBUG1_WAVE_Z_MASK (0x1000000UL) |
| #define QEO_DEBUG1_WAVE_Z_SHIFT (24U) |
| #define QEO_DEBUG2_ABZ_OWN_POSTION_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT) |
| #define QEO_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) |
| #define QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U) |
| #define QEO_DEBUG3_ABZ_OWN_POSTION_GET | ( | x | ) | (((uint32_t)(x) & QEO_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT) |
| #define QEO_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) |
| #define QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U) |
| #define QEO_LIMIT_WAVE0 (0UL) |
| #define QEO_LIMIT_WAVE1 (1UL) |
| #define QEO_LIMIT_WAVE2 (2UL) |
| #define QEO_POSTION_SEL_POSTION_SEL_GET | ( | x | ) | (((uint32_t)(x) & QEO_POSTION_SEL_POSTION_SEL_MASK) >> QEO_POSTION_SEL_POSTION_SEL_SHIFT) |
| #define QEO_POSTION_SEL_POSTION_SEL_MASK (0x1U) |
| #define QEO_POSTION_SEL_POSTION_SEL_SET | ( | x | ) | (((uint32_t)(x) << QEO_POSTION_SEL_POSTION_SEL_SHIFT) & QEO_POSTION_SEL_POSTION_SEL_MASK) |
| #define QEO_POSTION_SEL_POSTION_SEL_SHIFT (0U) |
| #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET | ( | x | ) | (((uint32_t)(x) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) |
| #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL) |
| #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET | ( | x | ) | (((uint32_t)(x) << QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) |
| #define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U) |
| #define QEO_PWM_MODE_PHASE_NUM_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PHASE_NUM_MASK) >> QEO_PWM_MODE_PHASE_NUM_SHIFT) |
| #define QEO_PWM_MODE_PHASE_NUM_MASK (0xFU) |
| #define QEO_PWM_MODE_PHASE_NUM_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PHASE_NUM_SHIFT) & QEO_PWM_MODE_PHASE_NUM_MASK) |
| #define QEO_PWM_MODE_PHASE_NUM_SHIFT (0U) |
| #define QEO_PWM_MODE_PWM0_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM0_SAFETY_MASK) >> QEO_PWM_MODE_PWM0_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL) |
| #define QEO_PWM_MODE_PWM0_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM0_SAFETY_SHIFT) & QEO_PWM_MODE_PWM0_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM0_SAFETY_SHIFT (16U) |
| #define QEO_PWM_MODE_PWM1_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM1_SAFETY_MASK) >> QEO_PWM_MODE_PWM1_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL) |
| #define QEO_PWM_MODE_PWM1_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM1_SAFETY_SHIFT) & QEO_PWM_MODE_PWM1_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM1_SAFETY_SHIFT (18U) |
| #define QEO_PWM_MODE_PWM2_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM2_SAFETY_MASK) >> QEO_PWM_MODE_PWM2_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL) |
| #define QEO_PWM_MODE_PWM2_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM2_SAFETY_SHIFT) & QEO_PWM_MODE_PWM2_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM2_SAFETY_SHIFT (20U) |
| #define QEO_PWM_MODE_PWM3_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM3_SAFETY_MASK) >> QEO_PWM_MODE_PWM3_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL) |
| #define QEO_PWM_MODE_PWM3_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM3_SAFETY_SHIFT) & QEO_PWM_MODE_PWM3_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM3_SAFETY_SHIFT (22U) |
| #define QEO_PWM_MODE_PWM4_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM4_SAFETY_MASK) >> QEO_PWM_MODE_PWM4_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL) |
| #define QEO_PWM_MODE_PWM4_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM4_SAFETY_SHIFT) & QEO_PWM_MODE_PWM4_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM4_SAFETY_SHIFT (24U) |
| #define QEO_PWM_MODE_PWM5_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM5_SAFETY_MASK) >> QEO_PWM_MODE_PWM5_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL) |
| #define QEO_PWM_MODE_PWM5_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM5_SAFETY_SHIFT) & QEO_PWM_MODE_PWM5_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM5_SAFETY_SHIFT (26U) |
| #define QEO_PWM_MODE_PWM6_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM6_SAFETY_MASK) >> QEO_PWM_MODE_PWM6_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL) |
| #define QEO_PWM_MODE_PWM6_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM6_SAFETY_SHIFT) & QEO_PWM_MODE_PWM6_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM6_SAFETY_SHIFT (28U) |
| #define QEO_PWM_MODE_PWM7_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM7_SAFETY_MASK) >> QEO_PWM_MODE_PWM7_SAFETY_SHIFT) |
| #define QEO_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL) |
| #define QEO_PWM_MODE_PWM7_SAFETY_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM7_SAFETY_SHIFT) & QEO_PWM_MODE_PWM7_SAFETY_MASK) |
| #define QEO_PWM_MODE_PWM7_SAFETY_SHIFT (30U) |
| #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) |
| #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U) |
| #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) |
| #define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U) |
| #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) |
| #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U) |
| #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) |
| #define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U) |
| #define QEO_PWM_MODE_REVISE_UP_DN_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_MODE_REVISE_UP_DN_MASK) >> QEO_PWM_MODE_REVISE_UP_DN_SHIFT) |
| #define QEO_PWM_MODE_REVISE_UP_DN_MASK (0x10U) |
| #define QEO_PWM_MODE_REVISE_UP_DN_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_MODE_REVISE_UP_DN_SHIFT) & QEO_PWM_MODE_REVISE_UP_DN_MASK) |
| #define QEO_PWM_MODE_REVISE_UP_DN_SHIFT (4U) |
| #define QEO_PWM_PHASE_SHIFT_A (0UL) |
| #define QEO_PWM_PHASE_SHIFT_B (1UL) |
| #define QEO_PWM_PHASE_SHIFT_C (2UL) |
| #define QEO_PWM_PHASE_SHIFT_D (3UL) |
| #define QEO_PWM_PHASE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_SHIFT_VAL_MASK) >> QEO_PWM_PHASE_SHIFT_VAL_SHIFT) |
| #define QEO_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFU) |
| #define QEO_PWM_PHASE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_SHIFT_VAL_SHIFT) & QEO_PWM_PHASE_SHIFT_VAL_MASK) |
| #define QEO_PWM_PHASE_SHIFT_VAL_SHIFT (0U) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE0 (12UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE1 (13UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE10 (22UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE11 (23UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE2 (14UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE3 (15UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE4 (16UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE5 (17UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE6 (18UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE7 (19UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE8 (20UL) |
| #define QEO_PWM_PHASE_TABLE_NEGEDGE9 (21UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE0 (0UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE1 (1UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE10 (10UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE11 (11UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE2 (2UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE3 (3UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE4 (4UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE5 (5UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE6 (6UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE7 (7UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE8 (8UL) |
| #define QEO_PWM_PHASE_TABLE_POSEDGE9 (9UL) |
| #define QEO_PWM_PHASE_TABLE_PWM0_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM0_MASK) >> QEO_PWM_PHASE_TABLE_PWM0_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM0_MASK (0x3U) |
| #define QEO_PWM_PHASE_TABLE_PWM0_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM0_SHIFT) & QEO_PWM_PHASE_TABLE_PWM0_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM0_SHIFT (0U) |
| #define QEO_PWM_PHASE_TABLE_PWM1_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM1_MASK) >> QEO_PWM_PHASE_TABLE_PWM1_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM1_MASK (0xCU) |
| #define QEO_PWM_PHASE_TABLE_PWM1_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM1_SHIFT) & QEO_PWM_PHASE_TABLE_PWM1_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM1_SHIFT (2U) |
| #define QEO_PWM_PHASE_TABLE_PWM2_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM2_MASK) >> QEO_PWM_PHASE_TABLE_PWM2_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM2_MASK (0x30U) |
| #define QEO_PWM_PHASE_TABLE_PWM2_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM2_SHIFT) & QEO_PWM_PHASE_TABLE_PWM2_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM2_SHIFT (4U) |
| #define QEO_PWM_PHASE_TABLE_PWM3_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM3_MASK) >> QEO_PWM_PHASE_TABLE_PWM3_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM3_MASK (0xC0U) |
| #define QEO_PWM_PHASE_TABLE_PWM3_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM3_SHIFT) & QEO_PWM_PHASE_TABLE_PWM3_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM3_SHIFT (6U) |
| #define QEO_PWM_PHASE_TABLE_PWM4_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM4_MASK) >> QEO_PWM_PHASE_TABLE_PWM4_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM4_MASK (0x300U) |
| #define QEO_PWM_PHASE_TABLE_PWM4_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM4_SHIFT) & QEO_PWM_PHASE_TABLE_PWM4_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM4_SHIFT (8U) |
| #define QEO_PWM_PHASE_TABLE_PWM5_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM5_MASK) >> QEO_PWM_PHASE_TABLE_PWM5_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM5_MASK (0xC00U) |
| #define QEO_PWM_PHASE_TABLE_PWM5_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM5_SHIFT) & QEO_PWM_PHASE_TABLE_PWM5_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM5_SHIFT (10U) |
| #define QEO_PWM_PHASE_TABLE_PWM6_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM6_MASK) >> QEO_PWM_PHASE_TABLE_PWM6_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM6_MASK (0x3000U) |
| #define QEO_PWM_PHASE_TABLE_PWM6_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM6_SHIFT) & QEO_PWM_PHASE_TABLE_PWM6_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM6_SHIFT (12U) |
| #define QEO_PWM_PHASE_TABLE_PWM7_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM7_MASK) >> QEO_PWM_PHASE_TABLE_PWM7_SHIFT) |
| #define QEO_PWM_PHASE_TABLE_PWM7_MASK (0xC000U) |
| #define QEO_PWM_PHASE_TABLE_PWM7_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM7_SHIFT) & QEO_PWM_PHASE_TABLE_PWM7_MASK) |
| #define QEO_PWM_PHASE_TABLE_PWM7_SHIFT (14U) |
| #define QEO_PWM_RESOLUTION_LINES_GET | ( | x | ) | (((uint32_t)(x) & QEO_PWM_RESOLUTION_LINES_MASK) >> QEO_PWM_RESOLUTION_LINES_SHIFT) |
| #define QEO_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) |
| #define QEO_PWM_RESOLUTION_LINES_SET | ( | x | ) | (((uint32_t)(x) << QEO_PWM_RESOLUTION_LINES_SHIFT) & QEO_PWM_RESOLUTION_LINES_MASK) |
| #define QEO_PWM_RESOLUTION_LINES_SHIFT (0U) |
| #define QEO_STATUS_PWM_FOURCE_GET | ( | x | ) | (((uint32_t)(x) & QEO_STATUS_PWM_FOURCE_MASK) >> QEO_STATUS_PWM_FOURCE_SHIFT) |
| #define QEO_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL) |
| #define QEO_STATUS_PWM_FOURCE_SHIFT (16U) |
| #define QEO_STATUS_PWM_SAFETY_GET | ( | x | ) | (((uint32_t)(x) & QEO_STATUS_PWM_SAFETY_MASK) >> QEO_STATUS_PWM_SAFETY_SHIFT) |
| #define QEO_STATUS_PWM_SAFETY_MASK (0x1U) |
| #define QEO_STATUS_PWM_SAFETY_SHIFT (0U) |
| #define QEO_WAVE_AMPLITUDE_AMP_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) |
| #define QEO_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU) |
| #define QEO_WAVE_AMPLITUDE_AMP_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) |
| #define QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U) |
| #define QEO_WAVE_AMPLITUDE_EN_SCAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) |
| #define QEO_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL) |
| #define QEO_WAVE_AMPLITUDE_EN_SCAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) |
| #define QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U) |
| #define QEO_WAVE_AMPLITUDE_WAVE0 (0UL) |
| #define QEO_WAVE_AMPLITUDE_WAVE1 (1UL) |
| #define QEO_WAVE_AMPLITUDE_WAVE2 (2UL) |
| #define QEO_WAVE_DEADZONE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) |
| #define QEO_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFU) |
| #define QEO_WAVE_DEADZONE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) |
| #define QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U) |
| #define QEO_WAVE_DEADZONE_SHIFT_WAVE0 (0UL) |
| #define QEO_WAVE_DEADZONE_SHIFT_WAVE1 (1UL) |
| #define QEO_WAVE_DEADZONE_SHIFT_WAVE2 (2UL) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT0_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT0_MASK (0xFFFFU) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT0_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT (0U) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT1_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT1_MASK (0xFFFF0000UL) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT1_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) |
| #define QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT (16U) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT0_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT0_MASK (0xFFFFU) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT0_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT (0U) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT1_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT1_MASK (0xFFFF0000UL) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT1_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) |
| #define QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT (16U) |
| #define QEO_WAVE_MID_POINT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MID_POINT_VAL_MASK) >> QEO_WAVE_MID_POINT_VAL_SHIFT) |
| #define QEO_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL) |
| #define QEO_WAVE_MID_POINT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MID_POINT_VAL_SHIFT) & QEO_WAVE_MID_POINT_VAL_MASK) |
| #define QEO_WAVE_MID_POINT_VAL_SHIFT (0U) |
| #define QEO_WAVE_MID_POINT_WAVE0 (0UL) |
| #define QEO_WAVE_MID_POINT_WAVE1 (1UL) |
| #define QEO_WAVE_MID_POINT_WAVE2 (2UL) |
| #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) |
| #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK (0x10U) |
| #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) |
| #define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT (4U) |
| #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) |
| #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK (0x20U) |
| #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) |
| #define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT (5U) |
| #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) |
| #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK (0x40U) |
| #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) |
| #define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT (6U) |
| #define QEO_WAVE_MODE_SADDLE_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) >> QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) |
| #define QEO_WAVE_MODE_SADDLE_TYPE_MASK (0x80U) |
| #define QEO_WAVE_MODE_SADDLE_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) |
| #define QEO_WAVE_MODE_SADDLE_TYPE_SHIFT (7U) |
| #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U) |
| #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U) |
| #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U) |
| #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U) |
| #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL) |
| #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U) |
| #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL) |
| #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U) |
| #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL) |
| #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U) |
| #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL) |
| #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) |
| #define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U) |
| #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) |
| #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U) |
| #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) |
| #define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U) |
| #define QEO_WAVE_PHASE_SHIFT_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) >> QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) |
| #define QEO_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFU) |
| #define QEO_WAVE_PHASE_SHIFT_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) |
| #define QEO_WAVE_PHASE_SHIFT_VAL_SHIFT (0U) |
| #define QEO_WAVE_PHASE_SHIFT_WAVE0 (0UL) |
| #define QEO_WAVE_PHASE_SHIFT_WAVE1 (1UL) |
| #define QEO_WAVE_PHASE_SHIFT_WAVE2 (2UL) |
| #define QEO_WAVE_RESOLUTION_LINES_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_RESOLUTION_LINES_MASK) >> QEO_WAVE_RESOLUTION_LINES_SHIFT) |
| #define QEO_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) |
| #define QEO_WAVE_RESOLUTION_LINES_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_RESOLUTION_LINES_SHIFT) & QEO_WAVE_RESOLUTION_LINES_MASK) |
| #define QEO_WAVE_RESOLUTION_LINES_SHIFT (0U) |
| #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) |
| #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK (0xFFFFU) |
| #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) |
| #define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT (0U) |
| #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) |
| #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK (0xFFFF0000UL) |
| #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) |
| #define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT (16U) |
| #define QEO_WAVE_VD_VQ_INJECT_WAVE0 (0UL) |
| #define QEO_WAVE_VD_VQ_INJECT_WAVE1 (1UL) |
| #define QEO_WAVE_VD_VQ_INJECT_WAVE2 (2UL) |
| #define QEO_WAVE_VD_VQ_LOAD_LOAD_GET | ( | x | ) | (((uint32_t)(x) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) |
| #define QEO_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U) |
| #define QEO_WAVE_VD_VQ_LOAD_LOAD_SET | ( | x | ) | (((uint32_t)(x) << QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) |
| #define QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U) |