HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_smix_regs.h File Reference

Go to the source code of this file.

Data Structures

struct  SMIX_Type
 

Macros

#define SMIX_DMAC_ID_REV_MASK   (0x7FFFFUL)
 
#define SMIX_DMAC_ID_REV_SHIFT   (0U)
 
#define SMIX_DMAC_ID_REV_GET(x)   (((uint32_t)(x) & SMIX_DMAC_ID_REV_MASK) >> SMIX_DMAC_ID_REV_SHIFT)
 
#define SMIX_DMAC_TC_ST_CH_MASK   (0x3FFFFFFUL)
 
#define SMIX_DMAC_TC_ST_CH_SHIFT   (0U)
 
#define SMIX_DMAC_TC_ST_CH_SET(x)   (((uint32_t)(x) << SMIX_DMAC_TC_ST_CH_SHIFT) & SMIX_DMAC_TC_ST_CH_MASK)
 
#define SMIX_DMAC_TC_ST_CH_GET(x)   (((uint32_t)(x) & SMIX_DMAC_TC_ST_CH_MASK) >> SMIX_DMAC_TC_ST_CH_SHIFT)
 
#define SMIX_DMAC_ABRT_ST_CH_MASK   (0x3FFFFFFUL)
 
#define SMIX_DMAC_ABRT_ST_CH_SHIFT   (0U)
 
#define SMIX_DMAC_ABRT_ST_CH_SET(x)   (((uint32_t)(x) << SMIX_DMAC_ABRT_ST_CH_SHIFT) & SMIX_DMAC_ABRT_ST_CH_MASK)
 
#define SMIX_DMAC_ABRT_ST_CH_GET(x)   (((uint32_t)(x) & SMIX_DMAC_ABRT_ST_CH_MASK) >> SMIX_DMAC_ABRT_ST_CH_SHIFT)
 
#define SMIX_DMAC_ERR_ST_CH_MASK   (0x3FFFFFFUL)
 
#define SMIX_DMAC_ERR_ST_CH_SHIFT   (0U)
 
#define SMIX_DMAC_ERR_ST_CH_SET(x)   (((uint32_t)(x) << SMIX_DMAC_ERR_ST_CH_SHIFT) & SMIX_DMAC_ERR_ST_CH_MASK)
 
#define SMIX_DMAC_ERR_ST_CH_GET(x)   (((uint32_t)(x) & SMIX_DMAC_ERR_ST_CH_MASK) >> SMIX_DMAC_ERR_ST_CH_SHIFT)
 
#define SMIX_DMAC_CTRL_SRST_MASK   (0x1U)
 
#define SMIX_DMAC_CTRL_SRST_SHIFT   (0U)
 
#define SMIX_DMAC_CTRL_SRST_SET(x)   (((uint32_t)(x) << SMIX_DMAC_CTRL_SRST_SHIFT) & SMIX_DMAC_CTRL_SRST_MASK)
 
#define SMIX_DMAC_CTRL_SRST_GET(x)   (((uint32_t)(x) & SMIX_DMAC_CTRL_SRST_MASK) >> SMIX_DMAC_CTRL_SRST_SHIFT)
 
#define SMIX_DMAC_ABRT_CMD_CH_MASK   (0x3FFFFFFUL)
 
#define SMIX_DMAC_ABRT_CMD_CH_SHIFT   (0U)
 
#define SMIX_DMAC_ABRT_CMD_CH_SET(x)   (((uint32_t)(x) << SMIX_DMAC_ABRT_CMD_CH_SHIFT) & SMIX_DMAC_ABRT_CMD_CH_MASK)
 
#define SMIX_DMAC_ABRT_CMD_CH_GET(x)   (((uint32_t)(x) & SMIX_DMAC_ABRT_CMD_CH_MASK) >> SMIX_DMAC_ABRT_CMD_CH_SHIFT)
 
#define SMIX_DMAC_CHEN_CH_MASK   (0x3FFFFFFUL)
 
#define SMIX_DMAC_CHEN_CH_SHIFT   (0U)
 
#define SMIX_DMAC_CHEN_CH_GET(x)   (((uint32_t)(x) & SMIX_DMAC_CHEN_CH_MASK) >> SMIX_DMAC_CHEN_CH_SHIFT)
 
#define SMIX_DMA_CH_CTL_SRCREQSEL_MASK   (0x7C000000UL)
 
#define SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT   (26U)
 
#define SMIX_DMA_CH_CTL_SRCREQSEL_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK)
 
#define SMIX_DMA_CH_CTL_SRCREQSEL_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) >> SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT)
 
#define SMIX_DMA_CH_CTL_DSTREQSEL_MASK   (0x3E00000UL)
 
#define SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT   (21U)
 
#define SMIX_DMA_CH_CTL_DSTREQSEL_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK)
 
#define SMIX_DMA_CH_CTL_DSTREQSEL_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) >> SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT)
 
#define SMIX_DMA_CH_CTL_PRIORITY_MASK   (0x80000UL)
 
#define SMIX_DMA_CH_CTL_PRIORITY_SHIFT   (19U)
 
#define SMIX_DMA_CH_CTL_PRIORITY_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_PRIORITY_SHIFT) & SMIX_DMA_CH_CTL_PRIORITY_MASK)
 
#define SMIX_DMA_CH_CTL_PRIORITY_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_PRIORITY_MASK) >> SMIX_DMA_CH_CTL_PRIORITY_SHIFT)
 
#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK   (0x78000UL)
 
#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT   (15U)
 
#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK)
 
#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) >> SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT)
 
#define SMIX_DMA_CH_CTL_SRCWIDTH_MASK   (0x6000U)
 
#define SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT   (13U)
 
#define SMIX_DMA_CH_CTL_SRCWIDTH_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK)
 
#define SMIX_DMA_CH_CTL_SRCWIDTH_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) >> SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT)
 
#define SMIX_DMA_CH_CTL_DSTWIDTH_MASK   (0x1800U)
 
#define SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT   (11U)
 
#define SMIX_DMA_CH_CTL_DSTWIDTH_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK)
 
#define SMIX_DMA_CH_CTL_DSTWIDTH_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) >> SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT)
 
#define SMIX_DMA_CH_CTL_SRCMODE_MASK   (0x400U)
 
#define SMIX_DMA_CH_CTL_SRCMODE_SHIFT   (10U)
 
#define SMIX_DMA_CH_CTL_SRCMODE_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCMODE_SHIFT) & SMIX_DMA_CH_CTL_SRCMODE_MASK)
 
#define SMIX_DMA_CH_CTL_SRCMODE_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCMODE_MASK) >> SMIX_DMA_CH_CTL_SRCMODE_SHIFT)
 
#define SMIX_DMA_CH_CTL_DSTMODE_MASK   (0x200U)
 
#define SMIX_DMA_CH_CTL_DSTMODE_SHIFT   (9U)
 
#define SMIX_DMA_CH_CTL_DSTMODE_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTMODE_SHIFT) & SMIX_DMA_CH_CTL_DSTMODE_MASK)
 
#define SMIX_DMA_CH_CTL_DSTMODE_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTMODE_MASK) >> SMIX_DMA_CH_CTL_DSTMODE_SHIFT)
 
#define SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK   (0x180U)
 
#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT   (7U)
 
#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK)
 
#define SMIX_DMA_CH_CTL_SRCADDRCTRL_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT)
 
#define SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK   (0x60U)
 
#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT   (5U)
 
#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK)
 
#define SMIX_DMA_CH_CTL_DSTADDRCTRL_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT)
 
#define SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK   (0x8U)
 
#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT   (3U)
 
#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK)
 
#define SMIX_DMA_CH_CTL_ABRT_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT)
 
#define SMIX_DMA_CH_CTL_ERR_INT_EN_MASK   (0x4U)
 
#define SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT   (2U)
 
#define SMIX_DMA_CH_CTL_ERR_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK)
 
#define SMIX_DMA_CH_CTL_ERR_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT)
 
#define SMIX_DMA_CH_CTL_TC_INT_EN_MASK   (0x2U)
 
#define SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT   (1U)
 
#define SMIX_DMA_CH_CTL_TC_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK)
 
#define SMIX_DMA_CH_CTL_TC_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) >> SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT)
 
#define SMIX_DMA_CH_CTL_EN_MASK   (0x1U)
 
#define SMIX_DMA_CH_CTL_EN_SHIFT   (0U)
 
#define SMIX_DMA_CH_CTL_EN_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_CTL_EN_SHIFT) & SMIX_DMA_CH_CTL_EN_MASK)
 
#define SMIX_DMA_CH_CTL_EN_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_CTL_EN_MASK) >> SMIX_DMA_CH_CTL_EN_SHIFT)
 
#define SMIX_DMA_CH_BURST_COUNT_NUM_MASK   (0xFFFFFFFFUL)
 
#define SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT   (0U)
 
#define SMIX_DMA_CH_BURST_COUNT_NUM_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK)
 
#define SMIX_DMA_CH_BURST_COUNT_NUM_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) >> SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT)
 
#define SMIX_DMA_CH_SRCADDR_PTR_MASK   (0xFFFFFFFFUL)
 
#define SMIX_DMA_CH_SRCADDR_PTR_SHIFT   (0U)
 
#define SMIX_DMA_CH_SRCADDR_PTR_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_SRCADDR_PTR_SHIFT) & SMIX_DMA_CH_SRCADDR_PTR_MASK)
 
#define SMIX_DMA_CH_SRCADDR_PTR_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_SRCADDR_PTR_MASK) >> SMIX_DMA_CH_SRCADDR_PTR_SHIFT)
 
#define SMIX_DMA_CH_DSTADDR_PTR_MASK   (0xFFFFFFFFUL)
 
#define SMIX_DMA_CH_DSTADDR_PTR_SHIFT   (0U)
 
#define SMIX_DMA_CH_DSTADDR_PTR_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_DSTADDR_PTR_SHIFT) & SMIX_DMA_CH_DSTADDR_PTR_MASK)
 
#define SMIX_DMA_CH_DSTADDR_PTR_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_DSTADDR_PTR_MASK) >> SMIX_DMA_CH_DSTADDR_PTR_SHIFT)
 
#define SMIX_DMA_CH_LLP_PTR_MASK   (0xFFFFFFFFUL)
 
#define SMIX_DMA_CH_LLP_PTR_SHIFT   (0U)
 
#define SMIX_DMA_CH_LLP_PTR_SET(x)   (((uint32_t)(x) << SMIX_DMA_CH_LLP_PTR_SHIFT) & SMIX_DMA_CH_LLP_PTR_MASK)
 
#define SMIX_DMA_CH_LLP_PTR_GET(x)   (((uint32_t)(x) & SMIX_DMA_CH_LLP_PTR_MASK) >> SMIX_DMA_CH_LLP_PTR_SHIFT)
 
#define SMIX_CALSAT_ST_DST_MASK   (0xC0000000UL)
 
#define SMIX_CALSAT_ST_DST_SHIFT   (30U)
 
#define SMIX_CALSAT_ST_DST_SET(x)   (((uint32_t)(x) << SMIX_CALSAT_ST_DST_SHIFT) & SMIX_CALSAT_ST_DST_MASK)
 
#define SMIX_CALSAT_ST_DST_GET(x)   (((uint32_t)(x) & SMIX_CALSAT_ST_DST_MASK) >> SMIX_CALSAT_ST_DST_SHIFT)
 
#define SMIX_CALSAT_ST_SRC_MASK   (0x3FFFU)
 
#define SMIX_CALSAT_ST_SRC_SHIFT   (0U)
 
#define SMIX_CALSAT_ST_SRC_SET(x)   (((uint32_t)(x) << SMIX_CALSAT_ST_SRC_SHIFT) & SMIX_CALSAT_ST_SRC_MASK)
 
#define SMIX_CALSAT_ST_SRC_GET(x)   (((uint32_t)(x) & SMIX_CALSAT_ST_SRC_MASK) >> SMIX_CALSAT_ST_SRC_SHIFT)
 
#define SMIX_FDOT_DONE_ST_DST_MASK   (0xC0000000UL)
 
#define SMIX_FDOT_DONE_ST_DST_SHIFT   (30U)
 
#define SMIX_FDOT_DONE_ST_DST_SET(x)   (((uint32_t)(x) << SMIX_FDOT_DONE_ST_DST_SHIFT) & SMIX_FDOT_DONE_ST_DST_MASK)
 
#define SMIX_FDOT_DONE_ST_DST_GET(x)   (((uint32_t)(x) & SMIX_FDOT_DONE_ST_DST_MASK) >> SMIX_FDOT_DONE_ST_DST_SHIFT)
 
#define SMIX_FDOT_DONE_ST_SRC_MASK   (0x3FFFU)
 
#define SMIX_FDOT_DONE_ST_SRC_SHIFT   (0U)
 
#define SMIX_FDOT_DONE_ST_SRC_SET(x)   (((uint32_t)(x) << SMIX_FDOT_DONE_ST_SRC_SHIFT) & SMIX_FDOT_DONE_ST_SRC_MASK)
 
#define SMIX_FDOT_DONE_ST_SRC_GET(x)   (((uint32_t)(x) & SMIX_FDOT_DONE_ST_SRC_MASK) >> SMIX_FDOT_DONE_ST_SRC_SHIFT)
 
#define SMIX_DATA_ST_DST_DA_MASK   (0xC0000000UL)
 
#define SMIX_DATA_ST_DST_DA_SHIFT   (30U)
 
#define SMIX_DATA_ST_DST_DA_GET(x)   (((uint32_t)(x) & SMIX_DATA_ST_DST_DA_MASK) >> SMIX_DATA_ST_DST_DA_SHIFT)
 
#define SMIX_DATA_ST_DST_UNDL_MASK   (0x30000000UL)
 
#define SMIX_DATA_ST_DST_UNDL_SHIFT   (28U)
 
#define SMIX_DATA_ST_DST_UNDL_GET(x)   (((uint32_t)(x) & SMIX_DATA_ST_DST_UNDL_MASK) >> SMIX_DATA_ST_DST_UNDL_SHIFT)
 
#define SMIX_DATA_ST_SRC_DN_MASK   (0x3FFFU)
 
#define SMIX_DATA_ST_SRC_DN_SHIFT   (0U)
 
#define SMIX_DATA_ST_SRC_DN_GET(x)   (((uint32_t)(x) & SMIX_DATA_ST_SRC_DN_MASK) >> SMIX_DATA_ST_SRC_DN_SHIFT)
 
#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK   (0x100000UL)
 
#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT   (20U)
 
#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK)
 
#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) >> SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT)
 
#define SMIX_DST_CH_CTRL_THRSH_MASK   (0xFF000UL)
 
#define SMIX_DST_CH_CTRL_THRSH_SHIFT   (12U)
 
#define SMIX_DST_CH_CTRL_THRSH_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_THRSH_SHIFT) & SMIX_DST_CH_CTRL_THRSH_MASK)
 
#define SMIX_DST_CH_CTRL_THRSH_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_THRSH_MASK) >> SMIX_DST_CH_CTRL_THRSH_SHIFT)
 
#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK   (0x800U)
 
#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT   (11U)
 
#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK)
 
#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT)
 
#define SMIX_DST_CH_CTRL_DA_INT_EN_MASK   (0x400U)
 
#define SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT   (10U)
 
#define SMIX_DST_CH_CTRL_DA_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK)
 
#define SMIX_DST_CH_CTRL_DA_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) >> SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT)
 
#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK   (0x200U)
 
#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT   (9U)
 
#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK)
 
#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) >> SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT)
 
#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK   (0x100U)
 
#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT   (8U)
 
#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK)
 
#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT)
 
#define SMIX_DST_CH_CTRL_DST_DEACT_MASK   (0x80U)
 
#define SMIX_DST_CH_CTRL_DST_DEACT_SHIFT   (7U)
 
#define SMIX_DST_CH_CTRL_DST_DEACT_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) & SMIX_DST_CH_CTRL_DST_DEACT_MASK)
 
#define SMIX_DST_CH_CTRL_DST_DEACT_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) >> SMIX_DST_CH_CTRL_DST_DEACT_SHIFT)
 
#define SMIX_DST_CH_CTRL_DST_ACT_MASK   (0x40U)
 
#define SMIX_DST_CH_CTRL_DST_ACT_SHIFT   (6U)
 
#define SMIX_DST_CH_CTRL_DST_ACT_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_ACT_SHIFT) & SMIX_DST_CH_CTRL_DST_ACT_MASK)
 
#define SMIX_DST_CH_CTRL_DST_ACT_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_ACT_MASK) >> SMIX_DST_CH_CTRL_DST_ACT_SHIFT)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK   (0x20U)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT   (5U)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK   (0x10U)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT   (4U)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK)
 
#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT)
 
#define SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK   (0x8U)
 
#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT   (3U)
 
#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK)
 
#define SMIX_DST_CH_CTRL_DSTFADIN_EN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) >> SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT)
 
#define SMIX_DST_CH_CTRL_DST_EN_MASK   (0x4U)
 
#define SMIX_DST_CH_CTRL_DST_EN_SHIFT   (2U)
 
#define SMIX_DST_CH_CTRL_DST_EN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_EN_SHIFT) & SMIX_DST_CH_CTRL_DST_EN_MASK)
 
#define SMIX_DST_CH_CTRL_DST_EN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_EN_MASK) >> SMIX_DST_CH_CTRL_DST_EN_SHIFT)
 
#define SMIX_DST_CH_CTRL_SOFTRST_MASK   (0x2U)
 
#define SMIX_DST_CH_CTRL_SOFTRST_SHIFT   (1U)
 
#define SMIX_DST_CH_CTRL_SOFTRST_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_SOFTRST_SHIFT) & SMIX_DST_CH_CTRL_SOFTRST_MASK)
 
#define SMIX_DST_CH_CTRL_SOFTRST_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_SOFTRST_MASK) >> SMIX_DST_CH_CTRL_SOFTRST_SHIFT)
 
#define SMIX_DST_CH_CTRL_MIXER_EN_MASK   (0x1U)
 
#define SMIX_DST_CH_CTRL_MIXER_EN_SHIFT   (0U)
 
#define SMIX_DST_CH_CTRL_MIXER_EN_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) & SMIX_DST_CH_CTRL_MIXER_EN_MASK)
 
#define SMIX_DST_CH_CTRL_MIXER_EN_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) >> SMIX_DST_CH_CTRL_MIXER_EN_SHIFT)
 
#define SMIX_DST_CH_GAIN_VAL_MASK   (0x7FFFU)
 
#define SMIX_DST_CH_GAIN_VAL_SHIFT   (0U)
 
#define SMIX_DST_CH_GAIN_VAL_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_GAIN_VAL_SHIFT) & SMIX_DST_CH_GAIN_VAL_MASK)
 
#define SMIX_DST_CH_GAIN_VAL_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_GAIN_VAL_MASK) >> SMIX_DST_CH_GAIN_VAL_SHIFT)
 
#define SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK   (0xFFFFFFFFUL)
 
#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT   (0U)
 
#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK)
 
#define SMIX_DST_CH_BUFSIZE_MAX_IDX_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) >> SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT)
 
#define SMIX_DST_CH_FADEIN_DELTA_MASK   (0xFFFFFUL)
 
#define SMIX_DST_CH_FADEIN_DELTA_SHIFT   (0U)
 
#define SMIX_DST_CH_FADEIN_DELTA_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_FADEIN_DELTA_SHIFT) & SMIX_DST_CH_FADEIN_DELTA_MASK)
 
#define SMIX_DST_CH_FADEIN_DELTA_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_FADEIN_DELTA_MASK) >> SMIX_DST_CH_FADEIN_DELTA_SHIFT)
 
#define SMIX_DST_CH_FADEOUT_DELTA_MASK   (0xFFFFFUL)
 
#define SMIX_DST_CH_FADEOUT_DELTA_SHIFT   (0U)
 
#define SMIX_DST_CH_FADEOUT_DELTA_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_DELTA_SHIFT) & SMIX_DST_CH_FADEOUT_DELTA_MASK)
 
#define SMIX_DST_CH_FADEOUT_DELTA_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_DELTA_MASK) >> SMIX_DST_CH_FADEOUT_DELTA_SHIFT)
 
#define SMIX_DST_CH_ST_FIFO_FILLINGS_MASK   (0x7FC0U)
 
#define SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT   (6U)
 
#define SMIX_DST_CH_ST_FIFO_FILLINGS_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT)
 
#define SMIX_DST_CH_ST_FDOUT_DONE_MASK   (0x20U)
 
#define SMIX_DST_CH_ST_FDOUT_DONE_SHIFT   (5U)
 
#define SMIX_DST_CH_ST_FDOUT_DONE_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_ST_FDOUT_DONE_MASK) >> SMIX_DST_CH_ST_FDOUT_DONE_SHIFT)
 
#define SMIX_DST_CH_ST_CALSAT_MASK   (0x10U)
 
#define SMIX_DST_CH_ST_CALSAT_SHIFT   (4U)
 
#define SMIX_DST_CH_ST_CALSAT_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_ST_CALSAT_MASK) >> SMIX_DST_CH_ST_CALSAT_SHIFT)
 
#define SMIX_DST_CH_ST_DA_MASK   (0x8U)
 
#define SMIX_DST_CH_ST_DA_SHIFT   (3U)
 
#define SMIX_DST_CH_ST_DA_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_ST_DA_MASK) >> SMIX_DST_CH_ST_DA_SHIFT)
 
#define SMIX_DST_CH_ST_MODE_MASK   (0x7U)
 
#define SMIX_DST_CH_ST_MODE_SHIFT   (0U)
 
#define SMIX_DST_CH_ST_MODE_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_ST_MODE_MASK) >> SMIX_DST_CH_ST_MODE_SHIFT)
 
#define SMIX_DST_CH_DATA_VAL_MASK   (0xFFFFFFFFUL)
 
#define SMIX_DST_CH_DATA_VAL_SHIFT   (0U)
 
#define SMIX_DST_CH_DATA_VAL_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_DATA_VAL_MASK) >> SMIX_DST_CH_DATA_VAL_SHIFT)
 
#define SMIX_DST_CH_SOURCE_EN_VAL_MASK   (0xFFU)
 
#define SMIX_DST_CH_SOURCE_EN_VAL_SHIFT   (0U)
 
#define SMIX_DST_CH_SOURCE_EN_VAL_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) & SMIX_DST_CH_SOURCE_EN_VAL_MASK)
 
#define SMIX_DST_CH_SOURCE_EN_VAL_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) >> SMIX_DST_CH_SOURCE_EN_VAL_SHIFT)
 
#define SMIX_DST_CH_SOURCE_ACT_VAL_MASK   (0xFFU)
 
#define SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT   (0U)
 
#define SMIX_DST_CH_SOURCE_ACT_VAL_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK)
 
#define SMIX_DST_CH_SOURCE_ACT_VAL_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT)
 
#define SMIX_DST_CH_SOURCE_DEACT_VAL_MASK   (0xFFU)
 
#define SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT   (0U)
 
#define SMIX_DST_CH_SOURCE_DEACT_VAL_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK)
 
#define SMIX_DST_CH_SOURCE_DEACT_VAL_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT)
 
#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK   (0xFFU)
 
#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT   (0U)
 
#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK)
 
#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT)
 
#define SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK   (0x80000000UL)
 
#define SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT   (31U)
 
#define SMIX_DST_CH_DEACT_ST_DST_DEACT_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK) >> SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT)
 
#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK   (0xFFU)
 
#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT   (0U)
 
#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK) >> SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT)
 
#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK   (0xFFU)
 
#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT   (0U)
 
#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET(x)   (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK)
 
#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET(x)   (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK   (0x200000UL)
 
#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT   (21U)
 
#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK)
 
#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) >> SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_THRSH_MASK   (0x1FE000UL)
 
#define SMIX_SOURCE_CH_CTRL_THRSH_SHIFT   (13U)
 
#define SMIX_SOURCE_CH_CTRL_THRSH_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) & SMIX_SOURCE_CH_CTRL_THRSH_MASK)
 
#define SMIX_SOURCE_CH_CTRL_THRSH_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) >> SMIX_SOURCE_CH_CTRL_THRSH_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK   (0x1000U)
 
#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT   (12U)
 
#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK)
 
#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK   (0x800U)
 
#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT   (11U)
 
#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK)
 
#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK   (0x700U)
 
#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT   (8U)
 
#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK)
 
#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) >> SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK   (0x80U)
 
#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT   (7U)
 
#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK)
 
#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK   (0x40U)
 
#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT   (6U)
 
#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK)
 
#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT)
 
#define SMIX_SOURCE_CH_CTRL_RATECONV_MASK   (0x7U)
 
#define SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_CTRL_RATECONV_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK)
 
#define SMIX_SOURCE_CH_CTRL_RATECONV_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) >> SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT)
 
#define SMIX_SOURCE_CH_GAIN_VAL_MASK   (0x7FFFU)
 
#define SMIX_SOURCE_CH_GAIN_VAL_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_GAIN_VAL_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_VAL_SHIFT) & SMIX_SOURCE_CH_GAIN_VAL_MASK)
 
#define SMIX_SOURCE_CH_GAIN_VAL_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_VAL_MASK) >> SMIX_SOURCE_CH_GAIN_VAL_SHIFT)
 
#define SMIX_SOURCE_CH_FADEIN_DELTA_MASK   (0xFFFFFUL)
 
#define SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_FADEIN_DELTA_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK)
 
#define SMIX_SOURCE_CH_FADEIN_DELTA_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) >> SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT)
 
#define SMIX_SOURCE_CH_FADEOUT_DELTA_MASK   (0xFFFFFUL)
 
#define SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_FADEOUT_DELTA_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK)
 
#define SMIX_SOURCE_CH_FADEOUT_DELTA_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) >> SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT)
 
#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK   (0xFFFFFFFFUL)
 
#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK)
 
#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) >> SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT)
 
#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK   (0x7FC00UL)
 
#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT   (10U)
 
#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT)
 
#define SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK   (0x200U)
 
#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT   (9U)
 
#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK)
 
#define SMIX_SOURCE_CH_ST_FDOUT_DONE_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) >> SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT)
 
#define SMIX_SOURCE_CH_ST_CALSAT_MASK   (0x100U)
 
#define SMIX_SOURCE_CH_ST_CALSAT_SHIFT   (8U)
 
#define SMIX_SOURCE_CH_ST_CALSAT_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_ST_CALSAT_SHIFT) & SMIX_SOURCE_CH_ST_CALSAT_MASK)
 
#define SMIX_SOURCE_CH_ST_CALSAT_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_ST_CALSAT_MASK) >> SMIX_SOURCE_CH_ST_CALSAT_SHIFT)
 
#define SMIX_SOURCE_CH_ST_DN_MASK   (0x80U)
 
#define SMIX_SOURCE_CH_ST_DN_SHIFT   (7U)
 
#define SMIX_SOURCE_CH_ST_DN_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_ST_DN_MASK) >> SMIX_SOURCE_CH_ST_DN_SHIFT)
 
#define SMIX_SOURCE_CH_ST_FIRPHASE_MASK   (0x78U)
 
#define SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT   (3U)
 
#define SMIX_SOURCE_CH_ST_FIRPHASE_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIRPHASE_MASK) >> SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT)
 
#define SMIX_SOURCE_CH_ST_MODE_MASK   (0x7U)
 
#define SMIX_SOURCE_CH_ST_MODE_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_ST_MODE_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_ST_MODE_MASK) >> SMIX_SOURCE_CH_ST_MODE_SHIFT)
 
#define SMIX_SOURCE_CH_DATA_VAL_MASK   (0xFFFFFFFFUL)
 
#define SMIX_SOURCE_CH_DATA_VAL_SHIFT   (0U)
 
#define SMIX_SOURCE_CH_DATA_VAL_SET(x)   (((uint32_t)(x) << SMIX_SOURCE_CH_DATA_VAL_SHIFT) & SMIX_SOURCE_CH_DATA_VAL_MASK)
 
#define SMIX_SOURCE_CH_DATA_VAL_GET(x)   (((uint32_t)(x) & SMIX_SOURCE_CH_DATA_VAL_MASK) >> SMIX_SOURCE_CH_DATA_VAL_SHIFT)
 
#define SMIX_DMA_CH_0   (0UL)
 
#define SMIX_DMA_CH_1   (1UL)
 
#define SMIX_DMA_CH_2   (2UL)
 
#define SMIX_DMA_CH_3   (3UL)
 
#define SMIX_DMA_CH_4   (4UL)
 
#define SMIX_DMA_CH_5   (5UL)
 
#define SMIX_DMA_CH_6   (6UL)
 
#define SMIX_DMA_CH_7   (7UL)
 
#define SMIX_DMA_CH_8   (8UL)
 
#define SMIX_DMA_CH_9   (9UL)
 
#define SMIX_DMA_CH_10   (10UL)
 
#define SMIX_DMA_CH_11   (11UL)
 
#define SMIX_DMA_CH_12   (12UL)
 
#define SMIX_DMA_CH_13   (13UL)
 
#define SMIX_DMA_CH_14   (14UL)
 
#define SMIX_DMA_CH_15   (15UL)
 
#define SMIX_DMA_CH_16   (16UL)
 
#define SMIX_DMA_CH_17   (17UL)
 
#define SMIX_DMA_CH_18   (18UL)
 
#define SMIX_DMA_CH_19   (19UL)
 
#define SMIX_DMA_CH_20   (20UL)
 
#define SMIX_DMA_CH_21   (21UL)
 
#define SMIX_DMA_CH_22   (22UL)
 
#define SMIX_DMA_CH_23   (23UL)
 
#define SMIX_DMA_CH_24   (24UL)
 
#define SMIX_DMA_CH_25   (25UL)
 
#define SMIX_DST_CH_0   (0UL)
 
#define SMIX_DST_CH_1   (1UL)
 
#define SMIX_SOURCE_CH_0   (0UL)
 
#define SMIX_SOURCE_CH_1   (1UL)
 
#define SMIX_SOURCE_CH_2   (2UL)
 
#define SMIX_SOURCE_CH_3   (3UL)
 
#define SMIX_SOURCE_CH_4   (4UL)
 
#define SMIX_SOURCE_CH_5   (5UL)
 
#define SMIX_SOURCE_CH_6   (6UL)
 
#define SMIX_SOURCE_CH_7   (7UL)
 
#define SMIX_SOURCE_CH_8   (8UL)
 
#define SMIX_SOURCE_CH_9   (9UL)
 
#define SMIX_SOURCE_CH_10   (10UL)
 
#define SMIX_SOURCE_CH_11   (11UL)
 
#define SMIX_SOURCE_CH_12   (12UL)
 
#define SMIX_SOURCE_CH_13   (13UL)
 

Macro Definition Documentation

◆ SMIX_CALSAT_ST_DST_GET

#define SMIX_CALSAT_ST_DST_GET (   x)    (((uint32_t)(x) & SMIX_CALSAT_ST_DST_MASK) >> SMIX_CALSAT_ST_DST_SHIFT)

◆ SMIX_CALSAT_ST_DST_MASK

#define SMIX_CALSAT_ST_DST_MASK   (0xC0000000UL)

◆ SMIX_CALSAT_ST_DST_SET

#define SMIX_CALSAT_ST_DST_SET (   x)    (((uint32_t)(x) << SMIX_CALSAT_ST_DST_SHIFT) & SMIX_CALSAT_ST_DST_MASK)

◆ SMIX_CALSAT_ST_DST_SHIFT

#define SMIX_CALSAT_ST_DST_SHIFT   (30U)

◆ SMIX_CALSAT_ST_SRC_GET

#define SMIX_CALSAT_ST_SRC_GET (   x)    (((uint32_t)(x) & SMIX_CALSAT_ST_SRC_MASK) >> SMIX_CALSAT_ST_SRC_SHIFT)

◆ SMIX_CALSAT_ST_SRC_MASK

#define SMIX_CALSAT_ST_SRC_MASK   (0x3FFFU)

◆ SMIX_CALSAT_ST_SRC_SET

#define SMIX_CALSAT_ST_SRC_SET (   x)    (((uint32_t)(x) << SMIX_CALSAT_ST_SRC_SHIFT) & SMIX_CALSAT_ST_SRC_MASK)

◆ SMIX_CALSAT_ST_SRC_SHIFT

#define SMIX_CALSAT_ST_SRC_SHIFT   (0U)

◆ SMIX_DATA_ST_DST_DA_GET

#define SMIX_DATA_ST_DST_DA_GET (   x)    (((uint32_t)(x) & SMIX_DATA_ST_DST_DA_MASK) >> SMIX_DATA_ST_DST_DA_SHIFT)

◆ SMIX_DATA_ST_DST_DA_MASK

#define SMIX_DATA_ST_DST_DA_MASK   (0xC0000000UL)

◆ SMIX_DATA_ST_DST_DA_SHIFT

#define SMIX_DATA_ST_DST_DA_SHIFT   (30U)

◆ SMIX_DATA_ST_DST_UNDL_GET

#define SMIX_DATA_ST_DST_UNDL_GET (   x)    (((uint32_t)(x) & SMIX_DATA_ST_DST_UNDL_MASK) >> SMIX_DATA_ST_DST_UNDL_SHIFT)

◆ SMIX_DATA_ST_DST_UNDL_MASK

#define SMIX_DATA_ST_DST_UNDL_MASK   (0x30000000UL)

◆ SMIX_DATA_ST_DST_UNDL_SHIFT

#define SMIX_DATA_ST_DST_UNDL_SHIFT   (28U)

◆ SMIX_DATA_ST_SRC_DN_GET

#define SMIX_DATA_ST_SRC_DN_GET (   x)    (((uint32_t)(x) & SMIX_DATA_ST_SRC_DN_MASK) >> SMIX_DATA_ST_SRC_DN_SHIFT)

◆ SMIX_DATA_ST_SRC_DN_MASK

#define SMIX_DATA_ST_SRC_DN_MASK   (0x3FFFU)

◆ SMIX_DATA_ST_SRC_DN_SHIFT

#define SMIX_DATA_ST_SRC_DN_SHIFT   (0U)

◆ SMIX_DMA_CH_0

#define SMIX_DMA_CH_0   (0UL)

◆ SMIX_DMA_CH_1

#define SMIX_DMA_CH_1   (1UL)

◆ SMIX_DMA_CH_10

#define SMIX_DMA_CH_10   (10UL)

◆ SMIX_DMA_CH_11

#define SMIX_DMA_CH_11   (11UL)

◆ SMIX_DMA_CH_12

#define SMIX_DMA_CH_12   (12UL)

◆ SMIX_DMA_CH_13

#define SMIX_DMA_CH_13   (13UL)

◆ SMIX_DMA_CH_14

#define SMIX_DMA_CH_14   (14UL)

◆ SMIX_DMA_CH_15

#define SMIX_DMA_CH_15   (15UL)

◆ SMIX_DMA_CH_16

#define SMIX_DMA_CH_16   (16UL)

◆ SMIX_DMA_CH_17

#define SMIX_DMA_CH_17   (17UL)

◆ SMIX_DMA_CH_18

#define SMIX_DMA_CH_18   (18UL)

◆ SMIX_DMA_CH_19

#define SMIX_DMA_CH_19   (19UL)

◆ SMIX_DMA_CH_2

#define SMIX_DMA_CH_2   (2UL)

◆ SMIX_DMA_CH_20

#define SMIX_DMA_CH_20   (20UL)

◆ SMIX_DMA_CH_21

#define SMIX_DMA_CH_21   (21UL)

◆ SMIX_DMA_CH_22

#define SMIX_DMA_CH_22   (22UL)

◆ SMIX_DMA_CH_23

#define SMIX_DMA_CH_23   (23UL)

◆ SMIX_DMA_CH_24

#define SMIX_DMA_CH_24   (24UL)

◆ SMIX_DMA_CH_25

#define SMIX_DMA_CH_25   (25UL)

◆ SMIX_DMA_CH_3

#define SMIX_DMA_CH_3   (3UL)

◆ SMIX_DMA_CH_4

#define SMIX_DMA_CH_4   (4UL)

◆ SMIX_DMA_CH_5

#define SMIX_DMA_CH_5   (5UL)

◆ SMIX_DMA_CH_6

#define SMIX_DMA_CH_6   (6UL)

◆ SMIX_DMA_CH_7

#define SMIX_DMA_CH_7   (7UL)

◆ SMIX_DMA_CH_8

#define SMIX_DMA_CH_8   (8UL)

◆ SMIX_DMA_CH_9

#define SMIX_DMA_CH_9   (9UL)

◆ SMIX_DMA_CH_BURST_COUNT_NUM_GET

#define SMIX_DMA_CH_BURST_COUNT_NUM_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) >> SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT)

◆ SMIX_DMA_CH_BURST_COUNT_NUM_MASK

#define SMIX_DMA_CH_BURST_COUNT_NUM_MASK   (0xFFFFFFFFUL)

◆ SMIX_DMA_CH_BURST_COUNT_NUM_SET

#define SMIX_DMA_CH_BURST_COUNT_NUM_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK)

◆ SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT

#define SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT   (0U)

◆ SMIX_DMA_CH_CTL_ABRT_INT_EN_GET

#define SMIX_DMA_CH_CTL_ABRT_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT)

◆ SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK

#define SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK   (0x8U)

◆ SMIX_DMA_CH_CTL_ABRT_INT_EN_SET

#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK)

◆ SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT

#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT   (3U)

◆ SMIX_DMA_CH_CTL_DSTADDRCTRL_GET

#define SMIX_DMA_CH_CTL_DSTADDRCTRL_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT)

◆ SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK

#define SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK   (0x60U)

◆ SMIX_DMA_CH_CTL_DSTADDRCTRL_SET

#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK)

◆ SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT

#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT   (5U)

◆ SMIX_DMA_CH_CTL_DSTMODE_GET

#define SMIX_DMA_CH_CTL_DSTMODE_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTMODE_MASK) >> SMIX_DMA_CH_CTL_DSTMODE_SHIFT)

◆ SMIX_DMA_CH_CTL_DSTMODE_MASK

#define SMIX_DMA_CH_CTL_DSTMODE_MASK   (0x200U)

◆ SMIX_DMA_CH_CTL_DSTMODE_SET

#define SMIX_DMA_CH_CTL_DSTMODE_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTMODE_SHIFT) & SMIX_DMA_CH_CTL_DSTMODE_MASK)

◆ SMIX_DMA_CH_CTL_DSTMODE_SHIFT

#define SMIX_DMA_CH_CTL_DSTMODE_SHIFT   (9U)

◆ SMIX_DMA_CH_CTL_DSTREQSEL_GET

#define SMIX_DMA_CH_CTL_DSTREQSEL_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) >> SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT)

◆ SMIX_DMA_CH_CTL_DSTREQSEL_MASK

#define SMIX_DMA_CH_CTL_DSTREQSEL_MASK   (0x3E00000UL)

◆ SMIX_DMA_CH_CTL_DSTREQSEL_SET

#define SMIX_DMA_CH_CTL_DSTREQSEL_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK)

◆ SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT

#define SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT   (21U)

◆ SMIX_DMA_CH_CTL_DSTWIDTH_GET

#define SMIX_DMA_CH_CTL_DSTWIDTH_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) >> SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT)

◆ SMIX_DMA_CH_CTL_DSTWIDTH_MASK

#define SMIX_DMA_CH_CTL_DSTWIDTH_MASK   (0x1800U)

◆ SMIX_DMA_CH_CTL_DSTWIDTH_SET

#define SMIX_DMA_CH_CTL_DSTWIDTH_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK)

◆ SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT

#define SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT   (11U)

◆ SMIX_DMA_CH_CTL_EN_GET

#define SMIX_DMA_CH_CTL_EN_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_EN_MASK) >> SMIX_DMA_CH_CTL_EN_SHIFT)

◆ SMIX_DMA_CH_CTL_EN_MASK

#define SMIX_DMA_CH_CTL_EN_MASK   (0x1U)

◆ SMIX_DMA_CH_CTL_EN_SET

#define SMIX_DMA_CH_CTL_EN_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_EN_SHIFT) & SMIX_DMA_CH_CTL_EN_MASK)

◆ SMIX_DMA_CH_CTL_EN_SHIFT

#define SMIX_DMA_CH_CTL_EN_SHIFT   (0U)

◆ SMIX_DMA_CH_CTL_ERR_INT_EN_GET

#define SMIX_DMA_CH_CTL_ERR_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT)

◆ SMIX_DMA_CH_CTL_ERR_INT_EN_MASK

#define SMIX_DMA_CH_CTL_ERR_INT_EN_MASK   (0x4U)

◆ SMIX_DMA_CH_CTL_ERR_INT_EN_SET

#define SMIX_DMA_CH_CTL_ERR_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK)

◆ SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT

#define SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT   (2U)

◆ SMIX_DMA_CH_CTL_PRIORITY_GET

#define SMIX_DMA_CH_CTL_PRIORITY_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_PRIORITY_MASK) >> SMIX_DMA_CH_CTL_PRIORITY_SHIFT)

◆ SMIX_DMA_CH_CTL_PRIORITY_MASK

#define SMIX_DMA_CH_CTL_PRIORITY_MASK   (0x80000UL)

◆ SMIX_DMA_CH_CTL_PRIORITY_SET

#define SMIX_DMA_CH_CTL_PRIORITY_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_PRIORITY_SHIFT) & SMIX_DMA_CH_CTL_PRIORITY_MASK)

◆ SMIX_DMA_CH_CTL_PRIORITY_SHIFT

#define SMIX_DMA_CH_CTL_PRIORITY_SHIFT   (19U)

◆ SMIX_DMA_CH_CTL_SRCADDRCTRL_GET

#define SMIX_DMA_CH_CTL_SRCADDRCTRL_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT)

◆ SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK

#define SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK   (0x180U)

◆ SMIX_DMA_CH_CTL_SRCADDRCTRL_SET

#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK)

◆ SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT

#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT   (7U)

◆ SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET

#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) >> SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT)

◆ SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK

#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK   (0x78000UL)

◆ SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET

#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK)

◆ SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT

#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT   (15U)

◆ SMIX_DMA_CH_CTL_SRCMODE_GET

#define SMIX_DMA_CH_CTL_SRCMODE_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCMODE_MASK) >> SMIX_DMA_CH_CTL_SRCMODE_SHIFT)

◆ SMIX_DMA_CH_CTL_SRCMODE_MASK

#define SMIX_DMA_CH_CTL_SRCMODE_MASK   (0x400U)

◆ SMIX_DMA_CH_CTL_SRCMODE_SET

#define SMIX_DMA_CH_CTL_SRCMODE_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCMODE_SHIFT) & SMIX_DMA_CH_CTL_SRCMODE_MASK)

◆ SMIX_DMA_CH_CTL_SRCMODE_SHIFT

#define SMIX_DMA_CH_CTL_SRCMODE_SHIFT   (10U)

◆ SMIX_DMA_CH_CTL_SRCREQSEL_GET

#define SMIX_DMA_CH_CTL_SRCREQSEL_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) >> SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT)

◆ SMIX_DMA_CH_CTL_SRCREQSEL_MASK

#define SMIX_DMA_CH_CTL_SRCREQSEL_MASK   (0x7C000000UL)

◆ SMIX_DMA_CH_CTL_SRCREQSEL_SET

#define SMIX_DMA_CH_CTL_SRCREQSEL_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK)

◆ SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT

#define SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT   (26U)

◆ SMIX_DMA_CH_CTL_SRCWIDTH_GET

#define SMIX_DMA_CH_CTL_SRCWIDTH_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) >> SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT)

◆ SMIX_DMA_CH_CTL_SRCWIDTH_MASK

#define SMIX_DMA_CH_CTL_SRCWIDTH_MASK   (0x6000U)

◆ SMIX_DMA_CH_CTL_SRCWIDTH_SET

#define SMIX_DMA_CH_CTL_SRCWIDTH_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK)

◆ SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT

#define SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT   (13U)

◆ SMIX_DMA_CH_CTL_TC_INT_EN_GET

#define SMIX_DMA_CH_CTL_TC_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) >> SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT)

◆ SMIX_DMA_CH_CTL_TC_INT_EN_MASK

#define SMIX_DMA_CH_CTL_TC_INT_EN_MASK   (0x2U)

◆ SMIX_DMA_CH_CTL_TC_INT_EN_SET

#define SMIX_DMA_CH_CTL_TC_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK)

◆ SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT

#define SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT   (1U)

◆ SMIX_DMA_CH_DSTADDR_PTR_GET

#define SMIX_DMA_CH_DSTADDR_PTR_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_DSTADDR_PTR_MASK) >> SMIX_DMA_CH_DSTADDR_PTR_SHIFT)

◆ SMIX_DMA_CH_DSTADDR_PTR_MASK

#define SMIX_DMA_CH_DSTADDR_PTR_MASK   (0xFFFFFFFFUL)

◆ SMIX_DMA_CH_DSTADDR_PTR_SET

#define SMIX_DMA_CH_DSTADDR_PTR_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_DSTADDR_PTR_SHIFT) & SMIX_DMA_CH_DSTADDR_PTR_MASK)

◆ SMIX_DMA_CH_DSTADDR_PTR_SHIFT

#define SMIX_DMA_CH_DSTADDR_PTR_SHIFT   (0U)

◆ SMIX_DMA_CH_LLP_PTR_GET

#define SMIX_DMA_CH_LLP_PTR_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_LLP_PTR_MASK) >> SMIX_DMA_CH_LLP_PTR_SHIFT)

◆ SMIX_DMA_CH_LLP_PTR_MASK

#define SMIX_DMA_CH_LLP_PTR_MASK   (0xFFFFFFFFUL)

◆ SMIX_DMA_CH_LLP_PTR_SET

#define SMIX_DMA_CH_LLP_PTR_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_LLP_PTR_SHIFT) & SMIX_DMA_CH_LLP_PTR_MASK)

◆ SMIX_DMA_CH_LLP_PTR_SHIFT

#define SMIX_DMA_CH_LLP_PTR_SHIFT   (0U)

◆ SMIX_DMA_CH_SRCADDR_PTR_GET

#define SMIX_DMA_CH_SRCADDR_PTR_GET (   x)    (((uint32_t)(x) & SMIX_DMA_CH_SRCADDR_PTR_MASK) >> SMIX_DMA_CH_SRCADDR_PTR_SHIFT)

◆ SMIX_DMA_CH_SRCADDR_PTR_MASK

#define SMIX_DMA_CH_SRCADDR_PTR_MASK   (0xFFFFFFFFUL)

◆ SMIX_DMA_CH_SRCADDR_PTR_SET

#define SMIX_DMA_CH_SRCADDR_PTR_SET (   x)    (((uint32_t)(x) << SMIX_DMA_CH_SRCADDR_PTR_SHIFT) & SMIX_DMA_CH_SRCADDR_PTR_MASK)

◆ SMIX_DMA_CH_SRCADDR_PTR_SHIFT

#define SMIX_DMA_CH_SRCADDR_PTR_SHIFT   (0U)

◆ SMIX_DMAC_ABRT_CMD_CH_GET

#define SMIX_DMAC_ABRT_CMD_CH_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_ABRT_CMD_CH_MASK) >> SMIX_DMAC_ABRT_CMD_CH_SHIFT)

◆ SMIX_DMAC_ABRT_CMD_CH_MASK

#define SMIX_DMAC_ABRT_CMD_CH_MASK   (0x3FFFFFFUL)

◆ SMIX_DMAC_ABRT_CMD_CH_SET

#define SMIX_DMAC_ABRT_CMD_CH_SET (   x)    (((uint32_t)(x) << SMIX_DMAC_ABRT_CMD_CH_SHIFT) & SMIX_DMAC_ABRT_CMD_CH_MASK)

◆ SMIX_DMAC_ABRT_CMD_CH_SHIFT

#define SMIX_DMAC_ABRT_CMD_CH_SHIFT   (0U)

◆ SMIX_DMAC_ABRT_ST_CH_GET

#define SMIX_DMAC_ABRT_ST_CH_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_ABRT_ST_CH_MASK) >> SMIX_DMAC_ABRT_ST_CH_SHIFT)

◆ SMIX_DMAC_ABRT_ST_CH_MASK

#define SMIX_DMAC_ABRT_ST_CH_MASK   (0x3FFFFFFUL)

◆ SMIX_DMAC_ABRT_ST_CH_SET

#define SMIX_DMAC_ABRT_ST_CH_SET (   x)    (((uint32_t)(x) << SMIX_DMAC_ABRT_ST_CH_SHIFT) & SMIX_DMAC_ABRT_ST_CH_MASK)

◆ SMIX_DMAC_ABRT_ST_CH_SHIFT

#define SMIX_DMAC_ABRT_ST_CH_SHIFT   (0U)

◆ SMIX_DMAC_CHEN_CH_GET

#define SMIX_DMAC_CHEN_CH_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_CHEN_CH_MASK) >> SMIX_DMAC_CHEN_CH_SHIFT)

◆ SMIX_DMAC_CHEN_CH_MASK

#define SMIX_DMAC_CHEN_CH_MASK   (0x3FFFFFFUL)

◆ SMIX_DMAC_CHEN_CH_SHIFT

#define SMIX_DMAC_CHEN_CH_SHIFT   (0U)

◆ SMIX_DMAC_CTRL_SRST_GET

#define SMIX_DMAC_CTRL_SRST_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_CTRL_SRST_MASK) >> SMIX_DMAC_CTRL_SRST_SHIFT)

◆ SMIX_DMAC_CTRL_SRST_MASK

#define SMIX_DMAC_CTRL_SRST_MASK   (0x1U)

◆ SMIX_DMAC_CTRL_SRST_SET

#define SMIX_DMAC_CTRL_SRST_SET (   x)    (((uint32_t)(x) << SMIX_DMAC_CTRL_SRST_SHIFT) & SMIX_DMAC_CTRL_SRST_MASK)

◆ SMIX_DMAC_CTRL_SRST_SHIFT

#define SMIX_DMAC_CTRL_SRST_SHIFT   (0U)

◆ SMIX_DMAC_ERR_ST_CH_GET

#define SMIX_DMAC_ERR_ST_CH_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_ERR_ST_CH_MASK) >> SMIX_DMAC_ERR_ST_CH_SHIFT)

◆ SMIX_DMAC_ERR_ST_CH_MASK

#define SMIX_DMAC_ERR_ST_CH_MASK   (0x3FFFFFFUL)

◆ SMIX_DMAC_ERR_ST_CH_SET

#define SMIX_DMAC_ERR_ST_CH_SET (   x)    (((uint32_t)(x) << SMIX_DMAC_ERR_ST_CH_SHIFT) & SMIX_DMAC_ERR_ST_CH_MASK)

◆ SMIX_DMAC_ERR_ST_CH_SHIFT

#define SMIX_DMAC_ERR_ST_CH_SHIFT   (0U)

◆ SMIX_DMAC_ID_REV_GET

#define SMIX_DMAC_ID_REV_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_ID_REV_MASK) >> SMIX_DMAC_ID_REV_SHIFT)

◆ SMIX_DMAC_ID_REV_MASK

#define SMIX_DMAC_ID_REV_MASK   (0x7FFFFUL)

◆ SMIX_DMAC_ID_REV_SHIFT

#define SMIX_DMAC_ID_REV_SHIFT   (0U)

◆ SMIX_DMAC_TC_ST_CH_GET

#define SMIX_DMAC_TC_ST_CH_GET (   x)    (((uint32_t)(x) & SMIX_DMAC_TC_ST_CH_MASK) >> SMIX_DMAC_TC_ST_CH_SHIFT)

◆ SMIX_DMAC_TC_ST_CH_MASK

#define SMIX_DMAC_TC_ST_CH_MASK   (0x3FFFFFFUL)

◆ SMIX_DMAC_TC_ST_CH_SET

#define SMIX_DMAC_TC_ST_CH_SET (   x)    (((uint32_t)(x) << SMIX_DMAC_TC_ST_CH_SHIFT) & SMIX_DMAC_TC_ST_CH_MASK)

◆ SMIX_DMAC_TC_ST_CH_SHIFT

#define SMIX_DMAC_TC_ST_CH_SHIFT   (0U)

◆ SMIX_DST_CH_0

#define SMIX_DST_CH_0   (0UL)

◆ SMIX_DST_CH_1

#define SMIX_DST_CH_1   (1UL)

◆ SMIX_DST_CH_BUFSIZE_MAX_IDX_GET

#define SMIX_DST_CH_BUFSIZE_MAX_IDX_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) >> SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT)

◆ SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK

#define SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK   (0xFFFFFFFFUL)

◆ SMIX_DST_CH_BUFSIZE_MAX_IDX_SET

#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK)

◆ SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT

#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT   (0U)

◆ SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET

#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) >> SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT)

◆ SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK

#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK   (0x200U)

◆ SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET

#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK)

◆ SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT

#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT   (9U)

◆ SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET

#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT)

◆ SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK

#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK   (0x800U)

◆ SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET

#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK)

◆ SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT

#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT   (11U)

◆ SMIX_DST_CH_CTRL_DA_INT_EN_GET

#define SMIX_DST_CH_CTRL_DA_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) >> SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT)

◆ SMIX_DST_CH_CTRL_DA_INT_EN_MASK

#define SMIX_DST_CH_CTRL_DA_INT_EN_MASK   (0x400U)

◆ SMIX_DST_CH_CTRL_DA_INT_EN_SET

#define SMIX_DST_CH_CTRL_DA_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK)

◆ SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT

#define SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT   (10U)

◆ SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET

#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) >> SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT)

◆ SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK

#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK   (0x100000UL)

◆ SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET

#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK)

◆ SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT

#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT   (20U)

◆ SMIX_DST_CH_CTRL_DST_ACT_GET

#define SMIX_DST_CH_CTRL_DST_ACT_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_ACT_MASK) >> SMIX_DST_CH_CTRL_DST_ACT_SHIFT)

◆ SMIX_DST_CH_CTRL_DST_ACT_MASK

#define SMIX_DST_CH_CTRL_DST_ACT_MASK   (0x40U)

◆ SMIX_DST_CH_CTRL_DST_ACT_SET

#define SMIX_DST_CH_CTRL_DST_ACT_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_ACT_SHIFT) & SMIX_DST_CH_CTRL_DST_ACT_MASK)

◆ SMIX_DST_CH_CTRL_DST_ACT_SHIFT

#define SMIX_DST_CH_CTRL_DST_ACT_SHIFT   (6U)

◆ SMIX_DST_CH_CTRL_DST_DEACT_GET

#define SMIX_DST_CH_CTRL_DST_DEACT_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) >> SMIX_DST_CH_CTRL_DST_DEACT_SHIFT)

◆ SMIX_DST_CH_CTRL_DST_DEACT_MASK

#define SMIX_DST_CH_CTRL_DST_DEACT_MASK   (0x80U)

◆ SMIX_DST_CH_CTRL_DST_DEACT_SET

#define SMIX_DST_CH_CTRL_DST_DEACT_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) & SMIX_DST_CH_CTRL_DST_DEACT_MASK)

◆ SMIX_DST_CH_CTRL_DST_DEACT_SHIFT

#define SMIX_DST_CH_CTRL_DST_DEACT_SHIFT   (7U)

◆ SMIX_DST_CH_CTRL_DST_EN_GET

#define SMIX_DST_CH_CTRL_DST_EN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_EN_MASK) >> SMIX_DST_CH_CTRL_DST_EN_SHIFT)

◆ SMIX_DST_CH_CTRL_DST_EN_MASK

#define SMIX_DST_CH_CTRL_DST_EN_MASK   (0x4U)

◆ SMIX_DST_CH_CTRL_DST_EN_SET

#define SMIX_DST_CH_CTRL_DST_EN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_EN_SHIFT) & SMIX_DST_CH_CTRL_DST_EN_MASK)

◆ SMIX_DST_CH_CTRL_DST_EN_SHIFT

#define SMIX_DST_CH_CTRL_DST_EN_SHIFT   (2U)

◆ SMIX_DST_CH_CTRL_DSTFADIN_EN_GET

#define SMIX_DST_CH_CTRL_DSTFADIN_EN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) >> SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT)

◆ SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK

#define SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK   (0x8U)

◆ SMIX_DST_CH_CTRL_DSTFADIN_EN_SET

#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK)

◆ SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT

#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT   (3U)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET

#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK

#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK   (0x10U)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET

#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT

#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT   (4U)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET

#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK

#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK   (0x20U)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET

#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK)

◆ SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT

#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT   (5U)

◆ SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET

#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT)

◆ SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK

#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK   (0x100U)

◆ SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET

#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK)

◆ SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT

#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT   (8U)

◆ SMIX_DST_CH_CTRL_MIXER_EN_GET

#define SMIX_DST_CH_CTRL_MIXER_EN_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) >> SMIX_DST_CH_CTRL_MIXER_EN_SHIFT)

◆ SMIX_DST_CH_CTRL_MIXER_EN_MASK

#define SMIX_DST_CH_CTRL_MIXER_EN_MASK   (0x1U)

◆ SMIX_DST_CH_CTRL_MIXER_EN_SET

#define SMIX_DST_CH_CTRL_MIXER_EN_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) & SMIX_DST_CH_CTRL_MIXER_EN_MASK)

◆ SMIX_DST_CH_CTRL_MIXER_EN_SHIFT

#define SMIX_DST_CH_CTRL_MIXER_EN_SHIFT   (0U)

◆ SMIX_DST_CH_CTRL_SOFTRST_GET

#define SMIX_DST_CH_CTRL_SOFTRST_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_SOFTRST_MASK) >> SMIX_DST_CH_CTRL_SOFTRST_SHIFT)

◆ SMIX_DST_CH_CTRL_SOFTRST_MASK

#define SMIX_DST_CH_CTRL_SOFTRST_MASK   (0x2U)

◆ SMIX_DST_CH_CTRL_SOFTRST_SET

#define SMIX_DST_CH_CTRL_SOFTRST_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_SOFTRST_SHIFT) & SMIX_DST_CH_CTRL_SOFTRST_MASK)

◆ SMIX_DST_CH_CTRL_SOFTRST_SHIFT

#define SMIX_DST_CH_CTRL_SOFTRST_SHIFT   (1U)

◆ SMIX_DST_CH_CTRL_THRSH_GET

#define SMIX_DST_CH_CTRL_THRSH_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_CTRL_THRSH_MASK) >> SMIX_DST_CH_CTRL_THRSH_SHIFT)

◆ SMIX_DST_CH_CTRL_THRSH_MASK

#define SMIX_DST_CH_CTRL_THRSH_MASK   (0xFF000UL)

◆ SMIX_DST_CH_CTRL_THRSH_SET

#define SMIX_DST_CH_CTRL_THRSH_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_CTRL_THRSH_SHIFT) & SMIX_DST_CH_CTRL_THRSH_MASK)

◆ SMIX_DST_CH_CTRL_THRSH_SHIFT

#define SMIX_DST_CH_CTRL_THRSH_SHIFT   (12U)

◆ SMIX_DST_CH_DATA_VAL_GET

#define SMIX_DST_CH_DATA_VAL_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_DATA_VAL_MASK) >> SMIX_DST_CH_DATA_VAL_SHIFT)

◆ SMIX_DST_CH_DATA_VAL_MASK

#define SMIX_DST_CH_DATA_VAL_MASK   (0xFFFFFFFFUL)

◆ SMIX_DST_CH_DATA_VAL_SHIFT

#define SMIX_DST_CH_DATA_VAL_SHIFT   (0U)

◆ SMIX_DST_CH_DEACT_ST_DST_DEACT_GET

#define SMIX_DST_CH_DEACT_ST_DST_DEACT_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK) >> SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT)

◆ SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK

#define SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK   (0x80000000UL)

◆ SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT

#define SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT   (31U)

◆ SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET

#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK) >> SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT)

◆ SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK

#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK   (0xFFU)

◆ SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT

#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT   (0U)

◆ SMIX_DST_CH_FADEIN_DELTA_GET

#define SMIX_DST_CH_FADEIN_DELTA_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_FADEIN_DELTA_MASK) >> SMIX_DST_CH_FADEIN_DELTA_SHIFT)

◆ SMIX_DST_CH_FADEIN_DELTA_MASK

#define SMIX_DST_CH_FADEIN_DELTA_MASK   (0xFFFFFUL)

◆ SMIX_DST_CH_FADEIN_DELTA_SET

#define SMIX_DST_CH_FADEIN_DELTA_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_FADEIN_DELTA_SHIFT) & SMIX_DST_CH_FADEIN_DELTA_MASK)

◆ SMIX_DST_CH_FADEIN_DELTA_SHIFT

#define SMIX_DST_CH_FADEIN_DELTA_SHIFT   (0U)

◆ SMIX_DST_CH_FADEOUT_DELTA_GET

#define SMIX_DST_CH_FADEOUT_DELTA_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_DELTA_MASK) >> SMIX_DST_CH_FADEOUT_DELTA_SHIFT)

◆ SMIX_DST_CH_FADEOUT_DELTA_MASK

#define SMIX_DST_CH_FADEOUT_DELTA_MASK   (0xFFFFFUL)

◆ SMIX_DST_CH_FADEOUT_DELTA_SET

#define SMIX_DST_CH_FADEOUT_DELTA_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_DELTA_SHIFT) & SMIX_DST_CH_FADEOUT_DELTA_MASK)

◆ SMIX_DST_CH_FADEOUT_DELTA_SHIFT

#define SMIX_DST_CH_FADEOUT_DELTA_SHIFT   (0U)

◆ SMIX_DST_CH_GAIN_VAL_GET

#define SMIX_DST_CH_GAIN_VAL_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_GAIN_VAL_MASK) >> SMIX_DST_CH_GAIN_VAL_SHIFT)

◆ SMIX_DST_CH_GAIN_VAL_MASK

#define SMIX_DST_CH_GAIN_VAL_MASK   (0x7FFFU)

◆ SMIX_DST_CH_GAIN_VAL_SET

#define SMIX_DST_CH_GAIN_VAL_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_GAIN_VAL_SHIFT) & SMIX_DST_CH_GAIN_VAL_MASK)

◆ SMIX_DST_CH_GAIN_VAL_SHIFT

#define SMIX_DST_CH_GAIN_VAL_SHIFT   (0U)

◆ SMIX_DST_CH_SOURCE_ACT_VAL_GET

#define SMIX_DST_CH_SOURCE_ACT_VAL_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT)

◆ SMIX_DST_CH_SOURCE_ACT_VAL_MASK

#define SMIX_DST_CH_SOURCE_ACT_VAL_MASK   (0xFFU)

◆ SMIX_DST_CH_SOURCE_ACT_VAL_SET

#define SMIX_DST_CH_SOURCE_ACT_VAL_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK)

◆ SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT

#define SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT   (0U)

◆ SMIX_DST_CH_SOURCE_DEACT_VAL_GET

#define SMIX_DST_CH_SOURCE_DEACT_VAL_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT)

◆ SMIX_DST_CH_SOURCE_DEACT_VAL_MASK

#define SMIX_DST_CH_SOURCE_DEACT_VAL_MASK   (0xFFU)

◆ SMIX_DST_CH_SOURCE_DEACT_VAL_SET

#define SMIX_DST_CH_SOURCE_DEACT_VAL_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK)

◆ SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT

#define SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT   (0U)

◆ SMIX_DST_CH_SOURCE_EN_VAL_GET

#define SMIX_DST_CH_SOURCE_EN_VAL_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) >> SMIX_DST_CH_SOURCE_EN_VAL_SHIFT)

◆ SMIX_DST_CH_SOURCE_EN_VAL_MASK

#define SMIX_DST_CH_SOURCE_EN_VAL_MASK   (0xFFU)

◆ SMIX_DST_CH_SOURCE_EN_VAL_SET

#define SMIX_DST_CH_SOURCE_EN_VAL_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) & SMIX_DST_CH_SOURCE_EN_VAL_MASK)

◆ SMIX_DST_CH_SOURCE_EN_VAL_SHIFT

#define SMIX_DST_CH_SOURCE_EN_VAL_SHIFT   (0U)

◆ SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET

#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT)

◆ SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK

#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK   (0xFFU)

◆ SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET

#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK)

◆ SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT

#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT   (0U)

◆ SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET

#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT)

◆ SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK

#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK   (0xFFU)

◆ SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET

#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET (   x)    (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK)

◆ SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT

#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT   (0U)

◆ SMIX_DST_CH_ST_CALSAT_GET

#define SMIX_DST_CH_ST_CALSAT_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_ST_CALSAT_MASK) >> SMIX_DST_CH_ST_CALSAT_SHIFT)

◆ SMIX_DST_CH_ST_CALSAT_MASK

#define SMIX_DST_CH_ST_CALSAT_MASK   (0x10U)

◆ SMIX_DST_CH_ST_CALSAT_SHIFT

#define SMIX_DST_CH_ST_CALSAT_SHIFT   (4U)

◆ SMIX_DST_CH_ST_DA_GET

#define SMIX_DST_CH_ST_DA_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_ST_DA_MASK) >> SMIX_DST_CH_ST_DA_SHIFT)

◆ SMIX_DST_CH_ST_DA_MASK

#define SMIX_DST_CH_ST_DA_MASK   (0x8U)

◆ SMIX_DST_CH_ST_DA_SHIFT

#define SMIX_DST_CH_ST_DA_SHIFT   (3U)

◆ SMIX_DST_CH_ST_FDOUT_DONE_GET

#define SMIX_DST_CH_ST_FDOUT_DONE_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_ST_FDOUT_DONE_MASK) >> SMIX_DST_CH_ST_FDOUT_DONE_SHIFT)

◆ SMIX_DST_CH_ST_FDOUT_DONE_MASK

#define SMIX_DST_CH_ST_FDOUT_DONE_MASK   (0x20U)

◆ SMIX_DST_CH_ST_FDOUT_DONE_SHIFT

#define SMIX_DST_CH_ST_FDOUT_DONE_SHIFT   (5U)

◆ SMIX_DST_CH_ST_FIFO_FILLINGS_GET

#define SMIX_DST_CH_ST_FIFO_FILLINGS_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT)

◆ SMIX_DST_CH_ST_FIFO_FILLINGS_MASK

#define SMIX_DST_CH_ST_FIFO_FILLINGS_MASK   (0x7FC0U)

◆ SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT

#define SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT   (6U)

◆ SMIX_DST_CH_ST_MODE_GET

#define SMIX_DST_CH_ST_MODE_GET (   x)    (((uint32_t)(x) & SMIX_DST_CH_ST_MODE_MASK) >> SMIX_DST_CH_ST_MODE_SHIFT)

◆ SMIX_DST_CH_ST_MODE_MASK

#define SMIX_DST_CH_ST_MODE_MASK   (0x7U)

◆ SMIX_DST_CH_ST_MODE_SHIFT

#define SMIX_DST_CH_ST_MODE_SHIFT   (0U)

◆ SMIX_FDOT_DONE_ST_DST_GET

#define SMIX_FDOT_DONE_ST_DST_GET (   x)    (((uint32_t)(x) & SMIX_FDOT_DONE_ST_DST_MASK) >> SMIX_FDOT_DONE_ST_DST_SHIFT)

◆ SMIX_FDOT_DONE_ST_DST_MASK

#define SMIX_FDOT_DONE_ST_DST_MASK   (0xC0000000UL)

◆ SMIX_FDOT_DONE_ST_DST_SET

#define SMIX_FDOT_DONE_ST_DST_SET (   x)    (((uint32_t)(x) << SMIX_FDOT_DONE_ST_DST_SHIFT) & SMIX_FDOT_DONE_ST_DST_MASK)

◆ SMIX_FDOT_DONE_ST_DST_SHIFT

#define SMIX_FDOT_DONE_ST_DST_SHIFT   (30U)

◆ SMIX_FDOT_DONE_ST_SRC_GET

#define SMIX_FDOT_DONE_ST_SRC_GET (   x)    (((uint32_t)(x) & SMIX_FDOT_DONE_ST_SRC_MASK) >> SMIX_FDOT_DONE_ST_SRC_SHIFT)

◆ SMIX_FDOT_DONE_ST_SRC_MASK

#define SMIX_FDOT_DONE_ST_SRC_MASK   (0x3FFFU)

◆ SMIX_FDOT_DONE_ST_SRC_SET

#define SMIX_FDOT_DONE_ST_SRC_SET (   x)    (((uint32_t)(x) << SMIX_FDOT_DONE_ST_SRC_SHIFT) & SMIX_FDOT_DONE_ST_SRC_MASK)

◆ SMIX_FDOT_DONE_ST_SRC_SHIFT

#define SMIX_FDOT_DONE_ST_SRC_SHIFT   (0U)

◆ SMIX_SOURCE_CH_0

#define SMIX_SOURCE_CH_0   (0UL)

◆ SMIX_SOURCE_CH_1

#define SMIX_SOURCE_CH_1   (1UL)

◆ SMIX_SOURCE_CH_10

#define SMIX_SOURCE_CH_10   (10UL)

◆ SMIX_SOURCE_CH_11

#define SMIX_SOURCE_CH_11   (11UL)

◆ SMIX_SOURCE_CH_12

#define SMIX_SOURCE_CH_12   (12UL)

◆ SMIX_SOURCE_CH_13

#define SMIX_SOURCE_CH_13   (13UL)

◆ SMIX_SOURCE_CH_2

#define SMIX_SOURCE_CH_2   (2UL)

◆ SMIX_SOURCE_CH_3

#define SMIX_SOURCE_CH_3   (3UL)

◆ SMIX_SOURCE_CH_4

#define SMIX_SOURCE_CH_4   (4UL)

◆ SMIX_SOURCE_CH_5

#define SMIX_SOURCE_CH_5   (5UL)

◆ SMIX_SOURCE_CH_6

#define SMIX_SOURCE_CH_6   (6UL)

◆ SMIX_SOURCE_CH_7

#define SMIX_SOURCE_CH_7   (7UL)

◆ SMIX_SOURCE_CH_8

#define SMIX_SOURCE_CH_8   (8UL)

◆ SMIX_SOURCE_CH_9

#define SMIX_SOURCE_CH_9   (9UL)

◆ SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET

#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) >> SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT)

◆ SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK

#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK   (0xFFFFFFFFUL)

◆ SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET

#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK)

◆ SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT

#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT   (0U)

◆ SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET

#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK

#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK   (0x80U)

◆ SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET

#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK)

◆ SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT

#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT   (7U)

◆ SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET

#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK

#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK   (0x1000U)

◆ SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET

#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK)

◆ SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT

#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT   (12U)

◆ SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET

#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK

#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK   (0x800U)

◆ SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET

#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK)

◆ SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT

#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT   (11U)

◆ SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET

#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK

#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK   (0x40U)

◆ SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET

#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK)

◆ SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT

#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT   (6U)

◆ SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET

#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) >> SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK

#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK   (0x200000UL)

◆ SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET

#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK)

◆ SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT

#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT   (21U)

◆ SMIX_SOURCE_CH_CTRL_RATECONV_GET

#define SMIX_SOURCE_CH_CTRL_RATECONV_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) >> SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_RATECONV_MASK

#define SMIX_SOURCE_CH_CTRL_RATECONV_MASK   (0x7U)

◆ SMIX_SOURCE_CH_CTRL_RATECONV_SET

#define SMIX_SOURCE_CH_CTRL_RATECONV_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK)

◆ SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT

#define SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT   (0U)

◆ SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET

#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) >> SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK

#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK   (0x700U)

◆ SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET

#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK)

◆ SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT

#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT   (8U)

◆ SMIX_SOURCE_CH_CTRL_THRSH_GET

#define SMIX_SOURCE_CH_CTRL_THRSH_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) >> SMIX_SOURCE_CH_CTRL_THRSH_SHIFT)

◆ SMIX_SOURCE_CH_CTRL_THRSH_MASK

#define SMIX_SOURCE_CH_CTRL_THRSH_MASK   (0x1FE000UL)

◆ SMIX_SOURCE_CH_CTRL_THRSH_SET

#define SMIX_SOURCE_CH_CTRL_THRSH_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) & SMIX_SOURCE_CH_CTRL_THRSH_MASK)

◆ SMIX_SOURCE_CH_CTRL_THRSH_SHIFT

#define SMIX_SOURCE_CH_CTRL_THRSH_SHIFT   (13U)

◆ SMIX_SOURCE_CH_DATA_VAL_GET

#define SMIX_SOURCE_CH_DATA_VAL_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_DATA_VAL_MASK) >> SMIX_SOURCE_CH_DATA_VAL_SHIFT)

◆ SMIX_SOURCE_CH_DATA_VAL_MASK

#define SMIX_SOURCE_CH_DATA_VAL_MASK   (0xFFFFFFFFUL)

◆ SMIX_SOURCE_CH_DATA_VAL_SET

#define SMIX_SOURCE_CH_DATA_VAL_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_DATA_VAL_SHIFT) & SMIX_SOURCE_CH_DATA_VAL_MASK)

◆ SMIX_SOURCE_CH_DATA_VAL_SHIFT

#define SMIX_SOURCE_CH_DATA_VAL_SHIFT   (0U)

◆ SMIX_SOURCE_CH_FADEIN_DELTA_GET

#define SMIX_SOURCE_CH_FADEIN_DELTA_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) >> SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT)

◆ SMIX_SOURCE_CH_FADEIN_DELTA_MASK

#define SMIX_SOURCE_CH_FADEIN_DELTA_MASK   (0xFFFFFUL)

◆ SMIX_SOURCE_CH_FADEIN_DELTA_SET

#define SMIX_SOURCE_CH_FADEIN_DELTA_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK)

◆ SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT

#define SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT   (0U)

◆ SMIX_SOURCE_CH_FADEOUT_DELTA_GET

#define SMIX_SOURCE_CH_FADEOUT_DELTA_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) >> SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT)

◆ SMIX_SOURCE_CH_FADEOUT_DELTA_MASK

#define SMIX_SOURCE_CH_FADEOUT_DELTA_MASK   (0xFFFFFUL)

◆ SMIX_SOURCE_CH_FADEOUT_DELTA_SET

#define SMIX_SOURCE_CH_FADEOUT_DELTA_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK)

◆ SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT

#define SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT   (0U)

◆ SMIX_SOURCE_CH_GAIN_VAL_GET

#define SMIX_SOURCE_CH_GAIN_VAL_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_VAL_MASK) >> SMIX_SOURCE_CH_GAIN_VAL_SHIFT)

◆ SMIX_SOURCE_CH_GAIN_VAL_MASK

#define SMIX_SOURCE_CH_GAIN_VAL_MASK   (0x7FFFU)

◆ SMIX_SOURCE_CH_GAIN_VAL_SET

#define SMIX_SOURCE_CH_GAIN_VAL_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_VAL_SHIFT) & SMIX_SOURCE_CH_GAIN_VAL_MASK)

◆ SMIX_SOURCE_CH_GAIN_VAL_SHIFT

#define SMIX_SOURCE_CH_GAIN_VAL_SHIFT   (0U)

◆ SMIX_SOURCE_CH_ST_CALSAT_GET

#define SMIX_SOURCE_CH_ST_CALSAT_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_ST_CALSAT_MASK) >> SMIX_SOURCE_CH_ST_CALSAT_SHIFT)

◆ SMIX_SOURCE_CH_ST_CALSAT_MASK

#define SMIX_SOURCE_CH_ST_CALSAT_MASK   (0x100U)

◆ SMIX_SOURCE_CH_ST_CALSAT_SET

#define SMIX_SOURCE_CH_ST_CALSAT_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_ST_CALSAT_SHIFT) & SMIX_SOURCE_CH_ST_CALSAT_MASK)

◆ SMIX_SOURCE_CH_ST_CALSAT_SHIFT

#define SMIX_SOURCE_CH_ST_CALSAT_SHIFT   (8U)

◆ SMIX_SOURCE_CH_ST_DN_GET

#define SMIX_SOURCE_CH_ST_DN_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_ST_DN_MASK) >> SMIX_SOURCE_CH_ST_DN_SHIFT)

◆ SMIX_SOURCE_CH_ST_DN_MASK

#define SMIX_SOURCE_CH_ST_DN_MASK   (0x80U)

◆ SMIX_SOURCE_CH_ST_DN_SHIFT

#define SMIX_SOURCE_CH_ST_DN_SHIFT   (7U)

◆ SMIX_SOURCE_CH_ST_FDOUT_DONE_GET

#define SMIX_SOURCE_CH_ST_FDOUT_DONE_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) >> SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT)

◆ SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK

#define SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK   (0x200U)

◆ SMIX_SOURCE_CH_ST_FDOUT_DONE_SET

#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SET (   x)    (((uint32_t)(x) << SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK)

◆ SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT

#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT   (9U)

◆ SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET

#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT)

◆ SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK

#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK   (0x7FC00UL)

◆ SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT

#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT   (10U)

◆ SMIX_SOURCE_CH_ST_FIRPHASE_GET

#define SMIX_SOURCE_CH_ST_FIRPHASE_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIRPHASE_MASK) >> SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT)

◆ SMIX_SOURCE_CH_ST_FIRPHASE_MASK

#define SMIX_SOURCE_CH_ST_FIRPHASE_MASK   (0x78U)

◆ SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT

#define SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT   (3U)

◆ SMIX_SOURCE_CH_ST_MODE_GET

#define SMIX_SOURCE_CH_ST_MODE_GET (   x)    (((uint32_t)(x) & SMIX_SOURCE_CH_ST_MODE_MASK) >> SMIX_SOURCE_CH_ST_MODE_SHIFT)

◆ SMIX_SOURCE_CH_ST_MODE_MASK

#define SMIX_SOURCE_CH_ST_MODE_MASK   (0x7U)

◆ SMIX_SOURCE_CH_ST_MODE_SHIFT

#define SMIX_SOURCE_CH_ST_MODE_SHIFT   (0U)