HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_tsw_regs.h File Reference

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Data Structures

struct  TSW_Type
 

Macros

#define TSW_LU_MAIN_CTRL_BYP_EN_MASK   (0x1U)
 
#define TSW_LU_MAIN_CTRL_BYP_EN_SHIFT   (0U)
 
#define TSW_LU_MAIN_CTRL_BYP_EN_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_CTRL_BYP_EN_SHIFT) & TSW_LU_MAIN_CTRL_BYP_EN_MASK)
 
#define TSW_LU_MAIN_CTRL_BYP_EN_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_CTRL_BYP_EN_MASK) >> TSW_LU_MAIN_CTRL_BYP_EN_SHIFT)
 
#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK   (0x2U)
 
#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT   (1U)
 
#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK)
 
#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT)
 
#define TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK   (0x1U)
 
#define TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT   (0U)
 
#define TSW_LU_MAIN_HITMEM_HITMEMCLR_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK)
 
#define TSW_LU_MAIN_HITMEM_HITMEMCLR_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT)
 
#define TSW_LU_MAIN_PARAM_NSTR_MASK   (0xFF00U)
 
#define TSW_LU_MAIN_PARAM_NSTR_SHIFT   (8U)
 
#define TSW_LU_MAIN_PARAM_NSTR_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PARAM_NSTR_MASK) >> TSW_LU_MAIN_PARAM_NSTR_SHIFT)
 
#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK   (0xFFU)
 
#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT   (0U)
 
#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK) >> TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT)
 
#define TSW_LU_MAIN_BYPASS_HIT_MASK   (0x1000000UL)
 
#define TSW_LU_MAIN_BYPASS_HIT_SHIFT   (24U)
 
#define TSW_LU_MAIN_BYPASS_HIT_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_MASK)
 
#define TSW_LU_MAIN_BYPASS_HIT_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_MASK) >> TSW_LU_MAIN_BYPASS_HIT_SHIFT)
 
#define TSW_LU_MAIN_BYPASS_UTAG_MASK   (0xE00000UL)
 
#define TSW_LU_MAIN_BYPASS_UTAG_SHIFT   (21U)
 
#define TSW_LU_MAIN_BYPASS_UTAG_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_UTAG_SHIFT) & TSW_LU_MAIN_BYPASS_UTAG_MASK)
 
#define TSW_LU_MAIN_BYPASS_UTAG_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_UTAG_MASK) >> TSW_LU_MAIN_BYPASS_UTAG_SHIFT)
 
#define TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK   (0x100000UL)
 
#define TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT   (20U)
 
#define TSW_LU_MAIN_BYPASS_HIT_VLAN_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK)
 
#define TSW_LU_MAIN_BYPASS_HIT_VLAN_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK) >> TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT)
 
#define TSW_LU_MAIN_BYPASS_DROP_MASK   (0x80000UL)
 
#define TSW_LU_MAIN_BYPASS_DROP_SHIFT   (19U)
 
#define TSW_LU_MAIN_BYPASS_DROP_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DROP_SHIFT) & TSW_LU_MAIN_BYPASS_DROP_MASK)
 
#define TSW_LU_MAIN_BYPASS_DROP_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DROP_MASK) >> TSW_LU_MAIN_BYPASS_DROP_SHIFT)
 
#define TSW_LU_MAIN_BYPASS_QUEUE_MASK   (0x70000UL)
 
#define TSW_LU_MAIN_BYPASS_QUEUE_SHIFT   (16U)
 
#define TSW_LU_MAIN_BYPASS_QUEUE_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_QUEUE_SHIFT) & TSW_LU_MAIN_BYPASS_QUEUE_MASK)
 
#define TSW_LU_MAIN_BYPASS_QUEUE_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_QUEUE_MASK) >> TSW_LU_MAIN_BYPASS_QUEUE_SHIFT)
 
#define TSW_LU_MAIN_BYPASS_DEST_MASK   (0xFFFFU)
 
#define TSW_LU_MAIN_BYPASS_DEST_SHIFT   (0U)
 
#define TSW_LU_MAIN_BYPASS_DEST_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DEST_SHIFT) & TSW_LU_MAIN_BYPASS_DEST_MASK)
 
#define TSW_LU_MAIN_BYPASS_DEST_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DEST_MASK) >> TSW_LU_MAIN_BYPASS_DEST_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP7_MASK   (0xE00000UL)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT   (21U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP7_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP7_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP6_MASK   (0x1C0000UL)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT   (18U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP6_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP6_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP5_MASK   (0x38000UL)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT   (15U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP5_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP5_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP4_MASK   (0x7000U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT   (12U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP4_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP4_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP3_MASK   (0xE00U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT   (9U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP3_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP3_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP2_MASK   (0x1C0U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT   (6U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP2_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP2_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP1_MASK   (0x38U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT   (3U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP1_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP1_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP0_MASK   (0x7U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT   (0U)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP0_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK)
 
#define TSW_LU_MAIN_PCP_REMAP_PCP0_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT)
 
#define TSW_LU_MAIN_VERSION_VER_HI_MASK   (0xFF000000UL)
 
#define TSW_LU_MAIN_VERSION_VER_HI_SHIFT   (24U)
 
#define TSW_LU_MAIN_VERSION_VER_HI_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_HI_MASK) >> TSW_LU_MAIN_VERSION_VER_HI_SHIFT)
 
#define TSW_LU_MAIN_VERSION_VER_LO_MASK   (0xFF0000UL)
 
#define TSW_LU_MAIN_VERSION_VER_LO_SHIFT   (16U)
 
#define TSW_LU_MAIN_VERSION_VER_LO_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_LO_MASK) >> TSW_LU_MAIN_VERSION_VER_LO_SHIFT)
 
#define TSW_LU_MAIN_VERSION_VER_REV_MASK   (0xFFU)
 
#define TSW_LU_MAIN_VERSION_VER_REV_SHIFT   (0U)
 
#define TSW_LU_MAIN_VERSION_VER_REV_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_REV_MASK) >> TSW_LU_MAIN_VERSION_VER_REV_SHIFT)
 
#define TSW_LU_MAIN_INTF_ACTION_UTAG_MASK   (0x1C00000UL)
 
#define TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT   (22U)
 
#define TSW_LU_MAIN_INTF_ACTION_UTAG_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK)
 
#define TSW_LU_MAIN_INTF_ACTION_UTAG_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK) >> TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT)
 
#define TSW_LU_MAIN_INTF_ACTION_QSEL_MASK   (0x300000UL)
 
#define TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT   (20U)
 
#define TSW_LU_MAIN_INTF_ACTION_QSEL_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK)
 
#define TSW_LU_MAIN_INTF_ACTION_QSEL_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK) >> TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT)
 
#define TSW_LU_MAIN_INTF_ACTION_DROP_MASK   (0x80000UL)
 
#define TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT   (19U)
 
#define TSW_LU_MAIN_INTF_ACTION_DROP_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK)
 
#define TSW_LU_MAIN_INTF_ACTION_DROP_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK) >> TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT)
 
#define TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK   (0x70000UL)
 
#define TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT   (16U)
 
#define TSW_LU_MAIN_INTF_ACTION_QUEUE_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK)
 
#define TSW_LU_MAIN_INTF_ACTION_QUEUE_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT)
 
#define TSW_LU_MAIN_INTF_ACTION_DEST_MASK   (0xFFFFU)
 
#define TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT   (0U)
 
#define TSW_LU_MAIN_INTF_ACTION_DEST_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK)
 
#define TSW_LU_MAIN_INTF_ACTION_DEST_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK) >> TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT)
 
#define TSW_LU_MAIN_BC_ACTION_UTAG_MASK   (0x1C00000UL)
 
#define TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT   (22U)
 
#define TSW_LU_MAIN_BC_ACTION_UTAG_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK)
 
#define TSW_LU_MAIN_BC_ACTION_UTAG_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK) >> TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT)
 
#define TSW_LU_MAIN_BC_ACTION_QSEL_MASK   (0x300000UL)
 
#define TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT   (20U)
 
#define TSW_LU_MAIN_BC_ACTION_QSEL_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK)
 
#define TSW_LU_MAIN_BC_ACTION_QSEL_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK) >> TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT)
 
#define TSW_LU_MAIN_BC_ACTION_DROP_MASK   (0x80000UL)
 
#define TSW_LU_MAIN_BC_ACTION_DROP_SHIFT   (19U)
 
#define TSW_LU_MAIN_BC_ACTION_DROP_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DROP_SHIFT) & TSW_LU_MAIN_BC_ACTION_DROP_MASK)
 
#define TSW_LU_MAIN_BC_ACTION_DROP_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DROP_MASK) >> TSW_LU_MAIN_BC_ACTION_DROP_SHIFT)
 
#define TSW_LU_MAIN_BC_ACTION_QUEUE_MASK   (0x70000UL)
 
#define TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT   (16U)
 
#define TSW_LU_MAIN_BC_ACTION_QUEUE_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK)
 
#define TSW_LU_MAIN_BC_ACTION_QUEUE_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT)
 
#define TSW_LU_MAIN_BC_ACTION_DEST_MASK   (0xFFFFU)
 
#define TSW_LU_MAIN_BC_ACTION_DEST_SHIFT   (0U)
 
#define TSW_LU_MAIN_BC_ACTION_DEST_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DEST_SHIFT) & TSW_LU_MAIN_BC_ACTION_DEST_MASK)
 
#define TSW_LU_MAIN_BC_ACTION_DEST_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DEST_MASK) >> TSW_LU_MAIN_BC_ACTION_DEST_SHIFT)
 
#define TSW_LU_MAIN_NN_ACTION_UTAG_MASK   (0x1C00000UL)
 
#define TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT   (22U)
 
#define TSW_LU_MAIN_NN_ACTION_UTAG_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK)
 
#define TSW_LU_MAIN_NN_ACTION_UTAG_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK) >> TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT)
 
#define TSW_LU_MAIN_NN_ACTION_QSEL_MASK   (0x300000UL)
 
#define TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT   (20U)
 
#define TSW_LU_MAIN_NN_ACTION_QSEL_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK)
 
#define TSW_LU_MAIN_NN_ACTION_QSEL_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK) >> TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT)
 
#define TSW_LU_MAIN_NN_ACTION_DROP_MASK   (0x80000UL)
 
#define TSW_LU_MAIN_NN_ACTION_DROP_SHIFT   (19U)
 
#define TSW_LU_MAIN_NN_ACTION_DROP_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DROP_SHIFT) & TSW_LU_MAIN_NN_ACTION_DROP_MASK)
 
#define TSW_LU_MAIN_NN_ACTION_DROP_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DROP_MASK) >> TSW_LU_MAIN_NN_ACTION_DROP_SHIFT)
 
#define TSW_LU_MAIN_NN_ACTION_QUEUE_MASK   (0x70000UL)
 
#define TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT   (16U)
 
#define TSW_LU_MAIN_NN_ACTION_QUEUE_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK)
 
#define TSW_LU_MAIN_NN_ACTION_QUEUE_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT)
 
#define TSW_LU_MAIN_NN_ACTION_DEST_MASK   (0xFFFFU)
 
#define TSW_LU_MAIN_NN_ACTION_DEST_SHIFT   (0U)
 
#define TSW_LU_MAIN_NN_ACTION_DEST_SET(x)   (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DEST_SHIFT) & TSW_LU_MAIN_NN_ACTION_DEST_MASK)
 
#define TSW_LU_MAIN_NN_ACTION_DEST_GET(x)   (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DEST_MASK) >> TSW_LU_MAIN_NN_ACTION_DEST_SHIFT)
 
#define TSW_APB2AXIS_CAM_STS_BUSY_MASK   (0x2U)
 
#define TSW_APB2AXIS_CAM_STS_BUSY_SHIFT   (1U)
 
#define TSW_APB2AXIS_CAM_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_BUSY_MASK) >> TSW_APB2AXIS_CAM_STS_BUSY_SHIFT)
 
#define TSW_APB2AXIS_CAM_STS_RDY_MASK   (0x1U)
 
#define TSW_APB2AXIS_CAM_STS_RDY_SHIFT   (0U)
 
#define TSW_APB2AXIS_CAM_STS_RDY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_RDY_MASK) >> TSW_APB2AXIS_CAM_STS_RDY_SHIFT)
 
#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK   (0xFFU)
 
#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT   (0U)
 
#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT)
 
#define TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK   (0x10U)
 
#define TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT   (4U)
 
#define TSW_APB2AXIS_CAM_FILLSTS_FULL_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT)
 
#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK   (0x1U)
 
#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT   (0U)
 
#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT)
 
#define TSW_APB2AXIS_CAM_RESET_RESET_MASK   (0x1U)
 
#define TSW_APB2AXIS_CAM_RESET_RESET_SHIFT   (0U)
 
#define TSW_APB2AXIS_CAM_RESET_RESET_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_CAM_RESET_RESET_SHIFT) & TSW_APB2AXIS_CAM_RESET_RESET_MASK)
 
#define TSW_APB2AXIS_CAM_RESET_RESET_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_RESET_RESET_MASK) >> TSW_APB2AXIS_CAM_RESET_RESET_SHIFT)
 
#define TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK   (0xFF00U)
 
#define TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT   (8U)
 
#define TSW_APB2AXIS_CAM_PARAM_DEPTH_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT)
 
#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK   (0xFFU)
 
#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT   (0U)
 
#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT)
 
#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK   (0xFFFF0000UL)
 
#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT   (16U)
 
#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET(x)   (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK)
 
#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_GET(x)   (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT)
 
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK   (0x300U)
 
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT   (8U)
 
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET(x)   (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK)
 
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_GET(x)   (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT)
 
#define TSW_APB2AXI_CAM_REQDATA_0_CH_MASK   (0x1U)
 
#define TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT   (0U)
 
#define TSW_APB2AXI_CAM_REQDATA_0_CH_SET(x)   (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK)
 
#define TSW_APB2AXI_CAM_REQDATA_0_CH_GET(x)   (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT)
 
#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT   (0U)
 
#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET(x)   (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK)
 
#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET(x)   (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) >> TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT)
 
#define TSW_APB2AXI_CAM_REQDATA_2_VID_MASK   (0xFFF0000UL)
 
#define TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT   (16U)
 
#define TSW_APB2AXI_CAM_REQDATA_2_VID_SET(x)   (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK)
 
#define TSW_APB2AXI_CAM_REQDATA_2_VID_GET(x)   (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT)
 
#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK   (0xFFFFU)
 
#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT   (0U)
 
#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET(x)   (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK)
 
#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_GET(x)   (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_STS_BUSY_MASK   (0x2U)
 
#define TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT   (1U)
 
#define TSW_APB2AXIS_ALMEM_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_BUSY_MASK) >> TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_STS_RDY_MASK   (0x1U)
 
#define TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_STS_RDY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_RDY_MASK) >> TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK   (0xFFU)
 
#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK   (0x10U)
 
#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT   (4U)
 
#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK   (0x1U)
 
#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_RESET_RESET_MASK   (0x1U)
 
#define TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_RESET_RESET_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK)
 
#define TSW_APB2AXIS_ALMEM_RESET_RESET_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK) >> TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK   (0xFF00U)
 
#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT   (8U)
 
#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK   (0xFFU)
 
#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK   (0x1C00000UL)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT   (22U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK   (0x300000UL)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT   (20U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK   (0x80000UL)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT   (19U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK   (0x70000UL)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT   (16U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK   (0xFFFFU)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK   (0x80000000UL)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT   (31U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK   (0x40000000UL)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT   (30U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK   (0xFFFFU)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT   (0U)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK)
 
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_STS_BUSY_MASK   (0x2U)
 
#define TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT   (1U)
 
#define TSW_AXIS2APB_ALMEM_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_BUSY_MASK) >> TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_STS_RDY_MASK   (0x1U)
 
#define TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_STS_RDY_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_RDY_MASK) >> TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK   (0xFFU)
 
#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK   (0x10U)
 
#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT   (4U)
 
#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK   (0x1U)
 
#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESET_RESET_MASK   (0x1U)
 
#define TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_RESET_RESET_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESET_RESET_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK) >> TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK   (0xFF00U)
 
#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT   (8U)
 
#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK   (0xFFU)
 
#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK   (0x1C00000UL)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT   (22U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK   (0x300000UL)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT   (20U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK   (0x80000UL)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT   (19U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK   (0x70000UL)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT   (16U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK   (0xFFFFU)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK   (0x80000000UL)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT   (31U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK   (0x40000000UL)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT   (30U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK   (0xFFFFU)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT   (0U)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK)
 
#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT)
 
#define TSW_HITMEM_HITMEM_REG_MASK   (0xFFFFFFFFUL)
 
#define TSW_HITMEM_HITMEM_REG_SHIFT   (0U)
 
#define TSW_HITMEM_HITMEM_REG_SET(x)   (((uint32_t)(x) << TSW_HITMEM_HITMEM_REG_SHIFT) & TSW_HITMEM_HITMEM_REG_MASK)
 
#define TSW_HITMEM_HITMEM_REG_GET(x)   (((uint32_t)(x) & TSW_HITMEM_HITMEM_REG_MASK) >> TSW_HITMEM_HITMEM_REG_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK   (0x2U)
 
#define TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT   (1U)
 
#define TSW_APB2AXIS_LOOKUP_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_STS_RDY_MASK   (0x1U)
 
#define TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_STS_RDY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_RDY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK   (0xFFU)
 
#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK   (0x10U)
 
#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT   (4U)
 
#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK   (0x1U)
 
#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK   (0x1U)
 
#define TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_RESET_RESET_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK)
 
#define TSW_APB2AXIS_LOOKUP_RESET_RESET_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK) >> TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK   (0xFF00U)
 
#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT   (8U)
 
#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK   (0xFFU)
 
#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK   (0xFFFFFFFFUL)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK   (0xFFFFU)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK   (0x10000UL)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT   (16U)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK   (0xFFFFU)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT   (0U)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SET(x)   (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK)
 
#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_GET(x)   (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK   (0x2U)
 
#define TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT   (1U)
 
#define TSW_AXIS2APB_LOOKUP_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_STS_RDY_MASK   (0x1U)
 
#define TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_STS_RDY_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_RDY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK   (0xFFU)
 
#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK   (0x10U)
 
#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT   (4U)
 
#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK   (0x1U)
 
#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK   (0x1U)
 
#define TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_RESET_RESET_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESET_RESET_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK) >> TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK   (0xFF00U)
 
#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT   (8U)
 
#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK   (0xFFU)
 
#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK   (0x2000000UL)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT   (25U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK   (0x1000000UL)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT   (24U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK   (0xE00000UL)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT   (21U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK   (0x100000UL)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT   (20U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK   (0x80000UL)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT   (19U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK   (0x70000UL)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT   (16U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK   (0xFFFFU)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK   (0xFFFFU)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT   (0U)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SET(x)   (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK)
 
#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_GET(x)   (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT)
 
#define TSW_CENTRAL_CSR_VERSION_VER_HI_MASK   (0xFF000000UL)
 
#define TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT   (24U)
 
#define TSW_CENTRAL_CSR_VERSION_VER_HI_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_HI_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT)
 
#define TSW_CENTRAL_CSR_VERSION_VER_LO_MASK   (0xFF0000UL)
 
#define TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT   (16U)
 
#define TSW_CENTRAL_CSR_VERSION_VER_LO_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_LO_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT)
 
#define TSW_CENTRAL_CSR_VERSION_VER_REV_MASK   (0xFFU)
 
#define TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT   (0U)
 
#define TSW_CENTRAL_CSR_VERSION_VER_REV_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_REV_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT)
 
#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK   (0x40000UL)
 
#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT   (18U)
 
#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT)
 
#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK   (0x20000UL)
 
#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT   (17U)
 
#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT)
 
#define TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK   (0x10000UL)
 
#define TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT   (16U)
 
#define TSW_CENTRAL_CSR_PARAM_TESTMODE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK) >> TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT)
 
#define TSW_CENTRAL_CSR_PARAM_TYPE_MASK   (0xFF00U)
 
#define TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT   (8U)
 
#define TSW_CENTRAL_CSR_PARAM_TYPE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TYPE_MASK) >> TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT)
 
#define TSW_CENTRAL_CSR_PARAM_NPORTS_MASK   (0xFFU)
 
#define TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT   (0U)
 
#define TSW_CENTRAL_CSR_PARAM_NPORTS_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_NPORTS_MASK) >> TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT)
 
#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK   (0xFFFFFFUL)
 
#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT   (0U)
 
#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK)
 
#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK) >> TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT)
 
#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK   (0xFF00U)
 
#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT   (8U)
 
#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT)
 
#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK   (0xFFU)
 
#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT   (0U)
 
#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK   (0xFF0000UL)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT   (16U)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK   (0xFF00U)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT   (8U)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK   (0xFFU)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT   (0U)
 
#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT)
 
#define TSW_CENTRAL_QCI_HWCFG_FMD_MASK   (0xFF0000UL)
 
#define TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT   (16U)
 
#define TSW_CENTRAL_QCI_HWCFG_FMD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FMD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT)
 
#define TSW_CENTRAL_QCI_HWCFG_GTD_MASK   (0xFF00U)
 
#define TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT   (8U)
 
#define TSW_CENTRAL_QCI_HWCFG_GTD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_GTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT)
 
#define TSW_CENTRAL_QCI_HWCFG_FTD_MASK   (0xFFU)
 
#define TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_HWCFG_FTD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT)
 
#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK   (0xFFU)
 
#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK)
 
#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT)
 
#define TSW_CENTRAL_QCI_METERSEL_INDEX_MASK   (0xFFU)
 
#define TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_METERSEL_INDEX_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK)
 
#define TSW_CENTRAL_QCI_METERSEL_INDEX_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT)
 
#define TSW_CENTRAL_QCI_GATESEL_INDEX_MASK   (0xFFU)
 
#define TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_GATESEL_INDEX_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK)
 
#define TSW_CENTRAL_QCI_GATESEL_INDEX_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK) >> TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK   (0x80000000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT   (31U)
 
#define TSW_CENTRAL_QCI_FCTRL_ENBLK_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_ENBLK_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK   (0x40000000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT   (30U)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFID_MASK   (0x20000000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT   (29U)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFID_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_ENFID_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_ENSID_MASK   (0x10000000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT   (28U)
 
#define TSW_CENTRAL_QCI_FCTRL_ENSID_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_ENSID_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK   (0x8000000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT   (27U)
 
#define TSW_CENTRAL_QCI_FCTRL_ENPCP_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_ENPCP_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_PCP_MASK   (0x7000000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT   (24U)
 
#define TSW_CENTRAL_QCI_FCTRL_PCP_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_PCP_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_FMD_MASK   (0xFF0000UL)
 
#define TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT   (16U)
 
#define TSW_CENTRAL_QCI_FCTRL_FMD_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_FMD_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK) >> TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_GID_MASK   (0xFF00U)
 
#define TSW_CENTRAL_QCI_FCTRL_GID_SHIFT   (8U)
 
#define TSW_CENTRAL_QCI_FCTRL_GID_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_GID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_GID_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_GID_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_GID_MASK) >> TSW_CENTRAL_QCI_FCTRL_GID_SHIFT)
 
#define TSW_CENTRAL_QCI_FCTRL_SID_MASK   (0xFFU)
 
#define TSW_CENTRAL_QCI_FCTRL_SID_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_FCTRL_SID_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_SID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_SID_MASK)
 
#define TSW_CENTRAL_QCI_FCTRL_SID_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_SID_MASK) >> TSW_CENTRAL_QCI_FCTRL_SID_SHIFT)
 
#define TSW_CENTRAL_QCI_FSIZE_BLK_MASK   (0x80000000UL)
 
#define TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT   (31U)
 
#define TSW_CENTRAL_QCI_FSIZE_BLK_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK)
 
#define TSW_CENTRAL_QCI_FSIZE_BLK_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK) >> TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT)
 
#define TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK   (0xFFFFU)
 
#define TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_FSIZE_MXSZ_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK)
 
#define TSW_CENTRAL_QCI_FSIZE_MXSZ_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK) >> TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT)
 
#define TSW_QCI_CNT_VALUE_MASK   (0xFFFFFFFFUL)
 
#define TSW_QCI_CNT_VALUE_SHIFT   (0U)
 
#define TSW_QCI_CNT_VALUE_GET(x)   (((uint32_t)(x) & TSW_QCI_CNT_VALUE_MASK) >> TSW_QCI_CNT_VALUE_SHIFT)
 
#define TSW_CENTRAL_QCI_MCTRL_RESET_MASK   (0x80000000UL)
 
#define TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT   (31U)
 
#define TSW_CENTRAL_QCI_MCTRL_RESET_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK)
 
#define TSW_CENTRAL_QCI_MCTRL_RESET_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK) >> TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFR_MASK   (0x10U)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT   (4U)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFR_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFR_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK   (0x8U)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT   (3U)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFREN_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK)
 
#define TSW_CENTRAL_QCI_MCTRL_MAFREN_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT)
 
#define TSW_CENTRAL_QCI_MCTRL_DOY_MASK   (0x4U)
 
#define TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT   (2U)
 
#define TSW_CENTRAL_QCI_MCTRL_DOY_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK)
 
#define TSW_CENTRAL_QCI_MCTRL_DOY_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK) >> TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT)
 
#define TSW_CENTRAL_QCI_MCTRL_CM_MASK   (0x2U)
 
#define TSW_CENTRAL_QCI_MCTRL_CM_SHIFT   (1U)
 
#define TSW_CENTRAL_QCI_MCTRL_CM_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CM_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CM_MASK)
 
#define TSW_CENTRAL_QCI_MCTRL_CM_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CM_MASK) >> TSW_CENTRAL_QCI_MCTRL_CM_SHIFT)
 
#define TSW_CENTRAL_QCI_MCTRL_CF_MASK   (0x1U)
 
#define TSW_CENTRAL_QCI_MCTRL_CF_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_MCTRL_CF_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CF_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CF_MASK)
 
#define TSW_CENTRAL_QCI_MCTRL_CF_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CF_MASK) >> TSW_CENTRAL_QCI_MCTRL_CF_SHIFT)
 
#define TSW_CENTRAL_QCI_CIR_CIR_MASK   (0xFFFFFFUL)
 
#define TSW_CENTRAL_QCI_CIR_CIR_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_CIR_CIR_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_CIR_CIR_SHIFT) & TSW_CENTRAL_QCI_CIR_CIR_MASK)
 
#define TSW_CENTRAL_QCI_CIR_CIR_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_CIR_CIR_MASK) >> TSW_CENTRAL_QCI_CIR_CIR_SHIFT)
 
#define TSW_CENTRAL_QCI_CBS_CBS_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_CBS_CBS_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_CBS_CBS_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_CBS_CBS_SHIFT) & TSW_CENTRAL_QCI_CBS_CBS_MASK)
 
#define TSW_CENTRAL_QCI_CBS_CBS_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_CBS_CBS_MASK) >> TSW_CENTRAL_QCI_CBS_CBS_SHIFT)
 
#define TSW_CENTRAL_QCI_EIR_EIR_MASK   (0xFFFFFFUL)
 
#define TSW_CENTRAL_QCI_EIR_EIR_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_EIR_EIR_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_EIR_EIR_SHIFT) & TSW_CENTRAL_QCI_EIR_EIR_MASK)
 
#define TSW_CENTRAL_QCI_EIR_EIR_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_EIR_EIR_MASK) >> TSW_CENTRAL_QCI_EIR_EIR_SHIFT)
 
#define TSW_CENTRAL_QCI_EBS_EBS_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_EBS_EBS_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_EBS_EBS_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_EBS_EBS_SHIFT) & TSW_CENTRAL_QCI_EBS_EBS_MASK)
 
#define TSW_CENTRAL_QCI_EBS_EBS_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_EBS_EBS_MASK) >> TSW_CENTRAL_QCI_EBS_EBS_SHIFT)
 
#define TSW_CENTRAL_QCI_GCTRL_IPV_MASK   (0xE0U)
 
#define TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT   (5U)
 
#define TSW_CENTRAL_QCI_GCTRL_IPV_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK)
 
#define TSW_CENTRAL_QCI_GCTRL_IPV_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK) >> TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT)
 
#define TSW_CENTRAL_QCI_GCTRL_STATE_MASK   (0x10U)
 
#define TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT   (4U)
 
#define TSW_CENTRAL_QCI_GCTRL_STATE_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK)
 
#define TSW_CENTRAL_QCI_GCTRL_STATE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK) >> TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT)
 
#define TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK   (0x8U)
 
#define TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT   (3U)
 
#define TSW_CENTRAL_QCI_GCTRL_CDOEE_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK)
 
#define TSW_CENTRAL_QCI_GCTRL_CDOEE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT)
 
#define TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK   (0x4U)
 
#define TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT   (2U)
 
#define TSW_CENTRAL_QCI_GCTRL_CDIRE_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK)
 
#define TSW_CENTRAL_QCI_GCTRL_CDIRE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT)
 
#define TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK   (0x2U)
 
#define TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT   (1U)
 
#define TSW_CENTRAL_QCI_GCTRL_CFGCH_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK)
 
#define TSW_CENTRAL_QCI_GCTRL_CFGCH_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK) >> TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT)
 
#define TSW_CENTRAL_QCI_GCTRL_EN_MASK   (0x1U)
 
#define TSW_CENTRAL_QCI_GCTRL_EN_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_GCTRL_EN_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_EN_SHIFT) & TSW_CENTRAL_QCI_GCTRL_EN_MASK)
 
#define TSW_CENTRAL_QCI_GCTRL_EN_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_EN_MASK) >> TSW_CENTRAL_QCI_GCTRL_EN_SHIFT)
 
#define TSW_CENTRAL_QCI_GSTATUS_IPV_MASK   (0xE0U)
 
#define TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT   (5U)
 
#define TSW_CENTRAL_QCI_GSTATUS_IPV_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_IPV_MASK) >> TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT)
 
#define TSW_CENTRAL_QCI_GSTATUS_STATE_MASK   (0x10U)
 
#define TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT   (4U)
 
#define TSW_CENTRAL_QCI_GSTATUS_STATE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_STATE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK   (0x8U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT   (3U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDOE_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDOE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK   (0x4U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT   (2U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDIR_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK)
 
#define TSW_CENTRAL_QCI_GSTATUS_CDIR_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK   (0x2U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT   (1U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGP_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK   (0x1U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK)
 
#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT)
 
#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK   (0xFU)
 
#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK)
 
#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK) >> TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT)
 
#define TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK   (0xF0000UL)
 
#define TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT   (16U)
 
#define TSW_CENTRAL_QCI_LISTLEN_OLEN_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT)
 
#define TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK   (0xFU)
 
#define TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_LISTLEN_ALEN_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK)
 
#define TSW_CENTRAL_QCI_LISTLEN_ALEN_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT)
 
#define TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK   (0x3FFFFFFFUL)
 
#define TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_ACYCLETM_ACT_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK)
 
#define TSW_CENTRAL_QCI_ACYCLETM_ACT_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK) >> TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT)
 
#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK   (0x3FFFFFFFUL)
 
#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK)
 
#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK) >> TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT)
 
#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK)
 
#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK) >> TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK   (0x80000000UL)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT   (31U)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK   (0x70000000UL)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT   (28U)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK   (0xFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK)
 
#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SET(x)   (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK)
 
#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK) >> TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT)
 
#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK   (0xFFFFFFFFUL)
 
#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT   (0U)
 
#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_GET(x)   (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT)
 
#define TSW_MM2S_DMA_CR_MXLEN_MASK   (0xFF000000UL)
 
#define TSW_MM2S_DMA_CR_MXLEN_SHIFT   (24U)
 
#define TSW_MM2S_DMA_CR_MXLEN_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_CR_MXLEN_SHIFT) & TSW_MM2S_DMA_CR_MXLEN_MASK)
 
#define TSW_MM2S_DMA_CR_MXLEN_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CR_MXLEN_MASK) >> TSW_MM2S_DMA_CR_MXLEN_SHIFT)
 
#define TSW_MM2S_DMA_CR_IRQEN_MASK   (0x8U)
 
#define TSW_MM2S_DMA_CR_IRQEN_SHIFT   (3U)
 
#define TSW_MM2S_DMA_CR_IRQEN_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_CR_IRQEN_SHIFT) & TSW_MM2S_DMA_CR_IRQEN_MASK)
 
#define TSW_MM2S_DMA_CR_IRQEN_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CR_IRQEN_MASK) >> TSW_MM2S_DMA_CR_IRQEN_SHIFT)
 
#define TSW_MM2S_DMA_CR_RESET_MASK   (0x4U)
 
#define TSW_MM2S_DMA_CR_RESET_SHIFT   (2U)
 
#define TSW_MM2S_DMA_CR_RESET_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_CR_RESET_SHIFT) & TSW_MM2S_DMA_CR_RESET_MASK)
 
#define TSW_MM2S_DMA_CR_RESET_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CR_RESET_MASK) >> TSW_MM2S_DMA_CR_RESET_SHIFT)
 
#define TSW_MM2S_DMA_CR_SOE_MASK   (0x2U)
 
#define TSW_MM2S_DMA_CR_SOE_SHIFT   (1U)
 
#define TSW_MM2S_DMA_CR_SOE_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_CR_SOE_SHIFT) & TSW_MM2S_DMA_CR_SOE_MASK)
 
#define TSW_MM2S_DMA_CR_SOE_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CR_SOE_MASK) >> TSW_MM2S_DMA_CR_SOE_SHIFT)
 
#define TSW_MM2S_DMA_CR_RUN_MASK   (0x1U)
 
#define TSW_MM2S_DMA_CR_RUN_SHIFT   (0U)
 
#define TSW_MM2S_DMA_CR_RUN_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_CR_RUN_SHIFT) & TSW_MM2S_DMA_CR_RUN_MASK)
 
#define TSW_MM2S_DMA_CR_RUN_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CR_RUN_MASK) >> TSW_MM2S_DMA_CR_RUN_SHIFT)
 
#define TSW_MM2S_DMA_SR_RBUFF_MASK   (0x80U)
 
#define TSW_MM2S_DMA_SR_RBUFF_SHIFT   (7U)
 
#define TSW_MM2S_DMA_SR_RBUFF_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFF_MASK) >> TSW_MM2S_DMA_SR_RBUFF_SHIFT)
 
#define TSW_MM2S_DMA_SR_RBUFE_MASK   (0x40U)
 
#define TSW_MM2S_DMA_SR_RBUFE_SHIFT   (6U)
 
#define TSW_MM2S_DMA_SR_RBUFE_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFE_MASK) >> TSW_MM2S_DMA_SR_RBUFE_SHIFT)
 
#define TSW_MM2S_DMA_SR_CBUFF_MASK   (0x20U)
 
#define TSW_MM2S_DMA_SR_CBUFF_SHIFT   (5U)
 
#define TSW_MM2S_DMA_SR_CBUFF_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFF_MASK) >> TSW_MM2S_DMA_SR_CBUFF_SHIFT)
 
#define TSW_MM2S_DMA_SR_CBUFE_MASK   (0x10U)
 
#define TSW_MM2S_DMA_SR_CBUFE_SHIFT   (4U)
 
#define TSW_MM2S_DMA_SR_CBUFE_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFE_MASK) >> TSW_MM2S_DMA_SR_CBUFE_SHIFT)
 
#define TSW_MM2S_DMA_SR_IRQ_MASK   (0x8U)
 
#define TSW_MM2S_DMA_SR_IRQ_SHIFT   (3U)
 
#define TSW_MM2S_DMA_SR_IRQ_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_SR_IRQ_SHIFT) & TSW_MM2S_DMA_SR_IRQ_MASK)
 
#define TSW_MM2S_DMA_SR_IRQ_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_IRQ_MASK) >> TSW_MM2S_DMA_SR_IRQ_SHIFT)
 
#define TSW_MM2S_DMA_SR_RSET_MASK   (0x4U)
 
#define TSW_MM2S_DMA_SR_RSET_SHIFT   (2U)
 
#define TSW_MM2S_DMA_SR_RSET_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_RSET_MASK) >> TSW_MM2S_DMA_SR_RSET_SHIFT)
 
#define TSW_MM2S_DMA_SR_BUSY_MASK   (0x2U)
 
#define TSW_MM2S_DMA_SR_BUSY_SHIFT   (1U)
 
#define TSW_MM2S_DMA_SR_BUSY_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_BUSY_MASK) >> TSW_MM2S_DMA_SR_BUSY_SHIFT)
 
#define TSW_MM2S_DMA_SR_STOP_MASK   (0x1U)
 
#define TSW_MM2S_DMA_SR_STOP_SHIFT   (0U)
 
#define TSW_MM2S_DMA_SR_STOP_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_SR_STOP_MASK) >> TSW_MM2S_DMA_SR_STOP_SHIFT)
 
#define TSW_MM2S_DMA_FILL_RFILL_MASK   (0xFFFF0000UL)
 
#define TSW_MM2S_DMA_FILL_RFILL_SHIFT   (16U)
 
#define TSW_MM2S_DMA_FILL_RFILL_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_FILL_RFILL_MASK) >> TSW_MM2S_DMA_FILL_RFILL_SHIFT)
 
#define TSW_MM2S_DMA_FILL_CFILL_MASK   (0xFFFFU)
 
#define TSW_MM2S_DMA_FILL_CFILL_SHIFT   (0U)
 
#define TSW_MM2S_DMA_FILL_CFILL_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_FILL_CFILL_MASK) >> TSW_MM2S_DMA_FILL_CFILL_SHIFT)
 
#define TSW_MM2S_DMA_CFG_DBUFD_MASK   (0xF000000UL)
 
#define TSW_MM2S_DMA_CFG_DBUFD_SHIFT   (24U)
 
#define TSW_MM2S_DMA_CFG_DBUFD_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CFG_DBUFD_MASK) >> TSW_MM2S_DMA_CFG_DBUFD_SHIFT)
 
#define TSW_MM2S_DMA_CFG_CBUFD_MASK   (0xF00000UL)
 
#define TSW_MM2S_DMA_CFG_CBUFD_SHIFT   (20U)
 
#define TSW_MM2S_DMA_CFG_CBUFD_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CFG_CBUFD_MASK) >> TSW_MM2S_DMA_CFG_CBUFD_SHIFT)
 
#define TSW_MM2S_DMA_CFG_ENA64_MASK   (0x80000UL)
 
#define TSW_MM2S_DMA_CFG_ENA64_SHIFT   (19U)
 
#define TSW_MM2S_DMA_CFG_ENA64_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ENA64_MASK) >> TSW_MM2S_DMA_CFG_ENA64_SHIFT)
 
#define TSW_MM2S_DMA_CFG_ASIZE_MASK   (0x70000UL)
 
#define TSW_MM2S_DMA_CFG_ASIZE_SHIFT   (16U)
 
#define TSW_MM2S_DMA_CFG_ASIZE_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ASIZE_MASK) >> TSW_MM2S_DMA_CFG_ASIZE_SHIFT)
 
#define TSW_MM2S_DMA_CFG_VER_MASK   (0xFFFFU)
 
#define TSW_MM2S_DMA_CFG_VER_SHIFT   (0U)
 
#define TSW_MM2S_DMA_CFG_VER_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CFG_VER_MASK) >> TSW_MM2S_DMA_CFG_VER_SHIFT)
 
#define TSW_MM2S_ADDRLO_ADDRLO_MASK   (0xFFFFFFFFUL)
 
#define TSW_MM2S_ADDRLO_ADDRLO_SHIFT   (0U)
 
#define TSW_MM2S_ADDRLO_ADDRLO_SET(x)   (((uint32_t)(x) << TSW_MM2S_ADDRLO_ADDRLO_SHIFT) & TSW_MM2S_ADDRLO_ADDRLO_MASK)
 
#define TSW_MM2S_ADDRLO_ADDRLO_GET(x)   (((uint32_t)(x) & TSW_MM2S_ADDRLO_ADDRLO_MASK) >> TSW_MM2S_ADDRLO_ADDRLO_SHIFT)
 
#define TSW_MM2S_LENGTH_LENGTH_MASK   (0xFFFFU)
 
#define TSW_MM2S_LENGTH_LENGTH_SHIFT   (0U)
 
#define TSW_MM2S_LENGTH_LENGTH_SET(x)   (((uint32_t)(x) << TSW_MM2S_LENGTH_LENGTH_SHIFT) & TSW_MM2S_LENGTH_LENGTH_MASK)
 
#define TSW_MM2S_LENGTH_LENGTH_GET(x)   (((uint32_t)(x) & TSW_MM2S_LENGTH_LENGTH_MASK) >> TSW_MM2S_LENGTH_LENGTH_SHIFT)
 
#define TSW_MM2S_CTRL_GO_MASK   (0x80000000UL)
 
#define TSW_MM2S_CTRL_GO_SHIFT   (31U)
 
#define TSW_MM2S_CTRL_GO_SET(x)   (((uint32_t)(x) << TSW_MM2S_CTRL_GO_SHIFT) & TSW_MM2S_CTRL_GO_MASK)
 
#define TSW_MM2S_CTRL_GO_GET(x)   (((uint32_t)(x) & TSW_MM2S_CTRL_GO_MASK) >> TSW_MM2S_CTRL_GO_SHIFT)
 
#define TSW_MM2S_CTRL_NGENLAST_MASK   (0x10U)
 
#define TSW_MM2S_CTRL_NGENLAST_SHIFT   (4U)
 
#define TSW_MM2S_CTRL_NGENLAST_SET(x)   (((uint32_t)(x) << TSW_MM2S_CTRL_NGENLAST_SHIFT) & TSW_MM2S_CTRL_NGENLAST_MASK)
 
#define TSW_MM2S_CTRL_NGENLAST_GET(x)   (((uint32_t)(x) & TSW_MM2S_CTRL_NGENLAST_MASK) >> TSW_MM2S_CTRL_NGENLAST_SHIFT)
 
#define TSW_MM2S_CTRL_ID_MASK   (0xFU)
 
#define TSW_MM2S_CTRL_ID_SHIFT   (0U)
 
#define TSW_MM2S_CTRL_ID_SET(x)   (((uint32_t)(x) << TSW_MM2S_CTRL_ID_SHIFT) & TSW_MM2S_CTRL_ID_MASK)
 
#define TSW_MM2S_CTRL_ID_GET(x)   (((uint32_t)(x) & TSW_MM2S_CTRL_ID_MASK) >> TSW_MM2S_CTRL_ID_SHIFT)
 
#define TSW_MM2S_RESP_LAST_MASK   (0x40000000UL)
 
#define TSW_MM2S_RESP_LAST_SHIFT   (30U)
 
#define TSW_MM2S_RESP_LAST_GET(x)   (((uint32_t)(x) & TSW_MM2S_RESP_LAST_MASK) >> TSW_MM2S_RESP_LAST_SHIFT)
 
#define TSW_MM2S_RESP_DECERR_MASK   (0x20000000UL)
 
#define TSW_MM2S_RESP_DECERR_SHIFT   (29U)
 
#define TSW_MM2S_RESP_DECERR_GET(x)   (((uint32_t)(x) & TSW_MM2S_RESP_DECERR_MASK) >> TSW_MM2S_RESP_DECERR_SHIFT)
 
#define TSW_MM2S_RESP_SLVERR_MASK   (0x10000000UL)
 
#define TSW_MM2S_RESP_SLVERR_SHIFT   (28U)
 
#define TSW_MM2S_RESP_SLVERR_GET(x)   (((uint32_t)(x) & TSW_MM2S_RESP_SLVERR_MASK) >> TSW_MM2S_RESP_SLVERR_SHIFT)
 
#define TSW_MM2S_RESP_ID_MASK   (0xF000000UL)
 
#define TSW_MM2S_RESP_ID_SHIFT   (24U)
 
#define TSW_MM2S_RESP_ID_GET(x)   (((uint32_t)(x) & TSW_MM2S_RESP_ID_MASK) >> TSW_MM2S_RESP_ID_SHIFT)
 
#define TSW_MM2S_RESP_LENGTH_MASK   (0xFFFFU)
 
#define TSW_MM2S_RESP_LENGTH_SHIFT   (0U)
 
#define TSW_MM2S_RESP_LENGTH_GET(x)   (((uint32_t)(x) & TSW_MM2S_RESP_LENGTH_MASK) >> TSW_MM2S_RESP_LENGTH_SHIFT)
 
#define TSW_S2MM_DMA_CR_MXLEN_MASK   (0xFF000000UL)
 
#define TSW_S2MM_DMA_CR_MXLEN_SHIFT   (24U)
 
#define TSW_S2MM_DMA_CR_MXLEN_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_CR_MXLEN_SHIFT) & TSW_S2MM_DMA_CR_MXLEN_MASK)
 
#define TSW_S2MM_DMA_CR_MXLEN_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CR_MXLEN_MASK) >> TSW_S2MM_DMA_CR_MXLEN_SHIFT)
 
#define TSW_S2MM_DMA_CR_IRQEN_MASK   (0x8U)
 
#define TSW_S2MM_DMA_CR_IRQEN_SHIFT   (3U)
 
#define TSW_S2MM_DMA_CR_IRQEN_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_CR_IRQEN_SHIFT) & TSW_S2MM_DMA_CR_IRQEN_MASK)
 
#define TSW_S2MM_DMA_CR_IRQEN_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CR_IRQEN_MASK) >> TSW_S2MM_DMA_CR_IRQEN_SHIFT)
 
#define TSW_S2MM_DMA_CR_RESET_MASK   (0x4U)
 
#define TSW_S2MM_DMA_CR_RESET_SHIFT   (2U)
 
#define TSW_S2MM_DMA_CR_RESET_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_CR_RESET_SHIFT) & TSW_S2MM_DMA_CR_RESET_MASK)
 
#define TSW_S2MM_DMA_CR_RESET_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CR_RESET_MASK) >> TSW_S2MM_DMA_CR_RESET_SHIFT)
 
#define TSW_S2MM_DMA_CR_SOE_MASK   (0x2U)
 
#define TSW_S2MM_DMA_CR_SOE_SHIFT   (1U)
 
#define TSW_S2MM_DMA_CR_SOE_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_CR_SOE_SHIFT) & TSW_S2MM_DMA_CR_SOE_MASK)
 
#define TSW_S2MM_DMA_CR_SOE_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CR_SOE_MASK) >> TSW_S2MM_DMA_CR_SOE_SHIFT)
 
#define TSW_S2MM_DMA_CR_RUN_MASK   (0x1U)
 
#define TSW_S2MM_DMA_CR_RUN_SHIFT   (0U)
 
#define TSW_S2MM_DMA_CR_RUN_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_CR_RUN_SHIFT) & TSW_S2MM_DMA_CR_RUN_MASK)
 
#define TSW_S2MM_DMA_CR_RUN_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CR_RUN_MASK) >> TSW_S2MM_DMA_CR_RUN_SHIFT)
 
#define TSW_S2MM_DMA_SR_RBUFF_MASK   (0x80U)
 
#define TSW_S2MM_DMA_SR_RBUFF_SHIFT   (7U)
 
#define TSW_S2MM_DMA_SR_RBUFF_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFF_MASK) >> TSW_S2MM_DMA_SR_RBUFF_SHIFT)
 
#define TSW_S2MM_DMA_SR_RBUFE_MASK   (0x40U)
 
#define TSW_S2MM_DMA_SR_RBUFE_SHIFT   (6U)
 
#define TSW_S2MM_DMA_SR_RBUFE_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFE_MASK) >> TSW_S2MM_DMA_SR_RBUFE_SHIFT)
 
#define TSW_S2MM_DMA_SR_CBUFF_MASK   (0x20U)
 
#define TSW_S2MM_DMA_SR_CBUFF_SHIFT   (5U)
 
#define TSW_S2MM_DMA_SR_CBUFF_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFF_MASK) >> TSW_S2MM_DMA_SR_CBUFF_SHIFT)
 
#define TSW_S2MM_DMA_SR_CBUFE_MASK   (0x10U)
 
#define TSW_S2MM_DMA_SR_CBUFE_SHIFT   (4U)
 
#define TSW_S2MM_DMA_SR_CBUFE_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFE_MASK) >> TSW_S2MM_DMA_SR_CBUFE_SHIFT)
 
#define TSW_S2MM_DMA_SR_IRQ_MASK   (0x8U)
 
#define TSW_S2MM_DMA_SR_IRQ_SHIFT   (3U)
 
#define TSW_S2MM_DMA_SR_IRQ_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_SR_IRQ_SHIFT) & TSW_S2MM_DMA_SR_IRQ_MASK)
 
#define TSW_S2MM_DMA_SR_IRQ_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_IRQ_MASK) >> TSW_S2MM_DMA_SR_IRQ_SHIFT)
 
#define TSW_S2MM_DMA_SR_RSET_MASK   (0x4U)
 
#define TSW_S2MM_DMA_SR_RSET_SHIFT   (2U)
 
#define TSW_S2MM_DMA_SR_RSET_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_RSET_MASK) >> TSW_S2MM_DMA_SR_RSET_SHIFT)
 
#define TSW_S2MM_DMA_SR_BUSY_MASK   (0x2U)
 
#define TSW_S2MM_DMA_SR_BUSY_SHIFT   (1U)
 
#define TSW_S2MM_DMA_SR_BUSY_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_BUSY_MASK) >> TSW_S2MM_DMA_SR_BUSY_SHIFT)
 
#define TSW_S2MM_DMA_SR_STOP_MASK   (0x1U)
 
#define TSW_S2MM_DMA_SR_STOP_SHIFT   (0U)
 
#define TSW_S2MM_DMA_SR_STOP_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_SR_STOP_MASK) >> TSW_S2MM_DMA_SR_STOP_SHIFT)
 
#define TSW_S2MM_DMA_FILL_RFILL_MASK   (0xFFFF0000UL)
 
#define TSW_S2MM_DMA_FILL_RFILL_SHIFT   (16U)
 
#define TSW_S2MM_DMA_FILL_RFILL_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_FILL_RFILL_MASK) >> TSW_S2MM_DMA_FILL_RFILL_SHIFT)
 
#define TSW_S2MM_DMA_FILL_CFILL_MASK   (0xFFFFU)
 
#define TSW_S2MM_DMA_FILL_CFILL_SHIFT   (0U)
 
#define TSW_S2MM_DMA_FILL_CFILL_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_FILL_CFILL_MASK) >> TSW_S2MM_DMA_FILL_CFILL_SHIFT)
 
#define TSW_S2MM_DMA_CFG_DBUFD_MASK   (0xF000000UL)
 
#define TSW_S2MM_DMA_CFG_DBUFD_SHIFT   (24U)
 
#define TSW_S2MM_DMA_CFG_DBUFD_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CFG_DBUFD_MASK) >> TSW_S2MM_DMA_CFG_DBUFD_SHIFT)
 
#define TSW_S2MM_DMA_CFG_CBUFD_MASK   (0xF00000UL)
 
#define TSW_S2MM_DMA_CFG_CBUFD_SHIFT   (20U)
 
#define TSW_S2MM_DMA_CFG_CBUFD_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CFG_CBUFD_MASK) >> TSW_S2MM_DMA_CFG_CBUFD_SHIFT)
 
#define TSW_S2MM_DMA_CFG_ENA64_MASK   (0x80000UL)
 
#define TSW_S2MM_DMA_CFG_ENA64_SHIFT   (19U)
 
#define TSW_S2MM_DMA_CFG_ENA64_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ENA64_MASK) >> TSW_S2MM_DMA_CFG_ENA64_SHIFT)
 
#define TSW_S2MM_DMA_CFG_ASIZE_MASK   (0x70000UL)
 
#define TSW_S2MM_DMA_CFG_ASIZE_SHIFT   (16U)
 
#define TSW_S2MM_DMA_CFG_ASIZE_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ASIZE_MASK) >> TSW_S2MM_DMA_CFG_ASIZE_SHIFT)
 
#define TSW_S2MM_DMA_CFG_VER_MASK   (0xFFFFU)
 
#define TSW_S2MM_DMA_CFG_VER_SHIFT   (0U)
 
#define TSW_S2MM_DMA_CFG_VER_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CFG_VER_MASK) >> TSW_S2MM_DMA_CFG_VER_SHIFT)
 
#define TSW_S2MM_ADDRLO_ADDRLO_MASK   (0xFFFFFFFFUL)
 
#define TSW_S2MM_ADDRLO_ADDRLO_SHIFT   (0U)
 
#define TSW_S2MM_ADDRLO_ADDRLO_SET(x)   (((uint32_t)(x) << TSW_S2MM_ADDRLO_ADDRLO_SHIFT) & TSW_S2MM_ADDRLO_ADDRLO_MASK)
 
#define TSW_S2MM_ADDRLO_ADDRLO_GET(x)   (((uint32_t)(x) & TSW_S2MM_ADDRLO_ADDRLO_MASK) >> TSW_S2MM_ADDRLO_ADDRLO_SHIFT)
 
#define TSW_S2MM_LENGTH_LENGTH_MASK   (0xFFFFU)
 
#define TSW_S2MM_LENGTH_LENGTH_SHIFT   (0U)
 
#define TSW_S2MM_LENGTH_LENGTH_SET(x)   (((uint32_t)(x) << TSW_S2MM_LENGTH_LENGTH_SHIFT) & TSW_S2MM_LENGTH_LENGTH_MASK)
 
#define TSW_S2MM_LENGTH_LENGTH_GET(x)   (((uint32_t)(x) & TSW_S2MM_LENGTH_LENGTH_MASK) >> TSW_S2MM_LENGTH_LENGTH_SHIFT)
 
#define TSW_S2MM_CTRL_GO_MASK   (0x80000000UL)
 
#define TSW_S2MM_CTRL_GO_SHIFT   (31U)
 
#define TSW_S2MM_CTRL_GO_SET(x)   (((uint32_t)(x) << TSW_S2MM_CTRL_GO_SHIFT) & TSW_S2MM_CTRL_GO_MASK)
 
#define TSW_S2MM_CTRL_GO_GET(x)   (((uint32_t)(x) & TSW_S2MM_CTRL_GO_MASK) >> TSW_S2MM_CTRL_GO_SHIFT)
 
#define TSW_S2MM_CTRL_ID_MASK   (0xFU)
 
#define TSW_S2MM_CTRL_ID_SHIFT   (0U)
 
#define TSW_S2MM_CTRL_ID_SET(x)   (((uint32_t)(x) << TSW_S2MM_CTRL_ID_SHIFT) & TSW_S2MM_CTRL_ID_MASK)
 
#define TSW_S2MM_CTRL_ID_GET(x)   (((uint32_t)(x) & TSW_S2MM_CTRL_ID_MASK) >> TSW_S2MM_CTRL_ID_SHIFT)
 
#define TSW_S2MM_RESP_LAST_MASK   (0x40000000UL)
 
#define TSW_S2MM_RESP_LAST_SHIFT   (30U)
 
#define TSW_S2MM_RESP_LAST_GET(x)   (((uint32_t)(x) & TSW_S2MM_RESP_LAST_MASK) >> TSW_S2MM_RESP_LAST_SHIFT)
 
#define TSW_S2MM_RESP_DECERR_MASK   (0x20000000UL)
 
#define TSW_S2MM_RESP_DECERR_SHIFT   (29U)
 
#define TSW_S2MM_RESP_DECERR_GET(x)   (((uint32_t)(x) & TSW_S2MM_RESP_DECERR_MASK) >> TSW_S2MM_RESP_DECERR_SHIFT)
 
#define TSW_S2MM_RESP_SLVERR_MASK   (0x10000000UL)
 
#define TSW_S2MM_RESP_SLVERR_SHIFT   (28U)
 
#define TSW_S2MM_RESP_SLVERR_GET(x)   (((uint32_t)(x) & TSW_S2MM_RESP_SLVERR_MASK) >> TSW_S2MM_RESP_SLVERR_SHIFT)
 
#define TSW_S2MM_RESP_ID_MASK   (0xF000000UL)
 
#define TSW_S2MM_RESP_ID_SHIFT   (24U)
 
#define TSW_S2MM_RESP_ID_GET(x)   (((uint32_t)(x) & TSW_S2MM_RESP_ID_MASK) >> TSW_S2MM_RESP_ID_SHIFT)
 
#define TSW_S2MM_RESP_LENGTH_MASK   (0xFFFFU)
 
#define TSW_S2MM_RESP_LENGTH_SHIFT   (0U)
 
#define TSW_S2MM_RESP_LENGTH_GET(x)   (((uint32_t)(x) & TSW_S2MM_RESP_LENGTH_MASK) >> TSW_S2MM_RESP_LENGTH_SHIFT)
 
#define TSW_PTP_EVT_TS_CTL_ATSEN_MASK   (0x1E000000UL)
 
#define TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT   (25U)
 
#define TSW_PTP_EVT_TS_CTL_ATSEN_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK)
 
#define TSW_PTP_EVT_TS_CTL_ATSEN_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK) >> TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT)
 
#define TSW_PTP_EVT_TS_CTL_ATSFC_MASK   (0x1000000UL)
 
#define TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT   (24U)
 
#define TSW_PTP_EVT_TS_CTL_ATSFC_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK)
 
#define TSW_PTP_EVT_TS_CTL_ATSFC_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK) >> TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT)
 
#define TSW_PTP_EVT_TS_CTL_TSTIG_MASK   (0x10U)
 
#define TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT   (4U)
 
#define TSW_PTP_EVT_TS_CTL_TSTIG_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK)
 
#define TSW_PTP_EVT_TS_CTL_TSTIG_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK) >> TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT)
 
#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK) >> TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT)
 
#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK) >> TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT)
 
#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK)
 
#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT)
 
#define TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_NS0_SCP_NS_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK)
 
#define TSW_PTP_EVT_SCP_NS0_SCP_NS_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_RD_CNT_MASK   (0x3E000000UL)
 
#define TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT   (25U)
 
#define TSW_PTP_EVT_TMR_STS_RD_CNT_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_RD_CNT_MASK) >> TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_ATSSTM_MASK   (0x1000000UL)
 
#define TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT   (24U)
 
#define TSW_PTP_EVT_TMR_STS_ATSSTM_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATSSTM_MASK) >> TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_ATPORT_MASK   (0xF0000UL)
 
#define TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT   (16U)
 
#define TSW_PTP_EVT_TMR_STS_ATPORT_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATPORT_MASK) >> TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK   (0x400U)
 
#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT   (10U)
 
#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK   (0x200U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT   (9U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK   (0x100U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT   (8U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK   (0x80U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT   (7U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK   (0x40U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT   (6U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK   (0x20U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT   (5U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK   (0x10U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT   (4U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK   (0x8U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT   (3U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK   (0x4U)
 
#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT   (2U)
 
#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK   (0x2U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT   (1U)
 
#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK   (0x60000000UL)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT   (29U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK   (0x7000000UL)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT   (24U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK   (0x600000UL)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT   (21U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK   (0x70000UL)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT   (16U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK   (0x6000U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT   (13U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK   (0x700U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT   (8U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK   (0x60U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT   (5U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK   (0x10U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT   (4U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK   (0xFU)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK)
 
#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT)
 
#define TSW_PTP_EVT_ATSLO_STSLO_MASK   (0x7FFFFFFFUL)
 
#define TSW_PTP_EVT_ATSLO_STSLO_SHIFT   (0U)
 
#define TSW_PTP_EVT_ATSLO_STSLO_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_ATSLO_STSLO_MASK) >> TSW_PTP_EVT_ATSLO_STSLO_SHIFT)
 
#define TSW_PTP_EVT_ATSHI_STSHI_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_ATSHI_STSHI_SHIFT   (0U)
 
#define TSW_PTP_EVT_ATSHI_STSHI_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_ATSHI_STSHI_MASK) >> TSW_PTP_EVT_ATSHI_STSHI_SHIFT)
 
#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK)
 
#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT)
 
#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK)
 
#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT)
 
#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK)
 
#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT)
 
#define TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_NS1_SCP_NS_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK)
 
#define TSW_PTP_EVT_SCP_NS1_SCP_NS_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT)
 
#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK)
 
#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT)
 
#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK)
 
#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT)
 
#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK)
 
#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT)
 
#define TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_NS2_SCP_NS_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK)
 
#define TSW_PTP_EVT_SCP_NS2_SCP_NS_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT)
 
#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK)
 
#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT)
 
#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK)
 
#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT)
 
#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK)
 
#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT)
 
#define TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT   (0U)
 
#define TSW_PTP_EVT_SCP_NS3_SCP_NS_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK)
 
#define TSW_PTP_EVT_SCP_NS3_SCP_NS_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT)
 
#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK)
 
#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT)
 
#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)
 
#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK)
 
#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT)
 
#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK   (0x8U)
 
#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT   (3U)
 
#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK)
 
#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT)
 
#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK   (0x4U)
 
#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT   (2U)
 
#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK)
 
#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT)
 
#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK   (0x2U)
 
#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT   (1U)
 
#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK)
 
#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT)
 
#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK   (0x1U)
 
#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK)
 
#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT)
 
#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK   (0x1F000000UL)
 
#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT   (24U)
 
#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK)
 
#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT)
 
#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK   (0x1F0000UL)
 
#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT   (16U)
 
#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK)
 
#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT)
 
#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK   (0x1F00U)
 
#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT   (8U)
 
#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK)
 
#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT)
 
#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK   (0x1FU)
 
#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT   (0U)
 
#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SET(x)   (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK)
 
#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_GET(x)   (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT)
 
#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK   (0x800U)
 
#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT   (11U)
 
#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK) >> TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK   (0x400U)
 
#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT   (10U)
 
#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK) >> TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_DMA0_RST_MASK   (0x100U)
 
#define TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT   (8U)
 
#define TSW_SOFT_RST_CTRL_DMA0_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_DMA0_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK) >> TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK   (0x20U)
 
#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT   (5U)
 
#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK   (0x10U)
 
#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT   (4U)
 
#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK   (0x8U)
 
#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT   (3U)
 
#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK   (0x4U)
 
#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT   (2U)
 
#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK   (0x2U)
 
#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT   (1U)
 
#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT)
 
#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK   (0x1U)
 
#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT   (0U)
 
#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SET(x)   (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK)
 
#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_GET(x)   (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK   (0x20000UL)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT   (17U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK   (0x10000UL)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT   (16U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK   (0xE000U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT   (13U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK   (0x1000U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT   (12U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK   (0xFFFU)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT   (0U)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK   (0x2U)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT   (1U)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK   (0x1U)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT   (0U)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK)
 
#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK   (0xFFU)
 
#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK   (0xFF00U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT   (8U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK   (0x80U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT   (7U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK   (0x30U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT   (4U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK   (0x8U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT   (3U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK   (0x6U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT   (1U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK   (0x1U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK   (0xFFF0000UL)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT   (16U)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK   (0xF0000000UL)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT   (28U)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK   (0xFFF0000UL)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT   (16U)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK)
 
#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK   (0x2U)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT   (1U)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK   (0x1U)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK   (0xFFU)
 
#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK   (0x80000000UL)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT   (31U)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK   (0xFFU)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK   (0x80000000UL)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT   (31U)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK   (0xFFU)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK   (0xFFU)
 
#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK   (0x80000000UL)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT   (31U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK   (0xFF0000UL)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT   (16U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK   (0x1F00U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT   (8U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK   (0x10U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT   (4U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK   (0x8U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT   (3U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK   (0x4U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT   (2U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK   (0x2U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT   (1U)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK   (0xFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK   (0xFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK   (0xFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT   (0U)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK)
 
#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT)
 
#define TSW_EGFRCNT_VALUE_MASK   (0xFFFFFFFFUL)
 
#define TSW_EGFRCNT_VALUE_SHIFT   (0U)
 
#define TSW_EGFRCNT_VALUE_GET(x)   (((uint32_t)(x) & TSW_EGFRCNT_VALUE_MASK) >> TSW_EGFRCNT_VALUE_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK   (0x800U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT   (11U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK   (0x400U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT   (10U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK   (0x200U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT   (9U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK   (0x100U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT   (8U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK   (0x8U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT   (3U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK   (0x4U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT   (2U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK   (0x2U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT   (1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK   (0x40U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT   (6U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK   (0x20U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT   (5U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK   (0x10U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT   (4U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK   (0x8U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT   (3U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK   (0x4U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT   (2U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK   (0x2U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT   (1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK   (0x7FU)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK   (0xFFFF0000UL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT   (16U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK   (0x200U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT   (9U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK   (0x100U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT   (8U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK   (0x40U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT   (6U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK   (0x20U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT   (5U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK   (0x10U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT   (4U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK   (0x8U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT   (3U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK   (0x4U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT   (2U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK   (0x2U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT   (1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK   (0xFF000000UL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT   (24U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK   (0xFF0000UL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT   (16U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK)
 
#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK   (0xFFU)
 
#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK   (0xFF00U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT   (8U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK   (0x80U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT   (7U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK   (0x30U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT   (4U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK   (0x8U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT   (3U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK   (0x6U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT   (1U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK   (0xFFF0000UL)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT   (16U)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK   (0xF0000000UL)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT   (28U)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK   (0xFFF0000UL)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT   (16U)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK   (0xFFFFU)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK)
 
#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK   (0x2U)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT   (1U)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK   (0x1U)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK   (0xFFU)
 
#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK   (0x80000000UL)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT   (31U)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK   (0xFFU)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK   (0x80000000UL)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT   (31U)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK   (0xFFU)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK   (0xFFU)
 
#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK   (0x80000000UL)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT   (31U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK   (0xFF0000UL)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT   (16U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK   (0x1F00U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT   (8U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK   (0x10U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT   (4U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK   (0x8U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT   (3U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK   (0x4U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT   (2U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK   (0x2U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT   (1U)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK   (0xFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK   (0xFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK   (0xFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT   (0U)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK)
 
#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT)
 
#define TSW_IGFRCNT_VALUE_MASK   (0xFFFFFFFFUL)
 
#define TSW_IGFRCNT_VALUE_SHIFT   (0U)
 
#define TSW_IGFRCNT_VALUE_GET(x)   (((uint32_t)(x) & TSW_IGFRCNT_VALUE_MASK) >> TSW_IGFRCNT_VALUE_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_CTRL_EN_MASK   (0x1U)
 
#define TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_CTRL_EN_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK)
 
#define TSW_CPU_PORT_MONITOR_CTRL_EN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK) >> TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK   (0x4U)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT   (2U)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSRX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSRX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK   (0x2U)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT   (1U)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSTX_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSTX_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK   (0x1U)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSALL_SET(x)   (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK)
 
#define TSW_CPU_PORT_MONITOR_RESET_RSALL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK   (0xFFFF0000UL)
 
#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT   (16U)
 
#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK   (0xFF00U)
 
#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT   (8U)
 
#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK   (0x7FU)
 
#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK   (0xFFFFFFFFUL)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT   (0U)
 
#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x)   (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK   (0xFFFF0000UL)
 
#define TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT   (16U)
 
#define TSW_TSNPORT_MAC_MAC_VER_VER_H_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_VER_VER_L_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK   (0x10000UL)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT   (16U)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK   (0x1F000000UL)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT   (24U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK   (0x100000UL)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT   (20U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK   (0x80000UL)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT   (19U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK   (0x10000UL)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT   (16U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK   (0x2000U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT   (13U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK   (0x1000U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT   (12U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK   (0x800U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT   (11U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK   (0x700U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT   (8U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK   (0x60U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT   (5U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK   (0x10U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT   (4U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK   (0x8U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT   (3U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK   (0x4U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT   (2U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK   (0x2U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT   (1U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK   (0x1U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK   (0x8000U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT   (15U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK   (0x100U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT   (8U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK   (0xFFU)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK   (0xC0000000UL)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT   (30U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK   (0x1F000000UL)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT   (24U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK   (0x1F0000UL)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT   (16U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK   (0x100U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT   (8U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK   (0x1U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK)
 
#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK   (0x800U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT   (11U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK   (0x400U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT   (10U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK   (0x200U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT   (9U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK   (0x100U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT   (8U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK   (0x8U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT   (3U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK   (0x4U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT   (2U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK   (0x1U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT   (0U)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK)
 
#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT)
 
#define TSW_TSNPORT_RTC_CR_TAIE_MASK   (0x8U)
 
#define TSW_TSNPORT_RTC_CR_TAIE_SHIFT   (3U)
 
#define TSW_TSNPORT_RTC_CR_TAIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAIE_SHIFT) & TSW_TSNPORT_RTC_CR_TAIE_MASK)
 
#define TSW_TSNPORT_RTC_CR_TAIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAIE_MASK) >> TSW_TSNPORT_RTC_CR_TAIE_SHIFT)
 
#define TSW_TSNPORT_RTC_CR_TAEN_MASK   (0x4U)
 
#define TSW_TSNPORT_RTC_CR_TAEN_SHIFT   (2U)
 
#define TSW_TSNPORT_RTC_CR_TAEN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAEN_SHIFT) & TSW_TSNPORT_RTC_CR_TAEN_MASK)
 
#define TSW_TSNPORT_RTC_CR_TAEN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAEN_MASK) >> TSW_TSNPORT_RTC_CR_TAEN_SHIFT)
 
#define TSW_TSNPORT_RTC_CR_ALIE_MASK   (0x2U)
 
#define TSW_TSNPORT_RTC_CR_ALIE_SHIFT   (1U)
 
#define TSW_TSNPORT_RTC_CR_ALIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_ALIE_SHIFT) & TSW_TSNPORT_RTC_CR_ALIE_MASK)
 
#define TSW_TSNPORT_RTC_CR_ALIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_ALIE_MASK) >> TSW_TSNPORT_RTC_CR_ALIE_SHIFT)
 
#define TSW_TSNPORT_RTC_SR_TAIS_MASK   (0x8U)
 
#define TSW_TSNPORT_RTC_SR_TAIS_SHIFT   (3U)
 
#define TSW_TSNPORT_RTC_SR_TAIS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_SR_TAIS_SHIFT) & TSW_TSNPORT_RTC_SR_TAIS_MASK)
 
#define TSW_TSNPORT_RTC_SR_TAIS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_TAIS_MASK) >> TSW_TSNPORT_RTC_SR_TAIS_SHIFT)
 
#define TSW_TSNPORT_RTC_SR_ALIS_MASK   (0x2U)
 
#define TSW_TSNPORT_RTC_SR_ALIS_SHIFT   (1U)
 
#define TSW_TSNPORT_RTC_SR_ALIS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_ALIS_MASK) >> TSW_TSNPORT_RTC_SR_ALIS_SHIFT)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT   (24U)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK   (0xFFFFFFUL)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK)
 
#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT)
 
#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK)
 
#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK) >> TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT)
 
#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK)
 
#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK) >> TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT)
 
#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK)
 
#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK) >> TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT)
 
#define TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT   (24U)
 
#define TSW_TSNPORT_RTC_OFS_CH_SEXT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT)
 
#define TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK   (0xFFFFFFUL)
 
#define TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_OFS_CH_SFNS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK)
 
#define TSW_TSNPORT_RTC_OFS_CH_SFNS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT)
 
#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK   (0x3FFFFFFFUL)
 
#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK)
 
#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK) >> TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT)
 
#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK)
 
#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK) >> TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT)
 
#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK)
 
#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK) >> TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT)
 
#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK   (0x1FFFFFFFUL)
 
#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK)
 
#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK) >> TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT)
 
#define TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK   (0x1F0000UL)
 
#define TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT   (16U)
 
#define TSW_TSNPORT_TSYN_CR_TMR_ALD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK)
 
#define TSW_TSNPORT_TSYN_CR_TMR_ALD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT)
 
#define TSW_TSNPORT_TSYN_CR_TMR_EN_MASK   (0x1F00U)
 
#define TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT   (8U)
 
#define TSW_TSNPORT_TSYN_CR_TMR_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK)
 
#define TSW_TSNPORT_TSYN_CR_TMR_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT)
 
#define TSW_TSNPORT_TSYN_CR_TMRIE_MASK   (0x4U)
 
#define TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT   (2U)
 
#define TSW_TSNPORT_TSYN_CR_TMRIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK)
 
#define TSW_TSNPORT_TSYN_CR_TMRIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK) >> TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT)
 
#define TSW_TSNPORT_TSYN_CR_RXIE_MASK   (0x2U)
 
#define TSW_TSNPORT_TSYN_CR_RXIE_SHIFT   (1U)
 
#define TSW_TSNPORT_TSYN_CR_RXIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_RXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_RXIE_MASK)
 
#define TSW_TSNPORT_TSYN_CR_RXIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_RXIE_MASK) >> TSW_TSNPORT_TSYN_CR_RXIE_SHIFT)
 
#define TSW_TSNPORT_TSYN_CR_TXIE_MASK   (0x1U)
 
#define TSW_TSNPORT_TSYN_CR_TXIE_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_CR_TXIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TXIE_MASK)
 
#define TSW_TSNPORT_TSYN_CR_TXIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TXIE_MASK) >> TSW_TSNPORT_TSYN_CR_TXIE_SHIFT)
 
#define TSW_TSNPORT_TSYN_SR_TMR_DN_MASK   (0x1F00U)
 
#define TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT   (8U)
 
#define TSW_TSNPORT_TSYN_SR_TMR_DN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK)
 
#define TSW_TSNPORT_TSYN_SR_TMR_DN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK) >> TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT)
 
#define TSW_TSNPORT_TSYN_SR_TMRIS_MASK   (0x4U)
 
#define TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT   (2U)
 
#define TSW_TSNPORT_TSYN_SR_TMRIS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMRIS_MASK) >> TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT)
 
#define TSW_TSNPORT_TSYN_SR_RXIS_MASK   (0x2U)
 
#define TSW_TSNPORT_TSYN_SR_RXIS_SHIFT   (1U)
 
#define TSW_TSNPORT_TSYN_SR_RXIS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_RXIS_MASK) >> TSW_TSNPORT_TSYN_SR_RXIS_SHIFT)
 
#define TSW_TSNPORT_TSYN_SR_TXIS_MASK   (0x1U)
 
#define TSW_TSNPORT_TSYN_SR_TXIS_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_SR_TXIS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TXIS_MASK) >> TSW_TSNPORT_TSYN_SR_TXIS_SHIFT)
 
#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT)
 
#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK)
 
#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT)
 
#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK)
 
#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK   (0x80000000UL)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT   (31U)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK   (0x40000000UL)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT   (30U)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK   (0x7U)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT)
 
#define TSW_TSNPORT_TSYNTMR_PERIOD_MASK   (0xFFFFFUL)
 
#define TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYNTMR_PERIOD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK)
 
#define TSW_TSNPORT_TSYNTMR_PERIOD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK) >> TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT)
 
#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK   (0xFFFFFUL)
 
#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK)
 
#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK) >> TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK   (0xFFFU)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT   (0U)
 
#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT)
 
#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT   (0U)
 
#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK) >> TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT)
 
#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT   (0U)
 
#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK)
 
#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK) >> TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK   (0x7000000UL)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT   (24U)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK   (0xFFU)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT   (0U)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT   (0U)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT   (0U)
 
#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT   (24U)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK   (0xFF0000UL)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT   (16U)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK   (0xFF00U)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT   (8U)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK   (0xFF00U)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT   (8U)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK) >> TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK   (0x2U)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT   (1U)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK   (0x1U)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK) >> TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT)
 
#define TSW_TSNPORT_MXSDU_SDU_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_MXSDU_SDU_SHIFT   (0U)
 
#define TSW_TSNPORT_MXSDU_SDU_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MXSDU_SDU_SHIFT) & TSW_TSNPORT_MXSDU_SDU_MASK)
 
#define TSW_TSNPORT_MXSDU_SDU_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MXSDU_SDU_MASK) >> TSW_TSNPORT_MXSDU_SDU_SHIFT)
 
#define TSW_TSNPORT_TXSEL_CBS_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_TXSEL_CBS_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_TXSEL_CBS_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TXSEL_CBS_EN_SHIFT) & TSW_TSNPORT_TXSEL_CBS_EN_MASK)
 
#define TSW_TSNPORT_TXSEL_CBS_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TXSEL_CBS_EN_MASK) >> TSW_TSNPORT_TXSEL_CBS_EN_SHIFT)
 
#define TSW_TSNPORT_IDSEL_INT_MASK   (0xF0000UL)
 
#define TSW_TSNPORT_IDSEL_INT_SHIFT   (16U)
 
#define TSW_TSNPORT_IDSEL_INT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_IDSEL_INT_SHIFT) & TSW_TSNPORT_IDSEL_INT_MASK)
 
#define TSW_TSNPORT_IDSEL_INT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_IDSEL_INT_MASK) >> TSW_TSNPORT_IDSEL_INT_SHIFT)
 
#define TSW_TSNPORT_IDSEL_FRACT_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_IDSEL_FRACT_SHIFT   (0U)
 
#define TSW_TSNPORT_IDSEL_FRACT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_IDSEL_FRACT_SHIFT) & TSW_TSNPORT_IDSEL_FRACT_MASK)
 
#define TSW_TSNPORT_IDSEL_FRACT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_IDSEL_FRACT_MASK) >> TSW_TSNPORT_IDSEL_FRACT_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK   (0x100000UL)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT   (20U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK   (0x70000UL)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT   (16U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK   (0x7000U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT   (12U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK   (0xFF0U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT   (4U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK   (0x100000UL)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT   (20U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK   (0x70000UL)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT   (16U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK   (0x7000U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT   (12U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK   (0xFF0U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT   (4U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK   (0x100000UL)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT   (20U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK   (0x70000UL)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT   (16U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK   (0x7000U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT   (12U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK   (0xFF0U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT   (4U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK   (0x100000UL)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT   (20U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK   (0x70000UL)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT   (16U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK   (0x7000U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT   (12U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK   (0xFF0U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT   (4U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK)
 
#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK   (0xFF00U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT   (8U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK   (0x4U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT   (2U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK   (0x2U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT   (1U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK   (0x1U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT   (0U)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK)
 
#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT   (24U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK   (0xFF0000UL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT   (16U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK   (0xFF00U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT   (8U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK   (0x8U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT   (3U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK   (0x4U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT   (2U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK   (0x2U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT   (1U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK   (0x3FFFFFFFUL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK   (0x3FFFFFFFUL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK   (0xFF0000UL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT   (16U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK   (0x3FFFFFFFUL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT)
 
#define TSW_TSNPORT_MXTK_TICK_MASK   (0xFFFFFFUL)
 
#define TSW_TSNPORT_MXTK_TICK_SHIFT   (0U)
 
#define TSW_TSNPORT_MXTK_TICK_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_MXTK_TICK_SHIFT) & TSW_TSNPORT_MXTK_TICK_MASK)
 
#define TSW_TSNPORT_MXTK_TICK_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MXTK_TICK_MASK) >> TSW_TSNPORT_MXTK_TICK_SHIFT)
 
#define TSW_TSNPORT_TXOV_VALUE_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TXOV_VALUE_SHIFT   (0U)
 
#define TSW_TSNPORT_TXOV_VALUE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TXOV_VALUE_SHIFT) & TSW_TSNPORT_TXOV_VALUE_MASK)
 
#define TSW_TSNPORT_TXOV_VALUE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TXOV_VALUE_MASK) >> TSW_TSNPORT_TXOV_VALUE_SHIFT)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK   (0x3FC00UL)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT   (10U)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK   (0x300U)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT   (8U)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK   (0xFFU)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT   (0U)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT   (0U)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK)
 
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT   (24U)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_HI_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK   (0xFF0000UL)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT   (16U)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_LO_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_VER_VER_REV_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK   (0x80000000UL)
 
#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT   (31U)
 
#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK)
 
#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK   (0x40000000UL)
 
#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT   (30U)
 
#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK)
 
#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK   (0x1U)
 
#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK)
 
#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK)
 
#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK   (0x80000000UL)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT   (31U)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK   (0x40000000UL)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT   (30U)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK   (0x20000000UL)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT   (29U)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK   (0x10000000UL)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT   (28U)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK   (0x8000000UL)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT   (27U)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK   (0x4000000UL)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT   (26U)
 
#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK   (0xE0000000UL)
 
#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT   (29U)
 
#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK   (0x7U)
 
#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK   (0x80000000UL)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT   (31U)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK   (0xFFU)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK   (0xE0U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT   (5U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK   (0x18U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT   (3U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK   (0x4U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT   (2U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK   (0x2U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT   (1U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK   (0x4U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT   (2U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK   (0x2U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT   (1U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK   (0x1U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK) >> TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK)
 
#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK)
 
#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT)
 
#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT   (0U)
 
#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK   (0x20000UL)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT   (17U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK   (0x10000UL)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT   (16U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK   (0xE000U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT   (13U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK   (0x1000U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT   (12U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK   (0xFFFU)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT   (0U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK   (0x2U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT   (1U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK   (0x1U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT   (0U)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK)
 
#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT   (24U)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK   (0xFFFFFFUL)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT   (0U)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK)
 
#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK   (0x800U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT   (11U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK   (0x400U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT   (10U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK   (0x200U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT   (9U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK   (0x100U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT   (8U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK   (0x8U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT   (3U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK   (0x4U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT   (2U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK   (0x2U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT   (1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK   (0x1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK   (0x40U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT   (6U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK   (0x20U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT   (5U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK   (0x10U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT   (4U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK   (0x8U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT   (3U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK   (0x4U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT   (2U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK   (0x2U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT   (1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK   (0x1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK   (0x7FU)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK   (0x1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK   (0xFFFF0000UL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT   (16U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK   (0x200U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT   (9U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK   (0x100U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT   (8U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK   (0x40U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT   (6U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK   (0x20U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT   (5U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK   (0x10U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT   (4U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK   (0x8U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT   (3U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK   (0x4U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT   (2U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK   (0x2U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT   (1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK   (0x1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK   (0x1U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK   (0xFF000000UL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT   (24U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK   (0xFF0000UL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT   (16U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK   (0xFFFFU)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK   (0x1FFFFFFUL)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT   (0U)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK)
 
#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK   (0x1U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT   (0U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK   (0x4U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT   (2U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK   (0x2U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT   (1U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK   (0x1U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT   (0U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK   (0xFFFF0000UL)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT   (16U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK   (0xFF00U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT   (8U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK   (0x7FU)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT   (0U)
 
#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK   (0xFFFFFFFFUL)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT   (0U)
 
#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)
 
#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK   (0x3F00U)
 
#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT   (8U)
 
#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK)
 
#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT)
 
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK   (0x3FU)
 
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT   (0U)
 
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK)
 
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT)
 
#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK   (0x300000UL)
 
#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT   (20U)
 
#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK)
 
#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) >> TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT)
 
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK   (0x80000UL)
 
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT   (19U)
 
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK)
 
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) >> TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT)
 
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK   (0xE000U)
 
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT   (13U)
 
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK)
 
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT)
 
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK   (0x400U)
 
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT   (10U)
 
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET(x)   (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK)
 
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET(x)   (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT)
 
#define TSW_HITMEM_HITMEM_REG_1   (0UL)
 
#define TSW_HITMEM_HITMEM_REG_2   (1UL)
 
#define TSW_HITMEM_HITMEM_REG_3   (2UL)
 
#define TSW_HITMEM_HITMEM_REG_4   (3UL)
 
#define TSW_QCI_CNT_CENTRAL_QCI_CNT0   (0UL)
 
#define TSW_QCI_CNT_CENTRAL_QCI_CNT1   (1UL)
 
#define TSW_QCI_CNT_CENTRAL_QCI_CNT2   (2UL)
 
#define TSW_QCI_CNT_CENTRAL_QCI_CNT3   (3UL)
 
#define TSW_QCI_CNT_CENTRAL_QCI_CNT4   (4UL)
 
#define TSW_QCI_CNT_CENTRAL_QCI_CNT5   (5UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT0   (0UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT1   (1UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT2   (2UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT3   (3UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT4   (4UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT5   (5UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT6   (6UL)
 
#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT7   (7UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT0   (0UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT1   (1UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT2   (2UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT3   (3UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT4   (4UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT5   (5UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT6   (6UL)
 
#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT7   (7UL)
 
#define TSW_MAC_EM1   (0UL)
 
#define TSW_MAC_PM1   (1UL)
 
#define TSW_TSNPORT_TSYNTMR_TSYN_TMR0   (0UL)
 
#define TSW_TSNPORT_TSYNTMR_TSYN_TMR1   (1UL)
 
#define TSW_TSNPORT_TSYNTMR_TSYN_TMR2   (2UL)
 
#define TSW_TSNPORT_TSYNTMR_TSYN_TMR3   (3UL)
 
#define TSW_TSNPORT_TSYNTMR_TSYN_TMR4   (4UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD0   (0UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD1   (1UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD2   (2UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD3   (3UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD4   (4UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD5   (5UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD6   (6UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD7   (7UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD8   (8UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD9   (9UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD10   (10UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD11   (11UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD12   (12UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD13   (13UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD14   (14UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD15   (15UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD16   (16UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD17   (17UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD18   (18UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD19   (19UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD20   (20UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD21   (21UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD22   (22UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD23   (23UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD24   (24UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD25   (25UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD26   (26UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD27   (27UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD28   (28UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD29   (29UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD30   (30UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD31   (31UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD32   (32UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD33   (33UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD34   (34UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD35   (35UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD36   (36UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD37   (37UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD38   (38UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD39   (39UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD40   (40UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD41   (41UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD42   (42UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD43   (43UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD44   (44UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD45   (45UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD46   (46UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD47   (47UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD48   (48UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD49   (49UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD50   (50UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD51   (51UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD52   (52UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD53   (53UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD54   (54UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD55   (55UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD56   (56UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD57   (57UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD58   (58UL)
 
#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD59   (59UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD0   (0UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD1   (1UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD2   (2UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD3   (3UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD4   (4UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD5   (5UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD6   (6UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD7   (7UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD8   (8UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD9   (9UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD10   (10UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD11   (11UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD12   (12UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD13   (13UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD14   (14UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD15   (15UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD16   (16UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD17   (17UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD18   (18UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD19   (19UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD20   (20UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD21   (21UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD22   (22UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD23   (23UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD24   (24UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD25   (25UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD26   (26UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD27   (27UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD28   (28UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD29   (29UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD30   (30UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD31   (31UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD32   (32UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD33   (33UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD34   (34UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD35   (35UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD36   (36UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD37   (37UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD38   (38UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD39   (39UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD40   (40UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD41   (41UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD42   (42UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD43   (43UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD44   (44UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD45   (45UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD46   (46UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD47   (47UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD48   (48UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD49   (49UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD50   (50UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD51   (51UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD52   (52UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD53   (53UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD54   (54UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD55   (55UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD56   (56UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD57   (57UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD58   (58UL)
 
#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD59   (59UL)
 
#define TSW_BIN_TX0   (0UL)
 
#define TSW_BIN_TX1   (1UL)
 
#define TSW_BIN_TX2   (2UL)
 
#define TSW_BIN_TX3   (3UL)
 
#define TSW_BIN_TX4   (4UL)
 
#define TSW_BIN_TX5   (5UL)
 
#define TSW_BIN_TX6   (6UL)
 
#define TSW_BIN_TX7   (7UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU0   (0UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU1   (1UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU2   (2UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU3   (3UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU4   (4UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU5   (5UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU6   (6UL)
 
#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU7   (7UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL0   (0UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL1   (1UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL2   (2UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL3   (3UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL4   (4UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL5   (5UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL6   (6UL)
 
#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL7   (7UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL0   (0UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL1   (1UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL2   (2UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL3   (3UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL04   (4UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL5   (5UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL6   (6UL)
 
#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL7   (7UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK0   (0UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK1   (1UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK2   (2UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK3   (3UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK4   (4UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK5   (5UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK6   (6UL)
 
#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK7   (7UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV0   (0UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV1   (1UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV2   (2UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV3   (3UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV4   (4UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV5   (5UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV6   (6UL)
 
#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV7   (7UL)
 
#define TSW_SHACL_ENT0   (0UL)
 
#define TSW_SHACL_ENT1   (1UL)
 
#define TSW_SHACL_ENT2   (2UL)
 
#define TSW_SHACL_ENT3   (3UL)
 
#define TSW_SHACL_ENT4   (4UL)
 
#define TSW_SHACL_ENT5   (5UL)
 
#define TSW_SHACL_ENT6   (6UL)
 
#define TSW_SHACL_ENT7   (7UL)
 
#define TSW_SHACL_ENT8   (8UL)
 
#define TSW_SHACL_ENT9   (9UL)
 
#define TSW_SHACL_ENT10   (10UL)
 
#define TSW_SHACL_ENT11   (11UL)
 
#define TSW_SHACL_ENT12   (12UL)
 
#define TSW_SHACL_ENT13   (13UL)
 
#define TSW_SHACL_ENT14   (14UL)
 
#define TSW_SHACL_ENT15   (15UL)
 
#define TSW_SHACL_ENT16   (16UL)
 
#define TSW_SHACL_ENT17   (17UL)
 
#define TSW_SHACL_ENT18   (18UL)
 
#define TSW_SHACL_ENT19   (19UL)
 
#define TSW_SHACL_ENT20   (20UL)
 
#define TSW_SHACL_ENT21   (21UL)
 
#define TSW_SHACL_ENT22   (22UL)
 
#define TSW_SHACL_ENT23   (23UL)
 
#define TSW_SHACL_ENT24   (24UL)
 
#define TSW_SHACL_ENT25   (25UL)
 
#define TSW_SHACL_ENT26   (26UL)
 
#define TSW_SHACL_ENT27   (27UL)
 
#define TSW_SHACL_ENT28   (28UL)
 
#define TSW_SHACL_ENT29   (29UL)
 
#define TSW_SHACL_ENT30   (30UL)
 
#define TSW_SHACL_ENT31   (31UL)
 
#define TSW_SHACL_ENT32   (32UL)
 
#define TSW_SHACL_ENT33   (33UL)
 
#define TSW_SHACL_ENT34   (34UL)
 
#define TSW_SHACL_ENT35   (35UL)
 
#define TSW_SHACL_ENT36   (36UL)
 
#define TSW_SHACL_ENT37   (37UL)
 
#define TSW_SHACL_ENT38   (38UL)
 
#define TSW_SHACL_ENT39   (39UL)
 
#define TSW_SHACL_ENT40   (40UL)
 
#define TSW_SHACL_ENT41   (41UL)
 
#define TSW_SHACL_ENT42   (42UL)
 
#define TSW_SHACL_ENT43   (43UL)
 
#define TSW_SHACL_ENT44   (44UL)
 
#define TSW_SHACL_ENT45   (45UL)
 
#define TSW_SHACL_ENT46   (46UL)
 
#define TSW_SHACL_ENT47   (47UL)
 
#define TSW_SHACL_ENT48   (48UL)
 
#define TSW_SHACL_ENT49   (49UL)
 
#define TSW_SHACL_ENT50   (50UL)
 
#define TSW_SHACL_ENT51   (51UL)
 
#define TSW_SHACL_ENT52   (52UL)
 
#define TSW_SHACL_ENT53   (53UL)
 
#define TSW_SHACL_ENT54   (54UL)
 
#define TSW_SHACL_ENT55   (55UL)
 
#define TSW_SHACL_ENT56   (56UL)
 
#define TSW_SHACL_ENT57   (57UL)
 
#define TSW_SHACL_ENT58   (58UL)
 
#define TSW_SHACL_ENT59   (59UL)
 
#define TSW_SHACL_ENT60   (60UL)
 
#define TSW_SHACL_ENT61   (61UL)
 
#define TSW_SHACL_ENT62   (62UL)
 
#define TSW_SHACL_ENT63   (63UL)
 
#define TSW_SHACL_ENT64   (64UL)
 
#define TSW_SHACL_ENT65   (65UL)
 
#define TSW_SHACL_ENT66   (66UL)
 
#define TSW_SHACL_ENT67   (67UL)
 
#define TSW_SHACL_ENT68   (68UL)
 
#define TSW_SHACL_ENT69   (69UL)
 
#define TSW_SHACL_ENT70   (70UL)
 
#define TSW_SHACL_ENT71   (71UL)
 
#define TSW_SHACL_ENT72   (72UL)
 
#define TSW_SHACL_ENT73   (73UL)
 
#define TSW_SHACL_ENT74   (74UL)
 
#define TSW_SHACL_ENT75   (75UL)
 
#define TSW_SHACL_ENT76   (76UL)
 
#define TSW_SHACL_ENT77   (77UL)
 
#define TSW_SHACL_ENT78   (78UL)
 
#define TSW_SHACL_ENT79   (79UL)
 
#define TSW_SHACL_ENT80   (80UL)
 
#define TSW_SHACL_ENT81   (81UL)
 
#define TSW_SHACL_ENT82   (82UL)
 
#define TSW_SHACL_ENT83   (83UL)
 
#define TSW_SHACL_ENT84   (84UL)
 
#define TSW_SHACL_ENT85   (85UL)
 
#define TSW_SHACL_ENT86   (86UL)
 
#define TSW_SHACL_ENT87   (87UL)
 
#define TSW_SHACL_ENT88   (88UL)
 
#define TSW_SHACL_ENT89   (89UL)
 
#define TSW_SHACL_ENT90   (90UL)
 
#define TSW_SHACL_ENT91   (91UL)
 
#define TSW_SHACL_ENT92   (92UL)
 
#define TSW_SHACL_ENT93   (93UL)
 
#define TSW_SHACL_ENT94   (94UL)
 
#define TSW_SHACL_ENT95   (95UL)
 
#define TSW_SHACL_ENT96   (96UL)
 
#define TSW_SHACL_ENT97   (97UL)
 
#define TSW_SHACL_ENT98   (98UL)
 
#define TSW_SHACL_ENT99   (99UL)
 
#define TSW_SHACL_ENT100   (100UL)
 
#define TSW_SHACL_ENT101   (101UL)
 
#define TSW_SHACL_ENT102   (102UL)
 
#define TSW_SHACL_ENT103   (103UL)
 
#define TSW_SHACL_ENT104   (104UL)
 
#define TSW_SHACL_ENT105   (105UL)
 
#define TSW_SHACL_ENT106   (106UL)
 
#define TSW_SHACL_ENT107   (107UL)
 
#define TSW_SHACL_ENT108   (108UL)
 
#define TSW_SHACL_ENT109   (109UL)
 
#define TSW_SHACL_ENT110   (110UL)
 
#define TSW_SHACL_ENT111   (111UL)
 
#define TSW_SHACL_ENT112   (112UL)
 
#define TSW_SHACL_ENT113   (113UL)
 
#define TSW_SHACL_ENT114   (114UL)
 
#define TSW_SHACL_ENT115   (115UL)
 
#define TSW_SHACL_ENT116   (116UL)
 
#define TSW_SHACL_ENT117   (117UL)
 
#define TSW_SHACL_ENT118   (118UL)
 
#define TSW_SHACL_ENT119   (119UL)
 
#define TSW_SHACL_ENT120   (120UL)
 
#define TSW_SHACL_ENT121   (121UL)
 
#define TSW_SHACL_ENT122   (122UL)
 
#define TSW_SHACL_ENT123   (123UL)
 
#define TSW_SHACL_ENT124   (124UL)
 
#define TSW_SHACL_ENT125   (125UL)
 
#define TSW_SHACL_ENT126   (126UL)
 
#define TSW_SHACL_ENT127   (127UL)
 
#define TSW_SHACL_ENT128   (128UL)
 
#define TSW_SHACL_ENT129   (129UL)
 
#define TSW_SHACL_ENT130   (130UL)
 
#define TSW_SHACL_ENT131   (131UL)
 
#define TSW_SHACL_ENT132   (132UL)
 
#define TSW_SHACL_ENT133   (133UL)
 
#define TSW_SHACL_ENT134   (134UL)
 
#define TSW_SHACL_ENT135   (135UL)
 
#define TSW_SHACL_ENT136   (136UL)
 
#define TSW_SHACL_ENT137   (137UL)
 
#define TSW_SHACL_ENT138   (138UL)
 
#define TSW_SHACL_ENT139   (139UL)
 
#define TSW_SHACL_ENT140   (140UL)
 
#define TSW_SHACL_ENT141   (141UL)
 
#define TSW_SHACL_ENT142   (142UL)
 
#define TSW_SHACL_ENT143   (143UL)
 
#define TSW_SHACL_ENT144   (144UL)
 
#define TSW_SHACL_ENT145   (145UL)
 
#define TSW_SHACL_ENT146   (146UL)
 
#define TSW_SHACL_ENT147   (147UL)
 
#define TSW_SHACL_ENT148   (148UL)
 
#define TSW_SHACL_ENT149   (149UL)
 
#define TSW_SHACL_ENT150   (150UL)
 
#define TSW_SHACL_ENT151   (151UL)
 
#define TSW_SHACL_ENT152   (152UL)
 
#define TSW_SHACL_ENT153   (153UL)
 
#define TSW_SHACL_ENT154   (154UL)
 
#define TSW_SHACL_ENT155   (155UL)
 
#define TSW_SHACL_ENT156   (156UL)
 
#define TSW_SHACL_ENT157   (157UL)
 
#define TSW_SHACL_ENT158   (158UL)
 
#define TSW_SHACL_ENT159   (159UL)
 
#define TSW_SHACL_ENT160   (160UL)
 
#define TSW_SHACL_ENT161   (161UL)
 
#define TSW_SHACL_ENT162   (162UL)
 
#define TSW_SHACL_ENT163   (163UL)
 
#define TSW_SHACL_ENT164   (164UL)
 
#define TSW_SHACL_ENT165   (165UL)
 
#define TSW_SHACL_ENT166   (166UL)
 
#define TSW_SHACL_ENT167   (167UL)
 
#define TSW_SHACL_ENT168   (168UL)
 
#define TSW_SHACL_ENT169   (169UL)
 
#define TSW_SHACL_ENT170   (170UL)
 
#define TSW_SHACL_ENT171   (171UL)
 
#define TSW_SHACL_ENT172   (172UL)
 
#define TSW_SHACL_ENT173   (173UL)
 
#define TSW_SHACL_ENT174   (174UL)
 
#define TSW_SHACL_ENT175   (175UL)
 
#define TSW_SHACL_ENT176   (176UL)
 
#define TSW_SHACL_ENT177   (177UL)
 
#define TSW_SHACL_ENT178   (178UL)
 
#define TSW_SHACL_ENT179   (179UL)
 
#define TSW_SHACL_ENT180   (180UL)
 
#define TSW_SHACL_ENT181   (181UL)
 
#define TSW_SHACL_ENT182   (182UL)
 
#define TSW_SHACL_ENT183   (183UL)
 
#define TSW_SHACL_ENT184   (184UL)
 
#define TSW_SHACL_ENT185   (185UL)
 
#define TSW_SHACL_ENT186   (186UL)
 
#define TSW_SHACL_ENT187   (187UL)
 
#define TSW_SHACL_ENT188   (188UL)
 
#define TSW_SHACL_ENT189   (189UL)
 
#define TSW_SHACL_ENT190   (190UL)
 
#define TSW_SHACL_ENT191   (191UL)
 
#define TSW_SHACL_ENT192   (192UL)
 
#define TSW_SHACL_ENT193   (193UL)
 
#define TSW_SHACL_ENT194   (194UL)
 
#define TSW_SHACL_ENT195   (195UL)
 
#define TSW_SHACL_ENT196   (196UL)
 
#define TSW_SHACL_ENT197   (197UL)
 
#define TSW_SHACL_ENT198   (198UL)
 
#define TSW_SHACL_ENT199   (199UL)
 
#define TSW_SHACL_ENT200   (200UL)
 
#define TSW_SHACL_ENT201   (201UL)
 
#define TSW_SHACL_ENT202   (202UL)
 
#define TSW_SHACL_ENT203   (203UL)
 
#define TSW_SHACL_ENT204   (204UL)
 
#define TSW_SHACL_ENT205   (205UL)
 
#define TSW_SHACL_ENT206   (206UL)
 
#define TSW_SHACL_ENT207   (207UL)
 
#define TSW_SHACL_ENT208   (208UL)
 
#define TSW_SHACL_ENT209   (209UL)
 
#define TSW_SHACL_ENT210   (210UL)
 
#define TSW_SHACL_ENT211   (211UL)
 
#define TSW_SHACL_ENT212   (212UL)
 
#define TSW_SHACL_ENT213   (213UL)
 
#define TSW_SHACL_ENT214   (214UL)
 
#define TSW_SHACL_ENT215   (215UL)
 
#define TSW_SHACL_ENT216   (216UL)
 
#define TSW_SHACL_ENT217   (217UL)
 
#define TSW_SHACL_ENT218   (218UL)
 
#define TSW_SHACL_ENT219   (219UL)
 
#define TSW_SHACL_ENT220   (220UL)
 
#define TSW_SHACL_ENT221   (221UL)
 
#define TSW_SHACL_ENT222   (222UL)
 
#define TSW_SHACL_ENT223   (223UL)
 
#define TSW_SHACL_ENT224   (224UL)
 
#define TSW_SHACL_ENT225   (225UL)
 
#define TSW_SHACL_ENT226   (226UL)
 
#define TSW_SHACL_ENT227   (227UL)
 
#define TSW_SHACL_ENT228   (228UL)
 
#define TSW_SHACL_ENT229   (229UL)
 
#define TSW_SHACL_ENT230   (230UL)
 
#define TSW_SHACL_ENT231   (231UL)
 
#define TSW_SHACL_ENT232   (232UL)
 
#define TSW_SHACL_ENT233   (233UL)
 
#define TSW_SHACL_ENT234   (234UL)
 
#define TSW_SHACL_ENT235   (235UL)
 
#define TSW_SHACL_ENT236   (236UL)
 
#define TSW_SHACL_ENT237   (237UL)
 
#define TSW_SHACL_ENT238   (238UL)
 
#define TSW_SHACL_ENT239   (239UL)
 
#define TSW_SHACL_ENT240   (240UL)
 
#define TSW_SHACL_ENT241   (241UL)
 
#define TSW_SHACL_ENT242   (242UL)
 
#define TSW_SHACL_ENT243   (243UL)
 
#define TSW_SHACL_ENT244   (244UL)
 
#define TSW_SHACL_ENT245   (245UL)
 
#define TSW_SHACL_ENT246   (246UL)
 
#define TSW_SHACL_ENT247   (247UL)
 
#define TSW_SHACL_ENT248   (248UL)
 
#define TSW_SHACL_ENT249   (249UL)
 
#define TSW_SHACL_ENT250   (250UL)
 
#define TSW_SHACL_ENT251   (251UL)
 
#define TSW_SHACL_ENT252   (252UL)
 
#define TSW_SHACL_ENT253   (253UL)
 
#define TSW_SHACL_ENT254   (254UL)
 
#define TSW_SHACL_ENT255   (255UL)
 
#define TSW_RXFIFO_E1   (0UL)
 
#define TSW_RXFIFO_P1   (1UL)
 
#define TSW_TSNPORT_PORT1   (0UL)
 
#define TSW_TSNPORT_PORT2   (1UL)
 
#define TSW_TSNPORT_PORT3   (2UL)
 

Macro Definition Documentation

◆ TSW_APB2AXI_CAM_REQDATA_0_CH_GET

#define TSW_APB2AXI_CAM_REQDATA_0_CH_GET (   x)    (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT)

◆ TSW_APB2AXI_CAM_REQDATA_0_CH_MASK

#define TSW_APB2AXI_CAM_REQDATA_0_CH_MASK   (0x1U)

◆ TSW_APB2AXI_CAM_REQDATA_0_CH_SET

#define TSW_APB2AXI_CAM_REQDATA_0_CH_SET (   x)    (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK)

◆ TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT

#define TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT   (0U)

◆ TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_GET

#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_GET (   x)    (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT)

◆ TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK

#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK   (0xFFFF0000UL)

◆ TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET

#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET (   x)    (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK)

◆ TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT

#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT   (16U)

◆ TSW_APB2AXI_CAM_REQDATA_0_TYPE_GET

#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_GET (   x)    (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT)

◆ TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK

#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK   (0x300U)

◆ TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET

#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET (   x)    (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK)

◆ TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT

#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT   (8U)

◆ TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET

#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET (   x)    (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) >> TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT)

◆ TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK

#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK   (0xFFFFFFFFUL)

◆ TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET

#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET (   x)    (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK)

◆ TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT

#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT   (0U)

◆ TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_GET

#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_GET (   x)    (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT)

◆ TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK

#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK   (0xFFFFU)

◆ TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET

#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET (   x)    (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK)

◆ TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT

#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT   (0U)

◆ TSW_APB2AXI_CAM_REQDATA_2_VID_GET

#define TSW_APB2AXI_CAM_REQDATA_2_VID_GET (   x)    (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT)

◆ TSW_APB2AXI_CAM_REQDATA_2_VID_MASK

#define TSW_APB2AXI_CAM_REQDATA_2_VID_MASK   (0xFFF0000UL)

◆ TSW_APB2AXI_CAM_REQDATA_2_VID_SET

#define TSW_APB2AXI_CAM_REQDATA_2_VID_SET (   x)    (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK)

◆ TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT

#define TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT   (16U)

◆ TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_GET

#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT)

◆ TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK

#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK   (0x1U)

◆ TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT

#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT   (0U)

◆ TSW_APB2AXIS_ALMEM_FILLSTS_FULL_GET

#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT)

◆ TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK

#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK   (0x10U)

◆ TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT

#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT   (4U)

◆ TSW_APB2AXIS_ALMEM_PARAM_DEPTH_GET

#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT)

◆ TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK

#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK   (0xFF00U)

◆ TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT

#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT   (8U)

◆ TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_GET

#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)

◆ TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK

#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK   (0xFFU)

◆ TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT

#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT   (0U)

◆ TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_GET

#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK

#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK   (0xFFU)

◆ TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT

#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT   (0U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK   (0xFFFFU)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT   (0U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK   (0x80000UL)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT   (19U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK   (0x300000UL)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT   (20U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK   (0x70000UL)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT   (16U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK   (0x1C00000UL)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT   (22U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK   (0xFFFFU)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT   (0U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK   (0x40000000UL)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT   (30U)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET

#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK

#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK   (0x80000000UL)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET

#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK)

◆ TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT

#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT   (31U)

◆ TSW_APB2AXIS_ALMEM_RESET_RESET_GET

#define TSW_APB2AXIS_ALMEM_RESET_RESET_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK) >> TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT)

◆ TSW_APB2AXIS_ALMEM_RESET_RESET_MASK

#define TSW_APB2AXIS_ALMEM_RESET_RESET_MASK   (0x1U)

◆ TSW_APB2AXIS_ALMEM_RESET_RESET_SET

#define TSW_APB2AXIS_ALMEM_RESET_RESET_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK)

◆ TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT

#define TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT   (0U)

◆ TSW_APB2AXIS_ALMEM_STS_BUSY_GET

#define TSW_APB2AXIS_ALMEM_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_BUSY_MASK) >> TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT)

◆ TSW_APB2AXIS_ALMEM_STS_BUSY_MASK

#define TSW_APB2AXIS_ALMEM_STS_BUSY_MASK   (0x2U)

◆ TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT

#define TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT   (1U)

◆ TSW_APB2AXIS_ALMEM_STS_RDY_GET

#define TSW_APB2AXIS_ALMEM_STS_RDY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_RDY_MASK) >> TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT)

◆ TSW_APB2AXIS_ALMEM_STS_RDY_MASK

#define TSW_APB2AXIS_ALMEM_STS_RDY_MASK   (0x1U)

◆ TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT

#define TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT   (0U)

◆ TSW_APB2AXIS_CAM_FILLSTS_EMPTY_GET

#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT)

◆ TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK

#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK   (0x1U)

◆ TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT

#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT   (0U)

◆ TSW_APB2AXIS_CAM_FILLSTS_FULL_GET

#define TSW_APB2AXIS_CAM_FILLSTS_FULL_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT)

◆ TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK

#define TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK   (0x10U)

◆ TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT

#define TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT   (4U)

◆ TSW_APB2AXIS_CAM_PARAM_DEPTH_GET

#define TSW_APB2AXIS_CAM_PARAM_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT)

◆ TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK

#define TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK   (0xFF00U)

◆ TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT

#define TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT   (8U)

◆ TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_GET

#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT)

◆ TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK

#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK   (0xFFU)

◆ TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT

#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT   (0U)

◆ TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_GET

#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT)

◆ TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK

#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK   (0xFFU)

◆ TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT

#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT   (0U)

◆ TSW_APB2AXIS_CAM_RESET_RESET_GET

#define TSW_APB2AXIS_CAM_RESET_RESET_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_RESET_RESET_MASK) >> TSW_APB2AXIS_CAM_RESET_RESET_SHIFT)

◆ TSW_APB2AXIS_CAM_RESET_RESET_MASK

#define TSW_APB2AXIS_CAM_RESET_RESET_MASK   (0x1U)

◆ TSW_APB2AXIS_CAM_RESET_RESET_SET

#define TSW_APB2AXIS_CAM_RESET_RESET_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_CAM_RESET_RESET_SHIFT) & TSW_APB2AXIS_CAM_RESET_RESET_MASK)

◆ TSW_APB2AXIS_CAM_RESET_RESET_SHIFT

#define TSW_APB2AXIS_CAM_RESET_RESET_SHIFT   (0U)

◆ TSW_APB2AXIS_CAM_STS_BUSY_GET

#define TSW_APB2AXIS_CAM_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_BUSY_MASK) >> TSW_APB2AXIS_CAM_STS_BUSY_SHIFT)

◆ TSW_APB2AXIS_CAM_STS_BUSY_MASK

#define TSW_APB2AXIS_CAM_STS_BUSY_MASK   (0x2U)

◆ TSW_APB2AXIS_CAM_STS_BUSY_SHIFT

#define TSW_APB2AXIS_CAM_STS_BUSY_SHIFT   (1U)

◆ TSW_APB2AXIS_CAM_STS_RDY_GET

#define TSW_APB2AXIS_CAM_STS_RDY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_RDY_MASK) >> TSW_APB2AXIS_CAM_STS_RDY_SHIFT)

◆ TSW_APB2AXIS_CAM_STS_RDY_MASK

#define TSW_APB2AXIS_CAM_STS_RDY_MASK   (0x1U)

◆ TSW_APB2AXIS_CAM_STS_RDY_SHIFT

#define TSW_APB2AXIS_CAM_STS_RDY_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_GET

#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK

#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK   (0x1U)

◆ TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT

#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_GET

#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK

#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK   (0x10U)

◆ TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT

#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT   (4U)

◆ TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_GET

#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK

#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK   (0xFF00U)

◆ TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT

#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT   (8U)

◆ TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_GET

#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK

#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK   (0xFFU)

◆ TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT

#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_GET

#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK

#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK   (0xFFU)

◆ TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT

#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_GET

#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK

#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK   (0xFFFFFFFFUL)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SET

#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT

#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_GET

#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK

#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK   (0xFFFFU)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SET

#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT

#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_GET

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK   (0x10000UL)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SET

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT   (16U)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_GET

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK   (0xFFFFU)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SET

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK)

◆ TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT

#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_RESET_RESET_GET

#define TSW_APB2AXIS_LOOKUP_RESET_RESET_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK) >> TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK

#define TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK   (0x1U)

◆ TSW_APB2AXIS_LOOKUP_RESET_RESET_SET

#define TSW_APB2AXIS_LOOKUP_RESET_RESET_SET (   x)    (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK)

◆ TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT

#define TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT   (0U)

◆ TSW_APB2AXIS_LOOKUP_STS_BUSY_GET

#define TSW_APB2AXIS_LOOKUP_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK

#define TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK   (0x2U)

◆ TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT

#define TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT   (1U)

◆ TSW_APB2AXIS_LOOKUP_STS_RDY_GET

#define TSW_APB2AXIS_LOOKUP_STS_RDY_GET (   x)    (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_RDY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT)

◆ TSW_APB2AXIS_LOOKUP_STS_RDY_MASK

#define TSW_APB2AXIS_LOOKUP_STS_RDY_MASK   (0x1U)

◆ TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT

#define TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_GET

#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT)

◆ TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK

#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK   (0x1U)

◆ TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT

#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_FILLSTS_FULL_GET

#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT)

◆ TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK

#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK   (0x10U)

◆ TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT

#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT   (4U)

◆ TSW_AXIS2APB_ALMEM_PARAM_DEPTH_GET

#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT)

◆ TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK

#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK   (0xFF00U)

◆ TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT

#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT   (8U)

◆ TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_GET

#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)

◆ TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK

#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK   (0xFFU)

◆ TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT

#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_RESET_RESET_GET

#define TSW_AXIS2APB_ALMEM_RESET_RESET_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK) >> TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESET_RESET_MASK

#define TSW_AXIS2APB_ALMEM_RESET_RESET_MASK   (0x1U)

◆ TSW_AXIS2APB_ALMEM_RESET_RESET_SET

#define TSW_AXIS2APB_ALMEM_RESET_RESET_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK)

◆ TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT

#define TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_GET

#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK

#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK   (0xFFU)

◆ TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT

#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK   (0xFFFFU)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK   (0x80000UL)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT   (19U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK   (0x300000UL)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT   (20U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK   (0x70000UL)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT   (16U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK   (0x1C00000UL)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT   (22U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK   (0xFFFFU)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT   (0U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK   (0x40000000UL)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT   (30U)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_GET

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK   (0x80000000UL)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SET

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK)

◆ TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT

#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT   (31U)

◆ TSW_AXIS2APB_ALMEM_STS_BUSY_GET

#define TSW_AXIS2APB_ALMEM_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_BUSY_MASK) >> TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT)

◆ TSW_AXIS2APB_ALMEM_STS_BUSY_MASK

#define TSW_AXIS2APB_ALMEM_STS_BUSY_MASK   (0x2U)

◆ TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT

#define TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT   (1U)

◆ TSW_AXIS2APB_ALMEM_STS_RDY_GET

#define TSW_AXIS2APB_ALMEM_STS_RDY_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_RDY_MASK) >> TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT)

◆ TSW_AXIS2APB_ALMEM_STS_RDY_MASK

#define TSW_AXIS2APB_ALMEM_STS_RDY_MASK   (0x1U)

◆ TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT

#define TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_GET

#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK

#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK   (0x1U)

◆ TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT

#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_GET

#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK

#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK   (0x10U)

◆ TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT

#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT   (4U)

◆ TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_GET

#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK

#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK   (0xFF00U)

◆ TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT

#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT   (8U)

◆ TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_GET

#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK

#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK   (0xFFU)

◆ TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT

#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_RESET_RESET_GET

#define TSW_AXIS2APB_LOOKUP_RESET_RESET_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK) >> TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK

#define TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK   (0x1U)

◆ TSW_AXIS2APB_LOOKUP_RESET_RESET_SET

#define TSW_AXIS2APB_LOOKUP_RESET_RESET_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_GET

#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK

#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK   (0xFFU)

◆ TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK   (0xFFFFU)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK   (0x80000UL)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT   (19U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK   (0x2000000UL)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT   (25U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK   (0x1000000UL)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT   (24U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK   (0x100000UL)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT   (20U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK   (0x70000UL)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT   (16U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK   (0xE00000UL)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT   (21U)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_GET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK

#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK   (0xFFFFU)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SET

#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SET (   x)    (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK)

◆ TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT

#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT   (0U)

◆ TSW_AXIS2APB_LOOKUP_STS_BUSY_GET

#define TSW_AXIS2APB_LOOKUP_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK

#define TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK   (0x2U)

◆ TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT

#define TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT   (1U)

◆ TSW_AXIS2APB_LOOKUP_STS_RDY_GET

#define TSW_AXIS2APB_LOOKUP_STS_RDY_GET (   x)    (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_RDY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT)

◆ TSW_AXIS2APB_LOOKUP_STS_RDY_MASK

#define TSW_AXIS2APB_LOOKUP_STS_RDY_MASK   (0x1U)

◆ TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT

#define TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT   (0U)

◆ TSW_BIN_TX0

#define TSW_BIN_TX0   (0UL)

◆ TSW_BIN_TX1

#define TSW_BIN_TX1   (1UL)

◆ TSW_BIN_TX2

#define TSW_BIN_TX2   (2UL)

◆ TSW_BIN_TX3

#define TSW_BIN_TX3   (3UL)

◆ TSW_BIN_TX4

#define TSW_BIN_TX4   (4UL)

◆ TSW_BIN_TX5

#define TSW_BIN_TX5   (5UL)

◆ TSW_BIN_TX6

#define TSW_BIN_TX6   (6UL)

◆ TSW_BIN_TX7

#define TSW_BIN_TX7   (7UL)

◆ TSW_CENTRAL_CSR_CB_PARAM_FRER_D_GET

#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT)

◆ TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK

#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK   (0xFFU)

◆ TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT

#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT   (0U)

◆ TSW_CENTRAL_CSR_CB_PARAM_SID_D_GET

#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT)

◆ TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK

#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK   (0xFF00U)

◆ TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT

#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT   (8U)

◆ TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_GET

#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK) >> TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT)

◆ TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK

#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK   (0xFFFFFFUL)

◆ TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SET

#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK)

◆ TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT

#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT   (0U)

◆ TSW_CENTRAL_CSR_PARAM_INCL_CB0_GET

#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT)

◆ TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK

#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK   (0x20000UL)

◆ TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT

#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT   (17U)

◆ TSW_CENTRAL_CSR_PARAM_INCL_QCI_GET

#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT)

◆ TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK

#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK   (0x40000UL)

◆ TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT

#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT   (18U)

◆ TSW_CENTRAL_CSR_PARAM_NPORTS_GET

#define TSW_CENTRAL_CSR_PARAM_NPORTS_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_NPORTS_MASK) >> TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT)

◆ TSW_CENTRAL_CSR_PARAM_NPORTS_MASK

#define TSW_CENTRAL_CSR_PARAM_NPORTS_MASK   (0xFFU)

◆ TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT

#define TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT   (0U)

◆ TSW_CENTRAL_CSR_PARAM_TESTMODE_GET

#define TSW_CENTRAL_CSR_PARAM_TESTMODE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK) >> TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT)

◆ TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK

#define TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK   (0x10000UL)

◆ TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT

#define TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT   (16U)

◆ TSW_CENTRAL_CSR_PARAM_TYPE_GET

#define TSW_CENTRAL_CSR_PARAM_TYPE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TYPE_MASK) >> TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT)

◆ TSW_CENTRAL_CSR_PARAM_TYPE_MASK

#define TSW_CENTRAL_CSR_PARAM_TYPE_MASK   (0xFF00U)

◆ TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT

#define TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT   (8U)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_GET

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK   (0xFF00U)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT   (8U)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_GET

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK   (0xFFU)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT   (0U)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_GET

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK   (0xFF0000UL)

◆ TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT

#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT   (16U)

◆ TSW_CENTRAL_CSR_VERSION_VER_HI_GET

#define TSW_CENTRAL_CSR_VERSION_VER_HI_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_HI_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT)

◆ TSW_CENTRAL_CSR_VERSION_VER_HI_MASK

#define TSW_CENTRAL_CSR_VERSION_VER_HI_MASK   (0xFF000000UL)

◆ TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT

#define TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT   (24U)

◆ TSW_CENTRAL_CSR_VERSION_VER_LO_GET

#define TSW_CENTRAL_CSR_VERSION_VER_LO_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_LO_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT)

◆ TSW_CENTRAL_CSR_VERSION_VER_LO_MASK

#define TSW_CENTRAL_CSR_VERSION_VER_LO_MASK   (0xFF0000UL)

◆ TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT

#define TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT   (16U)

◆ TSW_CENTRAL_CSR_VERSION_VER_REV_GET

#define TSW_CENTRAL_CSR_VERSION_VER_REV_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_REV_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT)

◆ TSW_CENTRAL_CSR_VERSION_VER_REV_MASK

#define TSW_CENTRAL_CSR_VERSION_VER_REV_MASK   (0xFFU)

◆ TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT

#define TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_ABASETM_H_ABTH_GET

#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK) >> TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT)

◆ TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK

#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_ABASETM_H_ABTH_SET

#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK)

◆ TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT

#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_ABASETM_L_ABTL_GET

#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK) >> TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT)

◆ TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK

#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK   (0x3FFFFFFFUL)

◆ TSW_CENTRAL_QCI_ABASETM_L_ABTL_SET

#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK)

◆ TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT

#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_ACYCLETM_ACT_GET

#define TSW_CENTRAL_QCI_ACYCLETM_ACT_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK) >> TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT)

◆ TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK

#define TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK   (0x3FFFFFFFUL)

◆ TSW_CENTRAL_QCI_ACYCLETM_ACT_SET

#define TSW_CENTRAL_QCI_ACYCLETM_ACT_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK)

◆ TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT

#define TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_GET

#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK) >> TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK

#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SET

#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK)

◆ TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_GET

#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK

#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK   (0x70000000UL)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SET

#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT   (28U)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_GET

#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK

#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK   (0xFFFFFFFUL)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SET

#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_GET

#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK

#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK   (0x80000000UL)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SET

#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK)

◆ TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT   (31U)

◆ TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_GET

#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK

#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_GET

#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK

#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_GET

#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT)

◆ TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK

#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT

#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_CBS_CBS_GET

#define TSW_CENTRAL_QCI_CBS_CBS_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_CBS_CBS_MASK) >> TSW_CENTRAL_QCI_CBS_CBS_SHIFT)

◆ TSW_CENTRAL_QCI_CBS_CBS_MASK

#define TSW_CENTRAL_QCI_CBS_CBS_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_CBS_CBS_SET

#define TSW_CENTRAL_QCI_CBS_CBS_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_CBS_CBS_SHIFT) & TSW_CENTRAL_QCI_CBS_CBS_MASK)

◆ TSW_CENTRAL_QCI_CBS_CBS_SHIFT

#define TSW_CENTRAL_QCI_CBS_CBS_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_CIR_CIR_GET

#define TSW_CENTRAL_QCI_CIR_CIR_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_CIR_CIR_MASK) >> TSW_CENTRAL_QCI_CIR_CIR_SHIFT)

◆ TSW_CENTRAL_QCI_CIR_CIR_MASK

#define TSW_CENTRAL_QCI_CIR_CIR_MASK   (0xFFFFFFUL)

◆ TSW_CENTRAL_QCI_CIR_CIR_SET

#define TSW_CENTRAL_QCI_CIR_CIR_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_CIR_CIR_SHIFT) & TSW_CENTRAL_QCI_CIR_CIR_MASK)

◆ TSW_CENTRAL_QCI_CIR_CIR_SHIFT

#define TSW_CENTRAL_QCI_CIR_CIR_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_EBS_EBS_GET

#define TSW_CENTRAL_QCI_EBS_EBS_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_EBS_EBS_MASK) >> TSW_CENTRAL_QCI_EBS_EBS_SHIFT)

◆ TSW_CENTRAL_QCI_EBS_EBS_MASK

#define TSW_CENTRAL_QCI_EBS_EBS_MASK   (0xFFFFFFFFUL)

◆ TSW_CENTRAL_QCI_EBS_EBS_SET

#define TSW_CENTRAL_QCI_EBS_EBS_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_EBS_EBS_SHIFT) & TSW_CENTRAL_QCI_EBS_EBS_MASK)

◆ TSW_CENTRAL_QCI_EBS_EBS_SHIFT

#define TSW_CENTRAL_QCI_EBS_EBS_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_EIR_EIR_GET

#define TSW_CENTRAL_QCI_EIR_EIR_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_EIR_EIR_MASK) >> TSW_CENTRAL_QCI_EIR_EIR_SHIFT)

◆ TSW_CENTRAL_QCI_EIR_EIR_MASK

#define TSW_CENTRAL_QCI_EIR_EIR_MASK   (0xFFFFFFUL)

◆ TSW_CENTRAL_QCI_EIR_EIR_SET

#define TSW_CENTRAL_QCI_EIR_EIR_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_EIR_EIR_SHIFT) & TSW_CENTRAL_QCI_EIR_EIR_MASK)

◆ TSW_CENTRAL_QCI_EIR_EIR_SHIFT

#define TSW_CENTRAL_QCI_EIR_EIR_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_FCTRL_ENBLK_GET

#define TSW_CENTRAL_QCI_FCTRL_ENBLK_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK

#define TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK   (0x80000000UL)

◆ TSW_CENTRAL_QCI_FCTRL_ENBLK_SET

#define TSW_CENTRAL_QCI_FCTRL_ENBLK_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT   (31U)

◆ TSW_CENTRAL_QCI_FCTRL_ENFID_GET

#define TSW_CENTRAL_QCI_FCTRL_ENFID_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_ENFID_MASK

#define TSW_CENTRAL_QCI_FCTRL_ENFID_MASK   (0x20000000UL)

◆ TSW_CENTRAL_QCI_FCTRL_ENFID_SET

#define TSW_CENTRAL_QCI_FCTRL_ENFID_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT   (29U)

◆ TSW_CENTRAL_QCI_FCTRL_ENFSZ_GET

#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK

#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK   (0x40000000UL)

◆ TSW_CENTRAL_QCI_FCTRL_ENFSZ_SET

#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT   (30U)

◆ TSW_CENTRAL_QCI_FCTRL_ENPCP_GET

#define TSW_CENTRAL_QCI_FCTRL_ENPCP_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK

#define TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK   (0x8000000UL)

◆ TSW_CENTRAL_QCI_FCTRL_ENPCP_SET

#define TSW_CENTRAL_QCI_FCTRL_ENPCP_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT   (27U)

◆ TSW_CENTRAL_QCI_FCTRL_ENSID_GET

#define TSW_CENTRAL_QCI_FCTRL_ENSID_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_ENSID_MASK

#define TSW_CENTRAL_QCI_FCTRL_ENSID_MASK   (0x10000000UL)

◆ TSW_CENTRAL_QCI_FCTRL_ENSID_SET

#define TSW_CENTRAL_QCI_FCTRL_ENSID_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT   (28U)

◆ TSW_CENTRAL_QCI_FCTRL_FMD_GET

#define TSW_CENTRAL_QCI_FCTRL_FMD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK) >> TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_FMD_MASK

#define TSW_CENTRAL_QCI_FCTRL_FMD_MASK   (0xFF0000UL)

◆ TSW_CENTRAL_QCI_FCTRL_FMD_SET

#define TSW_CENTRAL_QCI_FCTRL_FMD_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT   (16U)

◆ TSW_CENTRAL_QCI_FCTRL_GID_GET

#define TSW_CENTRAL_QCI_FCTRL_GID_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_GID_MASK) >> TSW_CENTRAL_QCI_FCTRL_GID_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_GID_MASK

#define TSW_CENTRAL_QCI_FCTRL_GID_MASK   (0xFF00U)

◆ TSW_CENTRAL_QCI_FCTRL_GID_SET

#define TSW_CENTRAL_QCI_FCTRL_GID_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_GID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_GID_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_GID_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_GID_SHIFT   (8U)

◆ TSW_CENTRAL_QCI_FCTRL_PCP_GET

#define TSW_CENTRAL_QCI_FCTRL_PCP_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_PCP_MASK

#define TSW_CENTRAL_QCI_FCTRL_PCP_MASK   (0x7000000UL)

◆ TSW_CENTRAL_QCI_FCTRL_PCP_SET

#define TSW_CENTRAL_QCI_FCTRL_PCP_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT   (24U)

◆ TSW_CENTRAL_QCI_FCTRL_SID_GET

#define TSW_CENTRAL_QCI_FCTRL_SID_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_SID_MASK) >> TSW_CENTRAL_QCI_FCTRL_SID_SHIFT)

◆ TSW_CENTRAL_QCI_FCTRL_SID_MASK

#define TSW_CENTRAL_QCI_FCTRL_SID_MASK   (0xFFU)

◆ TSW_CENTRAL_QCI_FCTRL_SID_SET

#define TSW_CENTRAL_QCI_FCTRL_SID_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_SID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_SID_MASK)

◆ TSW_CENTRAL_QCI_FCTRL_SID_SHIFT

#define TSW_CENTRAL_QCI_FCTRL_SID_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_FILTERSEL_INDEX_GET

#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT)

◆ TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK

#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK   (0xFFU)

◆ TSW_CENTRAL_QCI_FILTERSEL_INDEX_SET

#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK)

◆ TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT

#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_FSIZE_BLK_GET

#define TSW_CENTRAL_QCI_FSIZE_BLK_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK) >> TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT)

◆ TSW_CENTRAL_QCI_FSIZE_BLK_MASK

#define TSW_CENTRAL_QCI_FSIZE_BLK_MASK   (0x80000000UL)

◆ TSW_CENTRAL_QCI_FSIZE_BLK_SET

#define TSW_CENTRAL_QCI_FSIZE_BLK_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK)

◆ TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT

#define TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT   (31U)

◆ TSW_CENTRAL_QCI_FSIZE_MXSZ_GET

#define TSW_CENTRAL_QCI_FSIZE_MXSZ_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK) >> TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT)

◆ TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK

#define TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK   (0xFFFFU)

◆ TSW_CENTRAL_QCI_FSIZE_MXSZ_SET

#define TSW_CENTRAL_QCI_FSIZE_MXSZ_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK)

◆ TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT

#define TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_GATESEL_INDEX_GET

#define TSW_CENTRAL_QCI_GATESEL_INDEX_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK) >> TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT)

◆ TSW_CENTRAL_QCI_GATESEL_INDEX_MASK

#define TSW_CENTRAL_QCI_GATESEL_INDEX_MASK   (0xFFU)

◆ TSW_CENTRAL_QCI_GATESEL_INDEX_SET

#define TSW_CENTRAL_QCI_GATESEL_INDEX_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK)

◆ TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT

#define TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_GCTRL_CDIRE_GET

#define TSW_CENTRAL_QCI_GCTRL_CDIRE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT)

◆ TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK

#define TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK   (0x4U)

◆ TSW_CENTRAL_QCI_GCTRL_CDIRE_SET

#define TSW_CENTRAL_QCI_GCTRL_CDIRE_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK)

◆ TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT

#define TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT   (2U)

◆ TSW_CENTRAL_QCI_GCTRL_CDOEE_GET

#define TSW_CENTRAL_QCI_GCTRL_CDOEE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT)

◆ TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK

#define TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK   (0x8U)

◆ TSW_CENTRAL_QCI_GCTRL_CDOEE_SET

#define TSW_CENTRAL_QCI_GCTRL_CDOEE_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK)

◆ TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT

#define TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT   (3U)

◆ TSW_CENTRAL_QCI_GCTRL_CFGCH_GET

#define TSW_CENTRAL_QCI_GCTRL_CFGCH_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK) >> TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT)

◆ TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK

#define TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK   (0x2U)

◆ TSW_CENTRAL_QCI_GCTRL_CFGCH_SET

#define TSW_CENTRAL_QCI_GCTRL_CFGCH_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK)

◆ TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT

#define TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT   (1U)

◆ TSW_CENTRAL_QCI_GCTRL_EN_GET

#define TSW_CENTRAL_QCI_GCTRL_EN_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_EN_MASK) >> TSW_CENTRAL_QCI_GCTRL_EN_SHIFT)

◆ TSW_CENTRAL_QCI_GCTRL_EN_MASK

#define TSW_CENTRAL_QCI_GCTRL_EN_MASK   (0x1U)

◆ TSW_CENTRAL_QCI_GCTRL_EN_SET

#define TSW_CENTRAL_QCI_GCTRL_EN_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_EN_SHIFT) & TSW_CENTRAL_QCI_GCTRL_EN_MASK)

◆ TSW_CENTRAL_QCI_GCTRL_EN_SHIFT

#define TSW_CENTRAL_QCI_GCTRL_EN_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_GCTRL_IPV_GET

#define TSW_CENTRAL_QCI_GCTRL_IPV_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK) >> TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT)

◆ TSW_CENTRAL_QCI_GCTRL_IPV_MASK

#define TSW_CENTRAL_QCI_GCTRL_IPV_MASK   (0xE0U)

◆ TSW_CENTRAL_QCI_GCTRL_IPV_SET

#define TSW_CENTRAL_QCI_GCTRL_IPV_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK)

◆ TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT

#define TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT   (5U)

◆ TSW_CENTRAL_QCI_GCTRL_STATE_GET

#define TSW_CENTRAL_QCI_GCTRL_STATE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK) >> TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT)

◆ TSW_CENTRAL_QCI_GCTRL_STATE_MASK

#define TSW_CENTRAL_QCI_GCTRL_STATE_MASK   (0x10U)

◆ TSW_CENTRAL_QCI_GCTRL_STATE_SET

#define TSW_CENTRAL_QCI_GCTRL_STATE_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK)

◆ TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT

#define TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT   (4U)

◆ TSW_CENTRAL_QCI_GLISTINDEX_IDX_GET

#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK) >> TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT)

◆ TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK

#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK   (0xFU)

◆ TSW_CENTRAL_QCI_GLISTINDEX_IDX_SET

#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK)

◆ TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT

#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_GSTATUS_CDIR_GET

#define TSW_CENTRAL_QCI_GSTATUS_CDIR_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT)

◆ TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK

#define TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK   (0x4U)

◆ TSW_CENTRAL_QCI_GSTATUS_CDIR_SET

#define TSW_CENTRAL_QCI_GSTATUS_CDIR_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK)

◆ TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT

#define TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT   (2U)

◆ TSW_CENTRAL_QCI_GSTATUS_CDOE_GET

#define TSW_CENTRAL_QCI_GSTATUS_CDOE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT)

◆ TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK

#define TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK   (0x8U)

◆ TSW_CENTRAL_QCI_GSTATUS_CDOE_SET

#define TSW_CENTRAL_QCI_GSTATUS_CDOE_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK)

◆ TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT

#define TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT   (3U)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGERR_GET

#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK

#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK   (0x1U)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGERR_SET

#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT

#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGP_GET

#define TSW_CENTRAL_QCI_GSTATUS_CFGP_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK

#define TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK   (0x2U)

◆ TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT

#define TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT   (1U)

◆ TSW_CENTRAL_QCI_GSTATUS_IPV_GET

#define TSW_CENTRAL_QCI_GSTATUS_IPV_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_IPV_MASK) >> TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT)

◆ TSW_CENTRAL_QCI_GSTATUS_IPV_MASK

#define TSW_CENTRAL_QCI_GSTATUS_IPV_MASK   (0xE0U)

◆ TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT

#define TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT   (5U)

◆ TSW_CENTRAL_QCI_GSTATUS_STATE_GET

#define TSW_CENTRAL_QCI_GSTATUS_STATE_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_STATE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT)

◆ TSW_CENTRAL_QCI_GSTATUS_STATE_MASK

#define TSW_CENTRAL_QCI_GSTATUS_STATE_MASK   (0x10U)

◆ TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT

#define TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT   (4U)

◆ TSW_CENTRAL_QCI_HWCFG_FMD_GET

#define TSW_CENTRAL_QCI_HWCFG_FMD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FMD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT)

◆ TSW_CENTRAL_QCI_HWCFG_FMD_MASK

#define TSW_CENTRAL_QCI_HWCFG_FMD_MASK   (0xFF0000UL)

◆ TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT

#define TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT   (16U)

◆ TSW_CENTRAL_QCI_HWCFG_FTD_GET

#define TSW_CENTRAL_QCI_HWCFG_FTD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT)

◆ TSW_CENTRAL_QCI_HWCFG_FTD_MASK

#define TSW_CENTRAL_QCI_HWCFG_FTD_MASK   (0xFFU)

◆ TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT

#define TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_HWCFG_GTD_GET

#define TSW_CENTRAL_QCI_HWCFG_GTD_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_GTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT)

◆ TSW_CENTRAL_QCI_HWCFG_GTD_MASK

#define TSW_CENTRAL_QCI_HWCFG_GTD_MASK   (0xFF00U)

◆ TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT

#define TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT   (8U)

◆ TSW_CENTRAL_QCI_LISTLEN_ALEN_GET

#define TSW_CENTRAL_QCI_LISTLEN_ALEN_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT)

◆ TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK

#define TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK   (0xFU)

◆ TSW_CENTRAL_QCI_LISTLEN_ALEN_SET

#define TSW_CENTRAL_QCI_LISTLEN_ALEN_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK)

◆ TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT

#define TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_LISTLEN_OLEN_GET

#define TSW_CENTRAL_QCI_LISTLEN_OLEN_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT)

◆ TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK

#define TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK   (0xF0000UL)

◆ TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT

#define TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT   (16U)

◆ TSW_CENTRAL_QCI_MCTRL_CF_GET

#define TSW_CENTRAL_QCI_MCTRL_CF_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CF_MASK) >> TSW_CENTRAL_QCI_MCTRL_CF_SHIFT)

◆ TSW_CENTRAL_QCI_MCTRL_CF_MASK

#define TSW_CENTRAL_QCI_MCTRL_CF_MASK   (0x1U)

◆ TSW_CENTRAL_QCI_MCTRL_CF_SET

#define TSW_CENTRAL_QCI_MCTRL_CF_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CF_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CF_MASK)

◆ TSW_CENTRAL_QCI_MCTRL_CF_SHIFT

#define TSW_CENTRAL_QCI_MCTRL_CF_SHIFT   (0U)

◆ TSW_CENTRAL_QCI_MCTRL_CM_GET

#define TSW_CENTRAL_QCI_MCTRL_CM_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CM_MASK) >> TSW_CENTRAL_QCI_MCTRL_CM_SHIFT)

◆ TSW_CENTRAL_QCI_MCTRL_CM_MASK

#define TSW_CENTRAL_QCI_MCTRL_CM_MASK   (0x2U)

◆ TSW_CENTRAL_QCI_MCTRL_CM_SET

#define TSW_CENTRAL_QCI_MCTRL_CM_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CM_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CM_MASK)

◆ TSW_CENTRAL_QCI_MCTRL_CM_SHIFT

#define TSW_CENTRAL_QCI_MCTRL_CM_SHIFT   (1U)

◆ TSW_CENTRAL_QCI_MCTRL_DOY_GET

#define TSW_CENTRAL_QCI_MCTRL_DOY_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK) >> TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT)

◆ TSW_CENTRAL_QCI_MCTRL_DOY_MASK

#define TSW_CENTRAL_QCI_MCTRL_DOY_MASK   (0x4U)

◆ TSW_CENTRAL_QCI_MCTRL_DOY_SET

#define TSW_CENTRAL_QCI_MCTRL_DOY_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK)

◆ TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT

#define TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT   (2U)

◆ TSW_CENTRAL_QCI_MCTRL_MAFR_GET

#define TSW_CENTRAL_QCI_MCTRL_MAFR_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFR_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT)

◆ TSW_CENTRAL_QCI_MCTRL_MAFR_MASK

#define TSW_CENTRAL_QCI_MCTRL_MAFR_MASK   (0x10U)

◆ TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT

#define TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT   (4U)

◆ TSW_CENTRAL_QCI_MCTRL_MAFREN_GET

#define TSW_CENTRAL_QCI_MCTRL_MAFREN_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT)

◆ TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK

#define TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK   (0x8U)

◆ TSW_CENTRAL_QCI_MCTRL_MAFREN_SET

#define TSW_CENTRAL_QCI_MCTRL_MAFREN_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK)

◆ TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT

#define TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT   (3U)

◆ TSW_CENTRAL_QCI_MCTRL_RESET_GET

#define TSW_CENTRAL_QCI_MCTRL_RESET_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK) >> TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT)

◆ TSW_CENTRAL_QCI_MCTRL_RESET_MASK

#define TSW_CENTRAL_QCI_MCTRL_RESET_MASK   (0x80000000UL)

◆ TSW_CENTRAL_QCI_MCTRL_RESET_SET

#define TSW_CENTRAL_QCI_MCTRL_RESET_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK)

◆ TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT

#define TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT   (31U)

◆ TSW_CENTRAL_QCI_METERSEL_INDEX_GET

#define TSW_CENTRAL_QCI_METERSEL_INDEX_GET (   x)    (((uint32_t)(x) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT)

◆ TSW_CENTRAL_QCI_METERSEL_INDEX_MASK

#define TSW_CENTRAL_QCI_METERSEL_INDEX_MASK   (0xFFU)

◆ TSW_CENTRAL_QCI_METERSEL_INDEX_SET

#define TSW_CENTRAL_QCI_METERSEL_INDEX_SET (   x)    (((uint32_t)(x) << TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK)

◆ TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT

#define TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_GET

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK   (0x2U)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SET

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT   (1U)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_GET

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK   (0x1U)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SET

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK   (0x10U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT   (4U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK   (0x80000000UL)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT   (31U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK   (0x1F00U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT   (8U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK   (0x4U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT   (2U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK   (0x8U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT   (3U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK   (0xFF0000UL)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT   (16U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_GET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK   (0x2U)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SET

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT   (1U)

◆ TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_GET

#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK

#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK   (0xFFU)

◆ TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SET

#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_GET

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK   (0x80000000UL)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SET

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT   (31U)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_GET

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK   (0xFFU)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SET

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_GET

#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK

#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SET

#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_GET

#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK

#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SET

#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_GET

#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK

#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK   (0xFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SET

#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_GET

#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK

#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK   (0xFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SET

#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_GET

#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK

#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK   (0xFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SET

#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_GET

#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK

#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK   (0xFFU)

◆ TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SET

#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_GET

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK   (0x80000000UL)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SET

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT   (31U)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_GET

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK   (0xFFU)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SET

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK)

◆ TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT

#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_GET

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SET

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_GET

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK   (0xF0000000UL)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SET

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT   (28U)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_GET

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK   (0xFFF0000UL)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SET

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT   (16U)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_GET

#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK

#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SET

#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_GET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK   (0x30U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT   (4U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_GET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK   (0x1U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_GET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK   (0x6U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT   (1U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_GET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK   (0x80U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT   (7U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_GET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK   (0xFF00U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT   (8U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_GET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK   (0x8U)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SET

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT   (3U)

◆ TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_GET

#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK

#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK   (0xFFU)

◆ TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SET

#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_GET

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SET

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_GET

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK   (0xFFF0000UL)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SET

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT   (16U)

◆ TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_GET

#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK

#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SET

#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_GET

#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK

#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SET

#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT   (0U)

◆ TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_GET

#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT)

◆ TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK

#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SET

#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK)

◆ TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT

#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_GET

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK   (0x2U)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SET

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT   (1U)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_GET

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SET

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK   (0x10U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT   (4U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK   (0x80000000UL)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT   (31U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK   (0x1F00U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT   (8U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK   (0x4U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT   (2U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK   (0x8U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT   (3U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK   (0xFF0000UL)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT   (16U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_GET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK   (0x2U)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SET

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT   (1U)

◆ TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_GET

#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK

#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK   (0xFFU)

◆ TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SET

#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_GET

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK   (0x80000000UL)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SET

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT   (31U)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_GET

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK   (0xFFU)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SET

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_GET

#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK

#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SET

#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_GET

#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK

#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SET

#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_GET

#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK

#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK   (0xFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SET

#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_GET

#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK

#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK   (0xFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SET

#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_GET

#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK

#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK   (0xFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SET

#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_GET

#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK

#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK   (0xFFU)

◆ TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SET

#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_GET

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK   (0x80000000UL)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SET

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT   (31U)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_GET

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK   (0xFFU)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SET

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK)

◆ TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT

#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK   (0x2U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT   (1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK   (0x8U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT   (3U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK   (0x4U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT   (2U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK   (0x10U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT   (4U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK   (0x40U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT   (6U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK   (0x20U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT   (5U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK   (0x2U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT   (1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK   (0x4U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT   (2U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK   (0x200U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT   (9U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK   (0x8U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT   (3U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK   (0x100U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT   (8U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK   (0x400U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT   (10U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK   (0x800U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT   (11U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK   (0x7FU)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK   (0x40U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT   (6U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK   (0x20U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT   (5U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK   (0x10U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT   (4U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK   (0xFFFF0000UL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT   (16U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK   (0x8U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT   (3U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK   (0x100U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT   (8U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK   (0x4U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT   (2U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK   (0x200U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT   (9U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK   (0x2U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT   (1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK   (0xFF0000UL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT   (16U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK   (0xFF000000UL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT   (24U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_GET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SET

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK)

◆ TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT

#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_GET

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SET

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_GET

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK   (0xF0000000UL)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SET

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT   (28U)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_GET

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK   (0xFFF0000UL)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SET

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT   (16U)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_GET

#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK

#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SET

#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_GET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK   (0x30U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT   (4U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_GET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK   (0x1U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_GET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK   (0x6U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT   (1U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_GET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK   (0x80U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT   (7U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_GET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK   (0xFF00U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT   (8U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_GET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK   (0x8U)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SET

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT   (3U)

◆ TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_GET

#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK

#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK   (0xFFU)

◆ TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SET

#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_GET

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SET

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_GET

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK   (0xFFF0000UL)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SET

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT   (16U)

◆ TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_GET

#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK

#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SET

#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_GET

#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK

#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SET

#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT   (0U)

◆ TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_GET

#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT)

◆ TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK

#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK   (0xFFFFU)

◆ TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SET

#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK)

◆ TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT

#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_CTRL_EN_GET

#define TSW_CPU_PORT_MONITOR_CTRL_EN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK) >> TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT)

◆ TSW_CPU_PORT_MONITOR_CTRL_EN_MASK

#define TSW_CPU_PORT_MONITOR_CTRL_EN_MASK   (0x1U)

◆ TSW_CPU_PORT_MONITOR_CTRL_EN_SET

#define TSW_CPU_PORT_MONITOR_CTRL_EN_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK)

◆ TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT

#define TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_PARAM_CNTW_GET

#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT)

◆ TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK

#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK   (0x7FU)

◆ TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT

#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_GET

#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)

◆ TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK

#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK   (0xFFFF0000UL)

◆ TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT

#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT   (16U)

◆ TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_GET

#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)

◆ TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK

#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK   (0xFF00U)

◆ TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT

#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT   (8U)

◆ TSW_CPU_PORT_MONITOR_RESET_RSALL_GET

#define TSW_CPU_PORT_MONITOR_RESET_RSALL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK

#define TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK   (0x1U)

◆ TSW_CPU_PORT_MONITOR_RESET_RSALL_SET

#define TSW_CPU_PORT_MONITOR_RESET_RSALL_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK)

◆ TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT

#define TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RESET_RSRX_GET

#define TSW_CPU_PORT_MONITOR_RESET_RSRX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK

#define TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK   (0x4U)

◆ TSW_CPU_PORT_MONITOR_RESET_RSRX_SET

#define TSW_CPU_PORT_MONITOR_RESET_RSRX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK)

◆ TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT

#define TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT   (2U)

◆ TSW_CPU_PORT_MONITOR_RESET_RSTX_GET

#define TSW_CPU_PORT_MONITOR_RESET_RSTX_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK

#define TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK   (0x2U)

◆ TSW_CPU_PORT_MONITOR_RESET_RSTX_SET

#define TSW_CPU_PORT_MONITOR_RESET_RSTX_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK)

◆ TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT

#define TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT   (1U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT

#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT   (0U)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK   (0xFFFFFFFFUL)

◆ TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT

#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT   (0U)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_GET

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK   (0x1U)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SET

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT   (0U)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_GET

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK   (0x2U)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SET

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT   (1U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_GET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK   (0x10000UL)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT   (16U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_GET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK   (0x1000U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT   (12U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_GET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK   (0x20000UL)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT   (17U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_GET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK   (0xE000U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT   (13U)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_GET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_GET (   x)    (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK   (0xFFFU)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SET

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SET (   x)    (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK)

◆ TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT

#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT   (0U)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT0

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT0   (0UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT1

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT1   (1UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT2

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT2   (2UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT3

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT3   (3UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT4

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT4   (4UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT5

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT5   (5UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT6

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT6   (6UL)

◆ TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT7

#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT7   (7UL)

◆ TSW_EGFRCNT_VALUE_GET

#define TSW_EGFRCNT_VALUE_GET (   x)    (((uint32_t)(x) & TSW_EGFRCNT_VALUE_MASK) >> TSW_EGFRCNT_VALUE_SHIFT)

◆ TSW_EGFRCNT_VALUE_MASK

#define TSW_EGFRCNT_VALUE_MASK   (0xFFFFFFFFUL)

◆ TSW_EGFRCNT_VALUE_SHIFT

#define TSW_EGFRCNT_VALUE_SHIFT   (0U)

◆ TSW_HITMEM_HITMEM_REG_1

#define TSW_HITMEM_HITMEM_REG_1   (0UL)

◆ TSW_HITMEM_HITMEM_REG_2

#define TSW_HITMEM_HITMEM_REG_2   (1UL)

◆ TSW_HITMEM_HITMEM_REG_3

#define TSW_HITMEM_HITMEM_REG_3   (2UL)

◆ TSW_HITMEM_HITMEM_REG_4

#define TSW_HITMEM_HITMEM_REG_4   (3UL)

◆ TSW_HITMEM_HITMEM_REG_GET

#define TSW_HITMEM_HITMEM_REG_GET (   x)    (((uint32_t)(x) & TSW_HITMEM_HITMEM_REG_MASK) >> TSW_HITMEM_HITMEM_REG_SHIFT)

◆ TSW_HITMEM_HITMEM_REG_MASK

#define TSW_HITMEM_HITMEM_REG_MASK   (0xFFFFFFFFUL)

◆ TSW_HITMEM_HITMEM_REG_SET

#define TSW_HITMEM_HITMEM_REG_SET (   x)    (((uint32_t)(x) << TSW_HITMEM_HITMEM_REG_SHIFT) & TSW_HITMEM_HITMEM_REG_MASK)

◆ TSW_HITMEM_HITMEM_REG_SHIFT

#define TSW_HITMEM_HITMEM_REG_SHIFT   (0U)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT0

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT0   (0UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT1

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT1   (1UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT2

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT2   (2UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT3

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT3   (3UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT4

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT4   (4UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT5

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT5   (5UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT6

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT6   (6UL)

◆ TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT7

#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT7   (7UL)

◆ TSW_IGFRCNT_VALUE_GET

#define TSW_IGFRCNT_VALUE_GET (   x)    (((uint32_t)(x) & TSW_IGFRCNT_VALUE_MASK) >> TSW_IGFRCNT_VALUE_SHIFT)

◆ TSW_IGFRCNT_VALUE_MASK

#define TSW_IGFRCNT_VALUE_MASK   (0xFFFFFFFFUL)

◆ TSW_IGFRCNT_VALUE_SHIFT

#define TSW_IGFRCNT_VALUE_SHIFT   (0U)

◆ TSW_LU_MAIN_BC_ACTION_DEST_GET

#define TSW_LU_MAIN_BC_ACTION_DEST_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DEST_MASK) >> TSW_LU_MAIN_BC_ACTION_DEST_SHIFT)

◆ TSW_LU_MAIN_BC_ACTION_DEST_MASK

#define TSW_LU_MAIN_BC_ACTION_DEST_MASK   (0xFFFFU)

◆ TSW_LU_MAIN_BC_ACTION_DEST_SET

#define TSW_LU_MAIN_BC_ACTION_DEST_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DEST_SHIFT) & TSW_LU_MAIN_BC_ACTION_DEST_MASK)

◆ TSW_LU_MAIN_BC_ACTION_DEST_SHIFT

#define TSW_LU_MAIN_BC_ACTION_DEST_SHIFT   (0U)

◆ TSW_LU_MAIN_BC_ACTION_DROP_GET

#define TSW_LU_MAIN_BC_ACTION_DROP_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DROP_MASK) >> TSW_LU_MAIN_BC_ACTION_DROP_SHIFT)

◆ TSW_LU_MAIN_BC_ACTION_DROP_MASK

#define TSW_LU_MAIN_BC_ACTION_DROP_MASK   (0x80000UL)

◆ TSW_LU_MAIN_BC_ACTION_DROP_SET

#define TSW_LU_MAIN_BC_ACTION_DROP_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DROP_SHIFT) & TSW_LU_MAIN_BC_ACTION_DROP_MASK)

◆ TSW_LU_MAIN_BC_ACTION_DROP_SHIFT

#define TSW_LU_MAIN_BC_ACTION_DROP_SHIFT   (19U)

◆ TSW_LU_MAIN_BC_ACTION_QSEL_GET

#define TSW_LU_MAIN_BC_ACTION_QSEL_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK) >> TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT)

◆ TSW_LU_MAIN_BC_ACTION_QSEL_MASK

#define TSW_LU_MAIN_BC_ACTION_QSEL_MASK   (0x300000UL)

◆ TSW_LU_MAIN_BC_ACTION_QSEL_SET

#define TSW_LU_MAIN_BC_ACTION_QSEL_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK)

◆ TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT

#define TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT   (20U)

◆ TSW_LU_MAIN_BC_ACTION_QUEUE_GET

#define TSW_LU_MAIN_BC_ACTION_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT)

◆ TSW_LU_MAIN_BC_ACTION_QUEUE_MASK

#define TSW_LU_MAIN_BC_ACTION_QUEUE_MASK   (0x70000UL)

◆ TSW_LU_MAIN_BC_ACTION_QUEUE_SET

#define TSW_LU_MAIN_BC_ACTION_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK)

◆ TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT

#define TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT   (16U)

◆ TSW_LU_MAIN_BC_ACTION_UTAG_GET

#define TSW_LU_MAIN_BC_ACTION_UTAG_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK) >> TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT)

◆ TSW_LU_MAIN_BC_ACTION_UTAG_MASK

#define TSW_LU_MAIN_BC_ACTION_UTAG_MASK   (0x1C00000UL)

◆ TSW_LU_MAIN_BC_ACTION_UTAG_SET

#define TSW_LU_MAIN_BC_ACTION_UTAG_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK)

◆ TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT

#define TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT   (22U)

◆ TSW_LU_MAIN_BYPASS_DEST_GET

#define TSW_LU_MAIN_BYPASS_DEST_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DEST_MASK) >> TSW_LU_MAIN_BYPASS_DEST_SHIFT)

◆ TSW_LU_MAIN_BYPASS_DEST_MASK

#define TSW_LU_MAIN_BYPASS_DEST_MASK   (0xFFFFU)

◆ TSW_LU_MAIN_BYPASS_DEST_SET

#define TSW_LU_MAIN_BYPASS_DEST_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DEST_SHIFT) & TSW_LU_MAIN_BYPASS_DEST_MASK)

◆ TSW_LU_MAIN_BYPASS_DEST_SHIFT

#define TSW_LU_MAIN_BYPASS_DEST_SHIFT   (0U)

◆ TSW_LU_MAIN_BYPASS_DROP_GET

#define TSW_LU_MAIN_BYPASS_DROP_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DROP_MASK) >> TSW_LU_MAIN_BYPASS_DROP_SHIFT)

◆ TSW_LU_MAIN_BYPASS_DROP_MASK

#define TSW_LU_MAIN_BYPASS_DROP_MASK   (0x80000UL)

◆ TSW_LU_MAIN_BYPASS_DROP_SET

#define TSW_LU_MAIN_BYPASS_DROP_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DROP_SHIFT) & TSW_LU_MAIN_BYPASS_DROP_MASK)

◆ TSW_LU_MAIN_BYPASS_DROP_SHIFT

#define TSW_LU_MAIN_BYPASS_DROP_SHIFT   (19U)

◆ TSW_LU_MAIN_BYPASS_HIT_GET

#define TSW_LU_MAIN_BYPASS_HIT_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_MASK) >> TSW_LU_MAIN_BYPASS_HIT_SHIFT)

◆ TSW_LU_MAIN_BYPASS_HIT_MASK

#define TSW_LU_MAIN_BYPASS_HIT_MASK   (0x1000000UL)

◆ TSW_LU_MAIN_BYPASS_HIT_SET

#define TSW_LU_MAIN_BYPASS_HIT_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_MASK)

◆ TSW_LU_MAIN_BYPASS_HIT_SHIFT

#define TSW_LU_MAIN_BYPASS_HIT_SHIFT   (24U)

◆ TSW_LU_MAIN_BYPASS_HIT_VLAN_GET

#define TSW_LU_MAIN_BYPASS_HIT_VLAN_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK) >> TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT)

◆ TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK

#define TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK   (0x100000UL)

◆ TSW_LU_MAIN_BYPASS_HIT_VLAN_SET

#define TSW_LU_MAIN_BYPASS_HIT_VLAN_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK)

◆ TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT

#define TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT   (20U)

◆ TSW_LU_MAIN_BYPASS_QUEUE_GET

#define TSW_LU_MAIN_BYPASS_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_QUEUE_MASK) >> TSW_LU_MAIN_BYPASS_QUEUE_SHIFT)

◆ TSW_LU_MAIN_BYPASS_QUEUE_MASK

#define TSW_LU_MAIN_BYPASS_QUEUE_MASK   (0x70000UL)

◆ TSW_LU_MAIN_BYPASS_QUEUE_SET

#define TSW_LU_MAIN_BYPASS_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_QUEUE_SHIFT) & TSW_LU_MAIN_BYPASS_QUEUE_MASK)

◆ TSW_LU_MAIN_BYPASS_QUEUE_SHIFT

#define TSW_LU_MAIN_BYPASS_QUEUE_SHIFT   (16U)

◆ TSW_LU_MAIN_BYPASS_UTAG_GET

#define TSW_LU_MAIN_BYPASS_UTAG_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_UTAG_MASK) >> TSW_LU_MAIN_BYPASS_UTAG_SHIFT)

◆ TSW_LU_MAIN_BYPASS_UTAG_MASK

#define TSW_LU_MAIN_BYPASS_UTAG_MASK   (0xE00000UL)

◆ TSW_LU_MAIN_BYPASS_UTAG_SET

#define TSW_LU_MAIN_BYPASS_UTAG_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_UTAG_SHIFT) & TSW_LU_MAIN_BYPASS_UTAG_MASK)

◆ TSW_LU_MAIN_BYPASS_UTAG_SHIFT

#define TSW_LU_MAIN_BYPASS_UTAG_SHIFT   (21U)

◆ TSW_LU_MAIN_CTRL_BYP_EN_GET

#define TSW_LU_MAIN_CTRL_BYP_EN_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_CTRL_BYP_EN_MASK) >> TSW_LU_MAIN_CTRL_BYP_EN_SHIFT)

◆ TSW_LU_MAIN_CTRL_BYP_EN_MASK

#define TSW_LU_MAIN_CTRL_BYP_EN_MASK   (0x1U)

◆ TSW_LU_MAIN_CTRL_BYP_EN_SET

#define TSW_LU_MAIN_CTRL_BYP_EN_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_CTRL_BYP_EN_SHIFT) & TSW_LU_MAIN_CTRL_BYP_EN_MASK)

◆ TSW_LU_MAIN_CTRL_BYP_EN_SHIFT

#define TSW_LU_MAIN_CTRL_BYP_EN_SHIFT   (0U)

◆ TSW_LU_MAIN_HITMEM_CAMMEMCLR_GET

#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT)

◆ TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK

#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK   (0x2U)

◆ TSW_LU_MAIN_HITMEM_CAMMEMCLR_SET

#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK)

◆ TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT

#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT   (1U)

◆ TSW_LU_MAIN_HITMEM_HITMEMCLR_GET

#define TSW_LU_MAIN_HITMEM_HITMEMCLR_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT)

◆ TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK

#define TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK   (0x1U)

◆ TSW_LU_MAIN_HITMEM_HITMEMCLR_SET

#define TSW_LU_MAIN_HITMEM_HITMEMCLR_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK)

◆ TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT

#define TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT   (0U)

◆ TSW_LU_MAIN_INTF_ACTION_DEST_GET

#define TSW_LU_MAIN_INTF_ACTION_DEST_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK) >> TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT)

◆ TSW_LU_MAIN_INTF_ACTION_DEST_MASK

#define TSW_LU_MAIN_INTF_ACTION_DEST_MASK   (0xFFFFU)

◆ TSW_LU_MAIN_INTF_ACTION_DEST_SET

#define TSW_LU_MAIN_INTF_ACTION_DEST_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK)

◆ TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT

#define TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT   (0U)

◆ TSW_LU_MAIN_INTF_ACTION_DROP_GET

#define TSW_LU_MAIN_INTF_ACTION_DROP_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK) >> TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT)

◆ TSW_LU_MAIN_INTF_ACTION_DROP_MASK

#define TSW_LU_MAIN_INTF_ACTION_DROP_MASK   (0x80000UL)

◆ TSW_LU_MAIN_INTF_ACTION_DROP_SET

#define TSW_LU_MAIN_INTF_ACTION_DROP_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK)

◆ TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT

#define TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT   (19U)

◆ TSW_LU_MAIN_INTF_ACTION_QSEL_GET

#define TSW_LU_MAIN_INTF_ACTION_QSEL_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK) >> TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT)

◆ TSW_LU_MAIN_INTF_ACTION_QSEL_MASK

#define TSW_LU_MAIN_INTF_ACTION_QSEL_MASK   (0x300000UL)

◆ TSW_LU_MAIN_INTF_ACTION_QSEL_SET

#define TSW_LU_MAIN_INTF_ACTION_QSEL_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK)

◆ TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT

#define TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT   (20U)

◆ TSW_LU_MAIN_INTF_ACTION_QUEUE_GET

#define TSW_LU_MAIN_INTF_ACTION_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT)

◆ TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK

#define TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK   (0x70000UL)

◆ TSW_LU_MAIN_INTF_ACTION_QUEUE_SET

#define TSW_LU_MAIN_INTF_ACTION_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK)

◆ TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT

#define TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT   (16U)

◆ TSW_LU_MAIN_INTF_ACTION_UTAG_GET

#define TSW_LU_MAIN_INTF_ACTION_UTAG_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK) >> TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT)

◆ TSW_LU_MAIN_INTF_ACTION_UTAG_MASK

#define TSW_LU_MAIN_INTF_ACTION_UTAG_MASK   (0x1C00000UL)

◆ TSW_LU_MAIN_INTF_ACTION_UTAG_SET

#define TSW_LU_MAIN_INTF_ACTION_UTAG_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK)

◆ TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT

#define TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT   (22U)

◆ TSW_LU_MAIN_NN_ACTION_DEST_GET

#define TSW_LU_MAIN_NN_ACTION_DEST_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DEST_MASK) >> TSW_LU_MAIN_NN_ACTION_DEST_SHIFT)

◆ TSW_LU_MAIN_NN_ACTION_DEST_MASK

#define TSW_LU_MAIN_NN_ACTION_DEST_MASK   (0xFFFFU)

◆ TSW_LU_MAIN_NN_ACTION_DEST_SET

#define TSW_LU_MAIN_NN_ACTION_DEST_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DEST_SHIFT) & TSW_LU_MAIN_NN_ACTION_DEST_MASK)

◆ TSW_LU_MAIN_NN_ACTION_DEST_SHIFT

#define TSW_LU_MAIN_NN_ACTION_DEST_SHIFT   (0U)

◆ TSW_LU_MAIN_NN_ACTION_DROP_GET

#define TSW_LU_MAIN_NN_ACTION_DROP_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DROP_MASK) >> TSW_LU_MAIN_NN_ACTION_DROP_SHIFT)

◆ TSW_LU_MAIN_NN_ACTION_DROP_MASK

#define TSW_LU_MAIN_NN_ACTION_DROP_MASK   (0x80000UL)

◆ TSW_LU_MAIN_NN_ACTION_DROP_SET

#define TSW_LU_MAIN_NN_ACTION_DROP_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DROP_SHIFT) & TSW_LU_MAIN_NN_ACTION_DROP_MASK)

◆ TSW_LU_MAIN_NN_ACTION_DROP_SHIFT

#define TSW_LU_MAIN_NN_ACTION_DROP_SHIFT   (19U)

◆ TSW_LU_MAIN_NN_ACTION_QSEL_GET

#define TSW_LU_MAIN_NN_ACTION_QSEL_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK) >> TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT)

◆ TSW_LU_MAIN_NN_ACTION_QSEL_MASK

#define TSW_LU_MAIN_NN_ACTION_QSEL_MASK   (0x300000UL)

◆ TSW_LU_MAIN_NN_ACTION_QSEL_SET

#define TSW_LU_MAIN_NN_ACTION_QSEL_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK)

◆ TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT

#define TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT   (20U)

◆ TSW_LU_MAIN_NN_ACTION_QUEUE_GET

#define TSW_LU_MAIN_NN_ACTION_QUEUE_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT)

◆ TSW_LU_MAIN_NN_ACTION_QUEUE_MASK

#define TSW_LU_MAIN_NN_ACTION_QUEUE_MASK   (0x70000UL)

◆ TSW_LU_MAIN_NN_ACTION_QUEUE_SET

#define TSW_LU_MAIN_NN_ACTION_QUEUE_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK)

◆ TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT

#define TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT   (16U)

◆ TSW_LU_MAIN_NN_ACTION_UTAG_GET

#define TSW_LU_MAIN_NN_ACTION_UTAG_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK) >> TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT)

◆ TSW_LU_MAIN_NN_ACTION_UTAG_MASK

#define TSW_LU_MAIN_NN_ACTION_UTAG_MASK   (0x1C00000UL)

◆ TSW_LU_MAIN_NN_ACTION_UTAG_SET

#define TSW_LU_MAIN_NN_ACTION_UTAG_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK)

◆ TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT

#define TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT   (22U)

◆ TSW_LU_MAIN_PARAM_ADDRW_ENTRY_GET

#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK) >> TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT)

◆ TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK

#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK   (0xFFU)

◆ TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT

#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT   (0U)

◆ TSW_LU_MAIN_PARAM_NSTR_GET

#define TSW_LU_MAIN_PARAM_NSTR_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PARAM_NSTR_MASK) >> TSW_LU_MAIN_PARAM_NSTR_SHIFT)

◆ TSW_LU_MAIN_PARAM_NSTR_MASK

#define TSW_LU_MAIN_PARAM_NSTR_MASK   (0xFF00U)

◆ TSW_LU_MAIN_PARAM_NSTR_SHIFT

#define TSW_LU_MAIN_PARAM_NSTR_SHIFT   (8U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP0_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP0_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP0_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP0_MASK   (0x7U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP0_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP0_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT   (0U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP1_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP1_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP1_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP1_MASK   (0x38U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP1_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP1_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT   (3U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP2_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP2_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP2_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP2_MASK   (0x1C0U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP2_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP2_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT   (6U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP3_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP3_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP3_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP3_MASK   (0xE00U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP3_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP3_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT   (9U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP4_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP4_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP4_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP4_MASK   (0x7000U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP4_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP4_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT   (12U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP5_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP5_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP5_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP5_MASK   (0x38000UL)

◆ TSW_LU_MAIN_PCP_REMAP_PCP5_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP5_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT   (15U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP6_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP6_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP6_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP6_MASK   (0x1C0000UL)

◆ TSW_LU_MAIN_PCP_REMAP_PCP6_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP6_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT   (18U)

◆ TSW_LU_MAIN_PCP_REMAP_PCP7_GET

#define TSW_LU_MAIN_PCP_REMAP_PCP7_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT)

◆ TSW_LU_MAIN_PCP_REMAP_PCP7_MASK

#define TSW_LU_MAIN_PCP_REMAP_PCP7_MASK   (0xE00000UL)

◆ TSW_LU_MAIN_PCP_REMAP_PCP7_SET

#define TSW_LU_MAIN_PCP_REMAP_PCP7_SET (   x)    (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK)

◆ TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT

#define TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT   (21U)

◆ TSW_LU_MAIN_VERSION_VER_HI_GET

#define TSW_LU_MAIN_VERSION_VER_HI_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_HI_MASK) >> TSW_LU_MAIN_VERSION_VER_HI_SHIFT)

◆ TSW_LU_MAIN_VERSION_VER_HI_MASK

#define TSW_LU_MAIN_VERSION_VER_HI_MASK   (0xFF000000UL)

◆ TSW_LU_MAIN_VERSION_VER_HI_SHIFT

#define TSW_LU_MAIN_VERSION_VER_HI_SHIFT   (24U)

◆ TSW_LU_MAIN_VERSION_VER_LO_GET

#define TSW_LU_MAIN_VERSION_VER_LO_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_LO_MASK) >> TSW_LU_MAIN_VERSION_VER_LO_SHIFT)

◆ TSW_LU_MAIN_VERSION_VER_LO_MASK

#define TSW_LU_MAIN_VERSION_VER_LO_MASK   (0xFF0000UL)

◆ TSW_LU_MAIN_VERSION_VER_LO_SHIFT

#define TSW_LU_MAIN_VERSION_VER_LO_SHIFT   (16U)

◆ TSW_LU_MAIN_VERSION_VER_REV_GET

#define TSW_LU_MAIN_VERSION_VER_REV_GET (   x)    (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_REV_MASK) >> TSW_LU_MAIN_VERSION_VER_REV_SHIFT)

◆ TSW_LU_MAIN_VERSION_VER_REV_MASK

#define TSW_LU_MAIN_VERSION_VER_REV_MASK   (0xFFU)

◆ TSW_LU_MAIN_VERSION_VER_REV_SHIFT

#define TSW_LU_MAIN_VERSION_VER_REV_SHIFT   (0U)

◆ TSW_MAC_EM1

#define TSW_MAC_EM1   (0UL)

◆ TSW_MAC_PM1

#define TSW_MAC_PM1   (1UL)

◆ TSW_MM2S_ADDRLO_ADDRLO_GET

#define TSW_MM2S_ADDRLO_ADDRLO_GET (   x)    (((uint32_t)(x) & TSW_MM2S_ADDRLO_ADDRLO_MASK) >> TSW_MM2S_ADDRLO_ADDRLO_SHIFT)

◆ TSW_MM2S_ADDRLO_ADDRLO_MASK

#define TSW_MM2S_ADDRLO_ADDRLO_MASK   (0xFFFFFFFFUL)

◆ TSW_MM2S_ADDRLO_ADDRLO_SET

#define TSW_MM2S_ADDRLO_ADDRLO_SET (   x)    (((uint32_t)(x) << TSW_MM2S_ADDRLO_ADDRLO_SHIFT) & TSW_MM2S_ADDRLO_ADDRLO_MASK)

◆ TSW_MM2S_ADDRLO_ADDRLO_SHIFT

#define TSW_MM2S_ADDRLO_ADDRLO_SHIFT   (0U)

◆ TSW_MM2S_CTRL_GO_GET

#define TSW_MM2S_CTRL_GO_GET (   x)    (((uint32_t)(x) & TSW_MM2S_CTRL_GO_MASK) >> TSW_MM2S_CTRL_GO_SHIFT)

◆ TSW_MM2S_CTRL_GO_MASK

#define TSW_MM2S_CTRL_GO_MASK   (0x80000000UL)

◆ TSW_MM2S_CTRL_GO_SET

#define TSW_MM2S_CTRL_GO_SET (   x)    (((uint32_t)(x) << TSW_MM2S_CTRL_GO_SHIFT) & TSW_MM2S_CTRL_GO_MASK)

◆ TSW_MM2S_CTRL_GO_SHIFT

#define TSW_MM2S_CTRL_GO_SHIFT   (31U)

◆ TSW_MM2S_CTRL_ID_GET

#define TSW_MM2S_CTRL_ID_GET (   x)    (((uint32_t)(x) & TSW_MM2S_CTRL_ID_MASK) >> TSW_MM2S_CTRL_ID_SHIFT)

◆ TSW_MM2S_CTRL_ID_MASK

#define TSW_MM2S_CTRL_ID_MASK   (0xFU)

◆ TSW_MM2S_CTRL_ID_SET

#define TSW_MM2S_CTRL_ID_SET (   x)    (((uint32_t)(x) << TSW_MM2S_CTRL_ID_SHIFT) & TSW_MM2S_CTRL_ID_MASK)

◆ TSW_MM2S_CTRL_ID_SHIFT

#define TSW_MM2S_CTRL_ID_SHIFT   (0U)

◆ TSW_MM2S_CTRL_NGENLAST_GET

#define TSW_MM2S_CTRL_NGENLAST_GET (   x)    (((uint32_t)(x) & TSW_MM2S_CTRL_NGENLAST_MASK) >> TSW_MM2S_CTRL_NGENLAST_SHIFT)

◆ TSW_MM2S_CTRL_NGENLAST_MASK

#define TSW_MM2S_CTRL_NGENLAST_MASK   (0x10U)

◆ TSW_MM2S_CTRL_NGENLAST_SET

#define TSW_MM2S_CTRL_NGENLAST_SET (   x)    (((uint32_t)(x) << TSW_MM2S_CTRL_NGENLAST_SHIFT) & TSW_MM2S_CTRL_NGENLAST_MASK)

◆ TSW_MM2S_CTRL_NGENLAST_SHIFT

#define TSW_MM2S_CTRL_NGENLAST_SHIFT   (4U)

◆ TSW_MM2S_DMA_CFG_ASIZE_GET

#define TSW_MM2S_DMA_CFG_ASIZE_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ASIZE_MASK) >> TSW_MM2S_DMA_CFG_ASIZE_SHIFT)

◆ TSW_MM2S_DMA_CFG_ASIZE_MASK

#define TSW_MM2S_DMA_CFG_ASIZE_MASK   (0x70000UL)

◆ TSW_MM2S_DMA_CFG_ASIZE_SHIFT

#define TSW_MM2S_DMA_CFG_ASIZE_SHIFT   (16U)

◆ TSW_MM2S_DMA_CFG_CBUFD_GET

#define TSW_MM2S_DMA_CFG_CBUFD_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CFG_CBUFD_MASK) >> TSW_MM2S_DMA_CFG_CBUFD_SHIFT)

◆ TSW_MM2S_DMA_CFG_CBUFD_MASK

#define TSW_MM2S_DMA_CFG_CBUFD_MASK   (0xF00000UL)

◆ TSW_MM2S_DMA_CFG_CBUFD_SHIFT

#define TSW_MM2S_DMA_CFG_CBUFD_SHIFT   (20U)

◆ TSW_MM2S_DMA_CFG_DBUFD_GET

#define TSW_MM2S_DMA_CFG_DBUFD_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CFG_DBUFD_MASK) >> TSW_MM2S_DMA_CFG_DBUFD_SHIFT)

◆ TSW_MM2S_DMA_CFG_DBUFD_MASK

#define TSW_MM2S_DMA_CFG_DBUFD_MASK   (0xF000000UL)

◆ TSW_MM2S_DMA_CFG_DBUFD_SHIFT

#define TSW_MM2S_DMA_CFG_DBUFD_SHIFT   (24U)

◆ TSW_MM2S_DMA_CFG_ENA64_GET

#define TSW_MM2S_DMA_CFG_ENA64_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ENA64_MASK) >> TSW_MM2S_DMA_CFG_ENA64_SHIFT)

◆ TSW_MM2S_DMA_CFG_ENA64_MASK

#define TSW_MM2S_DMA_CFG_ENA64_MASK   (0x80000UL)

◆ TSW_MM2S_DMA_CFG_ENA64_SHIFT

#define TSW_MM2S_DMA_CFG_ENA64_SHIFT   (19U)

◆ TSW_MM2S_DMA_CFG_VER_GET

#define TSW_MM2S_DMA_CFG_VER_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CFG_VER_MASK) >> TSW_MM2S_DMA_CFG_VER_SHIFT)

◆ TSW_MM2S_DMA_CFG_VER_MASK

#define TSW_MM2S_DMA_CFG_VER_MASK   (0xFFFFU)

◆ TSW_MM2S_DMA_CFG_VER_SHIFT

#define TSW_MM2S_DMA_CFG_VER_SHIFT   (0U)

◆ TSW_MM2S_DMA_CR_IRQEN_GET

#define TSW_MM2S_DMA_CR_IRQEN_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CR_IRQEN_MASK) >> TSW_MM2S_DMA_CR_IRQEN_SHIFT)

◆ TSW_MM2S_DMA_CR_IRQEN_MASK

#define TSW_MM2S_DMA_CR_IRQEN_MASK   (0x8U)

◆ TSW_MM2S_DMA_CR_IRQEN_SET

#define TSW_MM2S_DMA_CR_IRQEN_SET (   x)    (((uint32_t)(x) << TSW_MM2S_DMA_CR_IRQEN_SHIFT) & TSW_MM2S_DMA_CR_IRQEN_MASK)

◆ TSW_MM2S_DMA_CR_IRQEN_SHIFT

#define TSW_MM2S_DMA_CR_IRQEN_SHIFT   (3U)

◆ TSW_MM2S_DMA_CR_MXLEN_GET

#define TSW_MM2S_DMA_CR_MXLEN_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CR_MXLEN_MASK) >> TSW_MM2S_DMA_CR_MXLEN_SHIFT)

◆ TSW_MM2S_DMA_CR_MXLEN_MASK

#define TSW_MM2S_DMA_CR_MXLEN_MASK   (0xFF000000UL)

◆ TSW_MM2S_DMA_CR_MXLEN_SET

#define TSW_MM2S_DMA_CR_MXLEN_SET (   x)    (((uint32_t)(x) << TSW_MM2S_DMA_CR_MXLEN_SHIFT) & TSW_MM2S_DMA_CR_MXLEN_MASK)

◆ TSW_MM2S_DMA_CR_MXLEN_SHIFT

#define TSW_MM2S_DMA_CR_MXLEN_SHIFT   (24U)

◆ TSW_MM2S_DMA_CR_RESET_GET

#define TSW_MM2S_DMA_CR_RESET_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CR_RESET_MASK) >> TSW_MM2S_DMA_CR_RESET_SHIFT)

◆ TSW_MM2S_DMA_CR_RESET_MASK

#define TSW_MM2S_DMA_CR_RESET_MASK   (0x4U)

◆ TSW_MM2S_DMA_CR_RESET_SET

#define TSW_MM2S_DMA_CR_RESET_SET (   x)    (((uint32_t)(x) << TSW_MM2S_DMA_CR_RESET_SHIFT) & TSW_MM2S_DMA_CR_RESET_MASK)

◆ TSW_MM2S_DMA_CR_RESET_SHIFT

#define TSW_MM2S_DMA_CR_RESET_SHIFT   (2U)

◆ TSW_MM2S_DMA_CR_RUN_GET

#define TSW_MM2S_DMA_CR_RUN_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CR_RUN_MASK) >> TSW_MM2S_DMA_CR_RUN_SHIFT)

◆ TSW_MM2S_DMA_CR_RUN_MASK

#define TSW_MM2S_DMA_CR_RUN_MASK   (0x1U)

◆ TSW_MM2S_DMA_CR_RUN_SET

#define TSW_MM2S_DMA_CR_RUN_SET (   x)    (((uint32_t)(x) << TSW_MM2S_DMA_CR_RUN_SHIFT) & TSW_MM2S_DMA_CR_RUN_MASK)

◆ TSW_MM2S_DMA_CR_RUN_SHIFT

#define TSW_MM2S_DMA_CR_RUN_SHIFT   (0U)

◆ TSW_MM2S_DMA_CR_SOE_GET

#define TSW_MM2S_DMA_CR_SOE_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_CR_SOE_MASK) >> TSW_MM2S_DMA_CR_SOE_SHIFT)

◆ TSW_MM2S_DMA_CR_SOE_MASK

#define TSW_MM2S_DMA_CR_SOE_MASK   (0x2U)

◆ TSW_MM2S_DMA_CR_SOE_SET

#define TSW_MM2S_DMA_CR_SOE_SET (   x)    (((uint32_t)(x) << TSW_MM2S_DMA_CR_SOE_SHIFT) & TSW_MM2S_DMA_CR_SOE_MASK)

◆ TSW_MM2S_DMA_CR_SOE_SHIFT

#define TSW_MM2S_DMA_CR_SOE_SHIFT   (1U)

◆ TSW_MM2S_DMA_FILL_CFILL_GET

#define TSW_MM2S_DMA_FILL_CFILL_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_FILL_CFILL_MASK) >> TSW_MM2S_DMA_FILL_CFILL_SHIFT)

◆ TSW_MM2S_DMA_FILL_CFILL_MASK

#define TSW_MM2S_DMA_FILL_CFILL_MASK   (0xFFFFU)

◆ TSW_MM2S_DMA_FILL_CFILL_SHIFT

#define TSW_MM2S_DMA_FILL_CFILL_SHIFT   (0U)

◆ TSW_MM2S_DMA_FILL_RFILL_GET

#define TSW_MM2S_DMA_FILL_RFILL_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_FILL_RFILL_MASK) >> TSW_MM2S_DMA_FILL_RFILL_SHIFT)

◆ TSW_MM2S_DMA_FILL_RFILL_MASK

#define TSW_MM2S_DMA_FILL_RFILL_MASK   (0xFFFF0000UL)

◆ TSW_MM2S_DMA_FILL_RFILL_SHIFT

#define TSW_MM2S_DMA_FILL_RFILL_SHIFT   (16U)

◆ TSW_MM2S_DMA_SR_BUSY_GET

#define TSW_MM2S_DMA_SR_BUSY_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_BUSY_MASK) >> TSW_MM2S_DMA_SR_BUSY_SHIFT)

◆ TSW_MM2S_DMA_SR_BUSY_MASK

#define TSW_MM2S_DMA_SR_BUSY_MASK   (0x2U)

◆ TSW_MM2S_DMA_SR_BUSY_SHIFT

#define TSW_MM2S_DMA_SR_BUSY_SHIFT   (1U)

◆ TSW_MM2S_DMA_SR_CBUFE_GET

#define TSW_MM2S_DMA_SR_CBUFE_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFE_MASK) >> TSW_MM2S_DMA_SR_CBUFE_SHIFT)

◆ TSW_MM2S_DMA_SR_CBUFE_MASK

#define TSW_MM2S_DMA_SR_CBUFE_MASK   (0x10U)

◆ TSW_MM2S_DMA_SR_CBUFE_SHIFT

#define TSW_MM2S_DMA_SR_CBUFE_SHIFT   (4U)

◆ TSW_MM2S_DMA_SR_CBUFF_GET

#define TSW_MM2S_DMA_SR_CBUFF_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFF_MASK) >> TSW_MM2S_DMA_SR_CBUFF_SHIFT)

◆ TSW_MM2S_DMA_SR_CBUFF_MASK

#define TSW_MM2S_DMA_SR_CBUFF_MASK   (0x20U)

◆ TSW_MM2S_DMA_SR_CBUFF_SHIFT

#define TSW_MM2S_DMA_SR_CBUFF_SHIFT   (5U)

◆ TSW_MM2S_DMA_SR_IRQ_GET

#define TSW_MM2S_DMA_SR_IRQ_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_IRQ_MASK) >> TSW_MM2S_DMA_SR_IRQ_SHIFT)

◆ TSW_MM2S_DMA_SR_IRQ_MASK

#define TSW_MM2S_DMA_SR_IRQ_MASK   (0x8U)

◆ TSW_MM2S_DMA_SR_IRQ_SET

#define TSW_MM2S_DMA_SR_IRQ_SET (   x)    (((uint32_t)(x) << TSW_MM2S_DMA_SR_IRQ_SHIFT) & TSW_MM2S_DMA_SR_IRQ_MASK)

◆ TSW_MM2S_DMA_SR_IRQ_SHIFT

#define TSW_MM2S_DMA_SR_IRQ_SHIFT   (3U)

◆ TSW_MM2S_DMA_SR_RBUFE_GET

#define TSW_MM2S_DMA_SR_RBUFE_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFE_MASK) >> TSW_MM2S_DMA_SR_RBUFE_SHIFT)

◆ TSW_MM2S_DMA_SR_RBUFE_MASK

#define TSW_MM2S_DMA_SR_RBUFE_MASK   (0x40U)

◆ TSW_MM2S_DMA_SR_RBUFE_SHIFT

#define TSW_MM2S_DMA_SR_RBUFE_SHIFT   (6U)

◆ TSW_MM2S_DMA_SR_RBUFF_GET

#define TSW_MM2S_DMA_SR_RBUFF_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFF_MASK) >> TSW_MM2S_DMA_SR_RBUFF_SHIFT)

◆ TSW_MM2S_DMA_SR_RBUFF_MASK

#define TSW_MM2S_DMA_SR_RBUFF_MASK   (0x80U)

◆ TSW_MM2S_DMA_SR_RBUFF_SHIFT

#define TSW_MM2S_DMA_SR_RBUFF_SHIFT   (7U)

◆ TSW_MM2S_DMA_SR_RSET_GET

#define TSW_MM2S_DMA_SR_RSET_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_RSET_MASK) >> TSW_MM2S_DMA_SR_RSET_SHIFT)

◆ TSW_MM2S_DMA_SR_RSET_MASK

#define TSW_MM2S_DMA_SR_RSET_MASK   (0x4U)

◆ TSW_MM2S_DMA_SR_RSET_SHIFT

#define TSW_MM2S_DMA_SR_RSET_SHIFT   (2U)

◆ TSW_MM2S_DMA_SR_STOP_GET

#define TSW_MM2S_DMA_SR_STOP_GET (   x)    (((uint32_t)(x) & TSW_MM2S_DMA_SR_STOP_MASK) >> TSW_MM2S_DMA_SR_STOP_SHIFT)

◆ TSW_MM2S_DMA_SR_STOP_MASK

#define TSW_MM2S_DMA_SR_STOP_MASK   (0x1U)

◆ TSW_MM2S_DMA_SR_STOP_SHIFT

#define TSW_MM2S_DMA_SR_STOP_SHIFT   (0U)

◆ TSW_MM2S_LENGTH_LENGTH_GET

#define TSW_MM2S_LENGTH_LENGTH_GET (   x)    (((uint32_t)(x) & TSW_MM2S_LENGTH_LENGTH_MASK) >> TSW_MM2S_LENGTH_LENGTH_SHIFT)

◆ TSW_MM2S_LENGTH_LENGTH_MASK

#define TSW_MM2S_LENGTH_LENGTH_MASK   (0xFFFFU)

◆ TSW_MM2S_LENGTH_LENGTH_SET

#define TSW_MM2S_LENGTH_LENGTH_SET (   x)    (((uint32_t)(x) << TSW_MM2S_LENGTH_LENGTH_SHIFT) & TSW_MM2S_LENGTH_LENGTH_MASK)

◆ TSW_MM2S_LENGTH_LENGTH_SHIFT

#define TSW_MM2S_LENGTH_LENGTH_SHIFT   (0U)

◆ TSW_MM2S_RESP_DECERR_GET

#define TSW_MM2S_RESP_DECERR_GET (   x)    (((uint32_t)(x) & TSW_MM2S_RESP_DECERR_MASK) >> TSW_MM2S_RESP_DECERR_SHIFT)

◆ TSW_MM2S_RESP_DECERR_MASK

#define TSW_MM2S_RESP_DECERR_MASK   (0x20000000UL)

◆ TSW_MM2S_RESP_DECERR_SHIFT

#define TSW_MM2S_RESP_DECERR_SHIFT   (29U)

◆ TSW_MM2S_RESP_ID_GET

#define TSW_MM2S_RESP_ID_GET (   x)    (((uint32_t)(x) & TSW_MM2S_RESP_ID_MASK) >> TSW_MM2S_RESP_ID_SHIFT)

◆ TSW_MM2S_RESP_ID_MASK

#define TSW_MM2S_RESP_ID_MASK   (0xF000000UL)

◆ TSW_MM2S_RESP_ID_SHIFT

#define TSW_MM2S_RESP_ID_SHIFT   (24U)

◆ TSW_MM2S_RESP_LAST_GET

#define TSW_MM2S_RESP_LAST_GET (   x)    (((uint32_t)(x) & TSW_MM2S_RESP_LAST_MASK) >> TSW_MM2S_RESP_LAST_SHIFT)

◆ TSW_MM2S_RESP_LAST_MASK

#define TSW_MM2S_RESP_LAST_MASK   (0x40000000UL)

◆ TSW_MM2S_RESP_LAST_SHIFT

#define TSW_MM2S_RESP_LAST_SHIFT   (30U)

◆ TSW_MM2S_RESP_LENGTH_GET

#define TSW_MM2S_RESP_LENGTH_GET (   x)    (((uint32_t)(x) & TSW_MM2S_RESP_LENGTH_MASK) >> TSW_MM2S_RESP_LENGTH_SHIFT)

◆ TSW_MM2S_RESP_LENGTH_MASK

#define TSW_MM2S_RESP_LENGTH_MASK   (0xFFFFU)

◆ TSW_MM2S_RESP_LENGTH_SHIFT

#define TSW_MM2S_RESP_LENGTH_SHIFT   (0U)

◆ TSW_MM2S_RESP_SLVERR_GET

#define TSW_MM2S_RESP_SLVERR_GET (   x)    (((uint32_t)(x) & TSW_MM2S_RESP_SLVERR_MASK) >> TSW_MM2S_RESP_SLVERR_SHIFT)

◆ TSW_MM2S_RESP_SLVERR_MASK

#define TSW_MM2S_RESP_SLVERR_MASK   (0x10000000UL)

◆ TSW_MM2S_RESP_SLVERR_SHIFT

#define TSW_MM2S_RESP_SLVERR_SHIFT   (28U)

◆ TSW_PTP_EVT_ATSHI_STSHI_GET

#define TSW_PTP_EVT_ATSHI_STSHI_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_ATSHI_STSHI_MASK) >> TSW_PTP_EVT_ATSHI_STSHI_SHIFT)

◆ TSW_PTP_EVT_ATSHI_STSHI_MASK

#define TSW_PTP_EVT_ATSHI_STSHI_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_ATSHI_STSHI_SHIFT

#define TSW_PTP_EVT_ATSHI_STSHI_SHIFT   (0U)

◆ TSW_PTP_EVT_ATSLO_STSLO_GET

#define TSW_PTP_EVT_ATSLO_STSLO_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_ATSLO_STSLO_MASK) >> TSW_PTP_EVT_ATSLO_STSLO_SHIFT)

◆ TSW_PTP_EVT_ATSLO_STSLO_MASK

#define TSW_PTP_EVT_ATSLO_STSLO_MASK   (0x7FFFFFFFUL)

◆ TSW_PTP_EVT_ATSLO_STSLO_SHIFT

#define TSW_PTP_EVT_ATSLO_STSLO_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_GET

#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT)

◆ TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK

#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SET

#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK)

◆ TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT

#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_GET

#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT)

◆ TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK

#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SET

#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK)

◆ TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT

#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_GET

#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT)

◆ TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK

#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SET

#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK)

◆ TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT

#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_GET

#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT)

◆ TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK

#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SET

#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK)

◆ TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT

#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_GET

#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT)

◆ TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK

#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SET

#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK)

◆ TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT

#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_GET

#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT)

◆ TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK

#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SET

#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK)

◆ TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT

#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_GET

#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT)

◆ TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK

#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SET

#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK)

◆ TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT

#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_GET

#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT)

◆ TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK

#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SET

#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK)

◆ TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT

#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD0_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK   (0xFU)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD1_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK   (0x700U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT   (8U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD2_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK   (0x70000UL)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT   (16U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD3_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK   (0x7000000UL)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT   (24U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_EN0_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK   (0x10U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_EN0_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT   (4U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE0_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK   (0x60U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT   (5U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE1_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK   (0x6000U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT   (13U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE2_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK   (0x600000UL)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT   (21U)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE3_GET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK   (0x60000000UL)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SET

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK)

◆ TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT

#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT   (29U)

◆ TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_GET

#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT)

◆ TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK

#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK   (0x2U)

◆ TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SET

#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK)

◆ TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT

#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT   (1U)

◆ TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_GET

#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT)

◆ TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK

#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK   (0x8U)

◆ TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SET

#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK)

◆ TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT

#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT   (3U)

◆ TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_GET

#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT)

◆ TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK

#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK   (0x4U)

◆ TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SET

#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK)

◆ TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT

#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT   (2U)

◆ TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_GET

#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT)

◆ TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK

#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK   (0x1U)

◆ TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SET

#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK)

◆ TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT

#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS_SEL_PPS0_SEL_GET

#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT)

◆ TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK

#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK   (0x1FU)

◆ TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SET

#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK)

◆ TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT

#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS_SEL_PPS1_SEL_GET

#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT)

◆ TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK

#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK   (0x1F00U)

◆ TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SET

#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK)

◆ TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT

#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT   (8U)

◆ TSW_PTP_EVT_PPS_SEL_PPS2_SEL_GET

#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT)

◆ TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK

#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK   (0x1F0000UL)

◆ TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SET

#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK)

◆ TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT

#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT   (16U)

◆ TSW_PTP_EVT_PPS_SEL_PPS3_SEL_GET

#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT)

◆ TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK

#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK   (0x1F000000UL)

◆ TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SET

#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK)

◆ TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT

#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT   (24U)

◆ TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_GET

#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK) >> TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT)

◆ TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK

#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT

#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT   (0U)

◆ TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_GET

#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK) >> TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT)

◆ TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK

#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT

#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_NS0_SCP_NS_GET

#define TSW_PTP_EVT_SCP_NS0_SCP_NS_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT)

◆ TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK

#define TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_PTP_EVT_SCP_NS0_SCP_NS_SET

#define TSW_PTP_EVT_SCP_NS0_SCP_NS_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK)

◆ TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT

#define TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_NS1_SCP_NS_GET

#define TSW_PTP_EVT_SCP_NS1_SCP_NS_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT)

◆ TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK

#define TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_PTP_EVT_SCP_NS1_SCP_NS_SET

#define TSW_PTP_EVT_SCP_NS1_SCP_NS_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK)

◆ TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT

#define TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_NS2_SCP_NS_GET

#define TSW_PTP_EVT_SCP_NS2_SCP_NS_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT)

◆ TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK

#define TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_PTP_EVT_SCP_NS2_SCP_NS_SET

#define TSW_PTP_EVT_SCP_NS2_SCP_NS_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK)

◆ TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT

#define TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_NS3_SCP_NS_GET

#define TSW_PTP_EVT_SCP_NS3_SCP_NS_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT)

◆ TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK

#define TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_PTP_EVT_SCP_NS3_SCP_NS_SET

#define TSW_PTP_EVT_SCP_NS3_SCP_NS_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK)

◆ TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT

#define TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_SEC0_SCP_SEC_GET

#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT)

◆ TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK

#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SET

#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK)

◆ TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT

#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_SEC1_SCP_SEC_GET

#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT)

◆ TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK

#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SET

#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK)

◆ TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT

#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_SEC2_SCP_SEC_GET

#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT)

◆ TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK

#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SET

#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK)

◆ TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT

#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT   (0U)

◆ TSW_PTP_EVT_SCP_SEC3_SCP_SEC_GET

#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT)

◆ TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK

#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SET

#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK)

◆ TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT

#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT   (0U)

◆ TSW_PTP_EVT_TMR_STS_ATPORT_GET

#define TSW_PTP_EVT_TMR_STS_ATPORT_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATPORT_MASK) >> TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_ATPORT_MASK

#define TSW_PTP_EVT_TMR_STS_ATPORT_MASK   (0xF0000UL)

◆ TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT

#define TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT   (16U)

◆ TSW_PTP_EVT_TMR_STS_ATSSTM_GET

#define TSW_PTP_EVT_TMR_STS_ATSSTM_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATSSTM_MASK) >> TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_ATSSTM_MASK

#define TSW_PTP_EVT_TMR_STS_ATSSTM_MASK   (0x1000000UL)

◆ TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT

#define TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT   (24U)

◆ TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_GET

#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK

#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK   (0x400U)

◆ TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT

#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT   (10U)

◆ TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_GET

#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK

#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK   (0x4U)

◆ TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT

#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT   (2U)

◆ TSW_PTP_EVT_TMR_STS_RD_CNT_GET

#define TSW_PTP_EVT_TMR_STS_RD_CNT_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_RD_CNT_MASK) >> TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_RD_CNT_MASK

#define TSW_PTP_EVT_TMR_STS_RD_CNT_MASK   (0x3E000000UL)

◆ TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT

#define TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT   (25U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK   (0x8U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT   (3U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK   (0x2U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT   (1U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK   (0x20U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT   (5U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK   (0x10U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT   (4U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK   (0x80U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT   (7U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK   (0x40U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT   (6U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK   (0x200U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT   (9U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_GET

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK   (0x100U)

◆ TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT

#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT   (8U)

◆ TSW_PTP_EVT_TS_CTL_ATSEN_GET

#define TSW_PTP_EVT_TS_CTL_ATSEN_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK) >> TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT)

◆ TSW_PTP_EVT_TS_CTL_ATSEN_MASK

#define TSW_PTP_EVT_TS_CTL_ATSEN_MASK   (0x1E000000UL)

◆ TSW_PTP_EVT_TS_CTL_ATSEN_SET

#define TSW_PTP_EVT_TS_CTL_ATSEN_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK)

◆ TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT

#define TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT   (25U)

◆ TSW_PTP_EVT_TS_CTL_ATSFC_GET

#define TSW_PTP_EVT_TS_CTL_ATSFC_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK) >> TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT)

◆ TSW_PTP_EVT_TS_CTL_ATSFC_MASK

#define TSW_PTP_EVT_TS_CTL_ATSFC_MASK   (0x1000000UL)

◆ TSW_PTP_EVT_TS_CTL_ATSFC_SET

#define TSW_PTP_EVT_TS_CTL_ATSFC_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK)

◆ TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT

#define TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT   (24U)

◆ TSW_PTP_EVT_TS_CTL_TSTIG_GET

#define TSW_PTP_EVT_TS_CTL_TSTIG_GET (   x)    (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK) >> TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT)

◆ TSW_PTP_EVT_TS_CTL_TSTIG_MASK

#define TSW_PTP_EVT_TS_CTL_TSTIG_MASK   (0x10U)

◆ TSW_PTP_EVT_TS_CTL_TSTIG_SET

#define TSW_PTP_EVT_TS_CTL_TSTIG_SET (   x)    (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK)

◆ TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT

#define TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT   (4U)

◆ TSW_QCI_CNT_CENTRAL_QCI_CNT0

#define TSW_QCI_CNT_CENTRAL_QCI_CNT0   (0UL)

◆ TSW_QCI_CNT_CENTRAL_QCI_CNT1

#define TSW_QCI_CNT_CENTRAL_QCI_CNT1   (1UL)

◆ TSW_QCI_CNT_CENTRAL_QCI_CNT2

#define TSW_QCI_CNT_CENTRAL_QCI_CNT2   (2UL)

◆ TSW_QCI_CNT_CENTRAL_QCI_CNT3

#define TSW_QCI_CNT_CENTRAL_QCI_CNT3   (3UL)

◆ TSW_QCI_CNT_CENTRAL_QCI_CNT4

#define TSW_QCI_CNT_CENTRAL_QCI_CNT4   (4UL)

◆ TSW_QCI_CNT_CENTRAL_QCI_CNT5

#define TSW_QCI_CNT_CENTRAL_QCI_CNT5   (5UL)

◆ TSW_QCI_CNT_VALUE_GET

#define TSW_QCI_CNT_VALUE_GET (   x)    (((uint32_t)(x) & TSW_QCI_CNT_VALUE_MASK) >> TSW_QCI_CNT_VALUE_SHIFT)

◆ TSW_QCI_CNT_VALUE_MASK

#define TSW_QCI_CNT_VALUE_MASK   (0xFFFFFFFFUL)

◆ TSW_QCI_CNT_VALUE_SHIFT

#define TSW_QCI_CNT_VALUE_SHIFT   (0U)

◆ TSW_RXFIFO_E1

#define TSW_RXFIFO_E1   (0UL)

◆ TSW_RXFIFO_P1

#define TSW_RXFIFO_P1   (1UL)

◆ TSW_S2MM_ADDRLO_ADDRLO_GET

#define TSW_S2MM_ADDRLO_ADDRLO_GET (   x)    (((uint32_t)(x) & TSW_S2MM_ADDRLO_ADDRLO_MASK) >> TSW_S2MM_ADDRLO_ADDRLO_SHIFT)

◆ TSW_S2MM_ADDRLO_ADDRLO_MASK

#define TSW_S2MM_ADDRLO_ADDRLO_MASK   (0xFFFFFFFFUL)

◆ TSW_S2MM_ADDRLO_ADDRLO_SET

#define TSW_S2MM_ADDRLO_ADDRLO_SET (   x)    (((uint32_t)(x) << TSW_S2MM_ADDRLO_ADDRLO_SHIFT) & TSW_S2MM_ADDRLO_ADDRLO_MASK)

◆ TSW_S2MM_ADDRLO_ADDRLO_SHIFT

#define TSW_S2MM_ADDRLO_ADDRLO_SHIFT   (0U)

◆ TSW_S2MM_CTRL_GO_GET

#define TSW_S2MM_CTRL_GO_GET (   x)    (((uint32_t)(x) & TSW_S2MM_CTRL_GO_MASK) >> TSW_S2MM_CTRL_GO_SHIFT)

◆ TSW_S2MM_CTRL_GO_MASK

#define TSW_S2MM_CTRL_GO_MASK   (0x80000000UL)

◆ TSW_S2MM_CTRL_GO_SET

#define TSW_S2MM_CTRL_GO_SET (   x)    (((uint32_t)(x) << TSW_S2MM_CTRL_GO_SHIFT) & TSW_S2MM_CTRL_GO_MASK)

◆ TSW_S2MM_CTRL_GO_SHIFT

#define TSW_S2MM_CTRL_GO_SHIFT   (31U)

◆ TSW_S2MM_CTRL_ID_GET

#define TSW_S2MM_CTRL_ID_GET (   x)    (((uint32_t)(x) & TSW_S2MM_CTRL_ID_MASK) >> TSW_S2MM_CTRL_ID_SHIFT)

◆ TSW_S2MM_CTRL_ID_MASK

#define TSW_S2MM_CTRL_ID_MASK   (0xFU)

◆ TSW_S2MM_CTRL_ID_SET

#define TSW_S2MM_CTRL_ID_SET (   x)    (((uint32_t)(x) << TSW_S2MM_CTRL_ID_SHIFT) & TSW_S2MM_CTRL_ID_MASK)

◆ TSW_S2MM_CTRL_ID_SHIFT

#define TSW_S2MM_CTRL_ID_SHIFT   (0U)

◆ TSW_S2MM_DMA_CFG_ASIZE_GET

#define TSW_S2MM_DMA_CFG_ASIZE_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ASIZE_MASK) >> TSW_S2MM_DMA_CFG_ASIZE_SHIFT)

◆ TSW_S2MM_DMA_CFG_ASIZE_MASK

#define TSW_S2MM_DMA_CFG_ASIZE_MASK   (0x70000UL)

◆ TSW_S2MM_DMA_CFG_ASIZE_SHIFT

#define TSW_S2MM_DMA_CFG_ASIZE_SHIFT   (16U)

◆ TSW_S2MM_DMA_CFG_CBUFD_GET

#define TSW_S2MM_DMA_CFG_CBUFD_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CFG_CBUFD_MASK) >> TSW_S2MM_DMA_CFG_CBUFD_SHIFT)

◆ TSW_S2MM_DMA_CFG_CBUFD_MASK

#define TSW_S2MM_DMA_CFG_CBUFD_MASK   (0xF00000UL)

◆ TSW_S2MM_DMA_CFG_CBUFD_SHIFT

#define TSW_S2MM_DMA_CFG_CBUFD_SHIFT   (20U)

◆ TSW_S2MM_DMA_CFG_DBUFD_GET

#define TSW_S2MM_DMA_CFG_DBUFD_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CFG_DBUFD_MASK) >> TSW_S2MM_DMA_CFG_DBUFD_SHIFT)

◆ TSW_S2MM_DMA_CFG_DBUFD_MASK

#define TSW_S2MM_DMA_CFG_DBUFD_MASK   (0xF000000UL)

◆ TSW_S2MM_DMA_CFG_DBUFD_SHIFT

#define TSW_S2MM_DMA_CFG_DBUFD_SHIFT   (24U)

◆ TSW_S2MM_DMA_CFG_ENA64_GET

#define TSW_S2MM_DMA_CFG_ENA64_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ENA64_MASK) >> TSW_S2MM_DMA_CFG_ENA64_SHIFT)

◆ TSW_S2MM_DMA_CFG_ENA64_MASK

#define TSW_S2MM_DMA_CFG_ENA64_MASK   (0x80000UL)

◆ TSW_S2MM_DMA_CFG_ENA64_SHIFT

#define TSW_S2MM_DMA_CFG_ENA64_SHIFT   (19U)

◆ TSW_S2MM_DMA_CFG_VER_GET

#define TSW_S2MM_DMA_CFG_VER_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CFG_VER_MASK) >> TSW_S2MM_DMA_CFG_VER_SHIFT)

◆ TSW_S2MM_DMA_CFG_VER_MASK

#define TSW_S2MM_DMA_CFG_VER_MASK   (0xFFFFU)

◆ TSW_S2MM_DMA_CFG_VER_SHIFT

#define TSW_S2MM_DMA_CFG_VER_SHIFT   (0U)

◆ TSW_S2MM_DMA_CR_IRQEN_GET

#define TSW_S2MM_DMA_CR_IRQEN_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CR_IRQEN_MASK) >> TSW_S2MM_DMA_CR_IRQEN_SHIFT)

◆ TSW_S2MM_DMA_CR_IRQEN_MASK

#define TSW_S2MM_DMA_CR_IRQEN_MASK   (0x8U)

◆ TSW_S2MM_DMA_CR_IRQEN_SET

#define TSW_S2MM_DMA_CR_IRQEN_SET (   x)    (((uint32_t)(x) << TSW_S2MM_DMA_CR_IRQEN_SHIFT) & TSW_S2MM_DMA_CR_IRQEN_MASK)

◆ TSW_S2MM_DMA_CR_IRQEN_SHIFT

#define TSW_S2MM_DMA_CR_IRQEN_SHIFT   (3U)

◆ TSW_S2MM_DMA_CR_MXLEN_GET

#define TSW_S2MM_DMA_CR_MXLEN_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CR_MXLEN_MASK) >> TSW_S2MM_DMA_CR_MXLEN_SHIFT)

◆ TSW_S2MM_DMA_CR_MXLEN_MASK

#define TSW_S2MM_DMA_CR_MXLEN_MASK   (0xFF000000UL)

◆ TSW_S2MM_DMA_CR_MXLEN_SET

#define TSW_S2MM_DMA_CR_MXLEN_SET (   x)    (((uint32_t)(x) << TSW_S2MM_DMA_CR_MXLEN_SHIFT) & TSW_S2MM_DMA_CR_MXLEN_MASK)

◆ TSW_S2MM_DMA_CR_MXLEN_SHIFT

#define TSW_S2MM_DMA_CR_MXLEN_SHIFT   (24U)

◆ TSW_S2MM_DMA_CR_RESET_GET

#define TSW_S2MM_DMA_CR_RESET_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CR_RESET_MASK) >> TSW_S2MM_DMA_CR_RESET_SHIFT)

◆ TSW_S2MM_DMA_CR_RESET_MASK

#define TSW_S2MM_DMA_CR_RESET_MASK   (0x4U)

◆ TSW_S2MM_DMA_CR_RESET_SET

#define TSW_S2MM_DMA_CR_RESET_SET (   x)    (((uint32_t)(x) << TSW_S2MM_DMA_CR_RESET_SHIFT) & TSW_S2MM_DMA_CR_RESET_MASK)

◆ TSW_S2MM_DMA_CR_RESET_SHIFT

#define TSW_S2MM_DMA_CR_RESET_SHIFT   (2U)

◆ TSW_S2MM_DMA_CR_RUN_GET

#define TSW_S2MM_DMA_CR_RUN_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CR_RUN_MASK) >> TSW_S2MM_DMA_CR_RUN_SHIFT)

◆ TSW_S2MM_DMA_CR_RUN_MASK

#define TSW_S2MM_DMA_CR_RUN_MASK   (0x1U)

◆ TSW_S2MM_DMA_CR_RUN_SET

#define TSW_S2MM_DMA_CR_RUN_SET (   x)    (((uint32_t)(x) << TSW_S2MM_DMA_CR_RUN_SHIFT) & TSW_S2MM_DMA_CR_RUN_MASK)

◆ TSW_S2MM_DMA_CR_RUN_SHIFT

#define TSW_S2MM_DMA_CR_RUN_SHIFT   (0U)

◆ TSW_S2MM_DMA_CR_SOE_GET

#define TSW_S2MM_DMA_CR_SOE_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_CR_SOE_MASK) >> TSW_S2MM_DMA_CR_SOE_SHIFT)

◆ TSW_S2MM_DMA_CR_SOE_MASK

#define TSW_S2MM_DMA_CR_SOE_MASK   (0x2U)

◆ TSW_S2MM_DMA_CR_SOE_SET

#define TSW_S2MM_DMA_CR_SOE_SET (   x)    (((uint32_t)(x) << TSW_S2MM_DMA_CR_SOE_SHIFT) & TSW_S2MM_DMA_CR_SOE_MASK)

◆ TSW_S2MM_DMA_CR_SOE_SHIFT

#define TSW_S2MM_DMA_CR_SOE_SHIFT   (1U)

◆ TSW_S2MM_DMA_FILL_CFILL_GET

#define TSW_S2MM_DMA_FILL_CFILL_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_FILL_CFILL_MASK) >> TSW_S2MM_DMA_FILL_CFILL_SHIFT)

◆ TSW_S2MM_DMA_FILL_CFILL_MASK

#define TSW_S2MM_DMA_FILL_CFILL_MASK   (0xFFFFU)

◆ TSW_S2MM_DMA_FILL_CFILL_SHIFT

#define TSW_S2MM_DMA_FILL_CFILL_SHIFT   (0U)

◆ TSW_S2MM_DMA_FILL_RFILL_GET

#define TSW_S2MM_DMA_FILL_RFILL_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_FILL_RFILL_MASK) >> TSW_S2MM_DMA_FILL_RFILL_SHIFT)

◆ TSW_S2MM_DMA_FILL_RFILL_MASK

#define TSW_S2MM_DMA_FILL_RFILL_MASK   (0xFFFF0000UL)

◆ TSW_S2MM_DMA_FILL_RFILL_SHIFT

#define TSW_S2MM_DMA_FILL_RFILL_SHIFT   (16U)

◆ TSW_S2MM_DMA_SR_BUSY_GET

#define TSW_S2MM_DMA_SR_BUSY_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_BUSY_MASK) >> TSW_S2MM_DMA_SR_BUSY_SHIFT)

◆ TSW_S2MM_DMA_SR_BUSY_MASK

#define TSW_S2MM_DMA_SR_BUSY_MASK   (0x2U)

◆ TSW_S2MM_DMA_SR_BUSY_SHIFT

#define TSW_S2MM_DMA_SR_BUSY_SHIFT   (1U)

◆ TSW_S2MM_DMA_SR_CBUFE_GET

#define TSW_S2MM_DMA_SR_CBUFE_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFE_MASK) >> TSW_S2MM_DMA_SR_CBUFE_SHIFT)

◆ TSW_S2MM_DMA_SR_CBUFE_MASK

#define TSW_S2MM_DMA_SR_CBUFE_MASK   (0x10U)

◆ TSW_S2MM_DMA_SR_CBUFE_SHIFT

#define TSW_S2MM_DMA_SR_CBUFE_SHIFT   (4U)

◆ TSW_S2MM_DMA_SR_CBUFF_GET

#define TSW_S2MM_DMA_SR_CBUFF_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFF_MASK) >> TSW_S2MM_DMA_SR_CBUFF_SHIFT)

◆ TSW_S2MM_DMA_SR_CBUFF_MASK

#define TSW_S2MM_DMA_SR_CBUFF_MASK   (0x20U)

◆ TSW_S2MM_DMA_SR_CBUFF_SHIFT

#define TSW_S2MM_DMA_SR_CBUFF_SHIFT   (5U)

◆ TSW_S2MM_DMA_SR_IRQ_GET

#define TSW_S2MM_DMA_SR_IRQ_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_IRQ_MASK) >> TSW_S2MM_DMA_SR_IRQ_SHIFT)

◆ TSW_S2MM_DMA_SR_IRQ_MASK

#define TSW_S2MM_DMA_SR_IRQ_MASK   (0x8U)

◆ TSW_S2MM_DMA_SR_IRQ_SET

#define TSW_S2MM_DMA_SR_IRQ_SET (   x)    (((uint32_t)(x) << TSW_S2MM_DMA_SR_IRQ_SHIFT) & TSW_S2MM_DMA_SR_IRQ_MASK)

◆ TSW_S2MM_DMA_SR_IRQ_SHIFT

#define TSW_S2MM_DMA_SR_IRQ_SHIFT   (3U)

◆ TSW_S2MM_DMA_SR_RBUFE_GET

#define TSW_S2MM_DMA_SR_RBUFE_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFE_MASK) >> TSW_S2MM_DMA_SR_RBUFE_SHIFT)

◆ TSW_S2MM_DMA_SR_RBUFE_MASK

#define TSW_S2MM_DMA_SR_RBUFE_MASK   (0x40U)

◆ TSW_S2MM_DMA_SR_RBUFE_SHIFT

#define TSW_S2MM_DMA_SR_RBUFE_SHIFT   (6U)

◆ TSW_S2MM_DMA_SR_RBUFF_GET

#define TSW_S2MM_DMA_SR_RBUFF_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFF_MASK) >> TSW_S2MM_DMA_SR_RBUFF_SHIFT)

◆ TSW_S2MM_DMA_SR_RBUFF_MASK

#define TSW_S2MM_DMA_SR_RBUFF_MASK   (0x80U)

◆ TSW_S2MM_DMA_SR_RBUFF_SHIFT

#define TSW_S2MM_DMA_SR_RBUFF_SHIFT   (7U)

◆ TSW_S2MM_DMA_SR_RSET_GET

#define TSW_S2MM_DMA_SR_RSET_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_RSET_MASK) >> TSW_S2MM_DMA_SR_RSET_SHIFT)

◆ TSW_S2MM_DMA_SR_RSET_MASK

#define TSW_S2MM_DMA_SR_RSET_MASK   (0x4U)

◆ TSW_S2MM_DMA_SR_RSET_SHIFT

#define TSW_S2MM_DMA_SR_RSET_SHIFT   (2U)

◆ TSW_S2MM_DMA_SR_STOP_GET

#define TSW_S2MM_DMA_SR_STOP_GET (   x)    (((uint32_t)(x) & TSW_S2MM_DMA_SR_STOP_MASK) >> TSW_S2MM_DMA_SR_STOP_SHIFT)

◆ TSW_S2MM_DMA_SR_STOP_MASK

#define TSW_S2MM_DMA_SR_STOP_MASK   (0x1U)

◆ TSW_S2MM_DMA_SR_STOP_SHIFT

#define TSW_S2MM_DMA_SR_STOP_SHIFT   (0U)

◆ TSW_S2MM_LENGTH_LENGTH_GET

#define TSW_S2MM_LENGTH_LENGTH_GET (   x)    (((uint32_t)(x) & TSW_S2MM_LENGTH_LENGTH_MASK) >> TSW_S2MM_LENGTH_LENGTH_SHIFT)

◆ TSW_S2MM_LENGTH_LENGTH_MASK

#define TSW_S2MM_LENGTH_LENGTH_MASK   (0xFFFFU)

◆ TSW_S2MM_LENGTH_LENGTH_SET

#define TSW_S2MM_LENGTH_LENGTH_SET (   x)    (((uint32_t)(x) << TSW_S2MM_LENGTH_LENGTH_SHIFT) & TSW_S2MM_LENGTH_LENGTH_MASK)

◆ TSW_S2MM_LENGTH_LENGTH_SHIFT

#define TSW_S2MM_LENGTH_LENGTH_SHIFT   (0U)

◆ TSW_S2MM_RESP_DECERR_GET

#define TSW_S2MM_RESP_DECERR_GET (   x)    (((uint32_t)(x) & TSW_S2MM_RESP_DECERR_MASK) >> TSW_S2MM_RESP_DECERR_SHIFT)

◆ TSW_S2MM_RESP_DECERR_MASK

#define TSW_S2MM_RESP_DECERR_MASK   (0x20000000UL)

◆ TSW_S2MM_RESP_DECERR_SHIFT

#define TSW_S2MM_RESP_DECERR_SHIFT   (29U)

◆ TSW_S2MM_RESP_ID_GET

#define TSW_S2MM_RESP_ID_GET (   x)    (((uint32_t)(x) & TSW_S2MM_RESP_ID_MASK) >> TSW_S2MM_RESP_ID_SHIFT)

◆ TSW_S2MM_RESP_ID_MASK

#define TSW_S2MM_RESP_ID_MASK   (0xF000000UL)

◆ TSW_S2MM_RESP_ID_SHIFT

#define TSW_S2MM_RESP_ID_SHIFT   (24U)

◆ TSW_S2MM_RESP_LAST_GET

#define TSW_S2MM_RESP_LAST_GET (   x)    (((uint32_t)(x) & TSW_S2MM_RESP_LAST_MASK) >> TSW_S2MM_RESP_LAST_SHIFT)

◆ TSW_S2MM_RESP_LAST_MASK

#define TSW_S2MM_RESP_LAST_MASK   (0x40000000UL)

◆ TSW_S2MM_RESP_LAST_SHIFT

#define TSW_S2MM_RESP_LAST_SHIFT   (30U)

◆ TSW_S2MM_RESP_LENGTH_GET

#define TSW_S2MM_RESP_LENGTH_GET (   x)    (((uint32_t)(x) & TSW_S2MM_RESP_LENGTH_MASK) >> TSW_S2MM_RESP_LENGTH_SHIFT)

◆ TSW_S2MM_RESP_LENGTH_MASK

#define TSW_S2MM_RESP_LENGTH_MASK   (0xFFFFU)

◆ TSW_S2MM_RESP_LENGTH_SHIFT

#define TSW_S2MM_RESP_LENGTH_SHIFT   (0U)

◆ TSW_S2MM_RESP_SLVERR_GET

#define TSW_S2MM_RESP_SLVERR_GET (   x)    (((uint32_t)(x) & TSW_S2MM_RESP_SLVERR_MASK) >> TSW_S2MM_RESP_SLVERR_SHIFT)

◆ TSW_S2MM_RESP_SLVERR_MASK

#define TSW_S2MM_RESP_SLVERR_MASK   (0x10000000UL)

◆ TSW_S2MM_RESP_SLVERR_SHIFT

#define TSW_S2MM_RESP_SLVERR_SHIFT   (28U)

◆ TSW_SHACL_ENT0

#define TSW_SHACL_ENT0   (0UL)

◆ TSW_SHACL_ENT1

#define TSW_SHACL_ENT1   (1UL)

◆ TSW_SHACL_ENT10

#define TSW_SHACL_ENT10   (10UL)

◆ TSW_SHACL_ENT100

#define TSW_SHACL_ENT100   (100UL)

◆ TSW_SHACL_ENT101

#define TSW_SHACL_ENT101   (101UL)

◆ TSW_SHACL_ENT102

#define TSW_SHACL_ENT102   (102UL)

◆ TSW_SHACL_ENT103

#define TSW_SHACL_ENT103   (103UL)

◆ TSW_SHACL_ENT104

#define TSW_SHACL_ENT104   (104UL)

◆ TSW_SHACL_ENT105

#define TSW_SHACL_ENT105   (105UL)

◆ TSW_SHACL_ENT106

#define TSW_SHACL_ENT106   (106UL)

◆ TSW_SHACL_ENT107

#define TSW_SHACL_ENT107   (107UL)

◆ TSW_SHACL_ENT108

#define TSW_SHACL_ENT108   (108UL)

◆ TSW_SHACL_ENT109

#define TSW_SHACL_ENT109   (109UL)

◆ TSW_SHACL_ENT11

#define TSW_SHACL_ENT11   (11UL)

◆ TSW_SHACL_ENT110

#define TSW_SHACL_ENT110   (110UL)

◆ TSW_SHACL_ENT111

#define TSW_SHACL_ENT111   (111UL)

◆ TSW_SHACL_ENT112

#define TSW_SHACL_ENT112   (112UL)

◆ TSW_SHACL_ENT113

#define TSW_SHACL_ENT113   (113UL)

◆ TSW_SHACL_ENT114

#define TSW_SHACL_ENT114   (114UL)

◆ TSW_SHACL_ENT115

#define TSW_SHACL_ENT115   (115UL)

◆ TSW_SHACL_ENT116

#define TSW_SHACL_ENT116   (116UL)

◆ TSW_SHACL_ENT117

#define TSW_SHACL_ENT117   (117UL)

◆ TSW_SHACL_ENT118

#define TSW_SHACL_ENT118   (118UL)

◆ TSW_SHACL_ENT119

#define TSW_SHACL_ENT119   (119UL)

◆ TSW_SHACL_ENT12

#define TSW_SHACL_ENT12   (12UL)

◆ TSW_SHACL_ENT120

#define TSW_SHACL_ENT120   (120UL)

◆ TSW_SHACL_ENT121

#define TSW_SHACL_ENT121   (121UL)

◆ TSW_SHACL_ENT122

#define TSW_SHACL_ENT122   (122UL)

◆ TSW_SHACL_ENT123

#define TSW_SHACL_ENT123   (123UL)

◆ TSW_SHACL_ENT124

#define TSW_SHACL_ENT124   (124UL)

◆ TSW_SHACL_ENT125

#define TSW_SHACL_ENT125   (125UL)

◆ TSW_SHACL_ENT126

#define TSW_SHACL_ENT126   (126UL)

◆ TSW_SHACL_ENT127

#define TSW_SHACL_ENT127   (127UL)

◆ TSW_SHACL_ENT128

#define TSW_SHACL_ENT128   (128UL)

◆ TSW_SHACL_ENT129

#define TSW_SHACL_ENT129   (129UL)

◆ TSW_SHACL_ENT13

#define TSW_SHACL_ENT13   (13UL)

◆ TSW_SHACL_ENT130

#define TSW_SHACL_ENT130   (130UL)

◆ TSW_SHACL_ENT131

#define TSW_SHACL_ENT131   (131UL)

◆ TSW_SHACL_ENT132

#define TSW_SHACL_ENT132   (132UL)

◆ TSW_SHACL_ENT133

#define TSW_SHACL_ENT133   (133UL)

◆ TSW_SHACL_ENT134

#define TSW_SHACL_ENT134   (134UL)

◆ TSW_SHACL_ENT135

#define TSW_SHACL_ENT135   (135UL)

◆ TSW_SHACL_ENT136

#define TSW_SHACL_ENT136   (136UL)

◆ TSW_SHACL_ENT137

#define TSW_SHACL_ENT137   (137UL)

◆ TSW_SHACL_ENT138

#define TSW_SHACL_ENT138   (138UL)

◆ TSW_SHACL_ENT139

#define TSW_SHACL_ENT139   (139UL)

◆ TSW_SHACL_ENT14

#define TSW_SHACL_ENT14   (14UL)

◆ TSW_SHACL_ENT140

#define TSW_SHACL_ENT140   (140UL)

◆ TSW_SHACL_ENT141

#define TSW_SHACL_ENT141   (141UL)

◆ TSW_SHACL_ENT142

#define TSW_SHACL_ENT142   (142UL)

◆ TSW_SHACL_ENT143

#define TSW_SHACL_ENT143   (143UL)

◆ TSW_SHACL_ENT144

#define TSW_SHACL_ENT144   (144UL)

◆ TSW_SHACL_ENT145

#define TSW_SHACL_ENT145   (145UL)

◆ TSW_SHACL_ENT146

#define TSW_SHACL_ENT146   (146UL)

◆ TSW_SHACL_ENT147

#define TSW_SHACL_ENT147   (147UL)

◆ TSW_SHACL_ENT148

#define TSW_SHACL_ENT148   (148UL)

◆ TSW_SHACL_ENT149

#define TSW_SHACL_ENT149   (149UL)

◆ TSW_SHACL_ENT15

#define TSW_SHACL_ENT15   (15UL)

◆ TSW_SHACL_ENT150

#define TSW_SHACL_ENT150   (150UL)

◆ TSW_SHACL_ENT151

#define TSW_SHACL_ENT151   (151UL)

◆ TSW_SHACL_ENT152

#define TSW_SHACL_ENT152   (152UL)

◆ TSW_SHACL_ENT153

#define TSW_SHACL_ENT153   (153UL)

◆ TSW_SHACL_ENT154

#define TSW_SHACL_ENT154   (154UL)

◆ TSW_SHACL_ENT155

#define TSW_SHACL_ENT155   (155UL)

◆ TSW_SHACL_ENT156

#define TSW_SHACL_ENT156   (156UL)

◆ TSW_SHACL_ENT157

#define TSW_SHACL_ENT157   (157UL)

◆ TSW_SHACL_ENT158

#define TSW_SHACL_ENT158   (158UL)

◆ TSW_SHACL_ENT159

#define TSW_SHACL_ENT159   (159UL)

◆ TSW_SHACL_ENT16

#define TSW_SHACL_ENT16   (16UL)

◆ TSW_SHACL_ENT160

#define TSW_SHACL_ENT160   (160UL)

◆ TSW_SHACL_ENT161

#define TSW_SHACL_ENT161   (161UL)

◆ TSW_SHACL_ENT162

#define TSW_SHACL_ENT162   (162UL)

◆ TSW_SHACL_ENT163

#define TSW_SHACL_ENT163   (163UL)

◆ TSW_SHACL_ENT164

#define TSW_SHACL_ENT164   (164UL)

◆ TSW_SHACL_ENT165

#define TSW_SHACL_ENT165   (165UL)

◆ TSW_SHACL_ENT166

#define TSW_SHACL_ENT166   (166UL)

◆ TSW_SHACL_ENT167

#define TSW_SHACL_ENT167   (167UL)

◆ TSW_SHACL_ENT168

#define TSW_SHACL_ENT168   (168UL)

◆ TSW_SHACL_ENT169

#define TSW_SHACL_ENT169   (169UL)

◆ TSW_SHACL_ENT17

#define TSW_SHACL_ENT17   (17UL)

◆ TSW_SHACL_ENT170

#define TSW_SHACL_ENT170   (170UL)

◆ TSW_SHACL_ENT171

#define TSW_SHACL_ENT171   (171UL)

◆ TSW_SHACL_ENT172

#define TSW_SHACL_ENT172   (172UL)

◆ TSW_SHACL_ENT173

#define TSW_SHACL_ENT173   (173UL)

◆ TSW_SHACL_ENT174

#define TSW_SHACL_ENT174   (174UL)

◆ TSW_SHACL_ENT175

#define TSW_SHACL_ENT175   (175UL)

◆ TSW_SHACL_ENT176

#define TSW_SHACL_ENT176   (176UL)

◆ TSW_SHACL_ENT177

#define TSW_SHACL_ENT177   (177UL)

◆ TSW_SHACL_ENT178

#define TSW_SHACL_ENT178   (178UL)

◆ TSW_SHACL_ENT179

#define TSW_SHACL_ENT179   (179UL)

◆ TSW_SHACL_ENT18

#define TSW_SHACL_ENT18   (18UL)

◆ TSW_SHACL_ENT180

#define TSW_SHACL_ENT180   (180UL)

◆ TSW_SHACL_ENT181

#define TSW_SHACL_ENT181   (181UL)

◆ TSW_SHACL_ENT182

#define TSW_SHACL_ENT182   (182UL)

◆ TSW_SHACL_ENT183

#define TSW_SHACL_ENT183   (183UL)

◆ TSW_SHACL_ENT184

#define TSW_SHACL_ENT184   (184UL)

◆ TSW_SHACL_ENT185

#define TSW_SHACL_ENT185   (185UL)

◆ TSW_SHACL_ENT186

#define TSW_SHACL_ENT186   (186UL)

◆ TSW_SHACL_ENT187

#define TSW_SHACL_ENT187   (187UL)

◆ TSW_SHACL_ENT188

#define TSW_SHACL_ENT188   (188UL)

◆ TSW_SHACL_ENT189

#define TSW_SHACL_ENT189   (189UL)

◆ TSW_SHACL_ENT19

#define TSW_SHACL_ENT19   (19UL)

◆ TSW_SHACL_ENT190

#define TSW_SHACL_ENT190   (190UL)

◆ TSW_SHACL_ENT191

#define TSW_SHACL_ENT191   (191UL)

◆ TSW_SHACL_ENT192

#define TSW_SHACL_ENT192   (192UL)

◆ TSW_SHACL_ENT193

#define TSW_SHACL_ENT193   (193UL)

◆ TSW_SHACL_ENT194

#define TSW_SHACL_ENT194   (194UL)

◆ TSW_SHACL_ENT195

#define TSW_SHACL_ENT195   (195UL)

◆ TSW_SHACL_ENT196

#define TSW_SHACL_ENT196   (196UL)

◆ TSW_SHACL_ENT197

#define TSW_SHACL_ENT197   (197UL)

◆ TSW_SHACL_ENT198

#define TSW_SHACL_ENT198   (198UL)

◆ TSW_SHACL_ENT199

#define TSW_SHACL_ENT199   (199UL)

◆ TSW_SHACL_ENT2

#define TSW_SHACL_ENT2   (2UL)

◆ TSW_SHACL_ENT20

#define TSW_SHACL_ENT20   (20UL)

◆ TSW_SHACL_ENT200

#define TSW_SHACL_ENT200   (200UL)

◆ TSW_SHACL_ENT201

#define TSW_SHACL_ENT201   (201UL)

◆ TSW_SHACL_ENT202

#define TSW_SHACL_ENT202   (202UL)

◆ TSW_SHACL_ENT203

#define TSW_SHACL_ENT203   (203UL)

◆ TSW_SHACL_ENT204

#define TSW_SHACL_ENT204   (204UL)

◆ TSW_SHACL_ENT205

#define TSW_SHACL_ENT205   (205UL)

◆ TSW_SHACL_ENT206

#define TSW_SHACL_ENT206   (206UL)

◆ TSW_SHACL_ENT207

#define TSW_SHACL_ENT207   (207UL)

◆ TSW_SHACL_ENT208

#define TSW_SHACL_ENT208   (208UL)

◆ TSW_SHACL_ENT209

#define TSW_SHACL_ENT209   (209UL)

◆ TSW_SHACL_ENT21

#define TSW_SHACL_ENT21   (21UL)

◆ TSW_SHACL_ENT210

#define TSW_SHACL_ENT210   (210UL)

◆ TSW_SHACL_ENT211

#define TSW_SHACL_ENT211   (211UL)

◆ TSW_SHACL_ENT212

#define TSW_SHACL_ENT212   (212UL)

◆ TSW_SHACL_ENT213

#define TSW_SHACL_ENT213   (213UL)

◆ TSW_SHACL_ENT214

#define TSW_SHACL_ENT214   (214UL)

◆ TSW_SHACL_ENT215

#define TSW_SHACL_ENT215   (215UL)

◆ TSW_SHACL_ENT216

#define TSW_SHACL_ENT216   (216UL)

◆ TSW_SHACL_ENT217

#define TSW_SHACL_ENT217   (217UL)

◆ TSW_SHACL_ENT218

#define TSW_SHACL_ENT218   (218UL)

◆ TSW_SHACL_ENT219

#define TSW_SHACL_ENT219   (219UL)

◆ TSW_SHACL_ENT22

#define TSW_SHACL_ENT22   (22UL)

◆ TSW_SHACL_ENT220

#define TSW_SHACL_ENT220   (220UL)

◆ TSW_SHACL_ENT221

#define TSW_SHACL_ENT221   (221UL)

◆ TSW_SHACL_ENT222

#define TSW_SHACL_ENT222   (222UL)

◆ TSW_SHACL_ENT223

#define TSW_SHACL_ENT223   (223UL)

◆ TSW_SHACL_ENT224

#define TSW_SHACL_ENT224   (224UL)

◆ TSW_SHACL_ENT225

#define TSW_SHACL_ENT225   (225UL)

◆ TSW_SHACL_ENT226

#define TSW_SHACL_ENT226   (226UL)

◆ TSW_SHACL_ENT227

#define TSW_SHACL_ENT227   (227UL)

◆ TSW_SHACL_ENT228

#define TSW_SHACL_ENT228   (228UL)

◆ TSW_SHACL_ENT229

#define TSW_SHACL_ENT229   (229UL)

◆ TSW_SHACL_ENT23

#define TSW_SHACL_ENT23   (23UL)

◆ TSW_SHACL_ENT230

#define TSW_SHACL_ENT230   (230UL)

◆ TSW_SHACL_ENT231

#define TSW_SHACL_ENT231   (231UL)

◆ TSW_SHACL_ENT232

#define TSW_SHACL_ENT232   (232UL)

◆ TSW_SHACL_ENT233

#define TSW_SHACL_ENT233   (233UL)

◆ TSW_SHACL_ENT234

#define TSW_SHACL_ENT234   (234UL)

◆ TSW_SHACL_ENT235

#define TSW_SHACL_ENT235   (235UL)

◆ TSW_SHACL_ENT236

#define TSW_SHACL_ENT236   (236UL)

◆ TSW_SHACL_ENT237

#define TSW_SHACL_ENT237   (237UL)

◆ TSW_SHACL_ENT238

#define TSW_SHACL_ENT238   (238UL)

◆ TSW_SHACL_ENT239

#define TSW_SHACL_ENT239   (239UL)

◆ TSW_SHACL_ENT24

#define TSW_SHACL_ENT24   (24UL)

◆ TSW_SHACL_ENT240

#define TSW_SHACL_ENT240   (240UL)

◆ TSW_SHACL_ENT241

#define TSW_SHACL_ENT241   (241UL)

◆ TSW_SHACL_ENT242

#define TSW_SHACL_ENT242   (242UL)

◆ TSW_SHACL_ENT243

#define TSW_SHACL_ENT243   (243UL)

◆ TSW_SHACL_ENT244

#define TSW_SHACL_ENT244   (244UL)

◆ TSW_SHACL_ENT245

#define TSW_SHACL_ENT245   (245UL)

◆ TSW_SHACL_ENT246

#define TSW_SHACL_ENT246   (246UL)

◆ TSW_SHACL_ENT247

#define TSW_SHACL_ENT247   (247UL)

◆ TSW_SHACL_ENT248

#define TSW_SHACL_ENT248   (248UL)

◆ TSW_SHACL_ENT249

#define TSW_SHACL_ENT249   (249UL)

◆ TSW_SHACL_ENT25

#define TSW_SHACL_ENT25   (25UL)

◆ TSW_SHACL_ENT250

#define TSW_SHACL_ENT250   (250UL)

◆ TSW_SHACL_ENT251

#define TSW_SHACL_ENT251   (251UL)

◆ TSW_SHACL_ENT252

#define TSW_SHACL_ENT252   (252UL)

◆ TSW_SHACL_ENT253

#define TSW_SHACL_ENT253   (253UL)

◆ TSW_SHACL_ENT254

#define TSW_SHACL_ENT254   (254UL)

◆ TSW_SHACL_ENT255

#define TSW_SHACL_ENT255   (255UL)

◆ TSW_SHACL_ENT26

#define TSW_SHACL_ENT26   (26UL)

◆ TSW_SHACL_ENT27

#define TSW_SHACL_ENT27   (27UL)

◆ TSW_SHACL_ENT28

#define TSW_SHACL_ENT28   (28UL)

◆ TSW_SHACL_ENT29

#define TSW_SHACL_ENT29   (29UL)

◆ TSW_SHACL_ENT3

#define TSW_SHACL_ENT3   (3UL)

◆ TSW_SHACL_ENT30

#define TSW_SHACL_ENT30   (30UL)

◆ TSW_SHACL_ENT31

#define TSW_SHACL_ENT31   (31UL)

◆ TSW_SHACL_ENT32

#define TSW_SHACL_ENT32   (32UL)

◆ TSW_SHACL_ENT33

#define TSW_SHACL_ENT33   (33UL)

◆ TSW_SHACL_ENT34

#define TSW_SHACL_ENT34   (34UL)

◆ TSW_SHACL_ENT35

#define TSW_SHACL_ENT35   (35UL)

◆ TSW_SHACL_ENT36

#define TSW_SHACL_ENT36   (36UL)

◆ TSW_SHACL_ENT37

#define TSW_SHACL_ENT37   (37UL)

◆ TSW_SHACL_ENT38

#define TSW_SHACL_ENT38   (38UL)

◆ TSW_SHACL_ENT39

#define TSW_SHACL_ENT39   (39UL)

◆ TSW_SHACL_ENT4

#define TSW_SHACL_ENT4   (4UL)

◆ TSW_SHACL_ENT40

#define TSW_SHACL_ENT40   (40UL)

◆ TSW_SHACL_ENT41

#define TSW_SHACL_ENT41   (41UL)

◆ TSW_SHACL_ENT42

#define TSW_SHACL_ENT42   (42UL)

◆ TSW_SHACL_ENT43

#define TSW_SHACL_ENT43   (43UL)

◆ TSW_SHACL_ENT44

#define TSW_SHACL_ENT44   (44UL)

◆ TSW_SHACL_ENT45

#define TSW_SHACL_ENT45   (45UL)

◆ TSW_SHACL_ENT46

#define TSW_SHACL_ENT46   (46UL)

◆ TSW_SHACL_ENT47

#define TSW_SHACL_ENT47   (47UL)

◆ TSW_SHACL_ENT48

#define TSW_SHACL_ENT48   (48UL)

◆ TSW_SHACL_ENT49

#define TSW_SHACL_ENT49   (49UL)

◆ TSW_SHACL_ENT5

#define TSW_SHACL_ENT5   (5UL)

◆ TSW_SHACL_ENT50

#define TSW_SHACL_ENT50   (50UL)

◆ TSW_SHACL_ENT51

#define TSW_SHACL_ENT51   (51UL)

◆ TSW_SHACL_ENT52

#define TSW_SHACL_ENT52   (52UL)

◆ TSW_SHACL_ENT53

#define TSW_SHACL_ENT53   (53UL)

◆ TSW_SHACL_ENT54

#define TSW_SHACL_ENT54   (54UL)

◆ TSW_SHACL_ENT55

#define TSW_SHACL_ENT55   (55UL)

◆ TSW_SHACL_ENT56

#define TSW_SHACL_ENT56   (56UL)

◆ TSW_SHACL_ENT57

#define TSW_SHACL_ENT57   (57UL)

◆ TSW_SHACL_ENT58

#define TSW_SHACL_ENT58   (58UL)

◆ TSW_SHACL_ENT59

#define TSW_SHACL_ENT59   (59UL)

◆ TSW_SHACL_ENT6

#define TSW_SHACL_ENT6   (6UL)

◆ TSW_SHACL_ENT60

#define TSW_SHACL_ENT60   (60UL)

◆ TSW_SHACL_ENT61

#define TSW_SHACL_ENT61   (61UL)

◆ TSW_SHACL_ENT62

#define TSW_SHACL_ENT62   (62UL)

◆ TSW_SHACL_ENT63

#define TSW_SHACL_ENT63   (63UL)

◆ TSW_SHACL_ENT64

#define TSW_SHACL_ENT64   (64UL)

◆ TSW_SHACL_ENT65

#define TSW_SHACL_ENT65   (65UL)

◆ TSW_SHACL_ENT66

#define TSW_SHACL_ENT66   (66UL)

◆ TSW_SHACL_ENT67

#define TSW_SHACL_ENT67   (67UL)

◆ TSW_SHACL_ENT68

#define TSW_SHACL_ENT68   (68UL)

◆ TSW_SHACL_ENT69

#define TSW_SHACL_ENT69   (69UL)

◆ TSW_SHACL_ENT7

#define TSW_SHACL_ENT7   (7UL)

◆ TSW_SHACL_ENT70

#define TSW_SHACL_ENT70   (70UL)

◆ TSW_SHACL_ENT71

#define TSW_SHACL_ENT71   (71UL)

◆ TSW_SHACL_ENT72

#define TSW_SHACL_ENT72   (72UL)

◆ TSW_SHACL_ENT73

#define TSW_SHACL_ENT73   (73UL)

◆ TSW_SHACL_ENT74

#define TSW_SHACL_ENT74   (74UL)

◆ TSW_SHACL_ENT75

#define TSW_SHACL_ENT75   (75UL)

◆ TSW_SHACL_ENT76

#define TSW_SHACL_ENT76   (76UL)

◆ TSW_SHACL_ENT77

#define TSW_SHACL_ENT77   (77UL)

◆ TSW_SHACL_ENT78

#define TSW_SHACL_ENT78   (78UL)

◆ TSW_SHACL_ENT79

#define TSW_SHACL_ENT79   (79UL)

◆ TSW_SHACL_ENT8

#define TSW_SHACL_ENT8   (8UL)

◆ TSW_SHACL_ENT80

#define TSW_SHACL_ENT80   (80UL)

◆ TSW_SHACL_ENT81

#define TSW_SHACL_ENT81   (81UL)

◆ TSW_SHACL_ENT82

#define TSW_SHACL_ENT82   (82UL)

◆ TSW_SHACL_ENT83

#define TSW_SHACL_ENT83   (83UL)

◆ TSW_SHACL_ENT84

#define TSW_SHACL_ENT84   (84UL)

◆ TSW_SHACL_ENT85

#define TSW_SHACL_ENT85   (85UL)

◆ TSW_SHACL_ENT86

#define TSW_SHACL_ENT86   (86UL)

◆ TSW_SHACL_ENT87

#define TSW_SHACL_ENT87   (87UL)

◆ TSW_SHACL_ENT88

#define TSW_SHACL_ENT88   (88UL)

◆ TSW_SHACL_ENT89

#define TSW_SHACL_ENT89   (89UL)

◆ TSW_SHACL_ENT9

#define TSW_SHACL_ENT9   (9UL)

◆ TSW_SHACL_ENT90

#define TSW_SHACL_ENT90   (90UL)

◆ TSW_SHACL_ENT91

#define TSW_SHACL_ENT91   (91UL)

◆ TSW_SHACL_ENT92

#define TSW_SHACL_ENT92   (92UL)

◆ TSW_SHACL_ENT93

#define TSW_SHACL_ENT93   (93UL)

◆ TSW_SHACL_ENT94

#define TSW_SHACL_ENT94   (94UL)

◆ TSW_SHACL_ENT95

#define TSW_SHACL_ENT95   (95UL)

◆ TSW_SHACL_ENT96

#define TSW_SHACL_ENT96   (96UL)

◆ TSW_SHACL_ENT97

#define TSW_SHACL_ENT97   (97UL)

◆ TSW_SHACL_ENT98

#define TSW_SHACL_ENT98   (98UL)

◆ TSW_SHACL_ENT99

#define TSW_SHACL_ENT99   (99UL)

◆ TSW_SOFT_RST_CTRL_DMA0_RST_GET

#define TSW_SOFT_RST_CTRL_DMA0_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK) >> TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_DMA0_RST_MASK

#define TSW_SOFT_RST_CTRL_DMA0_RST_MASK   (0x100U)

◆ TSW_SOFT_RST_CTRL_DMA0_RST_SET

#define TSW_SOFT_RST_CTRL_DMA0_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK)

◆ TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT

#define TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT   (8U)

◆ TSW_SOFT_RST_CTRL_PORT1_RX_RST_GET

#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK

#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK   (0x2U)

◆ TSW_SOFT_RST_CTRL_PORT1_RX_RST_SET

#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT   (1U)

◆ TSW_SOFT_RST_CTRL_PORT1_TX_RST_GET

#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK

#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK   (0x1U)

◆ TSW_SOFT_RST_CTRL_PORT1_TX_RST_SET

#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT   (0U)

◆ TSW_SOFT_RST_CTRL_PORT2_RX_RST_GET

#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK

#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK   (0x8U)

◆ TSW_SOFT_RST_CTRL_PORT2_RX_RST_SET

#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT   (3U)

◆ TSW_SOFT_RST_CTRL_PORT2_TX_RST_GET

#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK

#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK   (0x4U)

◆ TSW_SOFT_RST_CTRL_PORT2_TX_RST_SET

#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT   (2U)

◆ TSW_SOFT_RST_CTRL_PORT3_RX_RST_GET

#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK

#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK   (0x20U)

◆ TSW_SOFT_RST_CTRL_PORT3_RX_RST_SET

#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT   (5U)

◆ TSW_SOFT_RST_CTRL_PORT3_TX_RST_GET

#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK

#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK   (0x10U)

◆ TSW_SOFT_RST_CTRL_PORT3_TX_RST_SET

#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT   (4U)

◆ TSW_SOFT_RST_CTRL_PTP_EVT_RST_GET

#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK) >> TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK

#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK   (0x400U)

◆ TSW_SOFT_RST_CTRL_PTP_EVT_RST_SET

#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK)

◆ TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT

#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT   (10U)

◆ TSW_SOFT_RST_CTRL_TSN_CORE_RST_GET

#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_GET (   x)    (((uint32_t)(x) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK) >> TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT)

◆ TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK

#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK   (0x800U)

◆ TSW_SOFT_RST_CTRL_TSN_CORE_RST_SET

#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SET (   x)    (((uint32_t)(x) << TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK)

◆ TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT

#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT   (11U)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_GET

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK   (0x7000000UL)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SET

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT   (24U)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_GET

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK   (0xFFU)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SET

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT   (0U)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_GET

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT   (0U)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_GET

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT

#define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT   (0U)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD0

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD0   (0UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD1

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD1   (1UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD10

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD10   (10UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD11

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD11   (11UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD12

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD12   (12UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD13

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD13   (13UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD14

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD14   (14UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD15

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD15   (15UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD16

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD16   (16UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD17

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD17   (17UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD18

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD18   (18UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD19

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD19   (19UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD2

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD2   (2UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD20

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD20   (20UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD21

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD21   (21UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD22

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD22   (22UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD23

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD23   (23UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD24

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD24   (24UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD25

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD25   (25UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD26

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD26   (26UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD27

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD27   (27UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD28

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD28   (28UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD29

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD29   (29UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD3

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD3   (3UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD30

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD30   (30UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD31

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD31   (31UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD32

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD32   (32UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD33

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD33   (33UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD34

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD34   (34UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD35

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD35   (35UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD36

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD36   (36UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD37

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD37   (37UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD38

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD38   (38UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD39

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD39   (39UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD4

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD4   (4UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD40

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD40   (40UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD41

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD41   (41UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD42

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD42   (42UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD43

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD43   (43UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD44

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD44   (44UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD45

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD45   (45UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD46

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD46   (46UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD47

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD47   (47UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD48

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD48   (48UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD49

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD49   (49UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD5

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD5   (5UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD50

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD50   (50UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD51

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD51   (51UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD52

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD52   (52UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD53

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD53   (53UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD54

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD54   (54UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD55

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD55   (55UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD56

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD56   (56UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD57

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD57   (57UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD58

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD58   (58UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD59

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD59   (59UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD6

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD6   (6UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD7

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD7   (7UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD8

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD8   (8UL)

◆ TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD9

#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD9   (9UL)

◆ TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_GET

#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK) >> TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT)

◆ TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK

#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SET

#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK)

◆ TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT

#define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT   (0U)

◆ TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET

#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT)

◆ TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK

#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK   (0x3F00U)

◆ TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET

#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK)

◆ TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT

#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT   (8U)

◆ TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET

#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT)

◆ TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK

#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK   (0x3FU)

◆ TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET

#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK)

◆ TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT

#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT   (0U)

◆ TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET

#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) >> TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT)

◆ TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK

#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK   (0x300000UL)

◆ TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET

#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK)

◆ TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT

#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT   (20U)

◆ TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET

#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) >> TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT)

◆ TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK

#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK   (0x80000UL)

◆ TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET

#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK)

◆ TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT

#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT   (19U)

◆ TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET

#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT)

◆ TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK

#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK   (0xE000U)

◆ TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET

#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK)

◆ TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT

#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT   (13U)

◆ TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET

#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT)

◆ TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK

#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK   (0x400U)

◆ TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET

#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK)

◆ TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT

#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT   (10U)

◆ TSW_TSNPORT_IDSEL_FRACT_GET

#define TSW_TSNPORT_IDSEL_FRACT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_IDSEL_FRACT_MASK) >> TSW_TSNPORT_IDSEL_FRACT_SHIFT)

◆ TSW_TSNPORT_IDSEL_FRACT_MASK

#define TSW_TSNPORT_IDSEL_FRACT_MASK   (0xFFFFU)

◆ TSW_TSNPORT_IDSEL_FRACT_SET

#define TSW_TSNPORT_IDSEL_FRACT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_IDSEL_FRACT_SHIFT) & TSW_TSNPORT_IDSEL_FRACT_MASK)

◆ TSW_TSNPORT_IDSEL_FRACT_SHIFT

#define TSW_TSNPORT_IDSEL_FRACT_SHIFT   (0U)

◆ TSW_TSNPORT_IDSEL_INT_GET

#define TSW_TSNPORT_IDSEL_INT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_IDSEL_INT_MASK) >> TSW_TSNPORT_IDSEL_INT_SHIFT)

◆ TSW_TSNPORT_IDSEL_INT_MASK

#define TSW_TSNPORT_IDSEL_INT_MASK   (0xF0000UL)

◆ TSW_TSNPORT_IDSEL_INT_SET

#define TSW_TSNPORT_IDSEL_INT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_IDSEL_INT_SHIFT) & TSW_TSNPORT_IDSEL_INT_MASK)

◆ TSW_TSNPORT_IDSEL_INT_SHIFT

#define TSW_TSNPORT_IDSEL_INT_SHIFT   (16U)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL0

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL0   (0UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL04

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL04   (4UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL1

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL1   (1UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL2

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL2   (2UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL3

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL3   (3UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL5

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL5   (5UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL6

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL6   (6UL)

◆ TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL7

#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL7   (7UL)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK   (0x8U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT   (3U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK   (0x800U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT   (11U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK   (0x1U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK   (0x100U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT   (8U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK   (0x200U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT   (9U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK   (0x4U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT   (2U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_GET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK   (0x400U)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SET

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK)

◆ TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT

#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT   (10U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK   (0x700U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT   (8U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK   (0x2000U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT   (13U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK   (0x1F000000UL)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT   (24U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK   (0x10U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT   (4U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK   (0x8U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT   (3U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK   (0x80000UL)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT   (19U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK   (0x800U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT   (11U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK   (0x60U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT   (5U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK   (0x100000UL)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT   (20U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK   (0x1000U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT   (12U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK   (0x1U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK   (0x2U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT   (1U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK   (0x10000UL)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT   (16U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK   (0x4U)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK)

◆ TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT   (2U)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_GET

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK   (0xFFFFU)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SET

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK   (0x10000UL)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT   (16U)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_GET

#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK

#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SET

#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK)

◆ TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT

#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK   (0x100U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT   (8U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK   (0xFFU)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK   (0x8000U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT   (15U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK   (0x100U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT   (8U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK   (0xC0000000UL)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT   (30U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK   (0x1F000000UL)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT   (24U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK   (0x1U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK   (0x1F0000UL)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT   (16U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK   (0xFFFFU)

◆ TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_GET

#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK

#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK   (0xFFFFU)

◆ TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SET

#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK)

◆ TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT

#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_GET

#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK

#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT

#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_GET

#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK

#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT

#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_GET

#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK

#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT

#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_GET

#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK

#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT

#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT   (0U)

◆ TSW_TSNPORT_MAC_MAC_VER_VER_H_GET

#define TSW_TSNPORT_MAC_MAC_VER_VER_H_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK

#define TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK   (0xFFFF0000UL)

◆ TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT

#define TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT   (16U)

◆ TSW_TSNPORT_MAC_MAC_VER_VER_L_GET

#define TSW_TSNPORT_MAC_MAC_VER_VER_L_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT)

◆ TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK

#define TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK   (0xFFFFU)

◆ TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT

#define TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT

#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT   (0U)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT

#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT   (0U)

◆ TSW_TSNPORT_MXSDU_SDU_GET

#define TSW_TSNPORT_MXSDU_SDU_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MXSDU_SDU_MASK) >> TSW_TSNPORT_MXSDU_SDU_SHIFT)

◆ TSW_TSNPORT_MXSDU_SDU_MASK

#define TSW_TSNPORT_MXSDU_SDU_MASK   (0xFFFFU)

◆ TSW_TSNPORT_MXSDU_SDU_SET

#define TSW_TSNPORT_MXSDU_SDU_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MXSDU_SDU_SHIFT) & TSW_TSNPORT_MXSDU_SDU_MASK)

◆ TSW_TSNPORT_MXSDU_SDU_SHIFT

#define TSW_TSNPORT_MXSDU_SDU_SHIFT   (0U)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU0

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU0   (0UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU1

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU1   (1UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU2

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU2   (2UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU3

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU3   (3UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU4

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU4   (4UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU5

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU5   (5UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU6

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU6   (6UL)

◆ TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU7

#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU7   (7UL)

◆ TSW_TSNPORT_MXTK_TICK_GET

#define TSW_TSNPORT_MXTK_TICK_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_MXTK_TICK_MASK) >> TSW_TSNPORT_MXTK_TICK_SHIFT)

◆ TSW_TSNPORT_MXTK_TICK_MASK

#define TSW_TSNPORT_MXTK_TICK_MASK   (0xFFFFFFUL)

◆ TSW_TSNPORT_MXTK_TICK_SET

#define TSW_TSNPORT_MXTK_TICK_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_MXTK_TICK_SHIFT) & TSW_TSNPORT_MXTK_TICK_MASK)

◆ TSW_TSNPORT_MXTK_TICK_SHIFT

#define TSW_TSNPORT_MXTK_TICK_SHIFT   (0U)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK0

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK0   (0UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK1

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK1   (1UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK2

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK2   (2UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK3

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK3   (3UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK4

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK4   (4UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK5

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK5   (5UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK6

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK6   (6UL)

◆ TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK7

#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK7   (7UL)

◆ TSW_TSNPORT_PORT1

#define TSW_TSNPORT_PORT1   (0UL)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_GET

#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK

#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK   (0xFF0U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SET

#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT   (4U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_GET

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK   (0x1U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SET

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT   (0U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_GET

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK   (0x100000UL)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SET

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT   (20U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_GET

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK   (0x70000UL)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SET

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT

#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT   (16U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_GET

#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK

#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK   (0x7000U)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SET

#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK)

◆ TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT

#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT   (12U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_GET

#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK

#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK   (0xFF0U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SET

#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT   (4U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_GET

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK   (0x1U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SET

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT   (0U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_GET

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK   (0x100000UL)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SET

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT   (20U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_GET

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK   (0x70000UL)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SET

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT

#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT   (16U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_GET

#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK

#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK   (0x7000U)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SET

#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK)

◆ TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT

#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT   (12U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_GET

#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK

#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK   (0xFF0U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SET

#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT   (4U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_GET

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK   (0x1U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SET

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT   (0U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_GET

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK   (0x100000UL)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SET

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT   (20U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_GET

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK   (0x70000UL)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SET

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT

#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT   (16U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_GET

#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK

#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK   (0x7000U)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SET

#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK)

◆ TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT

#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT   (12U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_GET

#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK

#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK   (0xFF0U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SET

#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT   (4U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_GET

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK   (0x1U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SET

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT   (0U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_GET

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK   (0x100000UL)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SET

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT   (20U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_GET

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK   (0x70000UL)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SET

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT

#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT   (16U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_GET

#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK

#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK   (0x7000U)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SET

#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK)

◆ TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT

#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT   (12U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_GET

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK   (0x2U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT   (1U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_GET

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK   (0x1U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SET

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT   (0U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_GET

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK   (0x4U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT   (2U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_GET

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK   (0xFF00U)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SET

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK)

◆ TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT

#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT   (8U)

◆ TSW_TSNPORT_PORT2

#define TSW_TSNPORT_PORT2   (1UL)

◆ TSW_TSNPORT_PORT3

#define TSW_TSNPORT_PORT3   (2UL)

◆ TSW_TSNPORT_RTC_ALARM_NS_AL_NS_GET

#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK) >> TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT)

◆ TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK

#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SET

#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK)

◆ TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT

#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_ALARM_SH_AL_SH_GET

#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK) >> TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT)

◆ TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK

#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK   (0xFFFFU)

◆ TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SET

#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK)

◆ TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT

#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_ALARM_SL_AL_SL_GET

#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK) >> TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT)

◆ TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK

#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SET

#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK)

◆ TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT

#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_CR_ALIE_GET

#define TSW_TSNPORT_RTC_CR_ALIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_ALIE_MASK) >> TSW_TSNPORT_RTC_CR_ALIE_SHIFT)

◆ TSW_TSNPORT_RTC_CR_ALIE_MASK

#define TSW_TSNPORT_RTC_CR_ALIE_MASK   (0x2U)

◆ TSW_TSNPORT_RTC_CR_ALIE_SET

#define TSW_TSNPORT_RTC_CR_ALIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_ALIE_SHIFT) & TSW_TSNPORT_RTC_CR_ALIE_MASK)

◆ TSW_TSNPORT_RTC_CR_ALIE_SHIFT

#define TSW_TSNPORT_RTC_CR_ALIE_SHIFT   (1U)

◆ TSW_TSNPORT_RTC_CR_TAEN_GET

#define TSW_TSNPORT_RTC_CR_TAEN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAEN_MASK) >> TSW_TSNPORT_RTC_CR_TAEN_SHIFT)

◆ TSW_TSNPORT_RTC_CR_TAEN_MASK

#define TSW_TSNPORT_RTC_CR_TAEN_MASK   (0x4U)

◆ TSW_TSNPORT_RTC_CR_TAEN_SET

#define TSW_TSNPORT_RTC_CR_TAEN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAEN_SHIFT) & TSW_TSNPORT_RTC_CR_TAEN_MASK)

◆ TSW_TSNPORT_RTC_CR_TAEN_SHIFT

#define TSW_TSNPORT_RTC_CR_TAEN_SHIFT   (2U)

◆ TSW_TSNPORT_RTC_CR_TAIE_GET

#define TSW_TSNPORT_RTC_CR_TAIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAIE_MASK) >> TSW_TSNPORT_RTC_CR_TAIE_SHIFT)

◆ TSW_TSNPORT_RTC_CR_TAIE_MASK

#define TSW_TSNPORT_RTC_CR_TAIE_MASK   (0x8U)

◆ TSW_TSNPORT_RTC_CR_TAIE_SET

#define TSW_TSNPORT_RTC_CR_TAIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAIE_SHIFT) & TSW_TSNPORT_RTC_CR_TAIE_MASK)

◆ TSW_TSNPORT_RTC_CR_TAIE_SHIFT

#define TSW_TSNPORT_RTC_CR_TAIE_SHIFT   (3U)

◆ TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_GET

#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT)

◆ TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK

#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SET

#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK)

◆ TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT

#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_GET

#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT)

◆ TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK

#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT

#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_GET

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK   (0xFFFFFFUL)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SET

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_GET

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SET

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK)

◆ TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT

#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT   (24U)

◆ TSW_TSNPORT_RTC_OFS_CH_SEXT_GET

#define TSW_TSNPORT_RTC_OFS_CH_SEXT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT)

◆ TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK

#define TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT

#define TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT   (24U)

◆ TSW_TSNPORT_RTC_OFS_CH_SFNS_GET

#define TSW_TSNPORT_RTC_OFS_CH_SFNS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT)

◆ TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK

#define TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK   (0xFFFFFFUL)

◆ TSW_TSNPORT_RTC_OFS_CH_SFNS_SET

#define TSW_TSNPORT_RTC_OFS_CH_SFNS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK)

◆ TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT

#define TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_OFS_NS_OFS_NS_GET

#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK) >> TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT)

◆ TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK

#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK   (0x3FFFFFFFUL)

◆ TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SET

#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK)

◆ TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT

#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_OFS_SH_OFS_SH_GET

#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK) >> TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT)

◆ TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK

#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK   (0xFFFFU)

◆ TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SET

#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK)

◆ TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT

#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_OFS_SL_OFS_SL_GET

#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK) >> TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT)

◆ TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK

#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SET

#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK)

◆ TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT

#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT   (0U)

◆ TSW_TSNPORT_RTC_SR_ALIS_GET

#define TSW_TSNPORT_RTC_SR_ALIS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_ALIS_MASK) >> TSW_TSNPORT_RTC_SR_ALIS_SHIFT)

◆ TSW_TSNPORT_RTC_SR_ALIS_MASK

#define TSW_TSNPORT_RTC_SR_ALIS_MASK   (0x2U)

◆ TSW_TSNPORT_RTC_SR_ALIS_SHIFT

#define TSW_TSNPORT_RTC_SR_ALIS_SHIFT   (1U)

◆ TSW_TSNPORT_RTC_SR_TAIS_GET

#define TSW_TSNPORT_RTC_SR_TAIS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_TAIS_MASK) >> TSW_TSNPORT_RTC_SR_TAIS_SHIFT)

◆ TSW_TSNPORT_RTC_SR_TAIS_MASK

#define TSW_TSNPORT_RTC_SR_TAIS_MASK   (0x8U)

◆ TSW_TSNPORT_RTC_SR_TAIS_SET

#define TSW_TSNPORT_RTC_SR_TAIS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_SR_TAIS_SHIFT) & TSW_TSNPORT_RTC_SR_TAIS_MASK)

◆ TSW_TSNPORT_RTC_SR_TAIS_SHIFT

#define TSW_TSNPORT_RTC_SR_TAIS_SHIFT   (3U)

◆ TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_GET

#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK) >> TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT)

◆ TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK

#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK   (0x1FFFFFFFUL)

◆ TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SET

#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK)

◆ TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT

#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT   (0U)

◆ TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_GET

#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK) >> TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT)

◆ TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK

#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT

#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT   (0U)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD0

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD0   (0UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD1

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD1   (1UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD10

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD10   (10UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD11

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD11   (11UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD12

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD12   (12UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD13

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD13   (13UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD14

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD14   (14UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD15

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD15   (15UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD16

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD16   (16UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD17

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD17   (17UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD18

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD18   (18UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD19

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD19   (19UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD2

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD2   (2UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD20

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD20   (20UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD21

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD21   (21UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD22

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD22   (22UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD23

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD23   (23UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD24

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD24   (24UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD25

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD25   (25UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD26

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD26   (26UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD27

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD27   (27UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD28

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD28   (28UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD29

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD29   (29UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD3

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD3   (3UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD30

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD30   (30UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD31

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD31   (31UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD32

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD32   (32UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD33

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD33   (33UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD34

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD34   (34UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD35

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD35   (35UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD36

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD36   (36UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD37

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD37   (37UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD38

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD38   (38UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD39

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD39   (39UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD4

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD4   (4UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD40

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD40   (40UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD41

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD41   (41UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD42

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD42   (42UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD43

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD43   (43UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD44

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD44   (44UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD45

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD45   (45UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD46

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD46   (46UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD47

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD47   (47UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD48

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD48   (48UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD49

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD49   (49UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD5

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD5   (5UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD50

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD50   (50UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD51

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD51   (51UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD52

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD52   (52UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD53

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD53   (53UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD54

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD54   (54UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD55

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD55   (55UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD56

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD56   (56UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD57

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD57   (57UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD58

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD58   (58UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD59

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD59   (59UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD6

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD6   (6UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD7

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD7   (7UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD8

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD8   (8UL)

◆ TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD9

#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD9   (9UL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK   (0x2U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT   (1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK   (0x1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK   (0x8U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT   (3U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK   (0x4U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT   (2U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK   (0x10U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT   (4U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK   (0x40U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT   (6U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK   (0x20U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT   (5U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK   (0x2U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT   (1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK   (0x4U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT   (2U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK   (0x200U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT   (9U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK   (0x1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK   (0x8U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT   (3U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK   (0x100U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT   (8U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK   (0x400U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT   (10U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK   (0x800U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT   (11U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK   (0x7FU)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK   (0x1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK   (0x40U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT   (6U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK   (0x20U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT   (5U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK   (0x10U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT   (4U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK   (0xFFFF0000UL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT   (16U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK   (0x8U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT   (3U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK   (0x100U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT   (8U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK   (0x4U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT   (2U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK   (0x200U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT   (9U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK   (0x1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK   (0x2U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT   (1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK   (0xFF0000UL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT   (16U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK   (0xFFFFU)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT   (24U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK   (0x1U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT   (0U)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_GET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK   (0x1FFFFFFUL)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SET

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK)

◆ TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT

#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT   (0U)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_GET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT   (0U)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_GET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK   (0x300U)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT   (8U)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_GET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK   (0xFFU)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT   (0U)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_GET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK   (0x3FC00UL)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SET

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK)

◆ TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT   (10U)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_GET

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SET

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT   (24U)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_GET

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK   (0xFFFFFFUL)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SET

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK)

◆ TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT

#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT   (0U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK   (0x1U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SET

#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT   (0U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK   (0x7FU)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT   (0U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK   (0xFFFF0000UL)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT   (16U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK   (0xFF00U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT   (8U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK   (0x1U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SET

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT   (0U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK   (0x4U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SET

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT   (2U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_GET

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK   (0x2U)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SET

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK)

◆ TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT

#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT   (1U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK   (0x1U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT   (0U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK   (0x2U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT   (1U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK   (0x10000UL)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT   (16U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK   (0x1000U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT   (12U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK   (0x20000UL)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT   (17U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK   (0xE000U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT   (13U)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_GET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK   (0xFFFU)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SET

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK)

◆ TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT

#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_GET

#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT)

◆ TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK

#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK   (0x80000000UL)

◆ TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SET

#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK)

◆ TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT

#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT   (31U)

◆ TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_GET

#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT)

◆ TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK

#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK   (0x1U)

◆ TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SET

#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK)

◆ TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT

#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_GET

#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT)

◆ TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK

#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK   (0x40000000UL)

◆ TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SET

#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK)

◆ TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT

#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT   (30U)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_GET

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK   (0x4000000UL)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT   (26U)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_GET

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK   (0x20000000UL)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT   (29U)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_GET

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK   (0x80000000UL)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT   (31U)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_GET

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK   (0x40000000UL)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT   (30U)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_GET

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK   (0x10000000UL)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT   (28U)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_GET

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK   (0x8000000UL)

◆ TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT

#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT   (27U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_GET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK   (0x4U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT   (2U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_GET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK   (0x1U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_GET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK   (0x18U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT   (3U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_GET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK   (0x2U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT   (1U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_GET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK   (0xE0U)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SET

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT   (5U)

◆ TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_GET

#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK

#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SET

#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_HLD_GET

#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK

#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK   (0x1U)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_GET

#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK

#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK   (0x4U)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT   (2U)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_VOK_GET

#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK

#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK   (0x2U)

◆ TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT   (1U)

◆ TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_GET

#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK) >> TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT)

◆ TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK

#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SET

#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK)

◆ TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT

#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_GET

#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT)

◆ TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK

#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK   (0xFFFFU)

◆ TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT

#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_GET

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SET

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_GET

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SET

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK)

◆ TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT

#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_GET

#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK

#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT

#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_GET

#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK

#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT

#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_GET

#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK

#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK   (0xE0000000UL)

◆ TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT

#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT   (29U)

◆ TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_GET

#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK

#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK   (0x7U)

◆ TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT

#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_GET

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK   (0x80000000UL)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SET

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT   (31U)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_GET

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT

#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_TXUF_COUNTER_GET

#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT)

◆ TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK

#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SET

#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK)

◆ TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT

#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_EP_VER_VER_HI_GET

#define TSW_TSNPORT_TSN_EP_VER_VER_HI_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT)

◆ TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK

#define TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT

#define TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT   (24U)

◆ TSW_TSNPORT_TSN_EP_VER_VER_LO_GET

#define TSW_TSNPORT_TSN_EP_VER_VER_LO_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT)

◆ TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK

#define TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK   (0xFF0000UL)

◆ TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT

#define TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT   (16U)

◆ TSW_TSNPORT_TSN_EP_VER_VER_REV_GET

#define TSW_TSNPORT_TSN_EP_VER_VER_REV_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT)

◆ TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK

#define TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT

#define TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_GET

#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK) >> TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK

#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SET

#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_GET

#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK) >> TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK

#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK   (0xFFFFU)

◆ TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SET

#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_GET

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_GET

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT   (24U)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_GET

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK   (0xFF0000UL)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT   (16U)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_GET

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK   (0xFF00U)

◆ TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT   (8U)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_GET

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK   (0x1U)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SET

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_GET

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK   (0x2U)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SET

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT   (1U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK   (0x3FFFFFFFUL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK   (0x3FFFFFFFUL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK   (0xFF000000UL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT   (24U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK   (0x2U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT   (1U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK   (0x4U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT   (2U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK   (0x8U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT   (3U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK   (0x1U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK   (0xFF0000UL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT   (16U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK   (0xFF00U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT   (8U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK   (0xFF0000UL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT   (16U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_GET

#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK

#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK   (0x3FFFFFFFUL)

◆ TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_GET

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT   (0U)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_GET

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK   (0xFF00U)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SET

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK)

◆ TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT   (8U)

◆ TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_GET

#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT)

◆ TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK

#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK   (0xFFU)

◆ TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT

#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_CR_RXIE_GET

#define TSW_TSNPORT_TSYN_CR_RXIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_RXIE_MASK) >> TSW_TSNPORT_TSYN_CR_RXIE_SHIFT)

◆ TSW_TSNPORT_TSYN_CR_RXIE_MASK

#define TSW_TSNPORT_TSYN_CR_RXIE_MASK   (0x2U)

◆ TSW_TSNPORT_TSYN_CR_RXIE_SET

#define TSW_TSNPORT_TSYN_CR_RXIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_RXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_RXIE_MASK)

◆ TSW_TSNPORT_TSYN_CR_RXIE_SHIFT

#define TSW_TSNPORT_TSYN_CR_RXIE_SHIFT   (1U)

◆ TSW_TSNPORT_TSYN_CR_TMR_ALD_GET

#define TSW_TSNPORT_TSYN_CR_TMR_ALD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT)

◆ TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK

#define TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK   (0x1F0000UL)

◆ TSW_TSNPORT_TSYN_CR_TMR_ALD_SET

#define TSW_TSNPORT_TSYN_CR_TMR_ALD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK)

◆ TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT

#define TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT   (16U)

◆ TSW_TSNPORT_TSYN_CR_TMR_EN_GET

#define TSW_TSNPORT_TSYN_CR_TMR_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT)

◆ TSW_TSNPORT_TSYN_CR_TMR_EN_MASK

#define TSW_TSNPORT_TSYN_CR_TMR_EN_MASK   (0x1F00U)

◆ TSW_TSNPORT_TSYN_CR_TMR_EN_SET

#define TSW_TSNPORT_TSYN_CR_TMR_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK)

◆ TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT

#define TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT   (8U)

◆ TSW_TSNPORT_TSYN_CR_TMRIE_GET

#define TSW_TSNPORT_TSYN_CR_TMRIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK) >> TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT)

◆ TSW_TSNPORT_TSYN_CR_TMRIE_MASK

#define TSW_TSNPORT_TSYN_CR_TMRIE_MASK   (0x4U)

◆ TSW_TSNPORT_TSYN_CR_TMRIE_SET

#define TSW_TSNPORT_TSYN_CR_TMRIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK)

◆ TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT

#define TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT   (2U)

◆ TSW_TSNPORT_TSYN_CR_TXIE_GET

#define TSW_TSNPORT_TSYN_CR_TXIE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TXIE_MASK) >> TSW_TSNPORT_TSYN_CR_TXIE_SHIFT)

◆ TSW_TSNPORT_TSYN_CR_TXIE_MASK

#define TSW_TSNPORT_TSYN_CR_TXIE_MASK   (0x1U)

◆ TSW_TSNPORT_TSYN_CR_TXIE_SET

#define TSW_TSNPORT_TSYN_CR_TXIE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TXIE_MASK)

◆ TSW_TSNPORT_TSYN_CR_TXIE_SHIFT

#define TSW_TSNPORT_TSYN_CR_TXIE_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_GET

#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK) >> TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT)

◆ TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK

#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK   (0xFFFFFUL)

◆ TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SET

#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK)

◆ TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT

#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_GET

#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK

#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK   (0x40000000UL)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SET

#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT

#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT   (30U)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_OV_GET

#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK

#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK   (0x80000000UL)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SET

#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT

#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT   (31U)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_GET

#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK

#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK   (0x7U)

◆ TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT

#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_GET

#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT)

◆ TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK

#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK   (0xFFU)

◆ TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SET

#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK)

◆ TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT

#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_PTP_TX_STS_STS_GET

#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT)

◆ TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK

#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK   (0xFFU)

◆ TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT

#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_GET

#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT)

◆ TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK

#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK   (0xFFU)

◆ TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SET

#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK)

◆ TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT

#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_GET

#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK

#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK   (0xFFFU)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT

#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_GET

#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK

#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT

#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_GET

#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK

#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT

#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT   (0U)

◆ TSW_TSNPORT_TSYN_SR_RXIS_GET

#define TSW_TSNPORT_TSYN_SR_RXIS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_RXIS_MASK) >> TSW_TSNPORT_TSYN_SR_RXIS_SHIFT)

◆ TSW_TSNPORT_TSYN_SR_RXIS_MASK

#define TSW_TSNPORT_TSYN_SR_RXIS_MASK   (0x2U)

◆ TSW_TSNPORT_TSYN_SR_RXIS_SHIFT

#define TSW_TSNPORT_TSYN_SR_RXIS_SHIFT   (1U)

◆ TSW_TSNPORT_TSYN_SR_TMR_DN_GET

#define TSW_TSNPORT_TSYN_SR_TMR_DN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK) >> TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT)

◆ TSW_TSNPORT_TSYN_SR_TMR_DN_MASK

#define TSW_TSNPORT_TSYN_SR_TMR_DN_MASK   (0x1F00U)

◆ TSW_TSNPORT_TSYN_SR_TMR_DN_SET

#define TSW_TSNPORT_TSYN_SR_TMR_DN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK)

◆ TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT

#define TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT   (8U)

◆ TSW_TSNPORT_TSYN_SR_TMRIS_GET

#define TSW_TSNPORT_TSYN_SR_TMRIS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMRIS_MASK) >> TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT)

◆ TSW_TSNPORT_TSYN_SR_TMRIS_MASK

#define TSW_TSNPORT_TSYN_SR_TMRIS_MASK   (0x4U)

◆ TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT

#define TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT   (2U)

◆ TSW_TSNPORT_TSYN_SR_TXIS_GET

#define TSW_TSNPORT_TSYN_SR_TXIS_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TXIS_MASK) >> TSW_TSNPORT_TSYN_SR_TXIS_SHIFT)

◆ TSW_TSNPORT_TSYN_SR_TXIS_MASK

#define TSW_TSNPORT_TSYN_SR_TXIS_MASK   (0x1U)

◆ TSW_TSNPORT_TSYN_SR_TXIS_SHIFT

#define TSW_TSNPORT_TSYN_SR_TXIS_SHIFT   (0U)

◆ TSW_TSNPORT_TSYNTMR_PERIOD_GET

#define TSW_TSNPORT_TSYNTMR_PERIOD_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK) >> TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT)

◆ TSW_TSNPORT_TSYNTMR_PERIOD_MASK

#define TSW_TSNPORT_TSYNTMR_PERIOD_MASK   (0xFFFFFUL)

◆ TSW_TSNPORT_TSYNTMR_PERIOD_SET

#define TSW_TSNPORT_TSYNTMR_PERIOD_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK)

◆ TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT

#define TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT   (0U)

◆ TSW_TSNPORT_TSYNTMR_TSYN_TMR0

#define TSW_TSNPORT_TSYNTMR_TSYN_TMR0   (0UL)

◆ TSW_TSNPORT_TSYNTMR_TSYN_TMR1

#define TSW_TSNPORT_TSYNTMR_TSYN_TMR1   (1UL)

◆ TSW_TSNPORT_TSYNTMR_TSYN_TMR2

#define TSW_TSNPORT_TSYNTMR_TSYN_TMR2   (2UL)

◆ TSW_TSNPORT_TSYNTMR_TSYN_TMR3

#define TSW_TSNPORT_TSYNTMR_TSYN_TMR3   (3UL)

◆ TSW_TSNPORT_TSYNTMR_TSYN_TMR4

#define TSW_TSNPORT_TSYNTMR_TSYN_TMR4   (4UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV0

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV0   (0UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV1

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV1   (1UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV2

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV2   (2UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV3

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV3   (3UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV4

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV4   (4UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV5

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV5   (5UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV6

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV6   (6UL)

◆ TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV7

#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV7   (7UL)

◆ TSW_TSNPORT_TXOV_VALUE_GET

#define TSW_TSNPORT_TXOV_VALUE_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TXOV_VALUE_MASK) >> TSW_TSNPORT_TXOV_VALUE_SHIFT)

◆ TSW_TSNPORT_TXOV_VALUE_MASK

#define TSW_TSNPORT_TXOV_VALUE_MASK   (0xFFFFFFFFUL)

◆ TSW_TSNPORT_TXOV_VALUE_SET

#define TSW_TSNPORT_TXOV_VALUE_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TXOV_VALUE_SHIFT) & TSW_TSNPORT_TXOV_VALUE_MASK)

◆ TSW_TSNPORT_TXOV_VALUE_SHIFT

#define TSW_TSNPORT_TXOV_VALUE_SHIFT   (0U)

◆ TSW_TSNPORT_TXSEL_CBS_EN_GET

#define TSW_TSNPORT_TXSEL_CBS_EN_GET (   x)    (((uint32_t)(x) & TSW_TSNPORT_TXSEL_CBS_EN_MASK) >> TSW_TSNPORT_TXSEL_CBS_EN_SHIFT)

◆ TSW_TSNPORT_TXSEL_CBS_EN_MASK

#define TSW_TSNPORT_TXSEL_CBS_EN_MASK   (0x1U)

◆ TSW_TSNPORT_TXSEL_CBS_EN_SET

#define TSW_TSNPORT_TXSEL_CBS_EN_SET (   x)    (((uint32_t)(x) << TSW_TSNPORT_TXSEL_CBS_EN_SHIFT) & TSW_TSNPORT_TXSEL_CBS_EN_MASK)

◆ TSW_TSNPORT_TXSEL_CBS_EN_SHIFT

#define TSW_TSNPORT_TXSEL_CBS_EN_SHIFT   (0U)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL0

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL0   (0UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL1

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL1   (1UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL2

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL2   (2UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL3

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL3   (3UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL4

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL4   (4UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL5

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL5   (5UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL6

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL6   (6UL)

◆ TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL7

#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL7   (7UL)