hpm_uart_drv.h

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/*
 * Copyright (c) 2021-2022-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_UART_DRV_H
#define HPM_UART_DRV_H
#include "hpm_common.h"
#include "hpm_uart_regs.h"
#include "hpm_soc_feature.h"
 
enum {
    status_uart_no_suitable_baudrate_parameter_found = MAKE_STATUS(status_group_uart, 1),
};
 
/* @brief Parity */
typedef enum parity {
    parity_none = 0,
    parity_odd,
    parity_even,
    parity_always_1,
    parity_always_0,
} parity_setting_t;
 
/* @brief Stop bits */
typedef enum num_of_stop_bits {
    stop_bits_1 = 0,
    stop_bits_1_5,
    stop_bits_2,
} num_of_stop_bits_t;
 
/* @brief Word length */
typedef enum word_length {
    word_length_5_bits = 0,
    word_length_6_bits,
    word_length_7_bits,
    word_length_8_bits,
} word_length_t;
 
/* @brief UART fifo trigger levels */
typedef enum uart_fifo_trg_lvl {
#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1)
    uart_fifo_1_byte  = 0,
    uart_fifo_2_bytes = 1,
    uart_fifo_3_bytes = 2,
    uart_fifo_4_bytes = 3,
    uart_fifo_5_bytes = 4,
    uart_fifo_6_bytes = 5,
    uart_fifo_7_bytes = 6,
    uart_fifo_8_bytes = 7,
    uart_fifo_9_bytes = 8,
    uart_fifo_10_bytes = 9,
    uart_fifo_11_bytes = 10,
    uart_fifo_12_bytes = 11,
    uart_fifo_13_bytes = 12,
    uart_fifo_14_bytes = 13,
    uart_fifo_15_bytes = 14,
    uart_fifo_16_bytes = 15,
    uart_fifo_17_bytes = 16,
    uart_fifo_18_bytes = 17,
    uart_fifo_19_bytes = 18,
    uart_fifo_20_bytes = 19,
    uart_fifo_21_bytes = 20,
    uart_fifo_22_bytes = 21,
    uart_fifo_23_bytes = 22,
    uart_fifo_24_bytes = 23,
    uart_fifo_25_bytes = 24,
    uart_fifo_26_bytes = 25,
    uart_fifo_27_bytes = 26,
    uart_fifo_28_bytes = 27,
    uart_fifo_29_bytes = 28,
    uart_fifo_30_bytes = 29,
    uart_fifo_31_bytes = 30,
    uart_fifo_32_bytes = 31,
 
    uart_rx_fifo_trg_not_empty = uart_fifo_1_byte,
    uart_rx_fifo_trg_gt_one_quarter = (UART_SOC_FIFO_SIZE / 4) - 1,
    uart_rx_fifo_trg_gt_half = (UART_SOC_FIFO_SIZE / 2) - 1,
    uart_rx_fifo_trg_gt_three_quarters = ((UART_SOC_FIFO_SIZE * 3) / 4) - 1,
 
    uart_tx_fifo_trg_not_full = UART_SOC_FIFO_SIZE - 1,
    uart_tx_fifo_trg_lt_three_quarters = ((UART_SOC_FIFO_SIZE * 3) / 4) - 1,
    uart_tx_fifo_trg_lt_half = (UART_SOC_FIFO_SIZE / 2) - 1,
    uart_tx_fifo_trg_lt_one_quarter = (UART_SOC_FIFO_SIZE / 4) - 1,
#else
    uart_rx_fifo_trg_not_empty = 0,
    uart_rx_fifo_trg_gt_one_quarter = 1,
    uart_rx_fifo_trg_gt_half = 2,
    uart_rx_fifo_trg_gt_three_quarters = 3,
 
    uart_tx_fifo_trg_not_full = 0,
    uart_tx_fifo_trg_lt_three_quarters = 1,
    uart_tx_fifo_trg_lt_half = 2,
    uart_tx_fifo_trg_lt_one_quarter = 3,
#endif
} uart_fifo_trg_lvl_t;
 
/* @brief UART signals */
typedef enum uart_signal {
    uart_signal_rts = UART_MCR_RTS_MASK,
} uart_signal_t;
 
/* @brief UART signal levels */
typedef enum uart_signal_level {
    uart_signal_level_high,
    uart_signal_level_low,
} uart_signal_level_t;
 
/* @brief UART modem status */
typedef enum uart_modem_stat {
    uart_modem_stat_cts = UART_MSR_CTS_MASK,
    uart_modem_stat_dcts_changed = UART_MSR_DCTS_MASK,
} uart_modem_stat_t;
 
/* @brief UART interrupt enable masks */
typedef enum uart_intr_enable {
    uart_intr_rx_data_avail_or_timeout = UART_IER_ERBI_MASK,
    uart_intr_tx_slot_avail = UART_IER_ETHEI_MASK,
    uart_intr_rx_line_stat = UART_IER_ELSI_MASK,
    uart_intr_modem_stat = UART_IER_EMSI_MASK,
#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1)
    uart_intr_rx_line_idle = UART_IER_ERXIDLE_MASK,
#endif
#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1)
    uart_intr_tx_line_idle = UART_IER_ETXIDLE_MASK,
#endif
#if defined(HPM_IP_FEATURE_UART_ADDR_MATCH) && (HPM_IP_FEATURE_UART_ADDR_MATCH == 1)
    uart_intr_addr_match = UART_IER_EADDRM_MASK,
    uart_intr_addr_match_and_rxidle = UART_IER_EADDRM_IDLE_MASK,
    uart_intr_addr_datalost = UART_IER_EDATLOST_MASK,
#endif
#if defined(HPM_IP_FEATURE_UART_RX_LINE_ERROR_DETECT) && (HPM_IP_FEATURE_UART_RX_LINE_ERROR_DETECT == 1)
    uart_intr_errf = UART_IER_LSR_ERRF_IRQ_EN_MASK,
    uart_intr_break_err = UART_IER_LSR_BREAK_IRQ_EN_MASK,
    uart_intr_framing_err = UART_IER_LSR_FRAMING_IRQ_EN_MASK,
    uart_intr_parity_err = UART_IER_LSR_PARITY_IRQ_EN_MASK,
    uart_intr_overrun = UART_IER_LSR_OVERRUN_IRQ_EN_MASK,
#endif
} uart_intr_enable_t;
 
/* @brief UART interrupt IDs */
typedef enum uart_intr_id {
    uart_intr_id_modem_stat = 0x0,
    uart_intr_id_tx_slot_avail = 0x2,
    uart_intr_id_rx_data_avail = 0x4,
    uart_intr_id_rx_line_stat = 0x6,
    uart_intr_id_rx_timeout = 0xc,
} uart_intr_id_t;
 
/* @brief UART status */
typedef enum uart_stat {
    uart_stat_data_ready = UART_LSR_DR_MASK, /* rx data ready in fifo */
    uart_stat_overrun_error = UART_LSR_OE_MASK,
    uart_stat_parity_error = UART_LSR_PE_MASK,
    uart_stat_framing_error = UART_LSR_FE_MASK,
    uart_stat_line_break = UART_LSR_LBREAK_MASK,
    uart_stat_tx_slot_avail = UART_LSR_THRE_MASK,
    uart_stat_transmitter_empty = UART_LSR_TEMT_MASK,
    uart_stat_rx_fifo_error = UART_LSR_ERRF_MASK,
} uart_stat_t;
 
typedef struct uart_modem_config {
    bool auto_flow_ctrl_en;     
    bool loop_back_en;          
    bool set_rts_high;          
} uart_modem_config_t;
 
#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1)
typedef enum hpm_uart_rxline_idle_cond {
    uart_rxline_idle_cond_rxline_logic_one = 0,         
    uart_rxline_idle_cond_state_machine_idle = 1        
} uart_rxline_idle_cond_t;
 
typedef struct hpm_uart_rxline_idle_detect_config {
    bool detect_enable;                 
    bool detect_irq_enable;             
    uart_rxline_idle_cond_t idle_cond;  
    uint8_t threshold;                  
} uart_rxline_idle_config_t;
#endif
 
typedef struct hpm_uart_config {
    uint32_t src_freq_in_hz;                    
    uint32_t baudrate;                          
    uint8_t num_of_stop_bits;                   
    uint8_t word_length;                        
    uint8_t parity;                             
    uint8_t tx_fifo_level;                      
    uint8_t rx_fifo_level;                      
    bool dma_enable;                            
    bool fifo_enable;                           
    uart_modem_config_t modem_config;           
#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1)
    uart_rxline_idle_config_t  rxidle_config;   
#endif
#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1)
    uart_rxline_idle_config_t  txidle_config;   
#endif
#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1)
    bool rx_enable;                             
#endif
} uart_config_t;
 
#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1)
typedef struct {
    uint16_t stop_bit_len;
    bool en_stop_bit_insert;
    bool hardware_trig;
    bool trig_mode;
    bool trig_clr_rxfifo;
} uart_trig_config_t;
#endif
 
typedef struct {
    uint8_t tx_fifo_level;                      
    uint8_t rx_fifo_level;                      
    bool reset_tx_fifo;                         
    bool reset_rx_fifo;                         
    bool dma_enable;                            
    bool fifo_enable;                           
} uart_fifo_ctrl_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline uint8_t uart_get_fifo_size(UART_Type *ptr)
{
    return 16 << ((ptr->CFG & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT);
}
 
void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl);
 
static inline void uart_clear_rx_fifo(UART_Type *ptr)
{
    while (ptr->LSR & UART_LSR_DR_MASK) {
        ptr->RBR;
    }
}
 
#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1)
static inline void uart_enable_rx_function(UART_Type *ptr, bool enable)
{
    if (enable) {
        ptr->IDLE_CFG |= UART_IDLE_CFG_RXEN_MASK;
    } else {
        ptr->IDLE_CFG &= ~UART_IDLE_CFG_RXEN_MASK;
    }
}
#endif
 
static inline void uart_reset_tx_fifo(UART_Type *ptr)
{
#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1)
    ptr->FCRR |= UART_FCRR_TFIFORST_MASK;
#else
    ptr->FCR = UART_FCR_TFIFORST_MASK | (ptr->GPR);
#endif
}
 
static inline void uart_reset_rx_fifo(UART_Type *ptr)
{
#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1)
    ptr->FCRR |= UART_FCRR_RFIFORST_MASK;
#else
    ptr->FCR = UART_FCR_RFIFORST_MASK | (ptr->GPR);
#endif
}
 
static inline void uart_reset_all_fifo(UART_Type *ptr)
{
#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1)
    ptr->FCRR |= UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK;
#else
    ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK | (ptr->GPR);
#endif
}
 
static inline void uart_modem_enable_loopback(UART_Type *ptr)
{
    ptr->MCR |= UART_MCR_LOOP_MASK;
}
 
static inline void uart_modem_disable_loopback(UART_Type *ptr)
{
    ptr->MCR &= ~UART_MCR_LOOP_MASK;
}
 
static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr)
{
    ptr->MCR &= ~UART_MCR_AFE_MASK;
}
 
static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr)
{
    ptr->MCR |= UART_MCR_AFE_MASK;
}
 
static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config)
{
    ptr->MCR = UART_MCR_AFE_SET(config->auto_flow_ctrl_en)
        | UART_MCR_LOOP_SET(config->loop_back_en)
        | UART_MCR_RTS_SET(!config->set_rts_high);
}
 
static inline uint8_t uart_get_modem_status(UART_Type *ptr)
{
    return ptr->MSR;
}
 
static inline void uart_write_byte(UART_Type *ptr, uint8_t c)
{
    ptr->THR = UART_THR_THR_SET(c);
}
 
 
static inline uint8_t uart_read_byte(UART_Type *ptr)
{
    return (ptr->RBR & UART_RBR_RBR_MASK);
}
 
static inline bool uart_check_modem_status(UART_Type *ptr, uart_modem_stat_t mask)
{
    return ((ptr->MSR & mask) != 0U) ? true : false;
}
 
static inline void uart_disable_irq(UART_Type *ptr, uint32_t irq_mask)
{
    ptr->IER &= ~irq_mask;
}
 
static inline void uart_enable_irq(UART_Type *ptr, uint32_t irq_mask)
{
    ptr->IER |= irq_mask;
}
 
static inline uint32_t uart_get_enabled_irq(UART_Type *ptr)
{
    return ptr->IER;
}
 
static inline uint8_t uart_get_irq_id(UART_Type *ptr)
{
    return (ptr->IIR & UART_IIR_INTRID_MASK);
}
 
#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1)
 
/* if HPM_IP_FEATURE_UART_E00018_FIX = 1, the IIR2 register exists, should use IIR2 to get/clear rx idle status */
#if !defined(HPM_IP_FEATURE_UART_E00018_FIX) || (HPM_IP_FEATURE_UART_E00018_FIX == 0)
static inline bool uart_is_rxline_idle(UART_Type *ptr)
{
    return ((ptr->IIR & UART_IIR_RXIDLE_FLAG_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rxline_idle_flag(UART_Type *ptr)
{
    ptr->IIR = UART_IIR_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */
    ptr->FCR = ptr->GPR;
}
#endif
 
static inline void uart_enable_rxline_idle_detection(UART_Type *ptr)
{
    ptr->IDLE_CFG |= UART_IDLE_CFG_RX_IDLE_EN_MASK;
}
 
static inline void uart_disable_rxline_idle_detection(UART_Type *ptr)
{
    ptr->IDLE_CFG &= ~UART_IDLE_CFG_RX_IDLE_EN_MASK;
}
 
hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config);
 
#endif
 
#if defined(HPM_IP_FEATURE_UART_E00018_FIX) && (HPM_IP_FEATURE_UART_E00018_FIX == 1)
static inline bool uart_is_txline_idle(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_TXIDLE_FLAG_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_txline_idle_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_TXIDLE_FLAG_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_is_rxline_idle(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_RXIDLE_FLAG_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rxline_idle_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */
}
#endif
 
#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1)
static inline void uart_enable_txline_idle_detection(UART_Type *ptr)
{
    ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_MASK;
}
 
static inline void uart_disable_txline_idle_detection(UART_Type *ptr)
{
    ptr->IDLE_CFG &= ~UART_IDLE_CFG_TX_IDLE_EN_MASK;
}
 
hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config);
 
#endif
 
 
 
static inline uint32_t uart_get_status(UART_Type *ptr)
{
    return ptr->LSR;
}
 
static inline bool uart_check_status(UART_Type *ptr, uart_stat_t mask)
{
    return ((ptr->LSR & mask) != 0U) ? true : false;
}
 
void uart_default_config(UART_Type *ptr, uart_config_t *config);
 
hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config);
 
hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c);
 
hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *c);
 
hpm_stat_t uart_try_receive_byte(UART_Type *ptr, uint8_t *c);
 
void uart_set_signal_level(UART_Type *ptr,
                           uart_signal_t signal,
                           uart_signal_level_t level);
 
hpm_stat_t uart_flush(UART_Type *ptr);
 
hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte);
 
hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte);
 
hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz);
 
 
#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1)
void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config);
 
static inline void uart_software_trig_transfer(UART_Type *ptr)
{
    ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK;
    ptr->MOTO_CFG |= UART_MOTO_CFG_SWTRG_MASK;
}
 
static inline void uart_enable_hardware_trig_transfer(UART_Type *ptr, bool enable)
{
    if (enable) {
        ptr->MOTO_CFG |= UART_MOTO_CFG_HWTRG_EN_MASK;
    } else {
        ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK;
    }
}
 
static inline uint8_t uart_get_data_count_in_rx_fifo(UART_Type *ptr)
{
    return UART_LSR_RFIFO_NUM_GET(ptr->LSR);
}
 
static inline uint8_t uart_get_data_count_in_tx_fifo(UART_Type *ptr)
{
    return UART_LSR_TFIFO_NUM_GET(ptr->LSR);
}
#endif
 
#if defined(HPM_IP_FEATURE_UART_ADDR_MATCH) && (HPM_IP_FEATURE_UART_ADDR_MATCH == 1)
static inline void uart_enable_9bit_transmit_mode(UART_Type *ptr, bool enable)
{
    if (enable) {
        ptr->ADDR_CFG |= UART_ADDR_CFG_TXEN_9BIT_MASK
                            | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK
                            | UART_ADDR_CFG_RXEN_9BIT_MASK;
    } else {
        ptr->ADDR_CFG &= ~(UART_ADDR_CFG_TXEN_9BIT_MASK
                            | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK
                            | UART_ADDR_CFG_RXEN_9BIT_MASK);
    }
}
 
static inline void uart_enable_address0_match(UART_Type *ptr, uint8_t addr)
{
    ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR0_MASK;
    ptr->ADDR_CFG |= UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_ADDR0_SET(addr);
}
 
static inline void uart_enable_address1_match(UART_Type *ptr, uint8_t addr)
{
    ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR1_MASK;
    ptr->ADDR_CFG |= UART_ADDR_CFG_A1_EN_MASK | UART_ADDR_CFG_ADDR1_SET(addr);
}
 
static inline void uart_disable_address0_match(UART_Type *ptr)
{
    ptr->ADDR_CFG &= ~UART_ADDR_CFG_A0_EN_MASK;
}
 
static inline void uart_disable_address1_match(UART_Type *ptr)
{
    ptr->ADDR_CFG &= ~UART_ADDR_CFG_A1_EN_MASK;
}
 
static inline void uart_disable_address_match(UART_Type *ptr)
{
    ptr->ADDR_CFG &= ~(UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_A1_EN_MASK);
}
 
static inline bool uart_is_addr_match(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_ADDR_MATCH_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_addr_match_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_ADDR_MATCH_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_is_addr_match_and_rxidle(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_ADDR_MATCH_IDLE_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_addr_match_and_rxidle_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_ADDR_MATCH_IDLE_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_is_data_lost(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_DATA_LOST_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_data_lost_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_DATA_LOST_MASK; /* Write-1-Clear Logic */
}
#endif
 
static inline void uart_modem_write_rts_pin(UART_Type *ptr, uint8_t high)
{
    if (high == true) {
        ptr->MCR &= ~UART_MCR_RTS_MASK;
    } else {
        ptr->MCR |= UART_MCR_RTS_MASK;
    }
}
 
#if defined(HPM_IP_FEATURE_UART_DISABLE_DMA_TIMEOUT) && (HPM_IP_FEATURE_UART_DISABLE_DMA_TIMEOUT == 1)
static inline void uart_disable_rx_timeout_trig_dma(UART_Type *ptr)
{
    ptr->FCRR |= UART_FCRR_TMOUT_RXDMA_DIS_MASK;
}
 
static inline void uart_enable_rx_timeout_trig_dma(UART_Type *ptr)
{
    ptr->FCRR &= ~UART_FCRR_TMOUT_RXDMA_DIS_MASK;
}
#endif
 
#if defined(HPM_IP_FEATURE_UART_RX_LINE_ERROR_DETECT) && (HPM_IP_FEATURE_UART_RX_LINE_ERROR_DETECT == 1)
static inline bool uart_rx_is_fifo_error(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_LSR_ERRF_STS_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rx_fifo_error_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_LSR_ERRF_STS_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_rx_is_break(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_LSR_BREAK_STS_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rx_break_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_LSR_BREAK_STS_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_rx_is_framing_error(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_LSR_FRAMING_STS_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rx_framing_error_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_LSR_FRAMING_STS_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_rx_is_parity_error(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_LSR_PARITY_STS_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rx_parity_error_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_LSR_PARITY_STS_MASK; /* Write-1-Clear Logic */
}
 
static inline bool uart_rx_is_overrun(UART_Type *ptr)
{
    return ((ptr->IIR2 & UART_IIR2_LSR_OVERRUN_STS_MASK) != 0U) ? true : false;
}
 
static inline void uart_clear_rx_overrun_flag(UART_Type *ptr)
{
    ptr->IIR2 = UART_IIR2_LSR_OVERRUN_STS_MASK; /* Write-1-Clear Logic */
}
 
#endif
 
#if defined(HPM_IP_FEATURE_UART_DMA_STOP) && (HPM_IP_FEATURE_UART_DMA_STOP == 1)
static inline void uart_rx_enable_dma_auto_stop(UART_Type *ptr)
{
    ptr->FCRR |= UART_FCRR_DMA_STOP_EN_MASK;
}
 
static inline void uart_clear_rx_dma_auto_stop_flag(UART_Type *ptr)
{
    ptr->FCRR = UART_FCRR_DMA_STOPPED_WRITE_CLEAR_MASK;
}
#endif
 
#if defined(HPM_IP_FEATURE_UART_DE_DELAY) && (HPM_IP_FEATURE_UART_DE_DELAY == 1)
static inline void uart_set_de_delay_before_start_bit(UART_Type *ptr, uint8_t delay)
{
    ptr->MOTO_CFG = (ptr->MOTO_CFG & ~UART_MOTO_CFG_TXPRE_DLY_MASK) | UART_MOTO_CFG_TXPRE_DLY_SET(delay);
}
 
static inline void uart_set_de_delay_after_stop_bit(UART_Type *ptr, uint8_t delay)
{
    ptr->MOTO_CFG |= UART_MOTO_CFG_TXSTOP_OPT_MASK | UART_MOTO_CFG_TXSTOP_INSERT_MASK;
    ptr->MOTO_CFG = (ptr->MOTO_CFG & ~UART_MOTO_CFG_TXSTP_BITS_MASK) | UART_MOTO_CFG_TXSTP_BITS_SET(delay);
}
 
#endif
 
#ifdef __cplusplus
}
#endif
#endif    /* HPM_UART_DRV_H */