riscv_core.h

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/*
 * Copyright (c) 2021 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef RISCV_CORE_H
#define RISCV_CORE_H
 
#include "hpm_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define write_fcsr(v) __asm volatile("fscsr %0" : : "r"(v))
 
#define clear_csr(csr_num, bit) __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit))
 
#define read_clear_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })
 
#define read_set_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })
 
#define set_csr(csr_num, bit) __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit))
 
#define write_csr(csr_num, v) __asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v))
 
#define read_csr(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; })
 
#define read_fcsr() ({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; })
 
#define fencei() __asm volatile("fence.i")
 
#define fencerw() __asm volatile("fence rw, rw")
 
#define fenceiorw() __asm volatile("fence iorw, iorw")
 
#define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)
 
#define disable_fpu() read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)
 
#define clear_fcsr() write_fcsr(0)
 
#ifdef __cplusplus
}
#endif
 
 
#endif /* RISCV_CORE_H */