riscv_core.h File Reference

#include "hpm_common.h"

Go to the source code of this file.

Macros
#define	write_fcsr(v)   __asm volatile("fscsr %0" : : "r"(v))
	write fp csr More...
#define	clear_csr(csr_num, bit)   __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit))
	clear bits in csr More...
#define	read_clear_csr(csr_num, bit)   ({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })
	read and clear bits in csr More...
#define	read_set_csr(csr_num, bit)   ({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })
	read and set bits in csr More...
#define	set_csr(csr_num, bit)   __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit))
	set bits in csr More...
#define	write_csr(csr_num, v)   __asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v))
	write value to csr More...
#define	read_csr(csr_num)   ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; })
	read value of specific csr More...
#define	read_fcsr()   ({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; })
	read fp csr More...
#define	fencei()   __asm volatile("fence.i")
	execute fence.i More...
#define	fencerw()   __asm volatile("fence rw, rw")
	execute fence rw More...
#define	fenceiorw()   __asm volatile("fence iorw, iorw")
	execute fence iorw More...
#define	enable_fpu()   read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)
	enable fpu More...
#define	disable_fpu()   read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)
	disable fpu More...
#define	clear_fcsr()   write_fcsr(0)
	clear fcsr More...

Macro Definition Documentation

clear_csr

#define clear_csr	(		csr_num,
			bit
	)		__asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit))

clear bits in csr

Parameters

csr_num	specific csr
bit	bits to be cleared

clear_fcsr

#define clear_fcsr

(

)

write_fcsr(0)

clear fcsr

disable_fpu

#define disable_fpu

(

)

read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)

disable fpu

enable_fpu

#define enable_fpu

(

)

read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)

enable fpu

fencei

#define fencei

(

)

__asm volatile("fence.i")

execute fence.i

fenceiorw

#define fenceiorw

(

)

__asm volatile("fence iorw, iorw")

execute fence iorw

fencerw

#define fencerw

(

)

__asm volatile("fence rw, rw")

execute fence rw

read_clear_csr

#define read_clear_csr	(		csr_num,
			bit
	)		({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })

read and clear bits in csr

Parameters

csr_num	specific csr
bit	bits to be cleared

Returns

csr value before cleared

read_csr

#define read_csr

(

csr_num

)

({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; })

read value of specific csr

Parameters

csr_num

specific csr

Returns

csr value

read_fcsr

#define read_fcsr

(

)

({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; })

read fp csr

Returns

fp csr value

read_set_csr

#define read_set_csr	(		csr_num,
			bit
	)		({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })

read and set bits in csr

Parameters

csr_num	specific csr
bit	bits to be set

Returns

csr value before set

set_csr

#define set_csr	(		csr_num,
			bit
	)		__asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit))

set bits in csr

Parameters

csr_num	specific csr
bit	bits to be set

write_csr

#define write_csr	(		csr_num,
			v
	)		__asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v))

write value to csr

Parameters

csr_num	specific csr
v	value to be written

write_fcsr

#define write_fcsr

(

v

)

__asm volatile("fscsr %0" : : "r"(v))

write fp csr

Parameters

v	value to be set