HPM SDK
HPMicro Software Development Kit
Macros
hpm_trgmmux_src.h File Reference

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Macros

#define HPM_TRGM0_INPUT_SRC_VSS   (0x0UL)
 
#define HPM_TRGM0_INPUT_SRC_VDD   (0x1UL)
 
#define HPM_TRGM0_INPUT_SRC_USB0_SOF   (0x2UL)
 
#define HPM_TRGM0_INPUT_SRC_ENET0_PTP3   (0x3UL)
 
#define HPM_TRGM0_INPUT_SRC_ESC_SYNC0   (0x4UL)
 
#define HPM_TRGM0_INPUT_SRC_TSN_PTP3   (0x5UL)
 
#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0   (0x6UL)
 
#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1   (0x7UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0   (0x8UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1   (0x9UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0   (0xAUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1   (0xBUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN0   (0xCUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN1   (0xDUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_CAPIN0   (0xEUL)
 
#define HPM_TRGM0_INPUT_SRC_ESC_SYNC1   (0xFUL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH00   (0x10UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH01   (0x11UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH02   (0x12UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH03   (0x13UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH04   (0x14UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH05   (0x15UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH06   (0x16UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH07   (0x17UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH08   (0x18UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH09   (0x19UL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH10   (0x1AUL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH11   (0x1BUL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH12   (0x1CUL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH13   (0x1DUL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH14   (0x1EUL)
 
#define HPM_TRGM0_INPUT_SRC_SYNT_CH15   (0x1FUL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2   (0x20UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3   (0x21UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2   (0x22UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3   (0x23UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2   (0x24UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3   (0x25UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2   (0x26UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3   (0x27UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT2   (0x28UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT3   (0x29UL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT2   (0x2AUL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT3   (0x2BUL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT2   (0x2CUL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT3   (0x2DUL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT2   (0x2EUL)
 
#define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT3   (0x2FUL)
 
#define HPM_TRGM0_INPUT_SRC_CMP0_OUT   (0x30UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP1_OUT   (0x31UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP2_OUT   (0x32UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP3_OUT   (0x33UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP4_OUT   (0x34UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP5_OUT   (0x35UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP6_OUT   (0x36UL)
 
#define HPM_TRGM0_INPUT_SRC_CMP7_OUT   (0x37UL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0   (0x38UL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1   (0x39UL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2   (0x3AUL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3   (0x3BUL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4   (0x3CUL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5   (0x3DUL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6   (0x3EUL)
 
#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7   (0x3FUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0   (0x40UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_1   (0x41UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_2   (0x42UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_3   (0x43UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_4   (0x44UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_5   (0x45UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_6   (0x46UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_7   (0x47UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0   (0x48UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_1   (0x49UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_2   (0x4AUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_3   (0x4BUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_4   (0x4CUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_5   (0x4DUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_6   (0x4EUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_7   (0x46UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_0   (0x50UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_1   (0x51UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_2   (0x52UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_3   (0x53UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_4   (0x54UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_5   (0x55UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_6   (0x56UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_7   (0x57UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_0   (0x58UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_1   (0x59UL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_2   (0x5AUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_3   (0x5BUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_4   (0x5CUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_5   (0x5DUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_6   (0x5EUL)
 
#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_7   (0x5FUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P00   (0x60UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P01   (0x61UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P02   (0x62UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P03   (0x63UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P04   (0x64UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P05   (0x65UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P06   (0x66UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P07   (0x67UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P08   (0x68UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P09   (0x69UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P10   (0x6AUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P11   (0x6BUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P12   (0x6CUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P13   (0x6DUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P14   (0x6EUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P15   (0x6FUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P16   (0x70UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P17   (0x71UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P18   (0x72UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P19   (0x73UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P20   (0x74UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P21   (0x75UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P22   (0x76UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P23   (0x77UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P24   (0x78UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P25   (0x79UL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P26   (0x7AUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P27   (0x7BUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P28   (0x7CUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P29   (0x7DUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P30   (0x7EUL)
 
#define HPM_TRGM0_INPUT_SRC_TRGM0_P31   (0x7FUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT00   (0x80UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT01   (0x81UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT02   (0x82UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT03   (0x83UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT04   (0x84UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT05   (0x85UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT06   (0x86UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT07   (0x87UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT08   (0x88UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT09   (0x89UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT10   (0x8AUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT11   (0x8BUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT12   (0x8CUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT13   (0x8DUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT14   (0x8EUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT15   (0x8FUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT16   (0x90UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT17   (0x91UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT18   (0x92UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT19   (0x93UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT20   (0x94UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT21   (0x95UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT22   (0x96UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT23   (0x97UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT24   (0x98UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT25   (0x99UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT26   (0x9AUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT27   (0x9BUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT28   (0x9CUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT29   (0x9DUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT30   (0x9EUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT31   (0x9FUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT32   (0xA0UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT33   (0xA1UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT34   (0xA2UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT35   (0xA3UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT36   (0xA4UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT37   (0xA5UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT38   (0xA6UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT39   (0xA7UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT40   (0xA8UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT41   (0xA9UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT42   (0xAAUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT43   (0xABUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT44   (0xACUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT45   (0xADUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT46   (0xAEUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT47   (0xAFUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT48   (0xB0UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT49   (0xB1UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT50   (0xB2UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT51   (0xAAUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT52   (0xB4UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT53   (0xB5UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT54   (0xB6UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT55   (0xB7UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT56   (0xB8UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT57   (0xB9UL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT58   (0xBAUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT59   (0xBBUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT60   (0xBCUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT61   (0xBDUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT62   (0xBEUL)
 
#define HPM_TRGM0_INPUT_SRC_PLB_OUT63   (0xBFUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ0   (0xC0UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ1   (0xC1UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ2   (0xC2UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ3   (0xC3UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA0   (0xC4UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA1   (0xC5UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA2   (0xC6UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA3   (0xC7UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL0   (0xC8UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL1   (0xC9UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL2   (0xCAUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL3   (0xCBUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ0   (0xCCUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ1   (0xCDUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ2   (0xCEUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ3   (0xCFUL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL0   (0xD0UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL1   (0xD1UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL2   (0xD2UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL3   (0xD3UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA0   (0xD4UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA1   (0xD5UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA2   (0xD6UL)
 
#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA3   (0xD7UL)
 
#define HPM_TRGM0_INPUT_SRC_ADC0_TRGO   (0xD8UL)
 
#define HPM_TRGM0_INPUT_SRC_ADC1_TRGO   (0xD9UL)
 
#define HPM_TRGM0_INPUT_SRC_ADC2_TRGO   (0xDAUL)
 
#define HPM_TRGM0_INPUT_SRC_ADC3_TRGO   (0xDBUL)
 
#define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0   (0xDCUL)
 
#define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_1   (0xDDUL)
 
#define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_0   (0xDEUL)
 
#define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_1   (0xDFUL)
 
#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG   (0xE0UL)
 
#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO   (0xE1UL)
 
#define HPM_TRGM0_INPUT_SRC_QEI1_TRGO   (0xE2UL)
 
#define HPM_TRGM0_INPUT_SRC_QEI2_TRGO   (0xE3UL)
 
#define HPM_TRGM0_INPUT_SRC_QEI3_TRGO   (0xE4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0   (0x0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1   (0x1UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2   (0x2UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3   (0x3UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4   (0x4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5   (0x5UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6   (0x6UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7   (0x7UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO8   (0x8UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO9   (0x9UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO10   (0xAUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO11   (0xBUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO12   (0xCUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO13   (0xDUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO14   (0xEUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO15   (0xFUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO16   (0x10UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO17   (0x11UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO18   (0x12UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO19   (0x13UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO20   (0x14UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO21   (0x15UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO22   (0x16UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO23   (0x17UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO24   (0x18UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO25   (0x19UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO26   (0x1AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO27   (0x1BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO28   (0x1CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO29   (0x1DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO30   (0x1EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO31   (0x1FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC0   (0x20UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC1   (0x21UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC2   (0x22UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC3   (0x23UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC4   (0x24UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC5   (0x25UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC6   (0x26UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC7   (0x27UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC8   (0x28UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC9   (0x29UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC10   (0x2AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC11   (0x2BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC12   (0x2CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC13   (0x2DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC14   (0x2EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15   (0x2FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI   (0x30UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI   (0x31UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI   (0x32UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI   (0x33UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A   (0x34UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B   (0x35UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C   (0x36UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A   (0x37UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B   (0x38UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C   (0x39UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A   (0x3AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B   (0x3BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C   (0x3CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A   (0x3DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B   (0x3EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C   (0x3FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0   (0x40UL)
 
#define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN1   (0x41UL)
 
#define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN0   (0x42UL)
 
#define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN1   (0x43UL)
 
#define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN0   (0x44UL)
 
#define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN1   (0x45UL)
 
#define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN0   (0x46UL)
 
#define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN1   (0x47UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN   (0x48UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN   (0x49UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI2_TRIG_IN   (0x4AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI3_TRIG_IN   (0x4BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE   (0x4CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE   (0x4DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI2_PAUSE   (0x4EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEI3_PAUSE   (0x4FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0   (0x50UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1   (0x51UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0   (0x52UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1   (0x53UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN0   (0x54UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN1   (0x55UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN0   (0x56UL)
 
#define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN1   (0x57UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0   (0x58UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1   (0x59UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2   (0x5AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3   (0x5BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4   (0x5CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5   (0x5DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6   (0x5EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7   (0x5FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN   (0x60UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN   (0x61UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP2_WIN   (0x62UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP3_WIN   (0x63UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP4_WIN   (0x64UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP5_WIN   (0x65UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP6_WIN   (0x66UL)
 
#define HPM_TRGM0_OUTPUT_SRC_CMP7_WIN   (0x67UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2   (0x68UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3   (0x69UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI   (0x6AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2   (0x6BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3   (0x6CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI   (0x6DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2   (0x6EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3   (0x6FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI   (0x70UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2   (0x71UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3   (0x72UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI   (0x73UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN2   (0x74UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN3   (0x75UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_SYNCI   (0x76UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN2   (0x77UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN3   (0x78UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_SYNCI   (0x79UL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN2   (0x7AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN3   (0x7BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_SYNCI   (0x7CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN2   (0x7DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN3   (0x7EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_SYNCI   (0x7FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00   (0x80UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01   (0x81UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02   (0x82UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03   (0x83UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04   (0x84UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05   (0x85UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06   (0x86UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07   (0x87UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08   (0x88UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09   (0x89UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10   (0x8AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11   (0x8BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12   (0x8CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13   (0x8DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14   (0x8EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15   (0x8FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16   (0x90UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17   (0x91UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18   (0x92UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19   (0x93UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20   (0x94UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21   (0x95UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22   (0x96UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23   (0x97UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24   (0x98UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25   (0x99UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26   (0x9AUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27   (0x9BUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28   (0x9CUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29   (0x9DUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30   (0x9EUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31   (0x9FUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_32   (0xA0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_33   (0xA1UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_34   (0xA2UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_35   (0xA3UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_36   (0xA4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_37   (0xA5UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_38   (0xA6UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_39   (0xA7UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_40   (0xA8UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_41   (0xA9UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_42   (0xAAUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_43   (0xABUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_44   (0xACUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_45   (0xADUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_46   (0xAEUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_47   (0xAFUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_48   (0xB0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_49   (0xB1UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_50   (0xB2UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_51   (0xB3UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_52   (0xB4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_53   (0xB5UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_54   (0xB6UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_55   (0xB7UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_56   (0xB8UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_57   (0xB9UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_58   (0xBAUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_59   (0xBBUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_60   (0xBCUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_61   (0xBDUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_62   (0xBEUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_63   (0xBFUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN0   (0xC0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN1   (0xC1UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN2   (0xC2UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN3   (0xC3UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN4   (0xC4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN5   (0xC5UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN6   (0xC6UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN7   (0xC7UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0   (0xC8UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1   (0xC9UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2   (0xCAUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN3   (0xCBUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN4   (0xCCUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN5   (0xCDUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN6   (0xCEUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN7   (0xCFUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN0   (0xD0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN1   (0xD1UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN2   (0xD2UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN3   (0xD3UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN4   (0xD4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN5   (0xD5UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN6   (0xD6UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN7   (0xD7UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN0   (0xD8UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN1   (0xD9UL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN2   (0xDAUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN3   (0xDBUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN4   (0xDCUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN5   (0xDDUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN6   (0xDEUL)
 
#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN7   (0xDFUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP   (0xE0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP   (0xE1UL)
 
#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0   (0xE2UL)
 
#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1   (0xE3UL)
 
#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG   (0xE4UL)
 
#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0   (0xE5UL)
 
#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1   (0xE6UL)
 
#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0   (0xE7UL)
 
#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1   (0xE8UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN0   (0xE9UL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN1   (0xEAUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN2   (0xEBUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN3   (0xECUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN0   (0xEDUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN1   (0xEEUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN2   (0xEFUL)
 
#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN3   (0xF0UL)
 
#define HPM_TRGM0_OUTPUT_SRC_ESC_TRIG_IN   (0xF1UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN0   (0x0UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN1   (0x1UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN2   (0x2UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN3   (0x3UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN4   (0x4UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN5   (0x5UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN6   (0x6UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM0_IN7   (0x7UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN0   (0x8UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN1   (0x9UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN2   (0xAUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN3   (0xBUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN4   (0xCUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN5   (0xDUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN6   (0xEUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM1_IN7   (0xFUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN0   (0x10UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN1   (0x11UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN2   (0x12UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN3   (0x13UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN4   (0x14UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN5   (0x15UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN6   (0x16UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM2_IN7   (0x17UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN0   (0x18UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN1   (0x19UL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN2   (0x1AUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN3   (0x1BUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN4   (0x1CUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN5   (0x1DUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN6   (0x1EUL)
 
#define HPM_TRGM0_FILTER_SRC_PWM3_IN7   (0x1FUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN0   (0x20UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN1   (0x21UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN2   (0x22UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN3   (0x23UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN4   (0x24UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN5   (0x25UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN6   (0x26UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN7   (0x27UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN8   (0x28UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN9   (0x29UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN10   (0x2AUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN11   (0x2BUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN12   (0x2CUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN13   (0x2DUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN14   (0x2EUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN15   (0x2FUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN16   (0x30UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN17   (0x31UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN18   (0x32UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN19   (0x33UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN20   (0x34UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN21   (0x35UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN22   (0x36UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN23   (0x37UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN24   (0x38UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN25   (0x39UL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN26   (0x3AUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN27   (0x3BUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN28   (0x3CUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN29   (0x3DUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN30   (0x3EUL)
 
#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN31   (0x3FUL)
 
#define HPM_TRGM0_DMA_SRC_PWM0_REQ0   (0x0UL)
 
#define HPM_TRGM0_DMA_SRC_PWM0_REQ1   (0x1UL)
 
#define HPM_TRGM0_DMA_SRC_PWM0_REQ2   (0x2UL)
 
#define HPM_TRGM0_DMA_SRC_PWM0_REQ3   (0x3UL)
 
#define HPM_TRGM0_DMA_SRC_PWM1_REQ0   (0x4UL)
 
#define HPM_TRGM0_DMA_SRC_PWM1_REQ1   (0x5UL)
 
#define HPM_TRGM0_DMA_SRC_PWM1_REQ2   (0x6UL)
 
#define HPM_TRGM0_DMA_SRC_PWM1_REQ3   (0x7UL)
 
#define HPM_TRGM0_DMA_SRC_PWM2_REQ0   (0x8UL)
 
#define HPM_TRGM0_DMA_SRC_PWM2_REQ1   (0x9UL)
 
#define HPM_TRGM0_DMA_SRC_PWM2_REQ2   (0xAUL)
 
#define HPM_TRGM0_DMA_SRC_PWM2_REQ3   (0xBUL)
 
#define HPM_TRGM0_DMA_SRC_PWM3_REQ0   (0xCUL)
 
#define HPM_TRGM0_DMA_SRC_PWM3_REQ1   (0xDUL)
 
#define HPM_TRGM0_DMA_SRC_PWM3_REQ2   (0xEUL)
 
#define HPM_TRGM0_DMA_SRC_PWM3_REQ3   (0xFUL)
 
#define HPM_TRGM0_DMA_SRC_QEI0_REQ   (0x10UL)
 
#define HPM_TRGM0_DMA_SRC_QEI1_REQ   (0x11UL)
 
#define HPM_TRGM0_DMA_SRC_QEI2_REQ   (0x12UL)
 
#define HPM_TRGM0_DMA_SRC_QEI3_REQ   (0x13UL)
 
#define HPM_TRGM0_DMA_SRC_SEI_REQ0   (0x14UL)
 
#define HPM_TRGM0_DMA_SRC_SEI_REQ1   (0x15UL)
 
#define HPM_TRGM0_DMA_SRC_SEI_REQ2   (0x16UL)
 
#define HPM_TRGM0_DMA_SRC_SEI_REQ3   (0x17UL)
 
#define HPM_TRGM0_DMA_SRC_TRGM0   (0x18UL)
 
#define HPM_TRGM0_DMA_SRC_TRGM1   (0x19UL)
 

Macro Definition Documentation

◆ HPM_TRGM0_DMA_SRC_PWM0_REQ0

#define HPM_TRGM0_DMA_SRC_PWM0_REQ0   (0x0UL)

◆ HPM_TRGM0_DMA_SRC_PWM0_REQ1

#define HPM_TRGM0_DMA_SRC_PWM0_REQ1   (0x1UL)

◆ HPM_TRGM0_DMA_SRC_PWM0_REQ2

#define HPM_TRGM0_DMA_SRC_PWM0_REQ2   (0x2UL)

◆ HPM_TRGM0_DMA_SRC_PWM0_REQ3

#define HPM_TRGM0_DMA_SRC_PWM0_REQ3   (0x3UL)

◆ HPM_TRGM0_DMA_SRC_PWM1_REQ0

#define HPM_TRGM0_DMA_SRC_PWM1_REQ0   (0x4UL)

◆ HPM_TRGM0_DMA_SRC_PWM1_REQ1

#define HPM_TRGM0_DMA_SRC_PWM1_REQ1   (0x5UL)

◆ HPM_TRGM0_DMA_SRC_PWM1_REQ2

#define HPM_TRGM0_DMA_SRC_PWM1_REQ2   (0x6UL)

◆ HPM_TRGM0_DMA_SRC_PWM1_REQ3

#define HPM_TRGM0_DMA_SRC_PWM1_REQ3   (0x7UL)

◆ HPM_TRGM0_DMA_SRC_PWM2_REQ0

#define HPM_TRGM0_DMA_SRC_PWM2_REQ0   (0x8UL)

◆ HPM_TRGM0_DMA_SRC_PWM2_REQ1

#define HPM_TRGM0_DMA_SRC_PWM2_REQ1   (0x9UL)

◆ HPM_TRGM0_DMA_SRC_PWM2_REQ2

#define HPM_TRGM0_DMA_SRC_PWM2_REQ2   (0xAUL)

◆ HPM_TRGM0_DMA_SRC_PWM2_REQ3

#define HPM_TRGM0_DMA_SRC_PWM2_REQ3   (0xBUL)

◆ HPM_TRGM0_DMA_SRC_PWM3_REQ0

#define HPM_TRGM0_DMA_SRC_PWM3_REQ0   (0xCUL)

◆ HPM_TRGM0_DMA_SRC_PWM3_REQ1

#define HPM_TRGM0_DMA_SRC_PWM3_REQ1   (0xDUL)

◆ HPM_TRGM0_DMA_SRC_PWM3_REQ2

#define HPM_TRGM0_DMA_SRC_PWM3_REQ2   (0xEUL)

◆ HPM_TRGM0_DMA_SRC_PWM3_REQ3

#define HPM_TRGM0_DMA_SRC_PWM3_REQ3   (0xFUL)

◆ HPM_TRGM0_DMA_SRC_QEI0_REQ

#define HPM_TRGM0_DMA_SRC_QEI0_REQ   (0x10UL)

◆ HPM_TRGM0_DMA_SRC_QEI1_REQ

#define HPM_TRGM0_DMA_SRC_QEI1_REQ   (0x11UL)

◆ HPM_TRGM0_DMA_SRC_QEI2_REQ

#define HPM_TRGM0_DMA_SRC_QEI2_REQ   (0x12UL)

◆ HPM_TRGM0_DMA_SRC_QEI3_REQ

#define HPM_TRGM0_DMA_SRC_QEI3_REQ   (0x13UL)

◆ HPM_TRGM0_DMA_SRC_SEI_REQ0

#define HPM_TRGM0_DMA_SRC_SEI_REQ0   (0x14UL)

◆ HPM_TRGM0_DMA_SRC_SEI_REQ1

#define HPM_TRGM0_DMA_SRC_SEI_REQ1   (0x15UL)

◆ HPM_TRGM0_DMA_SRC_SEI_REQ2

#define HPM_TRGM0_DMA_SRC_SEI_REQ2   (0x16UL)

◆ HPM_TRGM0_DMA_SRC_SEI_REQ3

#define HPM_TRGM0_DMA_SRC_SEI_REQ3   (0x17UL)

◆ HPM_TRGM0_DMA_SRC_TRGM0

#define HPM_TRGM0_DMA_SRC_TRGM0   (0x18UL)

◆ HPM_TRGM0_DMA_SRC_TRGM1

#define HPM_TRGM0_DMA_SRC_TRGM1   (0x19UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN0

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN0   (0x20UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN1

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN1   (0x21UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN10

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN10   (0x2AUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN11

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN11   (0x2BUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN12

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN12   (0x2CUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN13

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN13   (0x2DUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN14

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN14   (0x2EUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN15

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN15   (0x2FUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN16

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN16   (0x30UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN17

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN17   (0x31UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN18

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN18   (0x32UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN19

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN19   (0x33UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN2

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN2   (0x22UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN20

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN20   (0x34UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN21

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN21   (0x35UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN22

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN22   (0x36UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN23

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN23   (0x37UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN24

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN24   (0x38UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN25

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN25   (0x39UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN26

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN26   (0x3AUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN27

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN27   (0x3BUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN28

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN28   (0x3CUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN29

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN29   (0x3DUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN3

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN3   (0x23UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN30

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN30   (0x3EUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN31

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN31   (0x3FUL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN4

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN4   (0x24UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN5

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN5   (0x25UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN6

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN6   (0x26UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN7

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN7   (0x27UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN8

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN8   (0x28UL)

◆ HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN9

#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN9   (0x29UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN0

#define HPM_TRGM0_FILTER_SRC_PWM0_IN0   (0x0UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN1

#define HPM_TRGM0_FILTER_SRC_PWM0_IN1   (0x1UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN2

#define HPM_TRGM0_FILTER_SRC_PWM0_IN2   (0x2UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN3

#define HPM_TRGM0_FILTER_SRC_PWM0_IN3   (0x3UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN4

#define HPM_TRGM0_FILTER_SRC_PWM0_IN4   (0x4UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN5

#define HPM_TRGM0_FILTER_SRC_PWM0_IN5   (0x5UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN6

#define HPM_TRGM0_FILTER_SRC_PWM0_IN6   (0x6UL)

◆ HPM_TRGM0_FILTER_SRC_PWM0_IN7

#define HPM_TRGM0_FILTER_SRC_PWM0_IN7   (0x7UL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN0

#define HPM_TRGM0_FILTER_SRC_PWM1_IN0   (0x8UL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN1

#define HPM_TRGM0_FILTER_SRC_PWM1_IN1   (0x9UL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN2

#define HPM_TRGM0_FILTER_SRC_PWM1_IN2   (0xAUL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN3

#define HPM_TRGM0_FILTER_SRC_PWM1_IN3   (0xBUL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN4

#define HPM_TRGM0_FILTER_SRC_PWM1_IN4   (0xCUL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN5

#define HPM_TRGM0_FILTER_SRC_PWM1_IN5   (0xDUL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN6

#define HPM_TRGM0_FILTER_SRC_PWM1_IN6   (0xEUL)

◆ HPM_TRGM0_FILTER_SRC_PWM1_IN7

#define HPM_TRGM0_FILTER_SRC_PWM1_IN7   (0xFUL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN0

#define HPM_TRGM0_FILTER_SRC_PWM2_IN0   (0x10UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN1

#define HPM_TRGM0_FILTER_SRC_PWM2_IN1   (0x11UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN2

#define HPM_TRGM0_FILTER_SRC_PWM2_IN2   (0x12UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN3

#define HPM_TRGM0_FILTER_SRC_PWM2_IN3   (0x13UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN4

#define HPM_TRGM0_FILTER_SRC_PWM2_IN4   (0x14UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN5

#define HPM_TRGM0_FILTER_SRC_PWM2_IN5   (0x15UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN6

#define HPM_TRGM0_FILTER_SRC_PWM2_IN6   (0x16UL)

◆ HPM_TRGM0_FILTER_SRC_PWM2_IN7

#define HPM_TRGM0_FILTER_SRC_PWM2_IN7   (0x17UL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN0

#define HPM_TRGM0_FILTER_SRC_PWM3_IN0   (0x18UL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN1

#define HPM_TRGM0_FILTER_SRC_PWM3_IN1   (0x19UL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN2

#define HPM_TRGM0_FILTER_SRC_PWM3_IN2   (0x1AUL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN3

#define HPM_TRGM0_FILTER_SRC_PWM3_IN3   (0x1BUL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN4

#define HPM_TRGM0_FILTER_SRC_PWM3_IN4   (0x1CUL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN5

#define HPM_TRGM0_FILTER_SRC_PWM3_IN5   (0x1DUL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN6

#define HPM_TRGM0_FILTER_SRC_PWM3_IN6   (0x1EUL)

◆ HPM_TRGM0_FILTER_SRC_PWM3_IN7

#define HPM_TRGM0_FILTER_SRC_PWM3_IN7   (0x1FUL)

◆ HPM_TRGM0_INPUT_SRC_ADC0_TRGO

#define HPM_TRGM0_INPUT_SRC_ADC0_TRGO   (0xD8UL)

◆ HPM_TRGM0_INPUT_SRC_ADC1_TRGO

#define HPM_TRGM0_INPUT_SRC_ADC1_TRGO   (0xD9UL)

◆ HPM_TRGM0_INPUT_SRC_ADC2_TRGO

#define HPM_TRGM0_INPUT_SRC_ADC2_TRGO   (0xDAUL)

◆ HPM_TRGM0_INPUT_SRC_ADC3_TRGO

#define HPM_TRGM0_INPUT_SRC_ADC3_TRGO   (0xDBUL)

◆ HPM_TRGM0_INPUT_SRC_CMP0_OUT

#define HPM_TRGM0_INPUT_SRC_CMP0_OUT   (0x30UL)

◆ HPM_TRGM0_INPUT_SRC_CMP1_OUT

#define HPM_TRGM0_INPUT_SRC_CMP1_OUT   (0x31UL)

◆ HPM_TRGM0_INPUT_SRC_CMP2_OUT

#define HPM_TRGM0_INPUT_SRC_CMP2_OUT   (0x32UL)

◆ HPM_TRGM0_INPUT_SRC_CMP3_OUT

#define HPM_TRGM0_INPUT_SRC_CMP3_OUT   (0x33UL)

◆ HPM_TRGM0_INPUT_SRC_CMP4_OUT

#define HPM_TRGM0_INPUT_SRC_CMP4_OUT   (0x34UL)

◆ HPM_TRGM0_INPUT_SRC_CMP5_OUT

#define HPM_TRGM0_INPUT_SRC_CMP5_OUT   (0x35UL)

◆ HPM_TRGM0_INPUT_SRC_CMP6_OUT

#define HPM_TRGM0_INPUT_SRC_CMP6_OUT   (0x36UL)

◆ HPM_TRGM0_INPUT_SRC_CMP7_OUT

#define HPM_TRGM0_INPUT_SRC_CMP7_OUT   (0x37UL)

◆ HPM_TRGM0_INPUT_SRC_DEBUG_FLAG

#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG   (0xE0UL)

◆ HPM_TRGM0_INPUT_SRC_ENET0_PTP3

#define HPM_TRGM0_INPUT_SRC_ENET0_PTP3   (0x3UL)

◆ HPM_TRGM0_INPUT_SRC_ESC_SYNC0

#define HPM_TRGM0_INPUT_SRC_ESC_SYNC0   (0x4UL)

◆ HPM_TRGM0_INPUT_SRC_ESC_SYNC1

#define HPM_TRGM0_INPUT_SRC_ESC_SYNC1   (0xFUL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2   (0x20UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3   (0x21UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2   (0x22UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3   (0x23UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2   (0x24UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3   (0x25UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2   (0x26UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3   (0x27UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR4_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT2   (0x28UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR4_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT3   (0x29UL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR5_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT2   (0x2AUL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR5_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT3   (0x2BUL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR6_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT2   (0x2CUL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR6_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT3   (0x2DUL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR7_OUT2

#define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT2   (0x2EUL)

◆ HPM_TRGM0_INPUT_SRC_GPTMR7_OUT3

#define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT3   (0x2FUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT00

#define HPM_TRGM0_INPUT_SRC_PLB_OUT00   (0x80UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT01

#define HPM_TRGM0_INPUT_SRC_PLB_OUT01   (0x81UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT02

#define HPM_TRGM0_INPUT_SRC_PLB_OUT02   (0x82UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT03

#define HPM_TRGM0_INPUT_SRC_PLB_OUT03   (0x83UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT04

#define HPM_TRGM0_INPUT_SRC_PLB_OUT04   (0x84UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT05

#define HPM_TRGM0_INPUT_SRC_PLB_OUT05   (0x85UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT06

#define HPM_TRGM0_INPUT_SRC_PLB_OUT06   (0x86UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT07

#define HPM_TRGM0_INPUT_SRC_PLB_OUT07   (0x87UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT08

#define HPM_TRGM0_INPUT_SRC_PLB_OUT08   (0x88UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT09

#define HPM_TRGM0_INPUT_SRC_PLB_OUT09   (0x89UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT10

#define HPM_TRGM0_INPUT_SRC_PLB_OUT10   (0x8AUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT11

#define HPM_TRGM0_INPUT_SRC_PLB_OUT11   (0x8BUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT12

#define HPM_TRGM0_INPUT_SRC_PLB_OUT12   (0x8CUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT13

#define HPM_TRGM0_INPUT_SRC_PLB_OUT13   (0x8DUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT14

#define HPM_TRGM0_INPUT_SRC_PLB_OUT14   (0x8EUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT15

#define HPM_TRGM0_INPUT_SRC_PLB_OUT15   (0x8FUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT16

#define HPM_TRGM0_INPUT_SRC_PLB_OUT16   (0x90UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT17

#define HPM_TRGM0_INPUT_SRC_PLB_OUT17   (0x91UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT18

#define HPM_TRGM0_INPUT_SRC_PLB_OUT18   (0x92UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT19

#define HPM_TRGM0_INPUT_SRC_PLB_OUT19   (0x93UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT20

#define HPM_TRGM0_INPUT_SRC_PLB_OUT20   (0x94UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT21

#define HPM_TRGM0_INPUT_SRC_PLB_OUT21   (0x95UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT22

#define HPM_TRGM0_INPUT_SRC_PLB_OUT22   (0x96UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT23

#define HPM_TRGM0_INPUT_SRC_PLB_OUT23   (0x97UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT24

#define HPM_TRGM0_INPUT_SRC_PLB_OUT24   (0x98UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT25

#define HPM_TRGM0_INPUT_SRC_PLB_OUT25   (0x99UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT26

#define HPM_TRGM0_INPUT_SRC_PLB_OUT26   (0x9AUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT27

#define HPM_TRGM0_INPUT_SRC_PLB_OUT27   (0x9BUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT28

#define HPM_TRGM0_INPUT_SRC_PLB_OUT28   (0x9CUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT29

#define HPM_TRGM0_INPUT_SRC_PLB_OUT29   (0x9DUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT30

#define HPM_TRGM0_INPUT_SRC_PLB_OUT30   (0x9EUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT31

#define HPM_TRGM0_INPUT_SRC_PLB_OUT31   (0x9FUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT32

#define HPM_TRGM0_INPUT_SRC_PLB_OUT32   (0xA0UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT33

#define HPM_TRGM0_INPUT_SRC_PLB_OUT33   (0xA1UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT34

#define HPM_TRGM0_INPUT_SRC_PLB_OUT34   (0xA2UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT35

#define HPM_TRGM0_INPUT_SRC_PLB_OUT35   (0xA3UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT36

#define HPM_TRGM0_INPUT_SRC_PLB_OUT36   (0xA4UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT37

#define HPM_TRGM0_INPUT_SRC_PLB_OUT37   (0xA5UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT38

#define HPM_TRGM0_INPUT_SRC_PLB_OUT38   (0xA6UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT39

#define HPM_TRGM0_INPUT_SRC_PLB_OUT39   (0xA7UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT40

#define HPM_TRGM0_INPUT_SRC_PLB_OUT40   (0xA8UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT41

#define HPM_TRGM0_INPUT_SRC_PLB_OUT41   (0xA9UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT42

#define HPM_TRGM0_INPUT_SRC_PLB_OUT42   (0xAAUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT43

#define HPM_TRGM0_INPUT_SRC_PLB_OUT43   (0xABUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT44

#define HPM_TRGM0_INPUT_SRC_PLB_OUT44   (0xACUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT45

#define HPM_TRGM0_INPUT_SRC_PLB_OUT45   (0xADUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT46

#define HPM_TRGM0_INPUT_SRC_PLB_OUT46   (0xAEUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT47

#define HPM_TRGM0_INPUT_SRC_PLB_OUT47   (0xAFUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT48

#define HPM_TRGM0_INPUT_SRC_PLB_OUT48   (0xB0UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT49

#define HPM_TRGM0_INPUT_SRC_PLB_OUT49   (0xB1UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT50

#define HPM_TRGM0_INPUT_SRC_PLB_OUT50   (0xB2UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT51

#define HPM_TRGM0_INPUT_SRC_PLB_OUT51   (0xAAUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT52

#define HPM_TRGM0_INPUT_SRC_PLB_OUT52   (0xB4UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT53

#define HPM_TRGM0_INPUT_SRC_PLB_OUT53   (0xB5UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT54

#define HPM_TRGM0_INPUT_SRC_PLB_OUT54   (0xB6UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT55

#define HPM_TRGM0_INPUT_SRC_PLB_OUT55   (0xB7UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT56

#define HPM_TRGM0_INPUT_SRC_PLB_OUT56   (0xB8UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT57

#define HPM_TRGM0_INPUT_SRC_PLB_OUT57   (0xB9UL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT58

#define HPM_TRGM0_INPUT_SRC_PLB_OUT58   (0xBAUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT59

#define HPM_TRGM0_INPUT_SRC_PLB_OUT59   (0xBBUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT60

#define HPM_TRGM0_INPUT_SRC_PLB_OUT60   (0xBCUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT61

#define HPM_TRGM0_INPUT_SRC_PLB_OUT61   (0xBDUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT62

#define HPM_TRGM0_INPUT_SRC_PLB_OUT62   (0xBEUL)

◆ HPM_TRGM0_INPUT_SRC_PLB_OUT63

#define HPM_TRGM0_INPUT_SRC_PLB_OUT63   (0xBFUL)

◆ HPM_TRGM0_INPUT_SRC_PTPC_CMP0

#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0   (0x6UL)

◆ HPM_TRGM0_INPUT_SRC_PTPC_CMP1

#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1   (0x7UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0

#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0   (0x8UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1

#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1   (0x9UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0   (0x40UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_1

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_1   (0x41UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_2

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_2   (0x42UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_3

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_3   (0x43UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_4

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_4   (0x44UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_5

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_5   (0x45UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_6

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_6   (0x46UL)

◆ HPM_TRGM0_INPUT_SRC_PWM0_TRGO_7

#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_7   (0x47UL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0

#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0   (0xAUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1

#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1   (0xBUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0   (0x48UL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_1

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_1   (0x49UL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_2

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_2   (0x4AUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_3

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_3   (0x4BUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_4

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_4   (0x4CUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_5

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_5   (0x4DUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_6

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_6   (0x4EUL)

◆ HPM_TRGM0_INPUT_SRC_PWM1_TRGO_7

#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_7   (0x46UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_CAPIN0

#define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN0   (0xCUL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_CAPIN1

#define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN1   (0xDUL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_0

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_0   (0x50UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_1

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_1   (0x51UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_2

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_2   (0x52UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_3

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_3   (0x53UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_4

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_4   (0x54UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_5

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_5   (0x55UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_6

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_6   (0x56UL)

◆ HPM_TRGM0_INPUT_SRC_PWM2_TRGO_7

#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_7   (0x57UL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_CAPIN0

#define HPM_TRGM0_INPUT_SRC_PWM3_CAPIN0   (0xEUL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_0

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_0   (0x58UL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_1

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_1   (0x59UL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_2

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_2   (0x5AUL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_3

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_3   (0x5BUL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_4

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_4   (0x5CUL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_5

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_5   (0x5DUL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_6

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_6   (0x5EUL)

◆ HPM_TRGM0_INPUT_SRC_PWM3_TRGO_7

#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_7   (0x5FUL)

◆ HPM_TRGM0_INPUT_SRC_QEI0_TRGO

#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO   (0xE1UL)

◆ HPM_TRGM0_INPUT_SRC_QEI1_TRGO

#define HPM_TRGM0_INPUT_SRC_QEI1_TRGO   (0xE2UL)

◆ HPM_TRGM0_INPUT_SRC_QEI2_TRGO

#define HPM_TRGM0_INPUT_SRC_QEI2_TRGO   (0xE3UL)

◆ HPM_TRGM0_INPUT_SRC_QEI3_TRGO

#define HPM_TRGM0_INPUT_SRC_QEI3_TRGO   (0xE4UL)

◆ HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0

#define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0   (0xDCUL)

◆ HPM_TRGM0_INPUT_SRC_RDC0_TRGO_1

#define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_1   (0xDDUL)

◆ HPM_TRGM0_INPUT_SRC_RDC1_TRGO_0

#define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_0   (0xDEUL)

◆ HPM_TRGM0_INPUT_SRC_RDC1_TRGO_1

#define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_1   (0xDFUL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHA0

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA0   (0xD4UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHA1

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA1   (0xD5UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHA2

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA2   (0xD6UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHA3

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA3   (0xD7UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ0

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ0   (0xCCUL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ1

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ1   (0xCDUL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ2

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ2   (0xCEUL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ3

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ3   (0xCFUL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPL0

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL0   (0xD0UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPL1

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL1   (0xD1UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPL2

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL2   (0xD2UL)

◆ HPM_TRGM0_INPUT_SRC_SDM0_COMPL3

#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL3   (0xD3UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHA0

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA0   (0xC4UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHA1

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA1   (0xC5UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHA2

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA2   (0xC6UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHA3

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA3   (0xC7UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ0

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ0   (0xC0UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ1

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ1   (0xC1UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ2

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ2   (0xC2UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ3

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ3   (0xC3UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPL0

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL0   (0xC8UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPL1

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL1   (0xC9UL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPL2

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL2   (0xCAUL)

◆ HPM_TRGM0_INPUT_SRC_SDM1_COMPL3

#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL3   (0xCBUL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_0

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0   (0x38UL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_1

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1   (0x39UL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_2

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2   (0x3AUL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_3

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3   (0x3BUL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_4

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4   (0x3CUL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_5

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5   (0x3DUL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_6

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6   (0x3EUL)

◆ HPM_TRGM0_INPUT_SRC_SEI_TRGO_7

#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7   (0x3FUL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH00

#define HPM_TRGM0_INPUT_SRC_SYNT_CH00   (0x10UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH01

#define HPM_TRGM0_INPUT_SRC_SYNT_CH01   (0x11UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH02

#define HPM_TRGM0_INPUT_SRC_SYNT_CH02   (0x12UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH03

#define HPM_TRGM0_INPUT_SRC_SYNT_CH03   (0x13UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH04

#define HPM_TRGM0_INPUT_SRC_SYNT_CH04   (0x14UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH05

#define HPM_TRGM0_INPUT_SRC_SYNT_CH05   (0x15UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH06

#define HPM_TRGM0_INPUT_SRC_SYNT_CH06   (0x16UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH07

#define HPM_TRGM0_INPUT_SRC_SYNT_CH07   (0x17UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH08

#define HPM_TRGM0_INPUT_SRC_SYNT_CH08   (0x18UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH09

#define HPM_TRGM0_INPUT_SRC_SYNT_CH09   (0x19UL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH10

#define HPM_TRGM0_INPUT_SRC_SYNT_CH10   (0x1AUL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH11

#define HPM_TRGM0_INPUT_SRC_SYNT_CH11   (0x1BUL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH12

#define HPM_TRGM0_INPUT_SRC_SYNT_CH12   (0x1CUL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH13

#define HPM_TRGM0_INPUT_SRC_SYNT_CH13   (0x1DUL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH14

#define HPM_TRGM0_INPUT_SRC_SYNT_CH14   (0x1EUL)

◆ HPM_TRGM0_INPUT_SRC_SYNT_CH15

#define HPM_TRGM0_INPUT_SRC_SYNT_CH15   (0x1FUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P00

#define HPM_TRGM0_INPUT_SRC_TRGM0_P00   (0x60UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P01

#define HPM_TRGM0_INPUT_SRC_TRGM0_P01   (0x61UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P02

#define HPM_TRGM0_INPUT_SRC_TRGM0_P02   (0x62UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P03

#define HPM_TRGM0_INPUT_SRC_TRGM0_P03   (0x63UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P04

#define HPM_TRGM0_INPUT_SRC_TRGM0_P04   (0x64UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P05

#define HPM_TRGM0_INPUT_SRC_TRGM0_P05   (0x65UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P06

#define HPM_TRGM0_INPUT_SRC_TRGM0_P06   (0x66UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P07

#define HPM_TRGM0_INPUT_SRC_TRGM0_P07   (0x67UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P08

#define HPM_TRGM0_INPUT_SRC_TRGM0_P08   (0x68UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P09

#define HPM_TRGM0_INPUT_SRC_TRGM0_P09   (0x69UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P10

#define HPM_TRGM0_INPUT_SRC_TRGM0_P10   (0x6AUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P11

#define HPM_TRGM0_INPUT_SRC_TRGM0_P11   (0x6BUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P12

#define HPM_TRGM0_INPUT_SRC_TRGM0_P12   (0x6CUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P13

#define HPM_TRGM0_INPUT_SRC_TRGM0_P13   (0x6DUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P14

#define HPM_TRGM0_INPUT_SRC_TRGM0_P14   (0x6EUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P15

#define HPM_TRGM0_INPUT_SRC_TRGM0_P15   (0x6FUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P16

#define HPM_TRGM0_INPUT_SRC_TRGM0_P16   (0x70UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P17

#define HPM_TRGM0_INPUT_SRC_TRGM0_P17   (0x71UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P18

#define HPM_TRGM0_INPUT_SRC_TRGM0_P18   (0x72UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P19

#define HPM_TRGM0_INPUT_SRC_TRGM0_P19   (0x73UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P20

#define HPM_TRGM0_INPUT_SRC_TRGM0_P20   (0x74UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P21

#define HPM_TRGM0_INPUT_SRC_TRGM0_P21   (0x75UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P22

#define HPM_TRGM0_INPUT_SRC_TRGM0_P22   (0x76UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P23

#define HPM_TRGM0_INPUT_SRC_TRGM0_P23   (0x77UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P24

#define HPM_TRGM0_INPUT_SRC_TRGM0_P24   (0x78UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P25

#define HPM_TRGM0_INPUT_SRC_TRGM0_P25   (0x79UL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P26

#define HPM_TRGM0_INPUT_SRC_TRGM0_P26   (0x7AUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P27

#define HPM_TRGM0_INPUT_SRC_TRGM0_P27   (0x7BUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P28

#define HPM_TRGM0_INPUT_SRC_TRGM0_P28   (0x7CUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P29

#define HPM_TRGM0_INPUT_SRC_TRGM0_P29   (0x7DUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P30

#define HPM_TRGM0_INPUT_SRC_TRGM0_P30   (0x7EUL)

◆ HPM_TRGM0_INPUT_SRC_TRGM0_P31

#define HPM_TRGM0_INPUT_SRC_TRGM0_P31   (0x7FUL)

◆ HPM_TRGM0_INPUT_SRC_TSN_PTP3

#define HPM_TRGM0_INPUT_SRC_TSN_PTP3   (0x5UL)

◆ HPM_TRGM0_INPUT_SRC_USB0_SOF

#define HPM_TRGM0_INPUT_SRC_USB0_SOF   (0x2UL)

◆ HPM_TRGM0_INPUT_SRC_VDD

#define HPM_TRGM0_INPUT_SRC_VDD   (0x1UL)

◆ HPM_TRGM0_INPUT_SRC_VSS

#define HPM_TRGM0_INPUT_SRC_VSS   (0x0UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI

#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI   (0x30UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI

#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI   (0x31UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI

#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI   (0x32UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI

#define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI   (0x33UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A   (0x34UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B   (0x35UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C   (0x36UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A   (0x37UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B   (0x38UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C   (0x39UL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A   (0x3AUL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B   (0x3BUL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C   (0x3CUL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A   (0x3DUL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B   (0x3EUL)

◆ HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C

#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C   (0x3FUL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP0_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN   (0x60UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP1_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN   (0x61UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP2_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP2_WIN   (0x62UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP3_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP3_WIN   (0x63UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP4_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP4_WIN   (0x64UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP5_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP5_WIN   (0x65UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP6_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP6_WIN   (0x66UL)

◆ HPM_TRGM0_OUTPUT_SRC_CMP7_WIN

#define HPM_TRGM0_OUTPUT_SRC_CMP7_WIN   (0x67UL)

◆ HPM_TRGM0_OUTPUT_SRC_ESC_TRIG_IN

#define HPM_TRGM0_OUTPUT_SRC_ESC_TRIG_IN   (0xF1UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2   (0x68UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3   (0x69UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI   (0x6AUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2   (0x6BUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3   (0x6CUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI   (0x6DUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2   (0x6EUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3   (0x6FUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI   (0x70UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2   (0x71UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3   (0x72UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI   (0x73UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN2   (0x74UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN3   (0x75UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR4_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_SYNCI   (0x76UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN2   (0x77UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN3   (0x78UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR5_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_SYNCI   (0x79UL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN2   (0x7AUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN3   (0x7BUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR6_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_SYNCI   (0x7CUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN2

#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN2   (0x7DUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN3

#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN3   (0x7EUL)

◆ HPM_TRGM0_OUTPUT_SRC_GPTMR7_SYNCI

#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_SYNCI   (0x7FUL)

◆ HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP

#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP   (0xE0UL)

◆ HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP

#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP   (0xE1UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0   (0x0UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1   (0x1UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO10

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO10   (0xAUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO11

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO11   (0xBUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO12

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO12   (0xCUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO13

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO13   (0xDUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO14

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO14   (0xEUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO15

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO15   (0xFUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO16

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO16   (0x10UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO17

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO17   (0x11UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO18

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO18   (0x12UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO19

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO19   (0x13UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2   (0x2UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO20

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO20   (0x14UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO21

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO21   (0x15UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO22

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO22   (0x16UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO23

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO23   (0x17UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO24

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO24   (0x18UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO25

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO25   (0x19UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO26

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO26   (0x1AUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO27

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO27   (0x1BUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO28

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO28   (0x1CUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO29

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO29   (0x1DUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3   (0x3UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO30

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO30   (0x1EUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO31

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO31   (0x1FUL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4   (0x4UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5   (0x5UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6   (0x6UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7   (0x7UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO8

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO8   (0x8UL)

◆ HPM_TRGM0_OUTPUT_SRC_MOT_GPIO9

#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO9   (0x9UL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN0   (0xE9UL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN1   (0xEAUL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN2   (0xEBUL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN3   (0xECUL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN0   (0xEDUL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN1   (0xEEUL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN2   (0xEFUL)

◆ HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN3   (0xF0UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_00

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00   (0x80UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_01

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01   (0x81UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_02

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02   (0x82UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_03

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03   (0x83UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_04

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04   (0x84UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_05

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05   (0x85UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_06

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06   (0x86UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_07

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07   (0x87UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_08

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08   (0x88UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_09

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09   (0x89UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_10

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10   (0x8AUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_11

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11   (0x8BUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_12

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12   (0x8CUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_13

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13   (0x8DUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_14

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14   (0x8EUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_15

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15   (0x8FUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_16

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16   (0x90UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_17

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17   (0x91UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_18

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18   (0x92UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_19

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19   (0x93UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_20

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20   (0x94UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_21

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21   (0x95UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_22

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22   (0x96UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_23

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23   (0x97UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_24

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24   (0x98UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_25

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25   (0x99UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_26

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26   (0x9AUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_27

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27   (0x9BUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_28

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28   (0x9CUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_29

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29   (0x9DUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_30

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30   (0x9EUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_31

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31   (0x9FUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_32

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_32   (0xA0UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_33

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_33   (0xA1UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_34

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_34   (0xA2UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_35

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_35   (0xA3UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_36

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_36   (0xA4UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_37

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_37   (0xA5UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_38

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_38   (0xA6UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_39

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_39   (0xA7UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_40

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_40   (0xA8UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_41

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_41   (0xA9UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_42

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_42   (0xAAUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_43

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_43   (0xABUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_44

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_44   (0xACUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_45

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_45   (0xADUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_46

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_46   (0xAEUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_47

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_47   (0xAFUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_48

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_48   (0xB0UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_49

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_49   (0xB1UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_50

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_50   (0xB2UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_51

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_51   (0xB3UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_52

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_52   (0xB4UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_53

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_53   (0xB5UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_54

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_54   (0xB6UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_55

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_55   (0xB7UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_56

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_56   (0xB8UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_57

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_57   (0xB9UL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_58

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_58   (0xBAUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_59

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_59   (0xBBUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_60

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_60   (0xBCUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_61

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_61   (0xBDUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_62

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_62   (0xBEUL)

◆ HPM_TRGM0_OUTPUT_SRC_PLB_IN_63

#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_63   (0xBFUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN0   (0xC0UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN1   (0xC1UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN2   (0xC2UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN3   (0xC3UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN4

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN4   (0xC4UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN5

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN5   (0xC5UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN6

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN6   (0xC6UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN7

#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN7   (0xC7UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0   (0xC8UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1   (0xC9UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2   (0xCAUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN3   (0xCBUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN4

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN4   (0xCCUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN5

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN5   (0xCDUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN6

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN6   (0xCEUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN7

#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN7   (0xCFUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN0   (0xD0UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN1   (0xD1UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN2   (0xD2UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN3   (0xD3UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN4

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN4   (0xD4UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN5

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN5   (0xD5UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN6

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN6   (0xD6UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN7

#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN7   (0xD7UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN0   (0xD8UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN1   (0xD9UL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN2   (0xDAUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN3   (0xDBUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN4

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN4   (0xDCUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN5

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN5   (0xDDUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN6

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN6   (0xDEUL)

◆ HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN7

#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN7   (0xDFUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE

#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE   (0x4CUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN

#define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN   (0x48UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE

#define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE   (0x4DUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN

#define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN   (0x49UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI2_PAUSE

#define HPM_TRGM0_OUTPUT_SRC_QEI2_PAUSE   (0x4EUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI2_TRIG_IN

#define HPM_TRGM0_OUTPUT_SRC_QEI2_TRIG_IN   (0x4AUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI3_PAUSE

#define HPM_TRGM0_OUTPUT_SRC_QEI3_PAUSE   (0x4FUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEI3_TRIG_IN

#define HPM_TRGM0_OUTPUT_SRC_QEI3_TRIG_IN   (0x4BUL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0   (0x50UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1   (0x51UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0   (0x52UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1   (0x53UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN0   (0x54UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN1   (0x55UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN0   (0x56UL)

◆ HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN1   (0x57UL)

◆ HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN0   (0x44UL)

◆ HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN1   (0x45UL)

◆ HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN0   (0x46UL)

◆ HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN1   (0x47UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC0

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC0   (0x20UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC1

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC1   (0x21UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC10

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC10   (0x2AUL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC11

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC11   (0x2BUL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC12

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC12   (0x2CUL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC13

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC13   (0x2DUL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC14

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC14   (0x2EUL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15   (0x2FUL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC2

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC2   (0x22UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC3

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC3   (0x23UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC4

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC4   (0x24UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC5

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC5   (0x25UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC6

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC6   (0x26UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC7

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC7   (0x27UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC8

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC8   (0x28UL)

◆ HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC9

#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC9   (0x29UL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0   (0x58UL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1   (0x59UL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2   (0x5AUL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3   (0x5BUL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4   (0x5CUL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5   (0x5DUL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6   (0x5EUL)

◆ HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7

#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7   (0x5FUL)

◆ HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG

#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG   (0xE4UL)

◆ HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0

#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0   (0xE7UL)

◆ HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1

#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1   (0xE8UL)

◆ HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0

#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0   (0xE5UL)

◆ HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1

#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1   (0xE6UL)

◆ HPM_TRGM0_OUTPUT_SRC_UART_TRIG0

#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0   (0xE2UL)

◆ HPM_TRGM0_OUTPUT_SRC_UART_TRIG1

#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1   (0xE3UL)

◆ HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0   (0x40UL)

◆ HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN1   (0x41UL)

◆ HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN0

#define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN0   (0x42UL)

◆ HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN1

#define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN1   (0x43UL)