HPM SDK
HPMicro Software Development Kit
Macros
hpm_csr_regs.h File Reference

Go to the source code of this file.

Macros

#define CSR_USTATUS   (0x0)
 
#define CSR_UIE   (0x4)
 
#define CSR_UTVEC   (0x5)
 
#define CSR_USCRATCH   (0x40)
 
#define CSR_UEPC   (0x41)
 
#define CSR_UCAUSE   (0x42)
 
#define CSR_UTVAL   (0x43)
 
#define CSR_UIP   (0x44)
 
#define CSR_MSTATUS   (0x300)
 
#define CSR_MISA   (0x301)
 
#define CSR_MIE   (0x304)
 
#define CSR_MTVEC   (0x305)
 
#define CSR_MCOUNTEREN   (0x306)
 
#define CSR_MHPMEVENT3   (0x323)
 
#define CSR_MHPMEVENT4   (0x324)
 
#define CSR_MHPMEVENT5   (0x325)
 
#define CSR_MHPMEVENT6   (0x326)
 
#define CSR_MSCRATCH   (0x340)
 
#define CSR_MEPC   (0x341)
 
#define CSR_MCAUSE   (0x342)
 
#define CSR_MTVAL   (0x343)
 
#define CSR_MIP   (0x344)
 
#define CSR_PMPCFG0   (0x3A0)
 
#define CSR_PMPCFG1   (0x3A1)
 
#define CSR_PMPCFG2   (0x3A2)
 
#define CSR_PMPCFG3   (0x3A3)
 
#define CSR_PMPADDR0   (0x3B0)
 
#define CSR_PMPADDR1   (0x3B1)
 
#define CSR_PMPADDR2   (0x3B2)
 
#define CSR_PMPADDR3   (0x3B3)
 
#define CSR_PMPADDR4   (0x3B4)
 
#define CSR_PMPADDR5   (0x3B5)
 
#define CSR_PMPADDR6   (0x3B6)
 
#define CSR_PMPADDR7   (0x3B7)
 
#define CSR_PMPADDR8   (0x3B8)
 
#define CSR_PMPADDR9   (0x3B9)
 
#define CSR_PMPADDR10   (0x3BA)
 
#define CSR_PMPADDR11   (0x3BB)
 
#define CSR_PMPADDR12   (0x3BC)
 
#define CSR_PMPADDR13   (0x3BD)
 
#define CSR_PMPADDR14   (0x3BE)
 
#define CSR_PMPADDR15   (0x3BF)
 
#define CSR_TSELECT   (0x7A0)
 
#define CSR_TDATA1   (0x7A1)
 
#define CSR_MCONTROL   (0x7A1)
 
#define CSR_ICOUNT   (0x7A1)
 
#define CSR_ITRIGGER   (0x7A1)
 
#define CSR_ETRIGGER   (0x7A1)
 
#define CSR_TDATA2   (0x7A2)
 
#define CSR_TDATA3   (0x7A3)
 
#define CSR_TEXTRA   (0x7A3)
 
#define CSR_TINFO   (0x7A4)
 
#define CSR_TCONTROL   (0x7A5)
 
#define CSR_MCONTEXT   (0x7A8)
 
#define CSR_SCONTEXT   (0x7AA)
 
#define CSR_DCSR   (0x7B0)
 
#define CSR_DPC   (0x7B1)
 
#define CSR_DSCRATCH0   (0x7B2)
 
#define CSR_DSCRATCH1   (0x7B3)
 
#define CSR_MCYCLE   (0xB00)
 
#define CSR_MINSTRET   (0xB02)
 
#define CSR_MHPMCOUNTER3   (0xB03)
 
#define CSR_MHPMCOUNTER4   (0xB04)
 
#define CSR_MHPMCOUNTER5   (0xB05)
 
#define CSR_MHPMCOUNTER6   (0xB06)
 
#define CSR_MCYCLEH   (0xB80)
 
#define CSR_MINSTRETH   (0xB82)
 
#define CSR_MHPMCOUNTER3H   (0xB83)
 
#define CSR_MHPMCOUNTER4H   (0xB84)
 
#define CSR_MHPMCOUNTER5H   (0xB85)
 
#define CSR_MHPMCOUNTER6H   (0xB86)
 
#define CSR_CYCLE   (0xC00)
 
#define CSR_CYCLEH   (0xC80)
 
#define CSR_MVENDORID   (0xF11)
 
#define CSR_MARCHID   (0xF12)
 
#define CSR_MIMPID   (0xF13)
 
#define CSR_MHARTID   (0xF14)
 
#define CSR_MCOUNTINHIBIT   (0x320)
 
#define CSR_MILMB   (0x7C0)
 
#define CSR_MDLMB   (0x7C1)
 
#define CSR_MECC_CODE   (0x7C2)
 
#define CSR_MNVEC   (0x7C3)
 
#define CSR_MXSTATUS   (0x7C4)
 
#define CSR_MPFT_CTL   (0x7C5)
 
#define CSR_MHSP_CTL   (0x7C6)
 
#define CSR_MSP_BOUND   (0x7C7)
 
#define CSR_MSP_BASE   (0x7C8)
 
#define CSR_MDCAUSE   (0x7C9)
 
#define CSR_MCACHE_CTL   (0x7CA)
 
#define CSR_MCCTLBEGINADDR   (0x7CB)
 
#define CSR_MCCTLCOMMAND   (0x7CC)
 
#define CSR_MCCTLDATA   (0x7CD)
 
#define CSR_MCOUNTERWEN   (0x7CE)
 
#define CSR_MCOUNTERINTEN   (0x7CF)
 
#define CSR_MMISC_CTL   (0x7D0)
 
#define CSR_MCOUNTERMASK_M   (0x7D1)
 
#define CSR_MCOUNTERMASK_S   (0x7D2)
 
#define CSR_MCOUNTERMASK_U   (0x7D3)
 
#define CSR_MCOUNTEROVF   (0x7D4)
 
#define CSR_DEXC2DBG   (0x7E0)
 
#define CSR_DDCAUSE   (0x7E1)
 
#define CSR_UITB   (0x800)
 
#define CSR_UCODE   (0x801)
 
#define CSR_UDCAUSE   (0x809)
 
#define CSR_UCCTLBEGINADDR   (0x80B)
 
#define CSR_UCCTLCOMMAND   (0x80C)
 
#define CSR_MICM_CFG   (0xFC0)
 
#define CSR_MDCM_CFG   (0xFC1)
 
#define CSR_MMSC_CFG   (0xFC2)
 
#define CSR_MMSC_CFG2   (0xFC3)
 
#define CSR_USTATUS_UPIE_MASK   (0x10U)
 
#define CSR_USTATUS_UPIE_SHIFT   (4U)
 
#define CSR_USTATUS_UPIE_SET(x)   (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK)
 
#define CSR_USTATUS_UPIE_GET(x)   (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT)
 
#define CSR_USTATUS_UIE_MASK   (0x1U)
 
#define CSR_USTATUS_UIE_SHIFT   (0U)
 
#define CSR_USTATUS_UIE_SET(x)   (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK)
 
#define CSR_USTATUS_UIE_GET(x)   (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT)
 
#define CSR_UIE_UEIE_MASK   (0x100U)
 
#define CSR_UIE_UEIE_SHIFT   (8U)
 
#define CSR_UIE_UEIE_SET(x)   (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK)
 
#define CSR_UIE_UEIE_GET(x)   (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT)
 
#define CSR_UIE_UTIE_MASK   (0x10U)
 
#define CSR_UIE_UTIE_SHIFT   (4U)
 
#define CSR_UIE_UTIE_SET(x)   (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK)
 
#define CSR_UIE_UTIE_GET(x)   (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT)
 
#define CSR_UIE_USIE_MASK   (0x1U)
 
#define CSR_UIE_USIE_SHIFT   (0U)
 
#define CSR_UIE_USIE_SET(x)   (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK)
 
#define CSR_UIE_USIE_GET(x)   (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT)
 
#define CSR_UTVEC_BASE_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_UTVEC_BASE_31_2_SHIFT   (2U)
 
#define CSR_UTVEC_BASE_31_2_SET(x)   (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK)
 
#define CSR_UTVEC_BASE_31_2_GET(x)   (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT)
 
#define CSR_USCRATCH_USCRATCH_MASK   (0xFFFFFFFFUL)
 
#define CSR_USCRATCH_USCRATCH_SHIFT   (0U)
 
#define CSR_USCRATCH_USCRATCH_SET(x)   (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK)
 
#define CSR_USCRATCH_USCRATCH_GET(x)   (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT)
 
#define CSR_UEPC_EPC_MASK   (0xFFFFFFFEUL)
 
#define CSR_UEPC_EPC_SHIFT   (1U)
 
#define CSR_UEPC_EPC_SET(x)   (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK)
 
#define CSR_UEPC_EPC_GET(x)   (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT)
 
#define CSR_UCAUSE_INTERRUPT_MASK   (0x80000000UL)
 
#define CSR_UCAUSE_INTERRUPT_SHIFT   (31U)
 
#define CSR_UCAUSE_INTERRUPT_SET(x)   (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK)
 
#define CSR_UCAUSE_INTERRUPT_GET(x)   (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT)
 
#define CSR_UCAUSE_EXCEPTION_CODE_MASK   (0x3FFU)
 
#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT   (0U)
 
#define CSR_UCAUSE_EXCEPTION_CODE_SET(x)   (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK)
 
#define CSR_UCAUSE_EXCEPTION_CODE_GET(x)   (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT)
 
#define CSR_UTVAL_UTVAL_MASK   (0xFFFFFFFFUL)
 
#define CSR_UTVAL_UTVAL_SHIFT   (0U)
 
#define CSR_UTVAL_UTVAL_SET(x)   (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK)
 
#define CSR_UTVAL_UTVAL_GET(x)   (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT)
 
#define CSR_UIP_UEIP_MASK   (0x100U)
 
#define CSR_UIP_UEIP_SHIFT   (8U)
 
#define CSR_UIP_UEIP_SET(x)   (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK)
 
#define CSR_UIP_UEIP_GET(x)   (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT)
 
#define CSR_UIP_UTIP_MASK   (0x10U)
 
#define CSR_UIP_UTIP_SHIFT   (4U)
 
#define CSR_UIP_UTIP_SET(x)   (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK)
 
#define CSR_UIP_UTIP_GET(x)   (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT)
 
#define CSR_UIP_USIP_MASK   (0x1U)
 
#define CSR_UIP_USIP_SHIFT   (0U)
 
#define CSR_UIP_USIP_SET(x)   (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK)
 
#define CSR_UIP_USIP_GET(x)   (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT)
 
#define CSR_MSTATUS_SD_MASK   (0x80000000UL)
 
#define CSR_MSTATUS_SD_SHIFT   (31U)
 
#define CSR_MSTATUS_SD_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT)
 
#define CSR_MSTATUS_MXR_MASK   (0x80000UL)
 
#define CSR_MSTATUS_MXR_SHIFT   (19U)
 
#define CSR_MSTATUS_MXR_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK)
 
#define CSR_MSTATUS_MXR_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT)
 
#define CSR_MSTATUS_MPRV_MASK   (0x20000UL)
 
#define CSR_MSTATUS_MPRV_SHIFT   (17U)
 
#define CSR_MSTATUS_MPRV_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK)
 
#define CSR_MSTATUS_MPRV_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT)
 
#define CSR_MSTATUS_XS_MASK   (0x18000UL)
 
#define CSR_MSTATUS_XS_SHIFT   (15U)
 
#define CSR_MSTATUS_XS_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT)
 
#define CSR_MSTATUS_FS_MASK   (0x6000U)
 
#define CSR_MSTATUS_FS_SHIFT   (13U)
 
#define CSR_MSTATUS_FS_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK)
 
#define CSR_MSTATUS_FS_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT)
 
#define CSR_MSTATUS_MPP_MASK   (0x1800U)
 
#define CSR_MSTATUS_MPP_SHIFT   (11U)
 
#define CSR_MSTATUS_MPP_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK)
 
#define CSR_MSTATUS_MPP_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT)
 
#define CSR_MSTATUS_MPIE_MASK   (0x80U)
 
#define CSR_MSTATUS_MPIE_SHIFT   (7U)
 
#define CSR_MSTATUS_MPIE_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK)
 
#define CSR_MSTATUS_MPIE_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT)
 
#define CSR_MSTATUS_UPIE_MASK   (0x10U)
 
#define CSR_MSTATUS_UPIE_SHIFT   (4U)
 
#define CSR_MSTATUS_UPIE_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK)
 
#define CSR_MSTATUS_UPIE_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT)
 
#define CSR_MSTATUS_MIE_MASK   (0x8U)
 
#define CSR_MSTATUS_MIE_SHIFT   (3U)
 
#define CSR_MSTATUS_MIE_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK)
 
#define CSR_MSTATUS_MIE_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT)
 
#define CSR_MSTATUS_UIE_MASK   (0x1U)
 
#define CSR_MSTATUS_UIE_SHIFT   (0U)
 
#define CSR_MSTATUS_UIE_SET(x)   (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK)
 
#define CSR_MSTATUS_UIE_GET(x)   (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT)
 
#define CSR_MISA_BASE_MASK   (0xC0000000UL)
 
#define CSR_MISA_BASE_SHIFT   (30U)
 
#define CSR_MISA_BASE_GET(x)   (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT)
 
#define CSR_MISA_Z_MASK   (0x2000000UL)
 
#define CSR_MISA_Z_SHIFT   (25U)
 
#define CSR_MISA_Z_GET(x)   (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT)
 
#define CSR_MISA_Y_MASK   (0x1000000UL)
 
#define CSR_MISA_Y_SHIFT   (24U)
 
#define CSR_MISA_Y_GET(x)   (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT)
 
#define CSR_MISA_X_MASK   (0x800000UL)
 
#define CSR_MISA_X_SHIFT   (23U)
 
#define CSR_MISA_X_GET(x)   (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT)
 
#define CSR_MISA_W_MASK   (0x400000UL)
 
#define CSR_MISA_W_SHIFT   (22U)
 
#define CSR_MISA_W_GET(x)   (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT)
 
#define CSR_MISA_V_MASK   (0x200000UL)
 
#define CSR_MISA_V_SHIFT   (21U)
 
#define CSR_MISA_V_GET(x)   (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT)
 
#define CSR_MISA_U_MASK   (0x100000UL)
 
#define CSR_MISA_U_SHIFT   (20U)
 
#define CSR_MISA_U_GET(x)   (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT)
 
#define CSR_MISA_T_MASK   (0x80000UL)
 
#define CSR_MISA_T_SHIFT   (19U)
 
#define CSR_MISA_T_GET(x)   (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT)
 
#define CSR_MISA_S_MASK   (0x40000UL)
 
#define CSR_MISA_S_SHIFT   (18U)
 
#define CSR_MISA_S_GET(x)   (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT)
 
#define CSR_MISA_R_MASK   (0x20000UL)
 
#define CSR_MISA_R_SHIFT   (17U)
 
#define CSR_MISA_R_GET(x)   (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT)
 
#define CSR_MISA_Q_MASK   (0x10000UL)
 
#define CSR_MISA_Q_SHIFT   (16U)
 
#define CSR_MISA_Q_GET(x)   (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT)
 
#define CSR_MISA_P_MASK   (0x8000U)
 
#define CSR_MISA_P_SHIFT   (15U)
 
#define CSR_MISA_P_GET(x)   (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT)
 
#define CSR_MISA_O_MASK   (0x4000U)
 
#define CSR_MISA_O_SHIFT   (14U)
 
#define CSR_MISA_O_GET(x)   (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT)
 
#define CSR_MISA_N_MASK   (0x2000U)
 
#define CSR_MISA_N_SHIFT   (13U)
 
#define CSR_MISA_N_GET(x)   (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT)
 
#define CSR_MISA_M_MASK   (0x1000U)
 
#define CSR_MISA_M_SHIFT   (12U)
 
#define CSR_MISA_M_GET(x)   (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT)
 
#define CSR_MISA_L_MASK   (0x800U)
 
#define CSR_MISA_L_SHIFT   (11U)
 
#define CSR_MISA_L_GET(x)   (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT)
 
#define CSR_MISA_K_MASK   (0x400U)
 
#define CSR_MISA_K_SHIFT   (10U)
 
#define CSR_MISA_K_GET(x)   (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT)
 
#define CSR_MISA_J_MASK   (0x200U)
 
#define CSR_MISA_J_SHIFT   (9U)
 
#define CSR_MISA_J_GET(x)   (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT)
 
#define CSR_MISA_I_MASK   (0x100U)
 
#define CSR_MISA_I_SHIFT   (8U)
 
#define CSR_MISA_I_GET(x)   (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT)
 
#define CSR_MISA_H_MASK   (0x80U)
 
#define CSR_MISA_H_SHIFT   (7U)
 
#define CSR_MISA_H_GET(x)   (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT)
 
#define CSR_MISA_G_MASK   (0x40U)
 
#define CSR_MISA_G_SHIFT   (6U)
 
#define CSR_MISA_G_GET(x)   (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT)
 
#define CSR_MISA_F_MASK   (0x20U)
 
#define CSR_MISA_F_SHIFT   (5U)
 
#define CSR_MISA_F_GET(x)   (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT)
 
#define CSR_MISA_E_MASK   (0x10U)
 
#define CSR_MISA_E_SHIFT   (4U)
 
#define CSR_MISA_E_GET(x)   (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT)
 
#define CSR_MISA_D_MASK   (0x8U)
 
#define CSR_MISA_D_SHIFT   (3U)
 
#define CSR_MISA_D_GET(x)   (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT)
 
#define CSR_MISA_C_MASK   (0x4U)
 
#define CSR_MISA_C_SHIFT   (2U)
 
#define CSR_MISA_C_GET(x)   (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT)
 
#define CSR_MISA_B_MASK   (0x2U)
 
#define CSR_MISA_B_SHIFT   (1U)
 
#define CSR_MISA_B_GET(x)   (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT)
 
#define CSR_MISA_A_MASK   (0x1U)
 
#define CSR_MISA_A_SHIFT   (0U)
 
#define CSR_MISA_A_GET(x)   (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT)
 
#define CSR_MIE_PMOVI_MASK   (0x40000UL)
 
#define CSR_MIE_PMOVI_SHIFT   (18U)
 
#define CSR_MIE_PMOVI_SET(x)   (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK)
 
#define CSR_MIE_PMOVI_GET(x)   (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT)
 
#define CSR_MIE_BWEI_MASK   (0x20000UL)
 
#define CSR_MIE_BWEI_SHIFT   (17U)
 
#define CSR_MIE_BWEI_SET(x)   (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK)
 
#define CSR_MIE_BWEI_GET(x)   (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT)
 
#define CSR_MIE_IMECCI_MASK   (0x10000UL)
 
#define CSR_MIE_IMECCI_SHIFT   (16U)
 
#define CSR_MIE_IMECCI_SET(x)   (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK)
 
#define CSR_MIE_IMECCI_GET(x)   (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT)
 
#define CSR_MIE_MEIE_MASK   (0x800U)
 
#define CSR_MIE_MEIE_SHIFT   (11U)
 
#define CSR_MIE_MEIE_SET(x)   (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK)
 
#define CSR_MIE_MEIE_GET(x)   (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT)
 
#define CSR_MIE_UEIE_MASK   (0x100U)
 
#define CSR_MIE_UEIE_SHIFT   (8U)
 
#define CSR_MIE_UEIE_SET(x)   (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK)
 
#define CSR_MIE_UEIE_GET(x)   (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT)
 
#define CSR_MIE_MTIE_MASK   (0x80U)
 
#define CSR_MIE_MTIE_SHIFT   (7U)
 
#define CSR_MIE_MTIE_SET(x)   (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK)
 
#define CSR_MIE_MTIE_GET(x)   (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT)
 
#define CSR_MIE_UTIE_MASK   (0x10U)
 
#define CSR_MIE_UTIE_SHIFT   (4U)
 
#define CSR_MIE_UTIE_SET(x)   (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK)
 
#define CSR_MIE_UTIE_GET(x)   (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT)
 
#define CSR_MIE_MSIE_MASK   (0x8U)
 
#define CSR_MIE_MSIE_SHIFT   (3U)
 
#define CSR_MIE_MSIE_SET(x)   (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK)
 
#define CSR_MIE_MSIE_GET(x)   (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT)
 
#define CSR_MIE_USIE_MASK   (0x1U)
 
#define CSR_MIE_USIE_SHIFT   (0U)
 
#define CSR_MIE_USIE_SET(x)   (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK)
 
#define CSR_MIE_USIE_GET(x)   (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT)
 
#define CSR_MTVEC_BASE_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_MTVEC_BASE_31_2_SHIFT   (2U)
 
#define CSR_MTVEC_BASE_31_2_SET(x)   (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK)
 
#define CSR_MTVEC_BASE_31_2_GET(x)   (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT)
 
#define CSR_MCOUNTEREN_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTEREN_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTEREN_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK)
 
#define CSR_MCOUNTEREN_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT)
 
#define CSR_MCOUNTEREN_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTEREN_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTEREN_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK)
 
#define CSR_MCOUNTEREN_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT)
 
#define CSR_MCOUNTEREN_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTEREN_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTEREN_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK)
 
#define CSR_MCOUNTEREN_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT)
 
#define CSR_MCOUNTEREN_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTEREN_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTEREN_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK)
 
#define CSR_MCOUNTEREN_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT)
 
#define CSR_MCOUNTEREN_IR_MASK   (0x4U)
 
#define CSR_MCOUNTEREN_IR_SHIFT   (2U)
 
#define CSR_MCOUNTEREN_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK)
 
#define CSR_MCOUNTEREN_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT)
 
#define CSR_MCOUNTEREN_TM_MASK   (0x2U)
 
#define CSR_MCOUNTEREN_TM_SHIFT   (1U)
 
#define CSR_MCOUNTEREN_TM_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK)
 
#define CSR_MCOUNTEREN_TM_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT)
 
#define CSR_MCOUNTEREN_CY_MASK   (0x1U)
 
#define CSR_MCOUNTEREN_CY_SHIFT   (0U)
 
#define CSR_MCOUNTEREN_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK)
 
#define CSR_MCOUNTEREN_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT)
 
#define CSR_MHPMEVENT3_SEL_MASK   (0x1F0U)
 
#define CSR_MHPMEVENT3_SEL_SHIFT   (4U)
 
#define CSR_MHPMEVENT3_SEL_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK)
 
#define CSR_MHPMEVENT3_SEL_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT)
 
#define CSR_MHPMEVENT3_TYPE_MASK   (0xFU)
 
#define CSR_MHPMEVENT3_TYPE_SHIFT   (0U)
 
#define CSR_MHPMEVENT3_TYPE_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK)
 
#define CSR_MHPMEVENT3_TYPE_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT)
 
#define CSR_MHPMEVENT4_SEL_MASK   (0x1F0U)
 
#define CSR_MHPMEVENT4_SEL_SHIFT   (4U)
 
#define CSR_MHPMEVENT4_SEL_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK)
 
#define CSR_MHPMEVENT4_SEL_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT)
 
#define CSR_MHPMEVENT4_TYPE_MASK   (0xFU)
 
#define CSR_MHPMEVENT4_TYPE_SHIFT   (0U)
 
#define CSR_MHPMEVENT4_TYPE_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK)
 
#define CSR_MHPMEVENT4_TYPE_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT)
 
#define CSR_MHPMEVENT5_SEL_MASK   (0x1F0U)
 
#define CSR_MHPMEVENT5_SEL_SHIFT   (4U)
 
#define CSR_MHPMEVENT5_SEL_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK)
 
#define CSR_MHPMEVENT5_SEL_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT)
 
#define CSR_MHPMEVENT5_TYPE_MASK   (0xFU)
 
#define CSR_MHPMEVENT5_TYPE_SHIFT   (0U)
 
#define CSR_MHPMEVENT5_TYPE_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK)
 
#define CSR_MHPMEVENT5_TYPE_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT)
 
#define CSR_MHPMEVENT6_SEL_MASK   (0x1F0U)
 
#define CSR_MHPMEVENT6_SEL_SHIFT   (4U)
 
#define CSR_MHPMEVENT6_SEL_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK)
 
#define CSR_MHPMEVENT6_SEL_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT)
 
#define CSR_MHPMEVENT6_TYPE_MASK   (0xFU)
 
#define CSR_MHPMEVENT6_TYPE_SHIFT   (0U)
 
#define CSR_MHPMEVENT6_TYPE_SET(x)   (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK)
 
#define CSR_MHPMEVENT6_TYPE_GET(x)   (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT)
 
#define CSR_MSCRATCH_MSCRATCH_MASK   (0xFFFFFFFFUL)
 
#define CSR_MSCRATCH_MSCRATCH_SHIFT   (0U)
 
#define CSR_MSCRATCH_MSCRATCH_SET(x)   (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK)
 
#define CSR_MSCRATCH_MSCRATCH_GET(x)   (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT)
 
#define CSR_MEPC_EPC_MASK   (0xFFFFFFFEUL)
 
#define CSR_MEPC_EPC_SHIFT   (1U)
 
#define CSR_MEPC_EPC_SET(x)   (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK)
 
#define CSR_MEPC_EPC_GET(x)   (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT)
 
#define CSR_MCAUSE_INTERRUPT_MASK   (0x80000000UL)
 
#define CSR_MCAUSE_INTERRUPT_SHIFT   (31U)
 
#define CSR_MCAUSE_INTERRUPT_SET(x)   (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK)
 
#define CSR_MCAUSE_INTERRUPT_GET(x)   (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT)
 
#define CSR_MCAUSE_EXCEPTION_CODE_MASK   (0xFFFU)
 
#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT   (0U)
 
#define CSR_MCAUSE_EXCEPTION_CODE_SET(x)   (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK)
 
#define CSR_MCAUSE_EXCEPTION_CODE_GET(x)   (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT)
 
#define CSR_MTVAL_MTVAL_MASK   (0xFFFFFFFFUL)
 
#define CSR_MTVAL_MTVAL_SHIFT   (0U)
 
#define CSR_MTVAL_MTVAL_SET(x)   (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK)
 
#define CSR_MTVAL_MTVAL_GET(x)   (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT)
 
#define CSR_MIP_PMOVI_MASK   (0x40000UL)
 
#define CSR_MIP_PMOVI_SHIFT   (18U)
 
#define CSR_MIP_PMOVI_SET(x)   (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK)
 
#define CSR_MIP_PMOVI_GET(x)   (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT)
 
#define CSR_MIP_BWEI_MASK   (0x20000UL)
 
#define CSR_MIP_BWEI_SHIFT   (17U)
 
#define CSR_MIP_BWEI_SET(x)   (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK)
 
#define CSR_MIP_BWEI_GET(x)   (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT)
 
#define CSR_MIP_IMECCI_MASK   (0x10000UL)
 
#define CSR_MIP_IMECCI_SHIFT   (16U)
 
#define CSR_MIP_IMECCI_SET(x)   (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK)
 
#define CSR_MIP_IMECCI_GET(x)   (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT)
 
#define CSR_MIP_MEIP_MASK   (0x800U)
 
#define CSR_MIP_MEIP_SHIFT   (11U)
 
#define CSR_MIP_MEIP_SET(x)   (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK)
 
#define CSR_MIP_MEIP_GET(x)   (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT)
 
#define CSR_MIP_SEIP_MASK   (0x200U)
 
#define CSR_MIP_SEIP_SHIFT   (9U)
 
#define CSR_MIP_SEIP_SET(x)   (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK)
 
#define CSR_MIP_SEIP_GET(x)   (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT)
 
#define CSR_MIP_UEIP_MASK   (0x100U)
 
#define CSR_MIP_UEIP_SHIFT   (8U)
 
#define CSR_MIP_UEIP_SET(x)   (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK)
 
#define CSR_MIP_UEIP_GET(x)   (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT)
 
#define CSR_MIP_MTIP_MASK   (0x80U)
 
#define CSR_MIP_MTIP_SHIFT   (7U)
 
#define CSR_MIP_MTIP_SET(x)   (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK)
 
#define CSR_MIP_MTIP_GET(x)   (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT)
 
#define CSR_MIP_STIP_MASK   (0x20U)
 
#define CSR_MIP_STIP_SHIFT   (5U)
 
#define CSR_MIP_STIP_SET(x)   (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK)
 
#define CSR_MIP_STIP_GET(x)   (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT)
 
#define CSR_MIP_UTIP_MASK   (0x10U)
 
#define CSR_MIP_UTIP_SHIFT   (4U)
 
#define CSR_MIP_UTIP_SET(x)   (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK)
 
#define CSR_MIP_UTIP_GET(x)   (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT)
 
#define CSR_MIP_MSIP_MASK   (0x8U)
 
#define CSR_MIP_MSIP_SHIFT   (3U)
 
#define CSR_MIP_MSIP_SET(x)   (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK)
 
#define CSR_MIP_MSIP_GET(x)   (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT)
 
#define CSR_MIP_SSIP_MASK   (0x2U)
 
#define CSR_MIP_SSIP_SHIFT   (1U)
 
#define CSR_MIP_SSIP_SET(x)   (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK)
 
#define CSR_MIP_SSIP_GET(x)   (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT)
 
#define CSR_MIP_USIP_MASK   (0x1U)
 
#define CSR_MIP_USIP_SHIFT   (0U)
 
#define CSR_MIP_USIP_SET(x)   (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK)
 
#define CSR_MIP_USIP_GET(x)   (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT)
 
#define CSR_PMPCFG0_PMP3CFG_MASK   (0xFF000000UL)
 
#define CSR_PMPCFG0_PMP3CFG_SHIFT   (24U)
 
#define CSR_PMPCFG0_PMP3CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK)
 
#define CSR_PMPCFG0_PMP3CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT)
 
#define CSR_PMPCFG0_PMP2CFG_MASK   (0xFF0000UL)
 
#define CSR_PMPCFG0_PMP2CFG_SHIFT   (16U)
 
#define CSR_PMPCFG0_PMP2CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK)
 
#define CSR_PMPCFG0_PMP2CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT)
 
#define CSR_PMPCFG0_PMP1CFG_MASK   (0xFF00U)
 
#define CSR_PMPCFG0_PMP1CFG_SHIFT   (8U)
 
#define CSR_PMPCFG0_PMP1CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK)
 
#define CSR_PMPCFG0_PMP1CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT)
 
#define CSR_PMPCFG0_PMP0CFG_MASK   (0xFFU)
 
#define CSR_PMPCFG0_PMP0CFG_SHIFT   (0U)
 
#define CSR_PMPCFG0_PMP0CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK)
 
#define CSR_PMPCFG0_PMP0CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT)
 
#define CSR_PMPCFG1_PMP7CFG_MASK   (0xFF000000UL)
 
#define CSR_PMPCFG1_PMP7CFG_SHIFT   (24U)
 
#define CSR_PMPCFG1_PMP7CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK)
 
#define CSR_PMPCFG1_PMP7CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT)
 
#define CSR_PMPCFG1_PMP6CFG_MASK   (0xFF0000UL)
 
#define CSR_PMPCFG1_PMP6CFG_SHIFT   (16U)
 
#define CSR_PMPCFG1_PMP6CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK)
 
#define CSR_PMPCFG1_PMP6CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT)
 
#define CSR_PMPCFG1_PMP5CFG_MASK   (0xFF00U)
 
#define CSR_PMPCFG1_PMP5CFG_SHIFT   (8U)
 
#define CSR_PMPCFG1_PMP5CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK)
 
#define CSR_PMPCFG1_PMP5CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT)
 
#define CSR_PMPCFG1_PMP4CFG_MASK   (0xFFU)
 
#define CSR_PMPCFG1_PMP4CFG_SHIFT   (0U)
 
#define CSR_PMPCFG1_PMP4CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK)
 
#define CSR_PMPCFG1_PMP4CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT)
 
#define CSR_PMPCFG2_PMP11CFG_MASK   (0xFF000000UL)
 
#define CSR_PMPCFG2_PMP11CFG_SHIFT   (24U)
 
#define CSR_PMPCFG2_PMP11CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK)
 
#define CSR_PMPCFG2_PMP11CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT)
 
#define CSR_PMPCFG2_PMP10CFG_MASK   (0xFF0000UL)
 
#define CSR_PMPCFG2_PMP10CFG_SHIFT   (16U)
 
#define CSR_PMPCFG2_PMP10CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK)
 
#define CSR_PMPCFG2_PMP10CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT)
 
#define CSR_PMPCFG2_PMP9CFG_MASK   (0xFF00U)
 
#define CSR_PMPCFG2_PMP9CFG_SHIFT   (8U)
 
#define CSR_PMPCFG2_PMP9CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK)
 
#define CSR_PMPCFG2_PMP9CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT)
 
#define CSR_PMPCFG2_PMP8CFG_MASK   (0xFFU)
 
#define CSR_PMPCFG2_PMP8CFG_SHIFT   (0U)
 
#define CSR_PMPCFG2_PMP8CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK)
 
#define CSR_PMPCFG2_PMP8CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT)
 
#define CSR_PMPCFG3_PMP15CFG_MASK   (0xFF000000UL)
 
#define CSR_PMPCFG3_PMP15CFG_SHIFT   (24U)
 
#define CSR_PMPCFG3_PMP15CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK)
 
#define CSR_PMPCFG3_PMP15CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT)
 
#define CSR_PMPCFG3_PMP14CFG_MASK   (0xFF0000UL)
 
#define CSR_PMPCFG3_PMP14CFG_SHIFT   (16U)
 
#define CSR_PMPCFG3_PMP14CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK)
 
#define CSR_PMPCFG3_PMP14CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT)
 
#define CSR_PMPCFG3_PMP13CFG_MASK   (0xFF00U)
 
#define CSR_PMPCFG3_PMP13CFG_SHIFT   (8U)
 
#define CSR_PMPCFG3_PMP13CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK)
 
#define CSR_PMPCFG3_PMP13CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT)
 
#define CSR_PMPCFG3_PMP12CFG_MASK   (0xFFU)
 
#define CSR_PMPCFG3_PMP12CFG_SHIFT   (0U)
 
#define CSR_PMPCFG3_PMP12CFG_SET(x)   (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK)
 
#define CSR_PMPCFG3_PMP12CFG_GET(x)   (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT)
 
#define CSR_PMPADDR0_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR0_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR0_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR1_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR1_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR1_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR2_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR2_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR2_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR3_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR3_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR3_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR4_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR4_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR4_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR5_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR5_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR5_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR6_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR6_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR6_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR7_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR7_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR7_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR8_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR8_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR8_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR9_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR9_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR9_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR10_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR10_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR10_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR11_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR11_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR11_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR12_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR12_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR12_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR13_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR13_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR13_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR14_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR14_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR14_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT)
 
#define CSR_PMPADDR15_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)
 
#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT   (2U)
 
#define CSR_PMPADDR15_PMPADDR_31_2_SET(x)   (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK)
 
#define CSR_PMPADDR15_PMPADDR_31_2_GET(x)   (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT)
 
#define CSR_TSELECT_TRIGGER_INDEX_MASK   (0xFFFFFFFFUL)
 
#define CSR_TSELECT_TRIGGER_INDEX_SHIFT   (0U)
 
#define CSR_TSELECT_TRIGGER_INDEX_SET(x)   (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK)
 
#define CSR_TSELECT_TRIGGER_INDEX_GET(x)   (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT)
 
#define CSR_TDATA1_TYPE_MASK   (0xF0000000UL)
 
#define CSR_TDATA1_TYPE_SHIFT   (28U)
 
#define CSR_TDATA1_TYPE_SET(x)   (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK)
 
#define CSR_TDATA1_TYPE_GET(x)   (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT)
 
#define CSR_TDATA1_DMODE_MASK   (0x8000000UL)
 
#define CSR_TDATA1_DMODE_SHIFT   (27U)
 
#define CSR_TDATA1_DMODE_SET(x)   (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK)
 
#define CSR_TDATA1_DMODE_GET(x)   (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT)
 
#define CSR_TDATA1_DATA_MASK   (0x7FFFFFFUL)
 
#define CSR_TDATA1_DATA_SHIFT   (0U)
 
#define CSR_TDATA1_DATA_SET(x)   (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK)
 
#define CSR_TDATA1_DATA_GET(x)   (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT)
 
#define CSR_MCONTROL_TYPE_MASK   (0xF0000000UL)
 
#define CSR_MCONTROL_TYPE_SHIFT   (28U)
 
#define CSR_MCONTROL_TYPE_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK)
 
#define CSR_MCONTROL_TYPE_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT)
 
#define CSR_MCONTROL_DMODE_MASK   (0x8000000UL)
 
#define CSR_MCONTROL_DMODE_SHIFT   (27U)
 
#define CSR_MCONTROL_DMODE_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK)
 
#define CSR_MCONTROL_DMODE_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT)
 
#define CSR_MCONTROL_MASKMAX_MASK   (0x7E00000UL)
 
#define CSR_MCONTROL_MASKMAX_SHIFT   (21U)
 
#define CSR_MCONTROL_MASKMAX_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT)
 
#define CSR_MCONTROL_ACTION_MASK   (0xF000U)
 
#define CSR_MCONTROL_ACTION_SHIFT   (12U)
 
#define CSR_MCONTROL_ACTION_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK)
 
#define CSR_MCONTROL_ACTION_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT)
 
#define CSR_MCONTROL_CHAIN_MASK   (0x800U)
 
#define CSR_MCONTROL_CHAIN_SHIFT   (11U)
 
#define CSR_MCONTROL_CHAIN_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK)
 
#define CSR_MCONTROL_CHAIN_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT)
 
#define CSR_MCONTROL_MATCH_MASK   (0x780U)
 
#define CSR_MCONTROL_MATCH_SHIFT   (7U)
 
#define CSR_MCONTROL_MATCH_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK)
 
#define CSR_MCONTROL_MATCH_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT)
 
#define CSR_MCONTROL_M_MASK   (0x40U)
 
#define CSR_MCONTROL_M_SHIFT   (6U)
 
#define CSR_MCONTROL_M_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK)
 
#define CSR_MCONTROL_M_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT)
 
#define CSR_MCONTROL_U_MASK   (0x8U)
 
#define CSR_MCONTROL_U_SHIFT   (3U)
 
#define CSR_MCONTROL_U_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK)
 
#define CSR_MCONTROL_U_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT)
 
#define CSR_MCONTROL_EXECUTE_MASK   (0x4U)
 
#define CSR_MCONTROL_EXECUTE_SHIFT   (2U)
 
#define CSR_MCONTROL_EXECUTE_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK)
 
#define CSR_MCONTROL_EXECUTE_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT)
 
#define CSR_MCONTROL_STORE_MASK   (0x2U)
 
#define CSR_MCONTROL_STORE_SHIFT   (1U)
 
#define CSR_MCONTROL_STORE_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK)
 
#define CSR_MCONTROL_STORE_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT)
 
#define CSR_MCONTROL_LOAD_MASK   (0x1U)
 
#define CSR_MCONTROL_LOAD_SHIFT   (0U)
 
#define CSR_MCONTROL_LOAD_SET(x)   (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK)
 
#define CSR_MCONTROL_LOAD_GET(x)   (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT)
 
#define CSR_ICOUNT_TYPE_MASK   (0xF0000000UL)
 
#define CSR_ICOUNT_TYPE_SHIFT   (28U)
 
#define CSR_ICOUNT_TYPE_SET(x)   (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK)
 
#define CSR_ICOUNT_TYPE_GET(x)   (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT)
 
#define CSR_ICOUNT_DMODE_MASK   (0x8000000UL)
 
#define CSR_ICOUNT_DMODE_SHIFT   (27U)
 
#define CSR_ICOUNT_DMODE_SET(x)   (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK)
 
#define CSR_ICOUNT_DMODE_GET(x)   (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT)
 
#define CSR_ICOUNT_COUNT_MASK   (0x400U)
 
#define CSR_ICOUNT_COUNT_SHIFT   (10U)
 
#define CSR_ICOUNT_COUNT_GET(x)   (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT)
 
#define CSR_ICOUNT_M_MASK   (0x200U)
 
#define CSR_ICOUNT_M_SHIFT   (9U)
 
#define CSR_ICOUNT_M_SET(x)   (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK)
 
#define CSR_ICOUNT_M_GET(x)   (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT)
 
#define CSR_ICOUNT_U_MASK   (0x40U)
 
#define CSR_ICOUNT_U_SHIFT   (6U)
 
#define CSR_ICOUNT_U_SET(x)   (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK)
 
#define CSR_ICOUNT_U_GET(x)   (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT)
 
#define CSR_ICOUNT_ACTION_MASK   (0x3FU)
 
#define CSR_ICOUNT_ACTION_SHIFT   (0U)
 
#define CSR_ICOUNT_ACTION_SET(x)   (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK)
 
#define CSR_ICOUNT_ACTION_GET(x)   (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT)
 
#define CSR_ITRIGGER_TYPE_MASK   (0xF0000000UL)
 
#define CSR_ITRIGGER_TYPE_SHIFT   (28U)
 
#define CSR_ITRIGGER_TYPE_SET(x)   (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK)
 
#define CSR_ITRIGGER_TYPE_GET(x)   (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT)
 
#define CSR_ITRIGGER_DMODE_MASK   (0x8000000UL)
 
#define CSR_ITRIGGER_DMODE_SHIFT   (27U)
 
#define CSR_ITRIGGER_DMODE_SET(x)   (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK)
 
#define CSR_ITRIGGER_DMODE_GET(x)   (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT)
 
#define CSR_ITRIGGER_M_MASK   (0x200U)
 
#define CSR_ITRIGGER_M_SHIFT   (9U)
 
#define CSR_ITRIGGER_M_SET(x)   (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK)
 
#define CSR_ITRIGGER_M_GET(x)   (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT)
 
#define CSR_ITRIGGER_U_MASK   (0x40U)
 
#define CSR_ITRIGGER_U_SHIFT   (6U)
 
#define CSR_ITRIGGER_U_SET(x)   (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK)
 
#define CSR_ITRIGGER_U_GET(x)   (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT)
 
#define CSR_ITRIGGER_ACTION_MASK   (0x3FU)
 
#define CSR_ITRIGGER_ACTION_SHIFT   (0U)
 
#define CSR_ITRIGGER_ACTION_SET(x)   (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK)
 
#define CSR_ITRIGGER_ACTION_GET(x)   (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT)
 
#define CSR_ETRIGGER_TYPE_MASK   (0xF0000000UL)
 
#define CSR_ETRIGGER_TYPE_SHIFT   (28U)
 
#define CSR_ETRIGGER_TYPE_SET(x)   (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK)
 
#define CSR_ETRIGGER_TYPE_GET(x)   (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT)
 
#define CSR_ETRIGGER_DMODE_MASK   (0x8000000UL)
 
#define CSR_ETRIGGER_DMODE_SHIFT   (27U)
 
#define CSR_ETRIGGER_DMODE_SET(x)   (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK)
 
#define CSR_ETRIGGER_DMODE_GET(x)   (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT)
 
#define CSR_ETRIGGER_NMI_MASK   (0x400U)
 
#define CSR_ETRIGGER_NMI_SHIFT   (10U)
 
#define CSR_ETRIGGER_NMI_SET(x)   (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK)
 
#define CSR_ETRIGGER_NMI_GET(x)   (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT)
 
#define CSR_ETRIGGER_M_MASK   (0x200U)
 
#define CSR_ETRIGGER_M_SHIFT   (9U)
 
#define CSR_ETRIGGER_M_SET(x)   (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK)
 
#define CSR_ETRIGGER_M_GET(x)   (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT)
 
#define CSR_ETRIGGER_U_MASK   (0x40U)
 
#define CSR_ETRIGGER_U_SHIFT   (6U)
 
#define CSR_ETRIGGER_U_SET(x)   (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK)
 
#define CSR_ETRIGGER_U_GET(x)   (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT)
 
#define CSR_ETRIGGER_ACTION_MASK   (0x3FU)
 
#define CSR_ETRIGGER_ACTION_SHIFT   (0U)
 
#define CSR_ETRIGGER_ACTION_SET(x)   (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK)
 
#define CSR_ETRIGGER_ACTION_GET(x)   (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT)
 
#define CSR_TDATA2_DATA_MASK   (0xFFFFFFFFUL)
 
#define CSR_TDATA2_DATA_SHIFT   (0U)
 
#define CSR_TDATA2_DATA_SET(x)   (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK)
 
#define CSR_TDATA2_DATA_GET(x)   (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT)
 
#define CSR_TDATA3_DATA_MASK   (0xFFFFFFFFUL)
 
#define CSR_TDATA3_DATA_SHIFT   (0U)
 
#define CSR_TDATA3_DATA_SET(x)   (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK)
 
#define CSR_TDATA3_DATA_GET(x)   (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT)
 
#define CSR_TEXTRA_MVALUE_MASK   (0xFC000000UL)
 
#define CSR_TEXTRA_MVALUE_SHIFT   (26U)
 
#define CSR_TEXTRA_MVALUE_SET(x)   (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK)
 
#define CSR_TEXTRA_MVALUE_GET(x)   (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT)
 
#define CSR_TEXTRA_MSELECT_MASK   (0x2000000UL)
 
#define CSR_TEXTRA_MSELECT_SHIFT   (25U)
 
#define CSR_TEXTRA_MSELECT_SET(x)   (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK)
 
#define CSR_TEXTRA_MSELECT_GET(x)   (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT)
 
#define CSR_TEXTRA_SVALUE_MASK   (0x7FCU)
 
#define CSR_TEXTRA_SVALUE_SHIFT   (2U)
 
#define CSR_TEXTRA_SVALUE_SET(x)   (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK)
 
#define CSR_TEXTRA_SVALUE_GET(x)   (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT)
 
#define CSR_TEXTRA_SSELECT_MASK   (0x3U)
 
#define CSR_TEXTRA_SSELECT_SHIFT   (0U)
 
#define CSR_TEXTRA_SSELECT_SET(x)   (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK)
 
#define CSR_TEXTRA_SSELECT_GET(x)   (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT)
 
#define CSR_TINFO_INFO_MASK   (0xFFFFU)
 
#define CSR_TINFO_INFO_SHIFT   (0U)
 
#define CSR_TINFO_INFO_GET(x)   (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT)
 
#define CSR_TCONTROL_MPTE_MASK   (0x80U)
 
#define CSR_TCONTROL_MPTE_SHIFT   (7U)
 
#define CSR_TCONTROL_MPTE_SET(x)   (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK)
 
#define CSR_TCONTROL_MPTE_GET(x)   (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT)
 
#define CSR_TCONTROL_MTE_MASK   (0x8U)
 
#define CSR_TCONTROL_MTE_SHIFT   (3U)
 
#define CSR_TCONTROL_MTE_SET(x)   (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK)
 
#define CSR_TCONTROL_MTE_GET(x)   (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT)
 
#define CSR_MCONTEXT_MCONTEXT_MASK   (0x3FU)
 
#define CSR_MCONTEXT_MCONTEXT_SHIFT   (0U)
 
#define CSR_MCONTEXT_MCONTEXT_SET(x)   (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK)
 
#define CSR_MCONTEXT_MCONTEXT_GET(x)   (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT)
 
#define CSR_SCONTEXT_SCONTEXT_MASK   (0x1FFU)
 
#define CSR_SCONTEXT_SCONTEXT_SHIFT   (0U)
 
#define CSR_SCONTEXT_SCONTEXT_SET(x)   (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK)
 
#define CSR_SCONTEXT_SCONTEXT_GET(x)   (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT)
 
#define CSR_DCSR_XDEBUGVER_MASK   (0xF0000000UL)
 
#define CSR_DCSR_XDEBUGVER_SHIFT   (28U)
 
#define CSR_DCSR_XDEBUGVER_GET(x)   (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT)
 
#define CSR_DCSR_EBREAKM_MASK   (0x8000U)
 
#define CSR_DCSR_EBREAKM_SHIFT   (15U)
 
#define CSR_DCSR_EBREAKM_SET(x)   (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK)
 
#define CSR_DCSR_EBREAKM_GET(x)   (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT)
 
#define CSR_DCSR_EBREAKU_MASK   (0x1000U)
 
#define CSR_DCSR_EBREAKU_SHIFT   (12U)
 
#define CSR_DCSR_EBREAKU_SET(x)   (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK)
 
#define CSR_DCSR_EBREAKU_GET(x)   (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT)
 
#define CSR_DCSR_STEPIE_MASK   (0x800U)
 
#define CSR_DCSR_STEPIE_SHIFT   (11U)
 
#define CSR_DCSR_STEPIE_SET(x)   (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK)
 
#define CSR_DCSR_STEPIE_GET(x)   (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT)
 
#define CSR_DCSR_STOPCOUNT_MASK   (0x400U)
 
#define CSR_DCSR_STOPCOUNT_SHIFT   (10U)
 
#define CSR_DCSR_STOPCOUNT_SET(x)   (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK)
 
#define CSR_DCSR_STOPCOUNT_GET(x)   (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT)
 
#define CSR_DCSR_STOPTIME_MASK   (0x200U)
 
#define CSR_DCSR_STOPTIME_SHIFT   (9U)
 
#define CSR_DCSR_STOPTIME_SET(x)   (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK)
 
#define CSR_DCSR_STOPTIME_GET(x)   (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT)
 
#define CSR_DCSR_CAUSE_MASK   (0x1C0U)
 
#define CSR_DCSR_CAUSE_SHIFT   (6U)
 
#define CSR_DCSR_CAUSE_GET(x)   (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT)
 
#define CSR_DCSR_MPRVEN_MASK   (0x10U)
 
#define CSR_DCSR_MPRVEN_SHIFT   (4U)
 
#define CSR_DCSR_MPRVEN_SET(x)   (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK)
 
#define CSR_DCSR_MPRVEN_GET(x)   (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT)
 
#define CSR_DCSR_NMIP_MASK   (0x8U)
 
#define CSR_DCSR_NMIP_SHIFT   (3U)
 
#define CSR_DCSR_NMIP_GET(x)   (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT)
 
#define CSR_DCSR_STEP_MASK   (0x4U)
 
#define CSR_DCSR_STEP_SHIFT   (2U)
 
#define CSR_DCSR_STEP_SET(x)   (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK)
 
#define CSR_DCSR_STEP_GET(x)   (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT)
 
#define CSR_DCSR_PRV_MASK   (0x3U)
 
#define CSR_DCSR_PRV_SHIFT   (0U)
 
#define CSR_DCSR_PRV_SET(x)   (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK)
 
#define CSR_DCSR_PRV_GET(x)   (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT)
 
#define CSR_DPC_DPC_MASK   (0xFFFFFFFFUL)
 
#define CSR_DPC_DPC_SHIFT   (0U)
 
#define CSR_DPC_DPC_SET(x)   (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK)
 
#define CSR_DPC_DPC_GET(x)   (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT)
 
#define CSR_DSCRATCH0_DSCRATCH_MASK   (0xFFFFFFFFUL)
 
#define CSR_DSCRATCH0_DSCRATCH_SHIFT   (0U)
 
#define CSR_DSCRATCH0_DSCRATCH_GET(x)   (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT)
 
#define CSR_DSCRATCH1_DSCRATCH_MASK   (0xFFFFFFFFUL)
 
#define CSR_DSCRATCH1_DSCRATCH_SHIFT   (0U)
 
#define CSR_DSCRATCH1_DSCRATCH_GET(x)   (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT)
 
#define CSR_MCYCLE_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MCYCLE_COUNTER_SHIFT   (0U)
 
#define CSR_MCYCLE_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK)
 
#define CSR_MCYCLE_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT)
 
#define CSR_MINSTRET_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MINSTRET_COUNTER_SHIFT   (0U)
 
#define CSR_MINSTRET_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK)
 
#define CSR_MINSTRET_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER3_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER3_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER3_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER3_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER4_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER4_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER4_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER4_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER5_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER5_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER5_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER5_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER6_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER6_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER6_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER6_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT)
 
#define CSR_MCYCLEH_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MCYCLEH_COUNTER_SHIFT   (0U)
 
#define CSR_MCYCLEH_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK)
 
#define CSR_MCYCLEH_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT)
 
#define CSR_MINSTRETH_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MINSTRETH_COUNTER_SHIFT   (0U)
 
#define CSR_MINSTRETH_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK)
 
#define CSR_MINSTRETH_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER3H_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER3H_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER3H_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER4H_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER4H_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER4H_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER5H_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER5H_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER5H_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT)
 
#define CSR_MHPMCOUNTER6H_COUNTER_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT   (0U)
 
#define CSR_MHPMCOUNTER6H_COUNTER_SET(x)   (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK)
 
#define CSR_MHPMCOUNTER6H_COUNTER_GET(x)   (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT)
 
#define CSR_CYCLE_CYCLE_MASK   (0xFFFFFFFFUL)
 
#define CSR_CYCLE_CYCLE_SHIFT   (0U)
 
#define CSR_CYCLE_CYCLE_SET(x)   (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK)
 
#define CSR_CYCLE_CYCLE_GET(x)   (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT)
 
#define CSR_CYCLEH_CYCLEH_MASK   (0xFFFFFFFFUL)
 
#define CSR_CYCLEH_CYCLEH_SHIFT   (0U)
 
#define CSR_CYCLEH_CYCLEH_SET(x)   (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK)
 
#define CSR_CYCLEH_CYCLEH_GET(x)   (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT)
 
#define CSR_MVENDORID_MVENDORID_MASK   (0xFFFFFFFFUL)
 
#define CSR_MVENDORID_MVENDORID_SHIFT   (0U)
 
#define CSR_MVENDORID_MVENDORID_GET(x)   (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT)
 
#define CSR_MARCHID_CPU_ID_MASK   (0x7FFFFFFFUL)
 
#define CSR_MARCHID_CPU_ID_SHIFT   (0U)
 
#define CSR_MARCHID_CPU_ID_GET(x)   (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT)
 
#define CSR_MIMPID_MAJOR_MASK   (0xFFFFFF00UL)
 
#define CSR_MIMPID_MAJOR_SHIFT   (8U)
 
#define CSR_MIMPID_MAJOR_GET(x)   (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT)
 
#define CSR_MIMPID_MINOR_MASK   (0xF0U)
 
#define CSR_MIMPID_MINOR_SHIFT   (4U)
 
#define CSR_MIMPID_MINOR_GET(x)   (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT)
 
#define CSR_MIMPID_EXTENSION_MASK   (0xFU)
 
#define CSR_MIMPID_EXTENSION_SHIFT   (0U)
 
#define CSR_MIMPID_EXTENSION_GET(x)   (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT)
 
#define CSR_MHARTID_MHARTID_MASK   (0xFFFFFFFFUL)
 
#define CSR_MHARTID_MHARTID_SHIFT   (0U)
 
#define CSR_MHARTID_MHARTID_GET(x)   (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT)
 
#define CSR_MCOUNTINHIBIT_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTINHIBIT_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTINHIBIT_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK)
 
#define CSR_MCOUNTINHIBIT_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT)
 
#define CSR_MCOUNTINHIBIT_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTINHIBIT_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTINHIBIT_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK)
 
#define CSR_MCOUNTINHIBIT_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT)
 
#define CSR_MCOUNTINHIBIT_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTINHIBIT_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTINHIBIT_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK)
 
#define CSR_MCOUNTINHIBIT_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT)
 
#define CSR_MCOUNTINHIBIT_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTINHIBIT_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTINHIBIT_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK)
 
#define CSR_MCOUNTINHIBIT_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT)
 
#define CSR_MCOUNTINHIBIT_IR_MASK   (0x4U)
 
#define CSR_MCOUNTINHIBIT_IR_SHIFT   (2U)
 
#define CSR_MCOUNTINHIBIT_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK)
 
#define CSR_MCOUNTINHIBIT_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT)
 
#define CSR_MCOUNTINHIBIT_TM_MASK   (0x2U)
 
#define CSR_MCOUNTINHIBIT_TM_SHIFT   (1U)
 
#define CSR_MCOUNTINHIBIT_TM_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK)
 
#define CSR_MCOUNTINHIBIT_TM_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT)
 
#define CSR_MCOUNTINHIBIT_CY_MASK   (0x1U)
 
#define CSR_MCOUNTINHIBIT_CY_SHIFT   (0U)
 
#define CSR_MCOUNTINHIBIT_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK)
 
#define CSR_MCOUNTINHIBIT_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT)
 
#define CSR_MILMB_IBPA_MASK   (0xFFFFFC00UL)
 
#define CSR_MILMB_IBPA_SHIFT   (10U)
 
#define CSR_MILMB_IBPA_GET(x)   (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT)
 
#define CSR_MILMB_RWECC_MASK   (0x8U)
 
#define CSR_MILMB_RWECC_SHIFT   (3U)
 
#define CSR_MILMB_RWECC_SET(x)   (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK)
 
#define CSR_MILMB_RWECC_GET(x)   (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT)
 
#define CSR_MILMB_ECCEN_MASK   (0x6U)
 
#define CSR_MILMB_ECCEN_SHIFT   (1U)
 
#define CSR_MILMB_ECCEN_SET(x)   (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK)
 
#define CSR_MILMB_ECCEN_GET(x)   (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT)
 
#define CSR_MILMB_IEN_MASK   (0x1U)
 
#define CSR_MILMB_IEN_SHIFT   (0U)
 
#define CSR_MILMB_IEN_GET(x)   (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT)
 
#define CSR_MDLMB_DBPA_MASK   (0xFFFFFC00UL)
 
#define CSR_MDLMB_DBPA_SHIFT   (10U)
 
#define CSR_MDLMB_DBPA_GET(x)   (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT)
 
#define CSR_MDLMB_RWECC_MASK   (0x8U)
 
#define CSR_MDLMB_RWECC_SHIFT   (3U)
 
#define CSR_MDLMB_RWECC_SET(x)   (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK)
 
#define CSR_MDLMB_RWECC_GET(x)   (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT)
 
#define CSR_MDLMB_ECCEN_MASK   (0x6U)
 
#define CSR_MDLMB_ECCEN_SHIFT   (1U)
 
#define CSR_MDLMB_ECCEN_SET(x)   (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK)
 
#define CSR_MDLMB_ECCEN_GET(x)   (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT)
 
#define CSR_MDLMB_DEN_MASK   (0x1U)
 
#define CSR_MDLMB_DEN_SHIFT   (0U)
 
#define CSR_MDLMB_DEN_GET(x)   (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT)
 
#define CSR_MECC_CODE_INSN_MASK   (0x400000UL)
 
#define CSR_MECC_CODE_INSN_SHIFT   (22U)
 
#define CSR_MECC_CODE_INSN_GET(x)   (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT)
 
#define CSR_MECC_CODE_RAMID_MASK   (0x3C0000UL)
 
#define CSR_MECC_CODE_RAMID_SHIFT   (18U)
 
#define CSR_MECC_CODE_RAMID_GET(x)   (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT)
 
#define CSR_MECC_CODE_P_MASK   (0x20000UL)
 
#define CSR_MECC_CODE_P_SHIFT   (17U)
 
#define CSR_MECC_CODE_P_GET(x)   (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT)
 
#define CSR_MECC_CODE_C_MASK   (0x10000UL)
 
#define CSR_MECC_CODE_C_SHIFT   (16U)
 
#define CSR_MECC_CODE_C_GET(x)   (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT)
 
#define CSR_MECC_CODE_CODE_MASK   (0x7FU)
 
#define CSR_MECC_CODE_CODE_SHIFT   (0U)
 
#define CSR_MECC_CODE_CODE_SET(x)   (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK)
 
#define CSR_MECC_CODE_CODE_GET(x)   (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT)
 
#define CSR_MNVEC_MNVEC_MASK   (0xFFFFFFFFUL)
 
#define CSR_MNVEC_MNVEC_SHIFT   (0U)
 
#define CSR_MNVEC_MNVEC_GET(x)   (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT)
 
#define CSR_MXSTATUS_PDME_MASK   (0x20U)
 
#define CSR_MXSTATUS_PDME_SHIFT   (5U)
 
#define CSR_MXSTATUS_PDME_SET(x)   (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK)
 
#define CSR_MXSTATUS_PDME_GET(x)   (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT)
 
#define CSR_MXSTATUS_DME_MASK   (0x10U)
 
#define CSR_MXSTATUS_DME_SHIFT   (4U)
 
#define CSR_MXSTATUS_DME_SET(x)   (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK)
 
#define CSR_MXSTATUS_DME_GET(x)   (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT)
 
#define CSR_MXSTATUS_PIME_MASK   (0x8U)
 
#define CSR_MXSTATUS_PIME_SHIFT   (3U)
 
#define CSR_MXSTATUS_PIME_SET(x)   (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK)
 
#define CSR_MXSTATUS_PIME_GET(x)   (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT)
 
#define CSR_MXSTATUS_IME_MASK   (0x4U)
 
#define CSR_MXSTATUS_IME_SHIFT   (2U)
 
#define CSR_MXSTATUS_IME_SET(x)   (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK)
 
#define CSR_MXSTATUS_IME_GET(x)   (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT)
 
#define CSR_MXSTATUS_PPFT_EN_MASK   (0x2U)
 
#define CSR_MXSTATUS_PPFT_EN_SHIFT   (1U)
 
#define CSR_MXSTATUS_PPFT_EN_SET(x)   (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK)
 
#define CSR_MXSTATUS_PPFT_EN_GET(x)   (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT)
 
#define CSR_MXSTATUS_PFT_EN_MASK   (0x1U)
 
#define CSR_MXSTATUS_PFT_EN_SHIFT   (0U)
 
#define CSR_MXSTATUS_PFT_EN_SET(x)   (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK)
 
#define CSR_MXSTATUS_PFT_EN_GET(x)   (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT)
 
#define CSR_MPFT_CTL_FAST_INT_MASK   (0x100U)
 
#define CSR_MPFT_CTL_FAST_INT_SHIFT   (8U)
 
#define CSR_MPFT_CTL_FAST_INT_SET(x)   (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK)
 
#define CSR_MPFT_CTL_FAST_INT_GET(x)   (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT)
 
#define CSR_MPFT_CTL_T_LEVEL_MASK   (0xF0U)
 
#define CSR_MPFT_CTL_T_LEVEL_SHIFT   (4U)
 
#define CSR_MPFT_CTL_T_LEVEL_SET(x)   (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK)
 
#define CSR_MPFT_CTL_T_LEVEL_GET(x)   (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT)
 
#define CSR_MHSP_CTL_M_MASK   (0x20U)
 
#define CSR_MHSP_CTL_M_SHIFT   (5U)
 
#define CSR_MHSP_CTL_M_SET(x)   (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK)
 
#define CSR_MHSP_CTL_M_GET(x)   (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT)
 
#define CSR_MHSP_CTL_S_MASK   (0x10U)
 
#define CSR_MHSP_CTL_S_SHIFT   (4U)
 
#define CSR_MHSP_CTL_S_SET(x)   (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK)
 
#define CSR_MHSP_CTL_S_GET(x)   (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT)
 
#define CSR_MHSP_CTL_U_MASK   (0x8U)
 
#define CSR_MHSP_CTL_U_SHIFT   (3U)
 
#define CSR_MHSP_CTL_U_SET(x)   (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK)
 
#define CSR_MHSP_CTL_U_GET(x)   (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT)
 
#define CSR_MHSP_CTL_SCHM_MASK   (0x4U)
 
#define CSR_MHSP_CTL_SCHM_SHIFT   (2U)
 
#define CSR_MHSP_CTL_SCHM_SET(x)   (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK)
 
#define CSR_MHSP_CTL_SCHM_GET(x)   (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT)
 
#define CSR_MHSP_CTL_UDF_EN_MASK   (0x2U)
 
#define CSR_MHSP_CTL_UDF_EN_SHIFT   (1U)
 
#define CSR_MHSP_CTL_UDF_EN_SET(x)   (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK)
 
#define CSR_MHSP_CTL_UDF_EN_GET(x)   (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT)
 
#define CSR_MHSP_CTL_OVF_EN_MASK   (0x1U)
 
#define CSR_MHSP_CTL_OVF_EN_SHIFT   (0U)
 
#define CSR_MHSP_CTL_OVF_EN_SET(x)   (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK)
 
#define CSR_MHSP_CTL_OVF_EN_GET(x)   (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT)
 
#define CSR_MSP_BOUND_MSP_BOUND_MASK   (0xFFFFFFFFUL)
 
#define CSR_MSP_BOUND_MSP_BOUND_SHIFT   (0U)
 
#define CSR_MSP_BOUND_MSP_BOUND_SET(x)   (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK)
 
#define CSR_MSP_BOUND_MSP_BOUND_GET(x)   (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT)
 
#define CSR_MSP_BASE_SP_BASE_MASK   (0xFFFFFFFFUL)
 
#define CSR_MSP_BASE_SP_BASE_SHIFT   (0U)
 
#define CSR_MSP_BASE_SP_BASE_SET(x)   (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK)
 
#define CSR_MSP_BASE_SP_BASE_GET(x)   (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT)
 
#define CSR_MDCAUSE_MDCAUSE_MASK   (0x7U)
 
#define CSR_MDCAUSE_MDCAUSE_SHIFT   (0U)
 
#define CSR_MDCAUSE_MDCAUSE_SET(x)   (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK)
 
#define CSR_MDCAUSE_MDCAUSE_GET(x)   (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT)
 
#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK   (0x800U)
 
#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT   (11U)
 
#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT)
 
#define CSR_MCACHE_CTL_CCTL_SUEN_MASK   (0x100U)
 
#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT   (8U)
 
#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK)
 
#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT)
 
#define CSR_MCACHE_CTL_DC_RWECC_MASK   (0x80U)
 
#define CSR_MCACHE_CTL_DC_RWECC_SHIFT   (7U)
 
#define CSR_MCACHE_CTL_DC_RWECC_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK)
 
#define CSR_MCACHE_CTL_DC_RWECC_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT)
 
#define CSR_MCACHE_CTL_IC_RWECC_MASK   (0x40U)
 
#define CSR_MCACHE_CTL_IC_RWECC_SHIFT   (6U)
 
#define CSR_MCACHE_CTL_IC_RWECC_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK)
 
#define CSR_MCACHE_CTL_IC_RWECC_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT)
 
#define CSR_MCACHE_CTL_DC_ECCEN_MASK   (0x30U)
 
#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT   (4U)
 
#define CSR_MCACHE_CTL_DC_ECCEN_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK)
 
#define CSR_MCACHE_CTL_DC_ECCEN_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT)
 
#define CSR_MCACHE_CTL_IC_ECCEN_MASK   (0xCU)
 
#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT   (2U)
 
#define CSR_MCACHE_CTL_IC_ECCEN_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK)
 
#define CSR_MCACHE_CTL_IC_ECCEN_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT)
 
#define CSR_MCACHE_CTL_DC_EN_MASK   (0x2U)
 
#define CSR_MCACHE_CTL_DC_EN_SHIFT   (1U)
 
#define CSR_MCACHE_CTL_DC_EN_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK)
 
#define CSR_MCACHE_CTL_DC_EN_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT)
 
#define CSR_MCACHE_CTL_IC_EN_MASK   (0x1U)
 
#define CSR_MCACHE_CTL_IC_EN_SHIFT   (0U)
 
#define CSR_MCACHE_CTL_IC_EN_SET(x)   (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK)
 
#define CSR_MCACHE_CTL_IC_EN_GET(x)   (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT)
 
#define CSR_MCCTLBEGINADDR_VA_MASK   (0xFFFFFFFFUL)
 
#define CSR_MCCTLBEGINADDR_VA_SHIFT   (0U)
 
#define CSR_MCCTLBEGINADDR_VA_SET(x)   (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK)
 
#define CSR_MCCTLBEGINADDR_VA_GET(x)   (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT)
 
#define CSR_MCCTLCOMMAND_VA_MASK   (0x1FU)
 
#define CSR_MCCTLCOMMAND_VA_SHIFT   (0U)
 
#define CSR_MCCTLCOMMAND_VA_SET(x)   (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK)
 
#define CSR_MCCTLCOMMAND_VA_GET(x)   (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT)
 
#define CSR_MCCTLDATA_VA_MASK   (0x1FU)
 
#define CSR_MCCTLDATA_VA_SHIFT   (0U)
 
#define CSR_MCCTLDATA_VA_SET(x)   (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK)
 
#define CSR_MCCTLDATA_VA_GET(x)   (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT)
 
#define CSR_MCOUNTERWEN_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTERWEN_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTERWEN_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK)
 
#define CSR_MCOUNTERWEN_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT)
 
#define CSR_MCOUNTERWEN_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTERWEN_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTERWEN_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK)
 
#define CSR_MCOUNTERWEN_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT)
 
#define CSR_MCOUNTERWEN_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTERWEN_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTERWEN_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK)
 
#define CSR_MCOUNTERWEN_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT)
 
#define CSR_MCOUNTERWEN_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTERWEN_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTERWEN_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK)
 
#define CSR_MCOUNTERWEN_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT)
 
#define CSR_MCOUNTERWEN_IR_MASK   (0x4U)
 
#define CSR_MCOUNTERWEN_IR_SHIFT   (2U)
 
#define CSR_MCOUNTERWEN_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK)
 
#define CSR_MCOUNTERWEN_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT)
 
#define CSR_MCOUNTERWEN_CY_MASK   (0x1U)
 
#define CSR_MCOUNTERWEN_CY_SHIFT   (0U)
 
#define CSR_MCOUNTERWEN_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK)
 
#define CSR_MCOUNTERWEN_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT)
 
#define CSR_MCOUNTERINTEN_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTERINTEN_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTERINTEN_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK)
 
#define CSR_MCOUNTERINTEN_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT)
 
#define CSR_MCOUNTERINTEN_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTERINTEN_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTERINTEN_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK)
 
#define CSR_MCOUNTERINTEN_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT)
 
#define CSR_MCOUNTERINTEN_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTERINTEN_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTERINTEN_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK)
 
#define CSR_MCOUNTERINTEN_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT)
 
#define CSR_MCOUNTERINTEN_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTERINTEN_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTERINTEN_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK)
 
#define CSR_MCOUNTERINTEN_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT)
 
#define CSR_MCOUNTERINTEN_IR_MASK   (0x4U)
 
#define CSR_MCOUNTERINTEN_IR_SHIFT   (2U)
 
#define CSR_MCOUNTERINTEN_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK)
 
#define CSR_MCOUNTERINTEN_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT)
 
#define CSR_MCOUNTERINTEN_CY_MASK   (0x1U)
 
#define CSR_MCOUNTERINTEN_CY_SHIFT   (0U)
 
#define CSR_MCOUNTERINTEN_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK)
 
#define CSR_MCOUNTERINTEN_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT)
 
#define CSR_MMISC_CTL_MSA_UNA_MASK   (0x40U)
 
#define CSR_MMISC_CTL_MSA_UNA_SHIFT   (6U)
 
#define CSR_MMISC_CTL_MSA_UNA_SET(x)   (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK)
 
#define CSR_MMISC_CTL_MSA_UNA_GET(x)   (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT)
 
#define CSR_MMISC_CTL_BRPE_MASK   (0x8U)
 
#define CSR_MMISC_CTL_BRPE_SHIFT   (3U)
 
#define CSR_MMISC_CTL_BRPE_SET(x)   (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK)
 
#define CSR_MMISC_CTL_BRPE_GET(x)   (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT)
 
#define CSR_MMISC_CTL_RVCOMPM_MASK   (0x4U)
 
#define CSR_MMISC_CTL_RVCOMPM_SHIFT   (2U)
 
#define CSR_MMISC_CTL_RVCOMPM_SET(x)   (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK)
 
#define CSR_MMISC_CTL_RVCOMPM_GET(x)   (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT)
 
#define CSR_MMISC_CTL_VEC_PLIC_MASK   (0x2U)
 
#define CSR_MMISC_CTL_VEC_PLIC_SHIFT   (1U)
 
#define CSR_MMISC_CTL_VEC_PLIC_SET(x)   (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK)
 
#define CSR_MMISC_CTL_VEC_PLIC_GET(x)   (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT)
 
#define CSR_MCOUNTERMASK_M_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTERMASK_M_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTERMASK_M_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK)
 
#define CSR_MCOUNTERMASK_M_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT)
 
#define CSR_MCOUNTERMASK_M_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTERMASK_M_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTERMASK_M_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK)
 
#define CSR_MCOUNTERMASK_M_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT)
 
#define CSR_MCOUNTERMASK_M_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTERMASK_M_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTERMASK_M_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK)
 
#define CSR_MCOUNTERMASK_M_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT)
 
#define CSR_MCOUNTERMASK_M_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTERMASK_M_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTERMASK_M_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK)
 
#define CSR_MCOUNTERMASK_M_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT)
 
#define CSR_MCOUNTERMASK_M_IR_MASK   (0x4U)
 
#define CSR_MCOUNTERMASK_M_IR_SHIFT   (2U)
 
#define CSR_MCOUNTERMASK_M_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK)
 
#define CSR_MCOUNTERMASK_M_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT)
 
#define CSR_MCOUNTERMASK_M_CY_MASK   (0x1U)
 
#define CSR_MCOUNTERMASK_M_CY_SHIFT   (0U)
 
#define CSR_MCOUNTERMASK_M_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK)
 
#define CSR_MCOUNTERMASK_M_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT)
 
#define CSR_MCOUNTERMASK_S_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTERMASK_S_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTERMASK_S_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK)
 
#define CSR_MCOUNTERMASK_S_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT)
 
#define CSR_MCOUNTERMASK_S_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTERMASK_S_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTERMASK_S_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK)
 
#define CSR_MCOUNTERMASK_S_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT)
 
#define CSR_MCOUNTERMASK_S_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTERMASK_S_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTERMASK_S_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK)
 
#define CSR_MCOUNTERMASK_S_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT)
 
#define CSR_MCOUNTERMASK_S_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTERMASK_S_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTERMASK_S_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK)
 
#define CSR_MCOUNTERMASK_S_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT)
 
#define CSR_MCOUNTERMASK_S_IR_MASK   (0x4U)
 
#define CSR_MCOUNTERMASK_S_IR_SHIFT   (2U)
 
#define CSR_MCOUNTERMASK_S_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK)
 
#define CSR_MCOUNTERMASK_S_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT)
 
#define CSR_MCOUNTERMASK_S_CY_MASK   (0x1U)
 
#define CSR_MCOUNTERMASK_S_CY_SHIFT   (0U)
 
#define CSR_MCOUNTERMASK_S_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK)
 
#define CSR_MCOUNTERMASK_S_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT)
 
#define CSR_MCOUNTERMASK_U_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTERMASK_U_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTERMASK_U_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK)
 
#define CSR_MCOUNTERMASK_U_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT)
 
#define CSR_MCOUNTERMASK_U_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTERMASK_U_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTERMASK_U_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK)
 
#define CSR_MCOUNTERMASK_U_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT)
 
#define CSR_MCOUNTERMASK_U_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTERMASK_U_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTERMASK_U_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK)
 
#define CSR_MCOUNTERMASK_U_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT)
 
#define CSR_MCOUNTERMASK_U_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTERMASK_U_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTERMASK_U_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK)
 
#define CSR_MCOUNTERMASK_U_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT)
 
#define CSR_MCOUNTERMASK_U_IR_MASK   (0x4U)
 
#define CSR_MCOUNTERMASK_U_IR_SHIFT   (2U)
 
#define CSR_MCOUNTERMASK_U_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK)
 
#define CSR_MCOUNTERMASK_U_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT)
 
#define CSR_MCOUNTERMASK_U_CY_MASK   (0x1U)
 
#define CSR_MCOUNTERMASK_U_CY_SHIFT   (0U)
 
#define CSR_MCOUNTERMASK_U_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK)
 
#define CSR_MCOUNTERMASK_U_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT)
 
#define CSR_MCOUNTEROVF_HPM6_MASK   (0x40U)
 
#define CSR_MCOUNTEROVF_HPM6_SHIFT   (6U)
 
#define CSR_MCOUNTEROVF_HPM6_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK)
 
#define CSR_MCOUNTEROVF_HPM6_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT)
 
#define CSR_MCOUNTEROVF_HPM5_MASK   (0x20U)
 
#define CSR_MCOUNTEROVF_HPM5_SHIFT   (5U)
 
#define CSR_MCOUNTEROVF_HPM5_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK)
 
#define CSR_MCOUNTEROVF_HPM5_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT)
 
#define CSR_MCOUNTEROVF_HPM4_MASK   (0x10U)
 
#define CSR_MCOUNTEROVF_HPM4_SHIFT   (4U)
 
#define CSR_MCOUNTEROVF_HPM4_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK)
 
#define CSR_MCOUNTEROVF_HPM4_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT)
 
#define CSR_MCOUNTEROVF_HPM3_MASK   (0x8U)
 
#define CSR_MCOUNTEROVF_HPM3_SHIFT   (3U)
 
#define CSR_MCOUNTEROVF_HPM3_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK)
 
#define CSR_MCOUNTEROVF_HPM3_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT)
 
#define CSR_MCOUNTEROVF_IR_MASK   (0x4U)
 
#define CSR_MCOUNTEROVF_IR_SHIFT   (2U)
 
#define CSR_MCOUNTEROVF_IR_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK)
 
#define CSR_MCOUNTEROVF_IR_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT)
 
#define CSR_MCOUNTEROVF_CY_MASK   (0x1U)
 
#define CSR_MCOUNTEROVF_CY_SHIFT   (0U)
 
#define CSR_MCOUNTEROVF_CY_SET(x)   (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK)
 
#define CSR_MCOUNTEROVF_CY_GET(x)   (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT)
 
#define CSR_DEXC2DBG_PMOV_MASK   (0x80000UL)
 
#define CSR_DEXC2DBG_PMOV_SHIFT   (19U)
 
#define CSR_DEXC2DBG_PMOV_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK)
 
#define CSR_DEXC2DBG_PMOV_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT)
 
#define CSR_DEXC2DBG_BWE_MASK   (0x8000U)
 
#define CSR_DEXC2DBG_BWE_SHIFT   (15U)
 
#define CSR_DEXC2DBG_BWE_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK)
 
#define CSR_DEXC2DBG_BWE_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT)
 
#define CSR_DEXC2DBG_SLPECC_MASK   (0x4000U)
 
#define CSR_DEXC2DBG_SLPECC_SHIFT   (14U)
 
#define CSR_DEXC2DBG_SLPECC_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK)
 
#define CSR_DEXC2DBG_SLPECC_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT)
 
#define CSR_DEXC2DBG_ACE_MASK   (0x2000U)
 
#define CSR_DEXC2DBG_ACE_SHIFT   (13U)
 
#define CSR_DEXC2DBG_ACE_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK)
 
#define CSR_DEXC2DBG_ACE_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT)
 
#define CSR_DEXC2DBG_HSP_MASK   (0x1000U)
 
#define CSR_DEXC2DBG_HSP_SHIFT   (12U)
 
#define CSR_DEXC2DBG_HSP_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK)
 
#define CSR_DEXC2DBG_HSP_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT)
 
#define CSR_DEXC2DBG_MEC_MASK   (0x800U)
 
#define CSR_DEXC2DBG_MEC_SHIFT   (11U)
 
#define CSR_DEXC2DBG_MEC_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK)
 
#define CSR_DEXC2DBG_MEC_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT)
 
#define CSR_DEXC2DBG_UEC_MASK   (0x100U)
 
#define CSR_DEXC2DBG_UEC_SHIFT   (8U)
 
#define CSR_DEXC2DBG_UEC_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK)
 
#define CSR_DEXC2DBG_UEC_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT)
 
#define CSR_DEXC2DBG_SAF_MASK   (0x80U)
 
#define CSR_DEXC2DBG_SAF_SHIFT   (7U)
 
#define CSR_DEXC2DBG_SAF_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK)
 
#define CSR_DEXC2DBG_SAF_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT)
 
#define CSR_DEXC2DBG_SAM_MASK   (0x40U)
 
#define CSR_DEXC2DBG_SAM_SHIFT   (6U)
 
#define CSR_DEXC2DBG_SAM_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK)
 
#define CSR_DEXC2DBG_SAM_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT)
 
#define CSR_DEXC2DBG_LAF_MASK   (0x20U)
 
#define CSR_DEXC2DBG_LAF_SHIFT   (5U)
 
#define CSR_DEXC2DBG_LAF_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK)
 
#define CSR_DEXC2DBG_LAF_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT)
 
#define CSR_DEXC2DBG_LAM_MASK   (0x10U)
 
#define CSR_DEXC2DBG_LAM_SHIFT   (4U)
 
#define CSR_DEXC2DBG_LAM_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK)
 
#define CSR_DEXC2DBG_LAM_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT)
 
#define CSR_DEXC2DBG_NMI_MASK   (0x8U)
 
#define CSR_DEXC2DBG_NMI_SHIFT   (3U)
 
#define CSR_DEXC2DBG_NMI_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK)
 
#define CSR_DEXC2DBG_NMI_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT)
 
#define CSR_DEXC2DBG_II_MASK   (0x4U)
 
#define CSR_DEXC2DBG_II_SHIFT   (2U)
 
#define CSR_DEXC2DBG_II_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK)
 
#define CSR_DEXC2DBG_II_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT)
 
#define CSR_DEXC2DBG_IAF_MASK   (0x2U)
 
#define CSR_DEXC2DBG_IAF_SHIFT   (1U)
 
#define CSR_DEXC2DBG_IAF_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK)
 
#define CSR_DEXC2DBG_IAF_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT)
 
#define CSR_DEXC2DBG_IAM_MASK   (0x1U)
 
#define CSR_DEXC2DBG_IAM_SHIFT   (0U)
 
#define CSR_DEXC2DBG_IAM_SET(x)   (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK)
 
#define CSR_DEXC2DBG_IAM_GET(x)   (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT)
 
#define CSR_DDCAUSE_SUBTYPE_MASK   (0xFF00U)
 
#define CSR_DDCAUSE_SUBTYPE_SHIFT   (8U)
 
#define CSR_DDCAUSE_SUBTYPE_GET(x)   (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT)
 
#define CSR_DDCAUSE_MAINTYPE_MASK   (0xFFU)
 
#define CSR_DDCAUSE_MAINTYPE_SHIFT   (0U)
 
#define CSR_DDCAUSE_MAINTYPE_GET(x)   (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT)
 
#define CSR_UITB_ADDR_MASK   (0xFFFFFFFCUL)
 
#define CSR_UITB_ADDR_SHIFT   (2U)
 
#define CSR_UITB_ADDR_SET(x)   (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK)
 
#define CSR_UITB_ADDR_GET(x)   (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT)
 
#define CSR_UITB_HW_MASK   (0x1U)
 
#define CSR_UITB_HW_SHIFT   (0U)
 
#define CSR_UITB_HW_GET(x)   (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT)
 
#define CSR_UCODE_OV_MASK   (0x1U)
 
#define CSR_UCODE_OV_SHIFT   (0U)
 
#define CSR_UCODE_OV_SET(x)   (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK)
 
#define CSR_UCODE_OV_GET(x)   (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT)
 
#define CSR_UDCAUSE_UDCAUSE_MASK   (0x7U)
 
#define CSR_UDCAUSE_UDCAUSE_SHIFT   (0U)
 
#define CSR_UDCAUSE_UDCAUSE_SET(x)   (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK)
 
#define CSR_UDCAUSE_UDCAUSE_GET(x)   (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT)
 
#define CSR_UCCTLBEGINADDR_VA_MASK   (0xFFFFFFFFUL)
 
#define CSR_UCCTLBEGINADDR_VA_SHIFT   (0U)
 
#define CSR_UCCTLBEGINADDR_VA_SET(x)   (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK)
 
#define CSR_UCCTLBEGINADDR_VA_GET(x)   (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT)
 
#define CSR_UCCTLCOMMAND_VA_MASK   (0x1FU)
 
#define CSR_UCCTLCOMMAND_VA_SHIFT   (0U)
 
#define CSR_UCCTLCOMMAND_VA_SET(x)   (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK)
 
#define CSR_UCCTLCOMMAND_VA_GET(x)   (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT)
 
#define CSR_MICM_CFG_SETH_MASK   (0x1000000UL)
 
#define CSR_MICM_CFG_SETH_SHIFT   (24U)
 
#define CSR_MICM_CFG_SETH_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT)
 
#define CSR_MICM_CFG_ILM_ECC_MASK   (0x600000UL)
 
#define CSR_MICM_CFG_ILM_ECC_SHIFT   (21U)
 
#define CSR_MICM_CFG_ILM_ECC_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT)
 
#define CSR_MICM_CFG_ILMSZ_MASK   (0xF8000UL)
 
#define CSR_MICM_CFG_ILMSZ_SHIFT   (15U)
 
#define CSR_MICM_CFG_ILMSZ_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT)
 
#define CSR_MICM_CFG_ILMB_MASK   (0x7000U)
 
#define CSR_MICM_CFG_ILMB_SHIFT   (12U)
 
#define CSR_MICM_CFG_ILMB_SET(x)   (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK)
 
#define CSR_MICM_CFG_ILMB_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT)
 
#define CSR_MICM_CFG_IC_ECC_MASK   (0xC00U)
 
#define CSR_MICM_CFG_IC_ECC_SHIFT   (10U)
 
#define CSR_MICM_CFG_IC_ECC_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT)
 
#define CSR_MICM_CFG_ILCK_MASK   (0x200U)
 
#define CSR_MICM_CFG_ILCK_SHIFT   (9U)
 
#define CSR_MICM_CFG_ILCK_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT)
 
#define CSR_MICM_CFG_ISZ_MASK   (0x1C0U)
 
#define CSR_MICM_CFG_ISZ_SHIFT   (6U)
 
#define CSR_MICM_CFG_ISZ_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT)
 
#define CSR_MICM_CFG_IWAY_MASK   (0x38U)
 
#define CSR_MICM_CFG_IWAY_SHIFT   (3U)
 
#define CSR_MICM_CFG_IWAY_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT)
 
#define CSR_MICM_CFG_ISET_MASK   (0x7U)
 
#define CSR_MICM_CFG_ISET_SHIFT   (0U)
 
#define CSR_MICM_CFG_ISET_GET(x)   (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT)
 
#define CSR_MDCM_CFG_SETH_MASK   (0x1000000UL)
 
#define CSR_MDCM_CFG_SETH_SHIFT   (24U)
 
#define CSR_MDCM_CFG_SETH_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT)
 
#define CSR_MDCM_CFG_DLM_ECC_MASK   (0x600000UL)
 
#define CSR_MDCM_CFG_DLM_ECC_SHIFT   (21U)
 
#define CSR_MDCM_CFG_DLM_ECC_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT)
 
#define CSR_MDCM_CFG_DLMSZ_MASK   (0xF8000UL)
 
#define CSR_MDCM_CFG_DLMSZ_SHIFT   (15U)
 
#define CSR_MDCM_CFG_DLMSZ_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT)
 
#define CSR_MDCM_CFG_DLMB_MASK   (0x7000U)
 
#define CSR_MDCM_CFG_DLMB_SHIFT   (12U)
 
#define CSR_MDCM_CFG_DLMB_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT)
 
#define CSR_MDCM_CFG_DC_ECC_MASK   (0xC00U)
 
#define CSR_MDCM_CFG_DC_ECC_SHIFT   (10U)
 
#define CSR_MDCM_CFG_DC_ECC_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT)
 
#define CSR_MDCM_CFG_DLCK_MASK   (0x200U)
 
#define CSR_MDCM_CFG_DLCK_SHIFT   (9U)
 
#define CSR_MDCM_CFG_DLCK_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT)
 
#define CSR_MDCM_CFG_DSZ_MASK   (0x1C0U)
 
#define CSR_MDCM_CFG_DSZ_SHIFT   (6U)
 
#define CSR_MDCM_CFG_DSZ_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT)
 
#define CSR_MDCM_CFG_DWAY_MASK   (0x38U)
 
#define CSR_MDCM_CFG_DWAY_SHIFT   (3U)
 
#define CSR_MDCM_CFG_DWAY_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT)
 
#define CSR_MDCM_CFG_DSET_MASK   (0x7U)
 
#define CSR_MDCM_CFG_DSET_SHIFT   (0U)
 
#define CSR_MDCM_CFG_DSET_GET(x)   (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT)
 
#define CSR_MMSC_CFG_MSC_EXT_MASK   (0x80000000UL)
 
#define CSR_MMSC_CFG_MSC_EXT_SHIFT   (31U)
 
#define CSR_MMSC_CFG_MSC_EXT_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT)
 
#define CSR_MMSC_CFG_PPMA_MASK   (0x40000000UL)
 
#define CSR_MMSC_CFG_PPMA_SHIFT   (30U)
 
#define CSR_MMSC_CFG_PPMA_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT)
 
#define CSR_MMSC_CFG_EDSP_MASK   (0x20000000UL)
 
#define CSR_MMSC_CFG_EDSP_SHIFT   (29U)
 
#define CSR_MMSC_CFG_EDSP_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT)
 
#define CSR_MMSC_CFG_VCCTL_MASK   (0xC0000UL)
 
#define CSR_MMSC_CFG_VCCTL_SHIFT   (18U)
 
#define CSR_MMSC_CFG_VCCTL_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT)
 
#define CSR_MMSC_CFG_EFHW_MASK   (0x20000UL)
 
#define CSR_MMSC_CFG_EFHW_SHIFT   (17U)
 
#define CSR_MMSC_CFG_EFHW_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT)
 
#define CSR_MMSC_CFG_CCTLCSR_MASK   (0x10000UL)
 
#define CSR_MMSC_CFG_CCTLCSR_SHIFT   (16U)
 
#define CSR_MMSC_CFG_CCTLCSR_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT)
 
#define CSR_MMSC_CFG_PMNDS_MASK   (0x8000U)
 
#define CSR_MMSC_CFG_PMNDS_SHIFT   (15U)
 
#define CSR_MMSC_CFG_PMNDS_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT)
 
#define CSR_MMSC_CFG_LMSLVP_MASK   (0x4000U)
 
#define CSR_MMSC_CFG_LMSLVP_SHIFT   (14U)
 
#define CSR_MMSC_CFG_LMSLVP_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT)
 
#define CSR_MMSC_CFG_EV5PE_MASK   (0x2000U)
 
#define CSR_MMSC_CFG_EV5PE_SHIFT   (13U)
 
#define CSR_MMSC_CFG_EV5PE_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT)
 
#define CSR_MMSC_CFG_VPLIC_MASK   (0x1000U)
 
#define CSR_MMSC_CFG_VPLIC_SHIFT   (12U)
 
#define CSR_MMSC_CFG_VPLIC_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT)
 
#define CSR_MMSC_CFG_ACE_MASK   (0x40U)
 
#define CSR_MMSC_CFG_ACE_SHIFT   (6U)
 
#define CSR_MMSC_CFG_ACE_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT)
 
#define CSR_MMSC_CFG_HSP_MASK   (0x20U)
 
#define CSR_MMSC_CFG_HSP_SHIFT   (5U)
 
#define CSR_MMSC_CFG_HSP_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT)
 
#define CSR_MMSC_CFG_PFT_MASK   (0x10U)
 
#define CSR_MMSC_CFG_PFT_SHIFT   (4U)
 
#define CSR_MMSC_CFG_PFT_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT)
 
#define CSR_MMSC_CFG_ECD_MASK   (0x8U)
 
#define CSR_MMSC_CFG_ECD_SHIFT   (3U)
 
#define CSR_MMSC_CFG_ECD_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT)
 
#define CSR_MMSC_CFG_TLB_ECC_MASK   (0x6U)
 
#define CSR_MMSC_CFG_TLB_ECC_SHIFT   (1U)
 
#define CSR_MMSC_CFG_TLB_ECC_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT)
 
#define CSR_MMSC_CFG_ECC_MASK   (0x1U)
 
#define CSR_MMSC_CFG_ECC_SHIFT   (0U)
 
#define CSR_MMSC_CFG_ECC_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT)
 
#define CSR_MMSC_CFG2_FINV_MASK   (0x20U)
 
#define CSR_MMSC_CFG2_FINV_SHIFT   (5U)
 
#define CSR_MMSC_CFG2_FINV_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT)
 
#define CSR_MMSC_CFG2_ZFH_MASK   (0x2U)
 
#define CSR_MMSC_CFG2_ZFH_SHIFT   (1U)
 
#define CSR_MMSC_CFG2_ZFH_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT)
 
#define CSR_MMSC_CFG2_BF16CVT_MASK   (0x1U)
 
#define CSR_MMSC_CFG2_BF16CVT_SHIFT   (0U)
 
#define CSR_MMSC_CFG2_BF16CVT_GET(x)   (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT)
 

Macro Definition Documentation

◆ CSR_CYCLE

#define CSR_CYCLE   (0xC00)

◆ CSR_CYCLE_CYCLE_GET

#define CSR_CYCLE_CYCLE_GET (   x)    (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT)

◆ CSR_CYCLE_CYCLE_MASK

#define CSR_CYCLE_CYCLE_MASK   (0xFFFFFFFFUL)

◆ CSR_CYCLE_CYCLE_SET

#define CSR_CYCLE_CYCLE_SET (   x)    (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK)

◆ CSR_CYCLE_CYCLE_SHIFT

#define CSR_CYCLE_CYCLE_SHIFT   (0U)

◆ CSR_CYCLEH

#define CSR_CYCLEH   (0xC80)

◆ CSR_CYCLEH_CYCLEH_GET

#define CSR_CYCLEH_CYCLEH_GET (   x)    (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT)

◆ CSR_CYCLEH_CYCLEH_MASK

#define CSR_CYCLEH_CYCLEH_MASK   (0xFFFFFFFFUL)

◆ CSR_CYCLEH_CYCLEH_SET

#define CSR_CYCLEH_CYCLEH_SET (   x)    (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK)

◆ CSR_CYCLEH_CYCLEH_SHIFT

#define CSR_CYCLEH_CYCLEH_SHIFT   (0U)

◆ CSR_DCSR

#define CSR_DCSR   (0x7B0)

◆ CSR_DCSR_CAUSE_GET

#define CSR_DCSR_CAUSE_GET (   x)    (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT)

◆ CSR_DCSR_CAUSE_MASK

#define CSR_DCSR_CAUSE_MASK   (0x1C0U)

◆ CSR_DCSR_CAUSE_SHIFT

#define CSR_DCSR_CAUSE_SHIFT   (6U)

◆ CSR_DCSR_EBREAKM_GET

#define CSR_DCSR_EBREAKM_GET (   x)    (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT)

◆ CSR_DCSR_EBREAKM_MASK

#define CSR_DCSR_EBREAKM_MASK   (0x8000U)

◆ CSR_DCSR_EBREAKM_SET

#define CSR_DCSR_EBREAKM_SET (   x)    (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK)

◆ CSR_DCSR_EBREAKM_SHIFT

#define CSR_DCSR_EBREAKM_SHIFT   (15U)

◆ CSR_DCSR_EBREAKU_GET

#define CSR_DCSR_EBREAKU_GET (   x)    (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT)

◆ CSR_DCSR_EBREAKU_MASK

#define CSR_DCSR_EBREAKU_MASK   (0x1000U)

◆ CSR_DCSR_EBREAKU_SET

#define CSR_DCSR_EBREAKU_SET (   x)    (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK)

◆ CSR_DCSR_EBREAKU_SHIFT

#define CSR_DCSR_EBREAKU_SHIFT   (12U)

◆ CSR_DCSR_MPRVEN_GET

#define CSR_DCSR_MPRVEN_GET (   x)    (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT)

◆ CSR_DCSR_MPRVEN_MASK

#define CSR_DCSR_MPRVEN_MASK   (0x10U)

◆ CSR_DCSR_MPRVEN_SET

#define CSR_DCSR_MPRVEN_SET (   x)    (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK)

◆ CSR_DCSR_MPRVEN_SHIFT

#define CSR_DCSR_MPRVEN_SHIFT   (4U)

◆ CSR_DCSR_NMIP_GET

#define CSR_DCSR_NMIP_GET (   x)    (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT)

◆ CSR_DCSR_NMIP_MASK

#define CSR_DCSR_NMIP_MASK   (0x8U)

◆ CSR_DCSR_NMIP_SHIFT

#define CSR_DCSR_NMIP_SHIFT   (3U)

◆ CSR_DCSR_PRV_GET

#define CSR_DCSR_PRV_GET (   x)    (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT)

◆ CSR_DCSR_PRV_MASK

#define CSR_DCSR_PRV_MASK   (0x3U)

◆ CSR_DCSR_PRV_SET

#define CSR_DCSR_PRV_SET (   x)    (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK)

◆ CSR_DCSR_PRV_SHIFT

#define CSR_DCSR_PRV_SHIFT   (0U)

◆ CSR_DCSR_STEP_GET

#define CSR_DCSR_STEP_GET (   x)    (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT)

◆ CSR_DCSR_STEP_MASK

#define CSR_DCSR_STEP_MASK   (0x4U)

◆ CSR_DCSR_STEP_SET

#define CSR_DCSR_STEP_SET (   x)    (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK)

◆ CSR_DCSR_STEP_SHIFT

#define CSR_DCSR_STEP_SHIFT   (2U)

◆ CSR_DCSR_STEPIE_GET

#define CSR_DCSR_STEPIE_GET (   x)    (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT)

◆ CSR_DCSR_STEPIE_MASK

#define CSR_DCSR_STEPIE_MASK   (0x800U)

◆ CSR_DCSR_STEPIE_SET

#define CSR_DCSR_STEPIE_SET (   x)    (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK)

◆ CSR_DCSR_STEPIE_SHIFT

#define CSR_DCSR_STEPIE_SHIFT   (11U)

◆ CSR_DCSR_STOPCOUNT_GET

#define CSR_DCSR_STOPCOUNT_GET (   x)    (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT)

◆ CSR_DCSR_STOPCOUNT_MASK

#define CSR_DCSR_STOPCOUNT_MASK   (0x400U)

◆ CSR_DCSR_STOPCOUNT_SET

#define CSR_DCSR_STOPCOUNT_SET (   x)    (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK)

◆ CSR_DCSR_STOPCOUNT_SHIFT

#define CSR_DCSR_STOPCOUNT_SHIFT   (10U)

◆ CSR_DCSR_STOPTIME_GET

#define CSR_DCSR_STOPTIME_GET (   x)    (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT)

◆ CSR_DCSR_STOPTIME_MASK

#define CSR_DCSR_STOPTIME_MASK   (0x200U)

◆ CSR_DCSR_STOPTIME_SET

#define CSR_DCSR_STOPTIME_SET (   x)    (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK)

◆ CSR_DCSR_STOPTIME_SHIFT

#define CSR_DCSR_STOPTIME_SHIFT   (9U)

◆ CSR_DCSR_XDEBUGVER_GET

#define CSR_DCSR_XDEBUGVER_GET (   x)    (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT)

◆ CSR_DCSR_XDEBUGVER_MASK

#define CSR_DCSR_XDEBUGVER_MASK   (0xF0000000UL)

◆ CSR_DCSR_XDEBUGVER_SHIFT

#define CSR_DCSR_XDEBUGVER_SHIFT   (28U)

◆ CSR_DDCAUSE

#define CSR_DDCAUSE   (0x7E1)

◆ CSR_DDCAUSE_MAINTYPE_GET

#define CSR_DDCAUSE_MAINTYPE_GET (   x)    (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT)

◆ CSR_DDCAUSE_MAINTYPE_MASK

#define CSR_DDCAUSE_MAINTYPE_MASK   (0xFFU)

◆ CSR_DDCAUSE_MAINTYPE_SHIFT

#define CSR_DDCAUSE_MAINTYPE_SHIFT   (0U)

◆ CSR_DDCAUSE_SUBTYPE_GET

#define CSR_DDCAUSE_SUBTYPE_GET (   x)    (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT)

◆ CSR_DDCAUSE_SUBTYPE_MASK

#define CSR_DDCAUSE_SUBTYPE_MASK   (0xFF00U)

◆ CSR_DDCAUSE_SUBTYPE_SHIFT

#define CSR_DDCAUSE_SUBTYPE_SHIFT   (8U)

◆ CSR_DEXC2DBG

#define CSR_DEXC2DBG   (0x7E0)

◆ CSR_DEXC2DBG_ACE_GET

#define CSR_DEXC2DBG_ACE_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT)

◆ CSR_DEXC2DBG_ACE_MASK

#define CSR_DEXC2DBG_ACE_MASK   (0x2000U)

◆ CSR_DEXC2DBG_ACE_SET

#define CSR_DEXC2DBG_ACE_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK)

◆ CSR_DEXC2DBG_ACE_SHIFT

#define CSR_DEXC2DBG_ACE_SHIFT   (13U)

◆ CSR_DEXC2DBG_BWE_GET

#define CSR_DEXC2DBG_BWE_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT)

◆ CSR_DEXC2DBG_BWE_MASK

#define CSR_DEXC2DBG_BWE_MASK   (0x8000U)

◆ CSR_DEXC2DBG_BWE_SET

#define CSR_DEXC2DBG_BWE_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK)

◆ CSR_DEXC2DBG_BWE_SHIFT

#define CSR_DEXC2DBG_BWE_SHIFT   (15U)

◆ CSR_DEXC2DBG_HSP_GET

#define CSR_DEXC2DBG_HSP_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT)

◆ CSR_DEXC2DBG_HSP_MASK

#define CSR_DEXC2DBG_HSP_MASK   (0x1000U)

◆ CSR_DEXC2DBG_HSP_SET

#define CSR_DEXC2DBG_HSP_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK)

◆ CSR_DEXC2DBG_HSP_SHIFT

#define CSR_DEXC2DBG_HSP_SHIFT   (12U)

◆ CSR_DEXC2DBG_IAF_GET

#define CSR_DEXC2DBG_IAF_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT)

◆ CSR_DEXC2DBG_IAF_MASK

#define CSR_DEXC2DBG_IAF_MASK   (0x2U)

◆ CSR_DEXC2DBG_IAF_SET

#define CSR_DEXC2DBG_IAF_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK)

◆ CSR_DEXC2DBG_IAF_SHIFT

#define CSR_DEXC2DBG_IAF_SHIFT   (1U)

◆ CSR_DEXC2DBG_IAM_GET

#define CSR_DEXC2DBG_IAM_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT)

◆ CSR_DEXC2DBG_IAM_MASK

#define CSR_DEXC2DBG_IAM_MASK   (0x1U)

◆ CSR_DEXC2DBG_IAM_SET

#define CSR_DEXC2DBG_IAM_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK)

◆ CSR_DEXC2DBG_IAM_SHIFT

#define CSR_DEXC2DBG_IAM_SHIFT   (0U)

◆ CSR_DEXC2DBG_II_GET

#define CSR_DEXC2DBG_II_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT)

◆ CSR_DEXC2DBG_II_MASK

#define CSR_DEXC2DBG_II_MASK   (0x4U)

◆ CSR_DEXC2DBG_II_SET

#define CSR_DEXC2DBG_II_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK)

◆ CSR_DEXC2DBG_II_SHIFT

#define CSR_DEXC2DBG_II_SHIFT   (2U)

◆ CSR_DEXC2DBG_LAF_GET

#define CSR_DEXC2DBG_LAF_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT)

◆ CSR_DEXC2DBG_LAF_MASK

#define CSR_DEXC2DBG_LAF_MASK   (0x20U)

◆ CSR_DEXC2DBG_LAF_SET

#define CSR_DEXC2DBG_LAF_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK)

◆ CSR_DEXC2DBG_LAF_SHIFT

#define CSR_DEXC2DBG_LAF_SHIFT   (5U)

◆ CSR_DEXC2DBG_LAM_GET

#define CSR_DEXC2DBG_LAM_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT)

◆ CSR_DEXC2DBG_LAM_MASK

#define CSR_DEXC2DBG_LAM_MASK   (0x10U)

◆ CSR_DEXC2DBG_LAM_SET

#define CSR_DEXC2DBG_LAM_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK)

◆ CSR_DEXC2DBG_LAM_SHIFT

#define CSR_DEXC2DBG_LAM_SHIFT   (4U)

◆ CSR_DEXC2DBG_MEC_GET

#define CSR_DEXC2DBG_MEC_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT)

◆ CSR_DEXC2DBG_MEC_MASK

#define CSR_DEXC2DBG_MEC_MASK   (0x800U)

◆ CSR_DEXC2DBG_MEC_SET

#define CSR_DEXC2DBG_MEC_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK)

◆ CSR_DEXC2DBG_MEC_SHIFT

#define CSR_DEXC2DBG_MEC_SHIFT   (11U)

◆ CSR_DEXC2DBG_NMI_GET

#define CSR_DEXC2DBG_NMI_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT)

◆ CSR_DEXC2DBG_NMI_MASK

#define CSR_DEXC2DBG_NMI_MASK   (0x8U)

◆ CSR_DEXC2DBG_NMI_SET

#define CSR_DEXC2DBG_NMI_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK)

◆ CSR_DEXC2DBG_NMI_SHIFT

#define CSR_DEXC2DBG_NMI_SHIFT   (3U)

◆ CSR_DEXC2DBG_PMOV_GET

#define CSR_DEXC2DBG_PMOV_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT)

◆ CSR_DEXC2DBG_PMOV_MASK

#define CSR_DEXC2DBG_PMOV_MASK   (0x80000UL)

◆ CSR_DEXC2DBG_PMOV_SET

#define CSR_DEXC2DBG_PMOV_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK)

◆ CSR_DEXC2DBG_PMOV_SHIFT

#define CSR_DEXC2DBG_PMOV_SHIFT   (19U)

◆ CSR_DEXC2DBG_SAF_GET

#define CSR_DEXC2DBG_SAF_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT)

◆ CSR_DEXC2DBG_SAF_MASK

#define CSR_DEXC2DBG_SAF_MASK   (0x80U)

◆ CSR_DEXC2DBG_SAF_SET

#define CSR_DEXC2DBG_SAF_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK)

◆ CSR_DEXC2DBG_SAF_SHIFT

#define CSR_DEXC2DBG_SAF_SHIFT   (7U)

◆ CSR_DEXC2DBG_SAM_GET

#define CSR_DEXC2DBG_SAM_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT)

◆ CSR_DEXC2DBG_SAM_MASK

#define CSR_DEXC2DBG_SAM_MASK   (0x40U)

◆ CSR_DEXC2DBG_SAM_SET

#define CSR_DEXC2DBG_SAM_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK)

◆ CSR_DEXC2DBG_SAM_SHIFT

#define CSR_DEXC2DBG_SAM_SHIFT   (6U)

◆ CSR_DEXC2DBG_SLPECC_GET

#define CSR_DEXC2DBG_SLPECC_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT)

◆ CSR_DEXC2DBG_SLPECC_MASK

#define CSR_DEXC2DBG_SLPECC_MASK   (0x4000U)

◆ CSR_DEXC2DBG_SLPECC_SET

#define CSR_DEXC2DBG_SLPECC_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK)

◆ CSR_DEXC2DBG_SLPECC_SHIFT

#define CSR_DEXC2DBG_SLPECC_SHIFT   (14U)

◆ CSR_DEXC2DBG_UEC_GET

#define CSR_DEXC2DBG_UEC_GET (   x)    (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT)

◆ CSR_DEXC2DBG_UEC_MASK

#define CSR_DEXC2DBG_UEC_MASK   (0x100U)

◆ CSR_DEXC2DBG_UEC_SET

#define CSR_DEXC2DBG_UEC_SET (   x)    (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK)

◆ CSR_DEXC2DBG_UEC_SHIFT

#define CSR_DEXC2DBG_UEC_SHIFT   (8U)

◆ CSR_DPC

#define CSR_DPC   (0x7B1)

◆ CSR_DPC_DPC_GET

#define CSR_DPC_DPC_GET (   x)    (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT)

◆ CSR_DPC_DPC_MASK

#define CSR_DPC_DPC_MASK   (0xFFFFFFFFUL)

◆ CSR_DPC_DPC_SET

#define CSR_DPC_DPC_SET (   x)    (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK)

◆ CSR_DPC_DPC_SHIFT

#define CSR_DPC_DPC_SHIFT   (0U)

◆ CSR_DSCRATCH0

#define CSR_DSCRATCH0   (0x7B2)

◆ CSR_DSCRATCH0_DSCRATCH_GET

#define CSR_DSCRATCH0_DSCRATCH_GET (   x)    (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT)

◆ CSR_DSCRATCH0_DSCRATCH_MASK

#define CSR_DSCRATCH0_DSCRATCH_MASK   (0xFFFFFFFFUL)

◆ CSR_DSCRATCH0_DSCRATCH_SHIFT

#define CSR_DSCRATCH0_DSCRATCH_SHIFT   (0U)

◆ CSR_DSCRATCH1

#define CSR_DSCRATCH1   (0x7B3)

◆ CSR_DSCRATCH1_DSCRATCH_GET

#define CSR_DSCRATCH1_DSCRATCH_GET (   x)    (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT)

◆ CSR_DSCRATCH1_DSCRATCH_MASK

#define CSR_DSCRATCH1_DSCRATCH_MASK   (0xFFFFFFFFUL)

◆ CSR_DSCRATCH1_DSCRATCH_SHIFT

#define CSR_DSCRATCH1_DSCRATCH_SHIFT   (0U)

◆ CSR_ETRIGGER

#define CSR_ETRIGGER   (0x7A1)

◆ CSR_ETRIGGER_ACTION_GET

#define CSR_ETRIGGER_ACTION_GET (   x)    (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT)

◆ CSR_ETRIGGER_ACTION_MASK

#define CSR_ETRIGGER_ACTION_MASK   (0x3FU)

◆ CSR_ETRIGGER_ACTION_SET

#define CSR_ETRIGGER_ACTION_SET (   x)    (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK)

◆ CSR_ETRIGGER_ACTION_SHIFT

#define CSR_ETRIGGER_ACTION_SHIFT   (0U)

◆ CSR_ETRIGGER_DMODE_GET

#define CSR_ETRIGGER_DMODE_GET (   x)    (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT)

◆ CSR_ETRIGGER_DMODE_MASK

#define CSR_ETRIGGER_DMODE_MASK   (0x8000000UL)

◆ CSR_ETRIGGER_DMODE_SET

#define CSR_ETRIGGER_DMODE_SET (   x)    (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK)

◆ CSR_ETRIGGER_DMODE_SHIFT

#define CSR_ETRIGGER_DMODE_SHIFT   (27U)

◆ CSR_ETRIGGER_M_GET

#define CSR_ETRIGGER_M_GET (   x)    (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT)

◆ CSR_ETRIGGER_M_MASK

#define CSR_ETRIGGER_M_MASK   (0x200U)

◆ CSR_ETRIGGER_M_SET

#define CSR_ETRIGGER_M_SET (   x)    (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK)

◆ CSR_ETRIGGER_M_SHIFT

#define CSR_ETRIGGER_M_SHIFT   (9U)

◆ CSR_ETRIGGER_NMI_GET

#define CSR_ETRIGGER_NMI_GET (   x)    (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT)

◆ CSR_ETRIGGER_NMI_MASK

#define CSR_ETRIGGER_NMI_MASK   (0x400U)

◆ CSR_ETRIGGER_NMI_SET

#define CSR_ETRIGGER_NMI_SET (   x)    (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK)

◆ CSR_ETRIGGER_NMI_SHIFT

#define CSR_ETRIGGER_NMI_SHIFT   (10U)

◆ CSR_ETRIGGER_TYPE_GET

#define CSR_ETRIGGER_TYPE_GET (   x)    (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT)

◆ CSR_ETRIGGER_TYPE_MASK

#define CSR_ETRIGGER_TYPE_MASK   (0xF0000000UL)

◆ CSR_ETRIGGER_TYPE_SET

#define CSR_ETRIGGER_TYPE_SET (   x)    (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK)

◆ CSR_ETRIGGER_TYPE_SHIFT

#define CSR_ETRIGGER_TYPE_SHIFT   (28U)

◆ CSR_ETRIGGER_U_GET

#define CSR_ETRIGGER_U_GET (   x)    (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT)

◆ CSR_ETRIGGER_U_MASK

#define CSR_ETRIGGER_U_MASK   (0x40U)

◆ CSR_ETRIGGER_U_SET

#define CSR_ETRIGGER_U_SET (   x)    (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK)

◆ CSR_ETRIGGER_U_SHIFT

#define CSR_ETRIGGER_U_SHIFT   (6U)

◆ CSR_ICOUNT

#define CSR_ICOUNT   (0x7A1)

◆ CSR_ICOUNT_ACTION_GET

#define CSR_ICOUNT_ACTION_GET (   x)    (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT)

◆ CSR_ICOUNT_ACTION_MASK

#define CSR_ICOUNT_ACTION_MASK   (0x3FU)

◆ CSR_ICOUNT_ACTION_SET

#define CSR_ICOUNT_ACTION_SET (   x)    (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK)

◆ CSR_ICOUNT_ACTION_SHIFT

#define CSR_ICOUNT_ACTION_SHIFT   (0U)

◆ CSR_ICOUNT_COUNT_GET

#define CSR_ICOUNT_COUNT_GET (   x)    (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT)

◆ CSR_ICOUNT_COUNT_MASK

#define CSR_ICOUNT_COUNT_MASK   (0x400U)

◆ CSR_ICOUNT_COUNT_SHIFT

#define CSR_ICOUNT_COUNT_SHIFT   (10U)

◆ CSR_ICOUNT_DMODE_GET

#define CSR_ICOUNT_DMODE_GET (   x)    (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT)

◆ CSR_ICOUNT_DMODE_MASK

#define CSR_ICOUNT_DMODE_MASK   (0x8000000UL)

◆ CSR_ICOUNT_DMODE_SET

#define CSR_ICOUNT_DMODE_SET (   x)    (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK)

◆ CSR_ICOUNT_DMODE_SHIFT

#define CSR_ICOUNT_DMODE_SHIFT   (27U)

◆ CSR_ICOUNT_M_GET

#define CSR_ICOUNT_M_GET (   x)    (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT)

◆ CSR_ICOUNT_M_MASK

#define CSR_ICOUNT_M_MASK   (0x200U)

◆ CSR_ICOUNT_M_SET

#define CSR_ICOUNT_M_SET (   x)    (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK)

◆ CSR_ICOUNT_M_SHIFT

#define CSR_ICOUNT_M_SHIFT   (9U)

◆ CSR_ICOUNT_TYPE_GET

#define CSR_ICOUNT_TYPE_GET (   x)    (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT)

◆ CSR_ICOUNT_TYPE_MASK

#define CSR_ICOUNT_TYPE_MASK   (0xF0000000UL)

◆ CSR_ICOUNT_TYPE_SET

#define CSR_ICOUNT_TYPE_SET (   x)    (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK)

◆ CSR_ICOUNT_TYPE_SHIFT

#define CSR_ICOUNT_TYPE_SHIFT   (28U)

◆ CSR_ICOUNT_U_GET

#define CSR_ICOUNT_U_GET (   x)    (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT)

◆ CSR_ICOUNT_U_MASK

#define CSR_ICOUNT_U_MASK   (0x40U)

◆ CSR_ICOUNT_U_SET

#define CSR_ICOUNT_U_SET (   x)    (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK)

◆ CSR_ICOUNT_U_SHIFT

#define CSR_ICOUNT_U_SHIFT   (6U)

◆ CSR_ITRIGGER

#define CSR_ITRIGGER   (0x7A1)

◆ CSR_ITRIGGER_ACTION_GET

#define CSR_ITRIGGER_ACTION_GET (   x)    (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT)

◆ CSR_ITRIGGER_ACTION_MASK

#define CSR_ITRIGGER_ACTION_MASK   (0x3FU)

◆ CSR_ITRIGGER_ACTION_SET

#define CSR_ITRIGGER_ACTION_SET (   x)    (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK)

◆ CSR_ITRIGGER_ACTION_SHIFT

#define CSR_ITRIGGER_ACTION_SHIFT   (0U)

◆ CSR_ITRIGGER_DMODE_GET

#define CSR_ITRIGGER_DMODE_GET (   x)    (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT)

◆ CSR_ITRIGGER_DMODE_MASK

#define CSR_ITRIGGER_DMODE_MASK   (0x8000000UL)

◆ CSR_ITRIGGER_DMODE_SET

#define CSR_ITRIGGER_DMODE_SET (   x)    (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK)

◆ CSR_ITRIGGER_DMODE_SHIFT

#define CSR_ITRIGGER_DMODE_SHIFT   (27U)

◆ CSR_ITRIGGER_M_GET

#define CSR_ITRIGGER_M_GET (   x)    (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT)

◆ CSR_ITRIGGER_M_MASK

#define CSR_ITRIGGER_M_MASK   (0x200U)

◆ CSR_ITRIGGER_M_SET

#define CSR_ITRIGGER_M_SET (   x)    (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK)

◆ CSR_ITRIGGER_M_SHIFT

#define CSR_ITRIGGER_M_SHIFT   (9U)

◆ CSR_ITRIGGER_TYPE_GET

#define CSR_ITRIGGER_TYPE_GET (   x)    (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT)

◆ CSR_ITRIGGER_TYPE_MASK

#define CSR_ITRIGGER_TYPE_MASK   (0xF0000000UL)

◆ CSR_ITRIGGER_TYPE_SET

#define CSR_ITRIGGER_TYPE_SET (   x)    (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK)

◆ CSR_ITRIGGER_TYPE_SHIFT

#define CSR_ITRIGGER_TYPE_SHIFT   (28U)

◆ CSR_ITRIGGER_U_GET

#define CSR_ITRIGGER_U_GET (   x)    (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT)

◆ CSR_ITRIGGER_U_MASK

#define CSR_ITRIGGER_U_MASK   (0x40U)

◆ CSR_ITRIGGER_U_SET

#define CSR_ITRIGGER_U_SET (   x)    (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK)

◆ CSR_ITRIGGER_U_SHIFT

#define CSR_ITRIGGER_U_SHIFT   (6U)

◆ CSR_MARCHID

#define CSR_MARCHID   (0xF12)

◆ CSR_MARCHID_CPU_ID_GET

#define CSR_MARCHID_CPU_ID_GET (   x)    (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT)

◆ CSR_MARCHID_CPU_ID_MASK

#define CSR_MARCHID_CPU_ID_MASK   (0x7FFFFFFFUL)

◆ CSR_MARCHID_CPU_ID_SHIFT

#define CSR_MARCHID_CPU_ID_SHIFT   (0U)

◆ CSR_MCACHE_CTL

#define CSR_MCACHE_CTL   (0x7CA)

◆ CSR_MCACHE_CTL_CCTL_SUEN_GET

#define CSR_MCACHE_CTL_CCTL_SUEN_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT)

◆ CSR_MCACHE_CTL_CCTL_SUEN_MASK

#define CSR_MCACHE_CTL_CCTL_SUEN_MASK   (0x100U)

◆ CSR_MCACHE_CTL_CCTL_SUEN_SET

#define CSR_MCACHE_CTL_CCTL_SUEN_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK)

◆ CSR_MCACHE_CTL_CCTL_SUEN_SHIFT

#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT   (8U)

◆ CSR_MCACHE_CTL_DC_ECCEN_GET

#define CSR_MCACHE_CTL_DC_ECCEN_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT)

◆ CSR_MCACHE_CTL_DC_ECCEN_MASK

#define CSR_MCACHE_CTL_DC_ECCEN_MASK   (0x30U)

◆ CSR_MCACHE_CTL_DC_ECCEN_SET

#define CSR_MCACHE_CTL_DC_ECCEN_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK)

◆ CSR_MCACHE_CTL_DC_ECCEN_SHIFT

#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT   (4U)

◆ CSR_MCACHE_CTL_DC_EN_GET

#define CSR_MCACHE_CTL_DC_EN_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT)

◆ CSR_MCACHE_CTL_DC_EN_MASK

#define CSR_MCACHE_CTL_DC_EN_MASK   (0x2U)

◆ CSR_MCACHE_CTL_DC_EN_SET

#define CSR_MCACHE_CTL_DC_EN_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK)

◆ CSR_MCACHE_CTL_DC_EN_SHIFT

#define CSR_MCACHE_CTL_DC_EN_SHIFT   (1U)

◆ CSR_MCACHE_CTL_DC_RWECC_GET

#define CSR_MCACHE_CTL_DC_RWECC_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT)

◆ CSR_MCACHE_CTL_DC_RWECC_MASK

#define CSR_MCACHE_CTL_DC_RWECC_MASK   (0x80U)

◆ CSR_MCACHE_CTL_DC_RWECC_SET

#define CSR_MCACHE_CTL_DC_RWECC_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK)

◆ CSR_MCACHE_CTL_DC_RWECC_SHIFT

#define CSR_MCACHE_CTL_DC_RWECC_SHIFT   (7U)

◆ CSR_MCACHE_CTL_IC_ECCEN_GET

#define CSR_MCACHE_CTL_IC_ECCEN_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT)

◆ CSR_MCACHE_CTL_IC_ECCEN_MASK

#define CSR_MCACHE_CTL_IC_ECCEN_MASK   (0xCU)

◆ CSR_MCACHE_CTL_IC_ECCEN_SET

#define CSR_MCACHE_CTL_IC_ECCEN_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK)

◆ CSR_MCACHE_CTL_IC_ECCEN_SHIFT

#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT   (2U)

◆ CSR_MCACHE_CTL_IC_EN_GET

#define CSR_MCACHE_CTL_IC_EN_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT)

◆ CSR_MCACHE_CTL_IC_EN_MASK

#define CSR_MCACHE_CTL_IC_EN_MASK   (0x1U)

◆ CSR_MCACHE_CTL_IC_EN_SET

#define CSR_MCACHE_CTL_IC_EN_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK)

◆ CSR_MCACHE_CTL_IC_EN_SHIFT

#define CSR_MCACHE_CTL_IC_EN_SHIFT   (0U)

◆ CSR_MCACHE_CTL_IC_FIRST_WORD_GET

#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT)

◆ CSR_MCACHE_CTL_IC_FIRST_WORD_MASK

#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK   (0x800U)

◆ CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT

#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT   (11U)

◆ CSR_MCACHE_CTL_IC_RWECC_GET

#define CSR_MCACHE_CTL_IC_RWECC_GET (   x)    (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT)

◆ CSR_MCACHE_CTL_IC_RWECC_MASK

#define CSR_MCACHE_CTL_IC_RWECC_MASK   (0x40U)

◆ CSR_MCACHE_CTL_IC_RWECC_SET

#define CSR_MCACHE_CTL_IC_RWECC_SET (   x)    (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK)

◆ CSR_MCACHE_CTL_IC_RWECC_SHIFT

#define CSR_MCACHE_CTL_IC_RWECC_SHIFT   (6U)

◆ CSR_MCAUSE

#define CSR_MCAUSE   (0x342)

◆ CSR_MCAUSE_EXCEPTION_CODE_GET

#define CSR_MCAUSE_EXCEPTION_CODE_GET (   x)    (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT)

◆ CSR_MCAUSE_EXCEPTION_CODE_MASK

#define CSR_MCAUSE_EXCEPTION_CODE_MASK   (0xFFFU)

◆ CSR_MCAUSE_EXCEPTION_CODE_SET

#define CSR_MCAUSE_EXCEPTION_CODE_SET (   x)    (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK)

◆ CSR_MCAUSE_EXCEPTION_CODE_SHIFT

#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT   (0U)

◆ CSR_MCAUSE_INTERRUPT_GET

#define CSR_MCAUSE_INTERRUPT_GET (   x)    (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT)

◆ CSR_MCAUSE_INTERRUPT_MASK

#define CSR_MCAUSE_INTERRUPT_MASK   (0x80000000UL)

◆ CSR_MCAUSE_INTERRUPT_SET

#define CSR_MCAUSE_INTERRUPT_SET (   x)    (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK)

◆ CSR_MCAUSE_INTERRUPT_SHIFT

#define CSR_MCAUSE_INTERRUPT_SHIFT   (31U)

◆ CSR_MCCTLBEGINADDR

#define CSR_MCCTLBEGINADDR   (0x7CB)

◆ CSR_MCCTLBEGINADDR_VA_GET

#define CSR_MCCTLBEGINADDR_VA_GET (   x)    (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT)

◆ CSR_MCCTLBEGINADDR_VA_MASK

#define CSR_MCCTLBEGINADDR_VA_MASK   (0xFFFFFFFFUL)

◆ CSR_MCCTLBEGINADDR_VA_SET

#define CSR_MCCTLBEGINADDR_VA_SET (   x)    (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK)

◆ CSR_MCCTLBEGINADDR_VA_SHIFT

#define CSR_MCCTLBEGINADDR_VA_SHIFT   (0U)

◆ CSR_MCCTLCOMMAND

#define CSR_MCCTLCOMMAND   (0x7CC)

◆ CSR_MCCTLCOMMAND_VA_GET

#define CSR_MCCTLCOMMAND_VA_GET (   x)    (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT)

◆ CSR_MCCTLCOMMAND_VA_MASK

#define CSR_MCCTLCOMMAND_VA_MASK   (0x1FU)

◆ CSR_MCCTLCOMMAND_VA_SET

#define CSR_MCCTLCOMMAND_VA_SET (   x)    (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK)

◆ CSR_MCCTLCOMMAND_VA_SHIFT

#define CSR_MCCTLCOMMAND_VA_SHIFT   (0U)

◆ CSR_MCCTLDATA

#define CSR_MCCTLDATA   (0x7CD)

◆ CSR_MCCTLDATA_VA_GET

#define CSR_MCCTLDATA_VA_GET (   x)    (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT)

◆ CSR_MCCTLDATA_VA_MASK

#define CSR_MCCTLDATA_VA_MASK   (0x1FU)

◆ CSR_MCCTLDATA_VA_SET

#define CSR_MCCTLDATA_VA_SET (   x)    (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK)

◆ CSR_MCCTLDATA_VA_SHIFT

#define CSR_MCCTLDATA_VA_SHIFT   (0U)

◆ CSR_MCONTEXT

#define CSR_MCONTEXT   (0x7A8)

◆ CSR_MCONTEXT_MCONTEXT_GET

#define CSR_MCONTEXT_MCONTEXT_GET (   x)    (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT)

◆ CSR_MCONTEXT_MCONTEXT_MASK

#define CSR_MCONTEXT_MCONTEXT_MASK   (0x3FU)

◆ CSR_MCONTEXT_MCONTEXT_SET

#define CSR_MCONTEXT_MCONTEXT_SET (   x)    (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK)

◆ CSR_MCONTEXT_MCONTEXT_SHIFT

#define CSR_MCONTEXT_MCONTEXT_SHIFT   (0U)

◆ CSR_MCONTROL

#define CSR_MCONTROL   (0x7A1)

◆ CSR_MCONTROL_ACTION_GET

#define CSR_MCONTROL_ACTION_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT)

◆ CSR_MCONTROL_ACTION_MASK

#define CSR_MCONTROL_ACTION_MASK   (0xF000U)

◆ CSR_MCONTROL_ACTION_SET

#define CSR_MCONTROL_ACTION_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK)

◆ CSR_MCONTROL_ACTION_SHIFT

#define CSR_MCONTROL_ACTION_SHIFT   (12U)

◆ CSR_MCONTROL_CHAIN_GET

#define CSR_MCONTROL_CHAIN_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT)

◆ CSR_MCONTROL_CHAIN_MASK

#define CSR_MCONTROL_CHAIN_MASK   (0x800U)

◆ CSR_MCONTROL_CHAIN_SET

#define CSR_MCONTROL_CHAIN_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK)

◆ CSR_MCONTROL_CHAIN_SHIFT

#define CSR_MCONTROL_CHAIN_SHIFT   (11U)

◆ CSR_MCONTROL_DMODE_GET

#define CSR_MCONTROL_DMODE_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT)

◆ CSR_MCONTROL_DMODE_MASK

#define CSR_MCONTROL_DMODE_MASK   (0x8000000UL)

◆ CSR_MCONTROL_DMODE_SET

#define CSR_MCONTROL_DMODE_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK)

◆ CSR_MCONTROL_DMODE_SHIFT

#define CSR_MCONTROL_DMODE_SHIFT   (27U)

◆ CSR_MCONTROL_EXECUTE_GET

#define CSR_MCONTROL_EXECUTE_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT)

◆ CSR_MCONTROL_EXECUTE_MASK

#define CSR_MCONTROL_EXECUTE_MASK   (0x4U)

◆ CSR_MCONTROL_EXECUTE_SET

#define CSR_MCONTROL_EXECUTE_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK)

◆ CSR_MCONTROL_EXECUTE_SHIFT

#define CSR_MCONTROL_EXECUTE_SHIFT   (2U)

◆ CSR_MCONTROL_LOAD_GET

#define CSR_MCONTROL_LOAD_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT)

◆ CSR_MCONTROL_LOAD_MASK

#define CSR_MCONTROL_LOAD_MASK   (0x1U)

◆ CSR_MCONTROL_LOAD_SET

#define CSR_MCONTROL_LOAD_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK)

◆ CSR_MCONTROL_LOAD_SHIFT

#define CSR_MCONTROL_LOAD_SHIFT   (0U)

◆ CSR_MCONTROL_M_GET

#define CSR_MCONTROL_M_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT)

◆ CSR_MCONTROL_M_MASK

#define CSR_MCONTROL_M_MASK   (0x40U)

◆ CSR_MCONTROL_M_SET

#define CSR_MCONTROL_M_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK)

◆ CSR_MCONTROL_M_SHIFT

#define CSR_MCONTROL_M_SHIFT   (6U)

◆ CSR_MCONTROL_MASKMAX_GET

#define CSR_MCONTROL_MASKMAX_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT)

◆ CSR_MCONTROL_MASKMAX_MASK

#define CSR_MCONTROL_MASKMAX_MASK   (0x7E00000UL)

◆ CSR_MCONTROL_MASKMAX_SHIFT

#define CSR_MCONTROL_MASKMAX_SHIFT   (21U)

◆ CSR_MCONTROL_MATCH_GET

#define CSR_MCONTROL_MATCH_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT)

◆ CSR_MCONTROL_MATCH_MASK

#define CSR_MCONTROL_MATCH_MASK   (0x780U)

◆ CSR_MCONTROL_MATCH_SET

#define CSR_MCONTROL_MATCH_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK)

◆ CSR_MCONTROL_MATCH_SHIFT

#define CSR_MCONTROL_MATCH_SHIFT   (7U)

◆ CSR_MCONTROL_STORE_GET

#define CSR_MCONTROL_STORE_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT)

◆ CSR_MCONTROL_STORE_MASK

#define CSR_MCONTROL_STORE_MASK   (0x2U)

◆ CSR_MCONTROL_STORE_SET

#define CSR_MCONTROL_STORE_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK)

◆ CSR_MCONTROL_STORE_SHIFT

#define CSR_MCONTROL_STORE_SHIFT   (1U)

◆ CSR_MCONTROL_TYPE_GET

#define CSR_MCONTROL_TYPE_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT)

◆ CSR_MCONTROL_TYPE_MASK

#define CSR_MCONTROL_TYPE_MASK   (0xF0000000UL)

◆ CSR_MCONTROL_TYPE_SET

#define CSR_MCONTROL_TYPE_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK)

◆ CSR_MCONTROL_TYPE_SHIFT

#define CSR_MCONTROL_TYPE_SHIFT   (28U)

◆ CSR_MCONTROL_U_GET

#define CSR_MCONTROL_U_GET (   x)    (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT)

◆ CSR_MCONTROL_U_MASK

#define CSR_MCONTROL_U_MASK   (0x8U)

◆ CSR_MCONTROL_U_SET

#define CSR_MCONTROL_U_SET (   x)    (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK)

◆ CSR_MCONTROL_U_SHIFT

#define CSR_MCONTROL_U_SHIFT   (3U)

◆ CSR_MCOUNTEREN

#define CSR_MCOUNTEREN   (0x306)

◆ CSR_MCOUNTEREN_CY_GET

#define CSR_MCOUNTEREN_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT)

◆ CSR_MCOUNTEREN_CY_MASK

#define CSR_MCOUNTEREN_CY_MASK   (0x1U)

◆ CSR_MCOUNTEREN_CY_SET

#define CSR_MCOUNTEREN_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK)

◆ CSR_MCOUNTEREN_CY_SHIFT

#define CSR_MCOUNTEREN_CY_SHIFT   (0U)

◆ CSR_MCOUNTEREN_HPM3_GET

#define CSR_MCOUNTEREN_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT)

◆ CSR_MCOUNTEREN_HPM3_MASK

#define CSR_MCOUNTEREN_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTEREN_HPM3_SET

#define CSR_MCOUNTEREN_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK)

◆ CSR_MCOUNTEREN_HPM3_SHIFT

#define CSR_MCOUNTEREN_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTEREN_HPM4_GET

#define CSR_MCOUNTEREN_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT)

◆ CSR_MCOUNTEREN_HPM4_MASK

#define CSR_MCOUNTEREN_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTEREN_HPM4_SET

#define CSR_MCOUNTEREN_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK)

◆ CSR_MCOUNTEREN_HPM4_SHIFT

#define CSR_MCOUNTEREN_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTEREN_HPM5_GET

#define CSR_MCOUNTEREN_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT)

◆ CSR_MCOUNTEREN_HPM5_MASK

#define CSR_MCOUNTEREN_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTEREN_HPM5_SET

#define CSR_MCOUNTEREN_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK)

◆ CSR_MCOUNTEREN_HPM5_SHIFT

#define CSR_MCOUNTEREN_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTEREN_HPM6_GET

#define CSR_MCOUNTEREN_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT)

◆ CSR_MCOUNTEREN_HPM6_MASK

#define CSR_MCOUNTEREN_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTEREN_HPM6_SET

#define CSR_MCOUNTEREN_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK)

◆ CSR_MCOUNTEREN_HPM6_SHIFT

#define CSR_MCOUNTEREN_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTEREN_IR_GET

#define CSR_MCOUNTEREN_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT)

◆ CSR_MCOUNTEREN_IR_MASK

#define CSR_MCOUNTEREN_IR_MASK   (0x4U)

◆ CSR_MCOUNTEREN_IR_SET

#define CSR_MCOUNTEREN_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK)

◆ CSR_MCOUNTEREN_IR_SHIFT

#define CSR_MCOUNTEREN_IR_SHIFT   (2U)

◆ CSR_MCOUNTEREN_TM_GET

#define CSR_MCOUNTEREN_TM_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT)

◆ CSR_MCOUNTEREN_TM_MASK

#define CSR_MCOUNTEREN_TM_MASK   (0x2U)

◆ CSR_MCOUNTEREN_TM_SET

#define CSR_MCOUNTEREN_TM_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK)

◆ CSR_MCOUNTEREN_TM_SHIFT

#define CSR_MCOUNTEREN_TM_SHIFT   (1U)

◆ CSR_MCOUNTERINTEN

#define CSR_MCOUNTERINTEN   (0x7CF)

◆ CSR_MCOUNTERINTEN_CY_GET

#define CSR_MCOUNTERINTEN_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT)

◆ CSR_MCOUNTERINTEN_CY_MASK

#define CSR_MCOUNTERINTEN_CY_MASK   (0x1U)

◆ CSR_MCOUNTERINTEN_CY_SET

#define CSR_MCOUNTERINTEN_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK)

◆ CSR_MCOUNTERINTEN_CY_SHIFT

#define CSR_MCOUNTERINTEN_CY_SHIFT   (0U)

◆ CSR_MCOUNTERINTEN_HPM3_GET

#define CSR_MCOUNTERINTEN_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT)

◆ CSR_MCOUNTERINTEN_HPM3_MASK

#define CSR_MCOUNTERINTEN_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTERINTEN_HPM3_SET

#define CSR_MCOUNTERINTEN_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK)

◆ CSR_MCOUNTERINTEN_HPM3_SHIFT

#define CSR_MCOUNTERINTEN_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTERINTEN_HPM4_GET

#define CSR_MCOUNTERINTEN_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT)

◆ CSR_MCOUNTERINTEN_HPM4_MASK

#define CSR_MCOUNTERINTEN_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTERINTEN_HPM4_SET

#define CSR_MCOUNTERINTEN_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK)

◆ CSR_MCOUNTERINTEN_HPM4_SHIFT

#define CSR_MCOUNTERINTEN_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTERINTEN_HPM5_GET

#define CSR_MCOUNTERINTEN_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT)

◆ CSR_MCOUNTERINTEN_HPM5_MASK

#define CSR_MCOUNTERINTEN_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTERINTEN_HPM5_SET

#define CSR_MCOUNTERINTEN_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK)

◆ CSR_MCOUNTERINTEN_HPM5_SHIFT

#define CSR_MCOUNTERINTEN_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTERINTEN_HPM6_GET

#define CSR_MCOUNTERINTEN_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT)

◆ CSR_MCOUNTERINTEN_HPM6_MASK

#define CSR_MCOUNTERINTEN_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTERINTEN_HPM6_SET

#define CSR_MCOUNTERINTEN_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK)

◆ CSR_MCOUNTERINTEN_HPM6_SHIFT

#define CSR_MCOUNTERINTEN_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTERINTEN_IR_GET

#define CSR_MCOUNTERINTEN_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT)

◆ CSR_MCOUNTERINTEN_IR_MASK

#define CSR_MCOUNTERINTEN_IR_MASK   (0x4U)

◆ CSR_MCOUNTERINTEN_IR_SET

#define CSR_MCOUNTERINTEN_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK)

◆ CSR_MCOUNTERINTEN_IR_SHIFT

#define CSR_MCOUNTERINTEN_IR_SHIFT   (2U)

◆ CSR_MCOUNTERMASK_M

#define CSR_MCOUNTERMASK_M   (0x7D1)

◆ CSR_MCOUNTERMASK_M_CY_GET

#define CSR_MCOUNTERMASK_M_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT)

◆ CSR_MCOUNTERMASK_M_CY_MASK

#define CSR_MCOUNTERMASK_M_CY_MASK   (0x1U)

◆ CSR_MCOUNTERMASK_M_CY_SET

#define CSR_MCOUNTERMASK_M_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK)

◆ CSR_MCOUNTERMASK_M_CY_SHIFT

#define CSR_MCOUNTERMASK_M_CY_SHIFT   (0U)

◆ CSR_MCOUNTERMASK_M_HPM3_GET

#define CSR_MCOUNTERMASK_M_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT)

◆ CSR_MCOUNTERMASK_M_HPM3_MASK

#define CSR_MCOUNTERMASK_M_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTERMASK_M_HPM3_SET

#define CSR_MCOUNTERMASK_M_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK)

◆ CSR_MCOUNTERMASK_M_HPM3_SHIFT

#define CSR_MCOUNTERMASK_M_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTERMASK_M_HPM4_GET

#define CSR_MCOUNTERMASK_M_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT)

◆ CSR_MCOUNTERMASK_M_HPM4_MASK

#define CSR_MCOUNTERMASK_M_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTERMASK_M_HPM4_SET

#define CSR_MCOUNTERMASK_M_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK)

◆ CSR_MCOUNTERMASK_M_HPM4_SHIFT

#define CSR_MCOUNTERMASK_M_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTERMASK_M_HPM5_GET

#define CSR_MCOUNTERMASK_M_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT)

◆ CSR_MCOUNTERMASK_M_HPM5_MASK

#define CSR_MCOUNTERMASK_M_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTERMASK_M_HPM5_SET

#define CSR_MCOUNTERMASK_M_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK)

◆ CSR_MCOUNTERMASK_M_HPM5_SHIFT

#define CSR_MCOUNTERMASK_M_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTERMASK_M_HPM6_GET

#define CSR_MCOUNTERMASK_M_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT)

◆ CSR_MCOUNTERMASK_M_HPM6_MASK

#define CSR_MCOUNTERMASK_M_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTERMASK_M_HPM6_SET

#define CSR_MCOUNTERMASK_M_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK)

◆ CSR_MCOUNTERMASK_M_HPM6_SHIFT

#define CSR_MCOUNTERMASK_M_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTERMASK_M_IR_GET

#define CSR_MCOUNTERMASK_M_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT)

◆ CSR_MCOUNTERMASK_M_IR_MASK

#define CSR_MCOUNTERMASK_M_IR_MASK   (0x4U)

◆ CSR_MCOUNTERMASK_M_IR_SET

#define CSR_MCOUNTERMASK_M_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK)

◆ CSR_MCOUNTERMASK_M_IR_SHIFT

#define CSR_MCOUNTERMASK_M_IR_SHIFT   (2U)

◆ CSR_MCOUNTERMASK_S

#define CSR_MCOUNTERMASK_S   (0x7D2)

◆ CSR_MCOUNTERMASK_S_CY_GET

#define CSR_MCOUNTERMASK_S_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT)

◆ CSR_MCOUNTERMASK_S_CY_MASK

#define CSR_MCOUNTERMASK_S_CY_MASK   (0x1U)

◆ CSR_MCOUNTERMASK_S_CY_SET

#define CSR_MCOUNTERMASK_S_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK)

◆ CSR_MCOUNTERMASK_S_CY_SHIFT

#define CSR_MCOUNTERMASK_S_CY_SHIFT   (0U)

◆ CSR_MCOUNTERMASK_S_HPM3_GET

#define CSR_MCOUNTERMASK_S_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT)

◆ CSR_MCOUNTERMASK_S_HPM3_MASK

#define CSR_MCOUNTERMASK_S_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTERMASK_S_HPM3_SET

#define CSR_MCOUNTERMASK_S_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK)

◆ CSR_MCOUNTERMASK_S_HPM3_SHIFT

#define CSR_MCOUNTERMASK_S_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTERMASK_S_HPM4_GET

#define CSR_MCOUNTERMASK_S_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT)

◆ CSR_MCOUNTERMASK_S_HPM4_MASK

#define CSR_MCOUNTERMASK_S_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTERMASK_S_HPM4_SET

#define CSR_MCOUNTERMASK_S_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK)

◆ CSR_MCOUNTERMASK_S_HPM4_SHIFT

#define CSR_MCOUNTERMASK_S_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTERMASK_S_HPM5_GET

#define CSR_MCOUNTERMASK_S_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT)

◆ CSR_MCOUNTERMASK_S_HPM5_MASK

#define CSR_MCOUNTERMASK_S_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTERMASK_S_HPM5_SET

#define CSR_MCOUNTERMASK_S_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK)

◆ CSR_MCOUNTERMASK_S_HPM5_SHIFT

#define CSR_MCOUNTERMASK_S_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTERMASK_S_HPM6_GET

#define CSR_MCOUNTERMASK_S_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT)

◆ CSR_MCOUNTERMASK_S_HPM6_MASK

#define CSR_MCOUNTERMASK_S_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTERMASK_S_HPM6_SET

#define CSR_MCOUNTERMASK_S_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK)

◆ CSR_MCOUNTERMASK_S_HPM6_SHIFT

#define CSR_MCOUNTERMASK_S_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTERMASK_S_IR_GET

#define CSR_MCOUNTERMASK_S_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT)

◆ CSR_MCOUNTERMASK_S_IR_MASK

#define CSR_MCOUNTERMASK_S_IR_MASK   (0x4U)

◆ CSR_MCOUNTERMASK_S_IR_SET

#define CSR_MCOUNTERMASK_S_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK)

◆ CSR_MCOUNTERMASK_S_IR_SHIFT

#define CSR_MCOUNTERMASK_S_IR_SHIFT   (2U)

◆ CSR_MCOUNTERMASK_U

#define CSR_MCOUNTERMASK_U   (0x7D3)

◆ CSR_MCOUNTERMASK_U_CY_GET

#define CSR_MCOUNTERMASK_U_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT)

◆ CSR_MCOUNTERMASK_U_CY_MASK

#define CSR_MCOUNTERMASK_U_CY_MASK   (0x1U)

◆ CSR_MCOUNTERMASK_U_CY_SET

#define CSR_MCOUNTERMASK_U_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK)

◆ CSR_MCOUNTERMASK_U_CY_SHIFT

#define CSR_MCOUNTERMASK_U_CY_SHIFT   (0U)

◆ CSR_MCOUNTERMASK_U_HPM3_GET

#define CSR_MCOUNTERMASK_U_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT)

◆ CSR_MCOUNTERMASK_U_HPM3_MASK

#define CSR_MCOUNTERMASK_U_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTERMASK_U_HPM3_SET

#define CSR_MCOUNTERMASK_U_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK)

◆ CSR_MCOUNTERMASK_U_HPM3_SHIFT

#define CSR_MCOUNTERMASK_U_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTERMASK_U_HPM4_GET

#define CSR_MCOUNTERMASK_U_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT)

◆ CSR_MCOUNTERMASK_U_HPM4_MASK

#define CSR_MCOUNTERMASK_U_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTERMASK_U_HPM4_SET

#define CSR_MCOUNTERMASK_U_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK)

◆ CSR_MCOUNTERMASK_U_HPM4_SHIFT

#define CSR_MCOUNTERMASK_U_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTERMASK_U_HPM5_GET

#define CSR_MCOUNTERMASK_U_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT)

◆ CSR_MCOUNTERMASK_U_HPM5_MASK

#define CSR_MCOUNTERMASK_U_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTERMASK_U_HPM5_SET

#define CSR_MCOUNTERMASK_U_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK)

◆ CSR_MCOUNTERMASK_U_HPM5_SHIFT

#define CSR_MCOUNTERMASK_U_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTERMASK_U_HPM6_GET

#define CSR_MCOUNTERMASK_U_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT)

◆ CSR_MCOUNTERMASK_U_HPM6_MASK

#define CSR_MCOUNTERMASK_U_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTERMASK_U_HPM6_SET

#define CSR_MCOUNTERMASK_U_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK)

◆ CSR_MCOUNTERMASK_U_HPM6_SHIFT

#define CSR_MCOUNTERMASK_U_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTERMASK_U_IR_GET

#define CSR_MCOUNTERMASK_U_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT)

◆ CSR_MCOUNTERMASK_U_IR_MASK

#define CSR_MCOUNTERMASK_U_IR_MASK   (0x4U)

◆ CSR_MCOUNTERMASK_U_IR_SET

#define CSR_MCOUNTERMASK_U_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK)

◆ CSR_MCOUNTERMASK_U_IR_SHIFT

#define CSR_MCOUNTERMASK_U_IR_SHIFT   (2U)

◆ CSR_MCOUNTEROVF

#define CSR_MCOUNTEROVF   (0x7D4)

◆ CSR_MCOUNTEROVF_CY_GET

#define CSR_MCOUNTEROVF_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT)

◆ CSR_MCOUNTEROVF_CY_MASK

#define CSR_MCOUNTEROVF_CY_MASK   (0x1U)

◆ CSR_MCOUNTEROVF_CY_SET

#define CSR_MCOUNTEROVF_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK)

◆ CSR_MCOUNTEROVF_CY_SHIFT

#define CSR_MCOUNTEROVF_CY_SHIFT   (0U)

◆ CSR_MCOUNTEROVF_HPM3_GET

#define CSR_MCOUNTEROVF_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT)

◆ CSR_MCOUNTEROVF_HPM3_MASK

#define CSR_MCOUNTEROVF_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTEROVF_HPM3_SET

#define CSR_MCOUNTEROVF_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK)

◆ CSR_MCOUNTEROVF_HPM3_SHIFT

#define CSR_MCOUNTEROVF_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTEROVF_HPM4_GET

#define CSR_MCOUNTEROVF_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT)

◆ CSR_MCOUNTEROVF_HPM4_MASK

#define CSR_MCOUNTEROVF_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTEROVF_HPM4_SET

#define CSR_MCOUNTEROVF_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK)

◆ CSR_MCOUNTEROVF_HPM4_SHIFT

#define CSR_MCOUNTEROVF_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTEROVF_HPM5_GET

#define CSR_MCOUNTEROVF_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT)

◆ CSR_MCOUNTEROVF_HPM5_MASK

#define CSR_MCOUNTEROVF_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTEROVF_HPM5_SET

#define CSR_MCOUNTEROVF_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK)

◆ CSR_MCOUNTEROVF_HPM5_SHIFT

#define CSR_MCOUNTEROVF_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTEROVF_HPM6_GET

#define CSR_MCOUNTEROVF_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT)

◆ CSR_MCOUNTEROVF_HPM6_MASK

#define CSR_MCOUNTEROVF_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTEROVF_HPM6_SET

#define CSR_MCOUNTEROVF_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK)

◆ CSR_MCOUNTEROVF_HPM6_SHIFT

#define CSR_MCOUNTEROVF_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTEROVF_IR_GET

#define CSR_MCOUNTEROVF_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT)

◆ CSR_MCOUNTEROVF_IR_MASK

#define CSR_MCOUNTEROVF_IR_MASK   (0x4U)

◆ CSR_MCOUNTEROVF_IR_SET

#define CSR_MCOUNTEROVF_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK)

◆ CSR_MCOUNTEROVF_IR_SHIFT

#define CSR_MCOUNTEROVF_IR_SHIFT   (2U)

◆ CSR_MCOUNTERWEN

#define CSR_MCOUNTERWEN   (0x7CE)

◆ CSR_MCOUNTERWEN_CY_GET

#define CSR_MCOUNTERWEN_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT)

◆ CSR_MCOUNTERWEN_CY_MASK

#define CSR_MCOUNTERWEN_CY_MASK   (0x1U)

◆ CSR_MCOUNTERWEN_CY_SET

#define CSR_MCOUNTERWEN_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK)

◆ CSR_MCOUNTERWEN_CY_SHIFT

#define CSR_MCOUNTERWEN_CY_SHIFT   (0U)

◆ CSR_MCOUNTERWEN_HPM3_GET

#define CSR_MCOUNTERWEN_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT)

◆ CSR_MCOUNTERWEN_HPM3_MASK

#define CSR_MCOUNTERWEN_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTERWEN_HPM3_SET

#define CSR_MCOUNTERWEN_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK)

◆ CSR_MCOUNTERWEN_HPM3_SHIFT

#define CSR_MCOUNTERWEN_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTERWEN_HPM4_GET

#define CSR_MCOUNTERWEN_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT)

◆ CSR_MCOUNTERWEN_HPM4_MASK

#define CSR_MCOUNTERWEN_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTERWEN_HPM4_SET

#define CSR_MCOUNTERWEN_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK)

◆ CSR_MCOUNTERWEN_HPM4_SHIFT

#define CSR_MCOUNTERWEN_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTERWEN_HPM5_GET

#define CSR_MCOUNTERWEN_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT)

◆ CSR_MCOUNTERWEN_HPM5_MASK

#define CSR_MCOUNTERWEN_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTERWEN_HPM5_SET

#define CSR_MCOUNTERWEN_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK)

◆ CSR_MCOUNTERWEN_HPM5_SHIFT

#define CSR_MCOUNTERWEN_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTERWEN_HPM6_GET

#define CSR_MCOUNTERWEN_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT)

◆ CSR_MCOUNTERWEN_HPM6_MASK

#define CSR_MCOUNTERWEN_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTERWEN_HPM6_SET

#define CSR_MCOUNTERWEN_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK)

◆ CSR_MCOUNTERWEN_HPM6_SHIFT

#define CSR_MCOUNTERWEN_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTERWEN_IR_GET

#define CSR_MCOUNTERWEN_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT)

◆ CSR_MCOUNTERWEN_IR_MASK

#define CSR_MCOUNTERWEN_IR_MASK   (0x4U)

◆ CSR_MCOUNTERWEN_IR_SET

#define CSR_MCOUNTERWEN_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK)

◆ CSR_MCOUNTERWEN_IR_SHIFT

#define CSR_MCOUNTERWEN_IR_SHIFT   (2U)

◆ CSR_MCOUNTINHIBIT

#define CSR_MCOUNTINHIBIT   (0x320)

◆ CSR_MCOUNTINHIBIT_CY_GET

#define CSR_MCOUNTINHIBIT_CY_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT)

◆ CSR_MCOUNTINHIBIT_CY_MASK

#define CSR_MCOUNTINHIBIT_CY_MASK   (0x1U)

◆ CSR_MCOUNTINHIBIT_CY_SET

#define CSR_MCOUNTINHIBIT_CY_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK)

◆ CSR_MCOUNTINHIBIT_CY_SHIFT

#define CSR_MCOUNTINHIBIT_CY_SHIFT   (0U)

◆ CSR_MCOUNTINHIBIT_HPM3_GET

#define CSR_MCOUNTINHIBIT_HPM3_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT)

◆ CSR_MCOUNTINHIBIT_HPM3_MASK

#define CSR_MCOUNTINHIBIT_HPM3_MASK   (0x8U)

◆ CSR_MCOUNTINHIBIT_HPM3_SET

#define CSR_MCOUNTINHIBIT_HPM3_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK)

◆ CSR_MCOUNTINHIBIT_HPM3_SHIFT

#define CSR_MCOUNTINHIBIT_HPM3_SHIFT   (3U)

◆ CSR_MCOUNTINHIBIT_HPM4_GET

#define CSR_MCOUNTINHIBIT_HPM4_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT)

◆ CSR_MCOUNTINHIBIT_HPM4_MASK

#define CSR_MCOUNTINHIBIT_HPM4_MASK   (0x10U)

◆ CSR_MCOUNTINHIBIT_HPM4_SET

#define CSR_MCOUNTINHIBIT_HPM4_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK)

◆ CSR_MCOUNTINHIBIT_HPM4_SHIFT

#define CSR_MCOUNTINHIBIT_HPM4_SHIFT   (4U)

◆ CSR_MCOUNTINHIBIT_HPM5_GET

#define CSR_MCOUNTINHIBIT_HPM5_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT)

◆ CSR_MCOUNTINHIBIT_HPM5_MASK

#define CSR_MCOUNTINHIBIT_HPM5_MASK   (0x20U)

◆ CSR_MCOUNTINHIBIT_HPM5_SET

#define CSR_MCOUNTINHIBIT_HPM5_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK)

◆ CSR_MCOUNTINHIBIT_HPM5_SHIFT

#define CSR_MCOUNTINHIBIT_HPM5_SHIFT   (5U)

◆ CSR_MCOUNTINHIBIT_HPM6_GET

#define CSR_MCOUNTINHIBIT_HPM6_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT)

◆ CSR_MCOUNTINHIBIT_HPM6_MASK

#define CSR_MCOUNTINHIBIT_HPM6_MASK   (0x40U)

◆ CSR_MCOUNTINHIBIT_HPM6_SET

#define CSR_MCOUNTINHIBIT_HPM6_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK)

◆ CSR_MCOUNTINHIBIT_HPM6_SHIFT

#define CSR_MCOUNTINHIBIT_HPM6_SHIFT   (6U)

◆ CSR_MCOUNTINHIBIT_IR_GET

#define CSR_MCOUNTINHIBIT_IR_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT)

◆ CSR_MCOUNTINHIBIT_IR_MASK

#define CSR_MCOUNTINHIBIT_IR_MASK   (0x4U)

◆ CSR_MCOUNTINHIBIT_IR_SET

#define CSR_MCOUNTINHIBIT_IR_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK)

◆ CSR_MCOUNTINHIBIT_IR_SHIFT

#define CSR_MCOUNTINHIBIT_IR_SHIFT   (2U)

◆ CSR_MCOUNTINHIBIT_TM_GET

#define CSR_MCOUNTINHIBIT_TM_GET (   x)    (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT)

◆ CSR_MCOUNTINHIBIT_TM_MASK

#define CSR_MCOUNTINHIBIT_TM_MASK   (0x2U)

◆ CSR_MCOUNTINHIBIT_TM_SET

#define CSR_MCOUNTINHIBIT_TM_SET (   x)    (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK)

◆ CSR_MCOUNTINHIBIT_TM_SHIFT

#define CSR_MCOUNTINHIBIT_TM_SHIFT   (1U)

◆ CSR_MCYCLE

#define CSR_MCYCLE   (0xB00)

◆ CSR_MCYCLE_COUNTER_GET

#define CSR_MCYCLE_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT)

◆ CSR_MCYCLE_COUNTER_MASK

#define CSR_MCYCLE_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MCYCLE_COUNTER_SET

#define CSR_MCYCLE_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK)

◆ CSR_MCYCLE_COUNTER_SHIFT

#define CSR_MCYCLE_COUNTER_SHIFT   (0U)

◆ CSR_MCYCLEH

#define CSR_MCYCLEH   (0xB80)

◆ CSR_MCYCLEH_COUNTER_GET

#define CSR_MCYCLEH_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT)

◆ CSR_MCYCLEH_COUNTER_MASK

#define CSR_MCYCLEH_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MCYCLEH_COUNTER_SET

#define CSR_MCYCLEH_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK)

◆ CSR_MCYCLEH_COUNTER_SHIFT

#define CSR_MCYCLEH_COUNTER_SHIFT   (0U)

◆ CSR_MDCAUSE

#define CSR_MDCAUSE   (0x7C9)

◆ CSR_MDCAUSE_MDCAUSE_GET

#define CSR_MDCAUSE_MDCAUSE_GET (   x)    (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT)

◆ CSR_MDCAUSE_MDCAUSE_MASK

#define CSR_MDCAUSE_MDCAUSE_MASK   (0x7U)

◆ CSR_MDCAUSE_MDCAUSE_SET

#define CSR_MDCAUSE_MDCAUSE_SET (   x)    (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK)

◆ CSR_MDCAUSE_MDCAUSE_SHIFT

#define CSR_MDCAUSE_MDCAUSE_SHIFT   (0U)

◆ CSR_MDCM_CFG

#define CSR_MDCM_CFG   (0xFC1)

◆ CSR_MDCM_CFG_DC_ECC_GET

#define CSR_MDCM_CFG_DC_ECC_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT)

◆ CSR_MDCM_CFG_DC_ECC_MASK

#define CSR_MDCM_CFG_DC_ECC_MASK   (0xC00U)

◆ CSR_MDCM_CFG_DC_ECC_SHIFT

#define CSR_MDCM_CFG_DC_ECC_SHIFT   (10U)

◆ CSR_MDCM_CFG_DLCK_GET

#define CSR_MDCM_CFG_DLCK_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT)

◆ CSR_MDCM_CFG_DLCK_MASK

#define CSR_MDCM_CFG_DLCK_MASK   (0x200U)

◆ CSR_MDCM_CFG_DLCK_SHIFT

#define CSR_MDCM_CFG_DLCK_SHIFT   (9U)

◆ CSR_MDCM_CFG_DLM_ECC_GET

#define CSR_MDCM_CFG_DLM_ECC_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT)

◆ CSR_MDCM_CFG_DLM_ECC_MASK

#define CSR_MDCM_CFG_DLM_ECC_MASK   (0x600000UL)

◆ CSR_MDCM_CFG_DLM_ECC_SHIFT

#define CSR_MDCM_CFG_DLM_ECC_SHIFT   (21U)

◆ CSR_MDCM_CFG_DLMB_GET

#define CSR_MDCM_CFG_DLMB_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT)

◆ CSR_MDCM_CFG_DLMB_MASK

#define CSR_MDCM_CFG_DLMB_MASK   (0x7000U)

◆ CSR_MDCM_CFG_DLMB_SHIFT

#define CSR_MDCM_CFG_DLMB_SHIFT   (12U)

◆ CSR_MDCM_CFG_DLMSZ_GET

#define CSR_MDCM_CFG_DLMSZ_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT)

◆ CSR_MDCM_CFG_DLMSZ_MASK

#define CSR_MDCM_CFG_DLMSZ_MASK   (0xF8000UL)

◆ CSR_MDCM_CFG_DLMSZ_SHIFT

#define CSR_MDCM_CFG_DLMSZ_SHIFT   (15U)

◆ CSR_MDCM_CFG_DSET_GET

#define CSR_MDCM_CFG_DSET_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT)

◆ CSR_MDCM_CFG_DSET_MASK

#define CSR_MDCM_CFG_DSET_MASK   (0x7U)

◆ CSR_MDCM_CFG_DSET_SHIFT

#define CSR_MDCM_CFG_DSET_SHIFT   (0U)

◆ CSR_MDCM_CFG_DSZ_GET

#define CSR_MDCM_CFG_DSZ_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT)

◆ CSR_MDCM_CFG_DSZ_MASK

#define CSR_MDCM_CFG_DSZ_MASK   (0x1C0U)

◆ CSR_MDCM_CFG_DSZ_SHIFT

#define CSR_MDCM_CFG_DSZ_SHIFT   (6U)

◆ CSR_MDCM_CFG_DWAY_GET

#define CSR_MDCM_CFG_DWAY_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT)

◆ CSR_MDCM_CFG_DWAY_MASK

#define CSR_MDCM_CFG_DWAY_MASK   (0x38U)

◆ CSR_MDCM_CFG_DWAY_SHIFT

#define CSR_MDCM_CFG_DWAY_SHIFT   (3U)

◆ CSR_MDCM_CFG_SETH_GET

#define CSR_MDCM_CFG_SETH_GET (   x)    (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT)

◆ CSR_MDCM_CFG_SETH_MASK

#define CSR_MDCM_CFG_SETH_MASK   (0x1000000UL)

◆ CSR_MDCM_CFG_SETH_SHIFT

#define CSR_MDCM_CFG_SETH_SHIFT   (24U)

◆ CSR_MDLMB

#define CSR_MDLMB   (0x7C1)

◆ CSR_MDLMB_DBPA_GET

#define CSR_MDLMB_DBPA_GET (   x)    (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT)

◆ CSR_MDLMB_DBPA_MASK

#define CSR_MDLMB_DBPA_MASK   (0xFFFFFC00UL)

◆ CSR_MDLMB_DBPA_SHIFT

#define CSR_MDLMB_DBPA_SHIFT   (10U)

◆ CSR_MDLMB_DEN_GET

#define CSR_MDLMB_DEN_GET (   x)    (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT)

◆ CSR_MDLMB_DEN_MASK

#define CSR_MDLMB_DEN_MASK   (0x1U)

◆ CSR_MDLMB_DEN_SHIFT

#define CSR_MDLMB_DEN_SHIFT   (0U)

◆ CSR_MDLMB_ECCEN_GET

#define CSR_MDLMB_ECCEN_GET (   x)    (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT)

◆ CSR_MDLMB_ECCEN_MASK

#define CSR_MDLMB_ECCEN_MASK   (0x6U)

◆ CSR_MDLMB_ECCEN_SET

#define CSR_MDLMB_ECCEN_SET (   x)    (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK)

◆ CSR_MDLMB_ECCEN_SHIFT

#define CSR_MDLMB_ECCEN_SHIFT   (1U)

◆ CSR_MDLMB_RWECC_GET

#define CSR_MDLMB_RWECC_GET (   x)    (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT)

◆ CSR_MDLMB_RWECC_MASK

#define CSR_MDLMB_RWECC_MASK   (0x8U)

◆ CSR_MDLMB_RWECC_SET

#define CSR_MDLMB_RWECC_SET (   x)    (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK)

◆ CSR_MDLMB_RWECC_SHIFT

#define CSR_MDLMB_RWECC_SHIFT   (3U)

◆ CSR_MECC_CODE

#define CSR_MECC_CODE   (0x7C2)

◆ CSR_MECC_CODE_C_GET

#define CSR_MECC_CODE_C_GET (   x)    (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT)

◆ CSR_MECC_CODE_C_MASK

#define CSR_MECC_CODE_C_MASK   (0x10000UL)

◆ CSR_MECC_CODE_C_SHIFT

#define CSR_MECC_CODE_C_SHIFT   (16U)

◆ CSR_MECC_CODE_CODE_GET

#define CSR_MECC_CODE_CODE_GET (   x)    (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT)

◆ CSR_MECC_CODE_CODE_MASK

#define CSR_MECC_CODE_CODE_MASK   (0x7FU)

◆ CSR_MECC_CODE_CODE_SET

#define CSR_MECC_CODE_CODE_SET (   x)    (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK)

◆ CSR_MECC_CODE_CODE_SHIFT

#define CSR_MECC_CODE_CODE_SHIFT   (0U)

◆ CSR_MECC_CODE_INSN_GET

#define CSR_MECC_CODE_INSN_GET (   x)    (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT)

◆ CSR_MECC_CODE_INSN_MASK

#define CSR_MECC_CODE_INSN_MASK   (0x400000UL)

◆ CSR_MECC_CODE_INSN_SHIFT

#define CSR_MECC_CODE_INSN_SHIFT   (22U)

◆ CSR_MECC_CODE_P_GET

#define CSR_MECC_CODE_P_GET (   x)    (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT)

◆ CSR_MECC_CODE_P_MASK

#define CSR_MECC_CODE_P_MASK   (0x20000UL)

◆ CSR_MECC_CODE_P_SHIFT

#define CSR_MECC_CODE_P_SHIFT   (17U)

◆ CSR_MECC_CODE_RAMID_GET

#define CSR_MECC_CODE_RAMID_GET (   x)    (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT)

◆ CSR_MECC_CODE_RAMID_MASK

#define CSR_MECC_CODE_RAMID_MASK   (0x3C0000UL)

◆ CSR_MECC_CODE_RAMID_SHIFT

#define CSR_MECC_CODE_RAMID_SHIFT   (18U)

◆ CSR_MEPC

#define CSR_MEPC   (0x341)

◆ CSR_MEPC_EPC_GET

#define CSR_MEPC_EPC_GET (   x)    (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT)

◆ CSR_MEPC_EPC_MASK

#define CSR_MEPC_EPC_MASK   (0xFFFFFFFEUL)

◆ CSR_MEPC_EPC_SET

#define CSR_MEPC_EPC_SET (   x)    (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK)

◆ CSR_MEPC_EPC_SHIFT

#define CSR_MEPC_EPC_SHIFT   (1U)

◆ CSR_MHARTID

#define CSR_MHARTID   (0xF14)

◆ CSR_MHARTID_MHARTID_GET

#define CSR_MHARTID_MHARTID_GET (   x)    (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT)

◆ CSR_MHARTID_MHARTID_MASK

#define CSR_MHARTID_MHARTID_MASK   (0xFFFFFFFFUL)

◆ CSR_MHARTID_MHARTID_SHIFT

#define CSR_MHARTID_MHARTID_SHIFT   (0U)

◆ CSR_MHPMCOUNTER3

#define CSR_MHPMCOUNTER3   (0xB03)

◆ CSR_MHPMCOUNTER3_COUNTER_GET

#define CSR_MHPMCOUNTER3_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER3_COUNTER_MASK

#define CSR_MHPMCOUNTER3_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER3_COUNTER_SET

#define CSR_MHPMCOUNTER3_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK)

◆ CSR_MHPMCOUNTER3_COUNTER_SHIFT

#define CSR_MHPMCOUNTER3_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER3H

#define CSR_MHPMCOUNTER3H   (0xB83)

◆ CSR_MHPMCOUNTER3H_COUNTER_GET

#define CSR_MHPMCOUNTER3H_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER3H_COUNTER_MASK

#define CSR_MHPMCOUNTER3H_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER3H_COUNTER_SET

#define CSR_MHPMCOUNTER3H_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK)

◆ CSR_MHPMCOUNTER3H_COUNTER_SHIFT

#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER4

#define CSR_MHPMCOUNTER4   (0xB04)

◆ CSR_MHPMCOUNTER4_COUNTER_GET

#define CSR_MHPMCOUNTER4_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER4_COUNTER_MASK

#define CSR_MHPMCOUNTER4_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER4_COUNTER_SET

#define CSR_MHPMCOUNTER4_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK)

◆ CSR_MHPMCOUNTER4_COUNTER_SHIFT

#define CSR_MHPMCOUNTER4_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER4H

#define CSR_MHPMCOUNTER4H   (0xB84)

◆ CSR_MHPMCOUNTER4H_COUNTER_GET

#define CSR_MHPMCOUNTER4H_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER4H_COUNTER_MASK

#define CSR_MHPMCOUNTER4H_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER4H_COUNTER_SET

#define CSR_MHPMCOUNTER4H_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK)

◆ CSR_MHPMCOUNTER4H_COUNTER_SHIFT

#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER5

#define CSR_MHPMCOUNTER5   (0xB05)

◆ CSR_MHPMCOUNTER5_COUNTER_GET

#define CSR_MHPMCOUNTER5_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER5_COUNTER_MASK

#define CSR_MHPMCOUNTER5_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER5_COUNTER_SET

#define CSR_MHPMCOUNTER5_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK)

◆ CSR_MHPMCOUNTER5_COUNTER_SHIFT

#define CSR_MHPMCOUNTER5_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER5H

#define CSR_MHPMCOUNTER5H   (0xB85)

◆ CSR_MHPMCOUNTER5H_COUNTER_GET

#define CSR_MHPMCOUNTER5H_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER5H_COUNTER_MASK

#define CSR_MHPMCOUNTER5H_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER5H_COUNTER_SET

#define CSR_MHPMCOUNTER5H_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK)

◆ CSR_MHPMCOUNTER5H_COUNTER_SHIFT

#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER6

#define CSR_MHPMCOUNTER6   (0xB06)

◆ CSR_MHPMCOUNTER6_COUNTER_GET

#define CSR_MHPMCOUNTER6_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER6_COUNTER_MASK

#define CSR_MHPMCOUNTER6_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER6_COUNTER_SET

#define CSR_MHPMCOUNTER6_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK)

◆ CSR_MHPMCOUNTER6_COUNTER_SHIFT

#define CSR_MHPMCOUNTER6_COUNTER_SHIFT   (0U)

◆ CSR_MHPMCOUNTER6H

#define CSR_MHPMCOUNTER6H   (0xB86)

◆ CSR_MHPMCOUNTER6H_COUNTER_GET

#define CSR_MHPMCOUNTER6H_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT)

◆ CSR_MHPMCOUNTER6H_COUNTER_MASK

#define CSR_MHPMCOUNTER6H_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MHPMCOUNTER6H_COUNTER_SET

#define CSR_MHPMCOUNTER6H_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK)

◆ CSR_MHPMCOUNTER6H_COUNTER_SHIFT

#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT   (0U)

◆ CSR_MHPMEVENT3

#define CSR_MHPMEVENT3   (0x323)

◆ CSR_MHPMEVENT3_SEL_GET

#define CSR_MHPMEVENT3_SEL_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT)

◆ CSR_MHPMEVENT3_SEL_MASK

#define CSR_MHPMEVENT3_SEL_MASK   (0x1F0U)

◆ CSR_MHPMEVENT3_SEL_SET

#define CSR_MHPMEVENT3_SEL_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK)

◆ CSR_MHPMEVENT3_SEL_SHIFT

#define CSR_MHPMEVENT3_SEL_SHIFT   (4U)

◆ CSR_MHPMEVENT3_TYPE_GET

#define CSR_MHPMEVENT3_TYPE_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT)

◆ CSR_MHPMEVENT3_TYPE_MASK

#define CSR_MHPMEVENT3_TYPE_MASK   (0xFU)

◆ CSR_MHPMEVENT3_TYPE_SET

#define CSR_MHPMEVENT3_TYPE_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK)

◆ CSR_MHPMEVENT3_TYPE_SHIFT

#define CSR_MHPMEVENT3_TYPE_SHIFT   (0U)

◆ CSR_MHPMEVENT4

#define CSR_MHPMEVENT4   (0x324)

◆ CSR_MHPMEVENT4_SEL_GET

#define CSR_MHPMEVENT4_SEL_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT)

◆ CSR_MHPMEVENT4_SEL_MASK

#define CSR_MHPMEVENT4_SEL_MASK   (0x1F0U)

◆ CSR_MHPMEVENT4_SEL_SET

#define CSR_MHPMEVENT4_SEL_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK)

◆ CSR_MHPMEVENT4_SEL_SHIFT

#define CSR_MHPMEVENT4_SEL_SHIFT   (4U)

◆ CSR_MHPMEVENT4_TYPE_GET

#define CSR_MHPMEVENT4_TYPE_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT)

◆ CSR_MHPMEVENT4_TYPE_MASK

#define CSR_MHPMEVENT4_TYPE_MASK   (0xFU)

◆ CSR_MHPMEVENT4_TYPE_SET

#define CSR_MHPMEVENT4_TYPE_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK)

◆ CSR_MHPMEVENT4_TYPE_SHIFT

#define CSR_MHPMEVENT4_TYPE_SHIFT   (0U)

◆ CSR_MHPMEVENT5

#define CSR_MHPMEVENT5   (0x325)

◆ CSR_MHPMEVENT5_SEL_GET

#define CSR_MHPMEVENT5_SEL_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT)

◆ CSR_MHPMEVENT5_SEL_MASK

#define CSR_MHPMEVENT5_SEL_MASK   (0x1F0U)

◆ CSR_MHPMEVENT5_SEL_SET

#define CSR_MHPMEVENT5_SEL_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK)

◆ CSR_MHPMEVENT5_SEL_SHIFT

#define CSR_MHPMEVENT5_SEL_SHIFT   (4U)

◆ CSR_MHPMEVENT5_TYPE_GET

#define CSR_MHPMEVENT5_TYPE_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT)

◆ CSR_MHPMEVENT5_TYPE_MASK

#define CSR_MHPMEVENT5_TYPE_MASK   (0xFU)

◆ CSR_MHPMEVENT5_TYPE_SET

#define CSR_MHPMEVENT5_TYPE_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK)

◆ CSR_MHPMEVENT5_TYPE_SHIFT

#define CSR_MHPMEVENT5_TYPE_SHIFT   (0U)

◆ CSR_MHPMEVENT6

#define CSR_MHPMEVENT6   (0x326)

◆ CSR_MHPMEVENT6_SEL_GET

#define CSR_MHPMEVENT6_SEL_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT)

◆ CSR_MHPMEVENT6_SEL_MASK

#define CSR_MHPMEVENT6_SEL_MASK   (0x1F0U)

◆ CSR_MHPMEVENT6_SEL_SET

#define CSR_MHPMEVENT6_SEL_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK)

◆ CSR_MHPMEVENT6_SEL_SHIFT

#define CSR_MHPMEVENT6_SEL_SHIFT   (4U)

◆ CSR_MHPMEVENT6_TYPE_GET

#define CSR_MHPMEVENT6_TYPE_GET (   x)    (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT)

◆ CSR_MHPMEVENT6_TYPE_MASK

#define CSR_MHPMEVENT6_TYPE_MASK   (0xFU)

◆ CSR_MHPMEVENT6_TYPE_SET

#define CSR_MHPMEVENT6_TYPE_SET (   x)    (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK)

◆ CSR_MHPMEVENT6_TYPE_SHIFT

#define CSR_MHPMEVENT6_TYPE_SHIFT   (0U)

◆ CSR_MHSP_CTL

#define CSR_MHSP_CTL   (0x7C6)

◆ CSR_MHSP_CTL_M_GET

#define CSR_MHSP_CTL_M_GET (   x)    (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT)

◆ CSR_MHSP_CTL_M_MASK

#define CSR_MHSP_CTL_M_MASK   (0x20U)

◆ CSR_MHSP_CTL_M_SET

#define CSR_MHSP_CTL_M_SET (   x)    (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK)

◆ CSR_MHSP_CTL_M_SHIFT

#define CSR_MHSP_CTL_M_SHIFT   (5U)

◆ CSR_MHSP_CTL_OVF_EN_GET

#define CSR_MHSP_CTL_OVF_EN_GET (   x)    (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT)

◆ CSR_MHSP_CTL_OVF_EN_MASK

#define CSR_MHSP_CTL_OVF_EN_MASK   (0x1U)

◆ CSR_MHSP_CTL_OVF_EN_SET

#define CSR_MHSP_CTL_OVF_EN_SET (   x)    (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK)

◆ CSR_MHSP_CTL_OVF_EN_SHIFT

#define CSR_MHSP_CTL_OVF_EN_SHIFT   (0U)

◆ CSR_MHSP_CTL_S_GET

#define CSR_MHSP_CTL_S_GET (   x)    (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT)

◆ CSR_MHSP_CTL_S_MASK

#define CSR_MHSP_CTL_S_MASK   (0x10U)

◆ CSR_MHSP_CTL_S_SET

#define CSR_MHSP_CTL_S_SET (   x)    (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK)

◆ CSR_MHSP_CTL_S_SHIFT

#define CSR_MHSP_CTL_S_SHIFT   (4U)

◆ CSR_MHSP_CTL_SCHM_GET

#define CSR_MHSP_CTL_SCHM_GET (   x)    (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT)

◆ CSR_MHSP_CTL_SCHM_MASK

#define CSR_MHSP_CTL_SCHM_MASK   (0x4U)

◆ CSR_MHSP_CTL_SCHM_SET

#define CSR_MHSP_CTL_SCHM_SET (   x)    (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK)

◆ CSR_MHSP_CTL_SCHM_SHIFT

#define CSR_MHSP_CTL_SCHM_SHIFT   (2U)

◆ CSR_MHSP_CTL_U_GET

#define CSR_MHSP_CTL_U_GET (   x)    (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT)

◆ CSR_MHSP_CTL_U_MASK

#define CSR_MHSP_CTL_U_MASK   (0x8U)

◆ CSR_MHSP_CTL_U_SET

#define CSR_MHSP_CTL_U_SET (   x)    (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK)

◆ CSR_MHSP_CTL_U_SHIFT

#define CSR_MHSP_CTL_U_SHIFT   (3U)

◆ CSR_MHSP_CTL_UDF_EN_GET

#define CSR_MHSP_CTL_UDF_EN_GET (   x)    (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT)

◆ CSR_MHSP_CTL_UDF_EN_MASK

#define CSR_MHSP_CTL_UDF_EN_MASK   (0x2U)

◆ CSR_MHSP_CTL_UDF_EN_SET

#define CSR_MHSP_CTL_UDF_EN_SET (   x)    (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK)

◆ CSR_MHSP_CTL_UDF_EN_SHIFT

#define CSR_MHSP_CTL_UDF_EN_SHIFT   (1U)

◆ CSR_MICM_CFG

#define CSR_MICM_CFG   (0xFC0)

◆ CSR_MICM_CFG_IC_ECC_GET

#define CSR_MICM_CFG_IC_ECC_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT)

◆ CSR_MICM_CFG_IC_ECC_MASK

#define CSR_MICM_CFG_IC_ECC_MASK   (0xC00U)

◆ CSR_MICM_CFG_IC_ECC_SHIFT

#define CSR_MICM_CFG_IC_ECC_SHIFT   (10U)

◆ CSR_MICM_CFG_ILCK_GET

#define CSR_MICM_CFG_ILCK_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT)

◆ CSR_MICM_CFG_ILCK_MASK

#define CSR_MICM_CFG_ILCK_MASK   (0x200U)

◆ CSR_MICM_CFG_ILCK_SHIFT

#define CSR_MICM_CFG_ILCK_SHIFT   (9U)

◆ CSR_MICM_CFG_ILM_ECC_GET

#define CSR_MICM_CFG_ILM_ECC_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT)

◆ CSR_MICM_CFG_ILM_ECC_MASK

#define CSR_MICM_CFG_ILM_ECC_MASK   (0x600000UL)

◆ CSR_MICM_CFG_ILM_ECC_SHIFT

#define CSR_MICM_CFG_ILM_ECC_SHIFT   (21U)

◆ CSR_MICM_CFG_ILMB_GET

#define CSR_MICM_CFG_ILMB_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT)

◆ CSR_MICM_CFG_ILMB_MASK

#define CSR_MICM_CFG_ILMB_MASK   (0x7000U)

◆ CSR_MICM_CFG_ILMB_SET

#define CSR_MICM_CFG_ILMB_SET (   x)    (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK)

◆ CSR_MICM_CFG_ILMB_SHIFT

#define CSR_MICM_CFG_ILMB_SHIFT   (12U)

◆ CSR_MICM_CFG_ILMSZ_GET

#define CSR_MICM_CFG_ILMSZ_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT)

◆ CSR_MICM_CFG_ILMSZ_MASK

#define CSR_MICM_CFG_ILMSZ_MASK   (0xF8000UL)

◆ CSR_MICM_CFG_ILMSZ_SHIFT

#define CSR_MICM_CFG_ILMSZ_SHIFT   (15U)

◆ CSR_MICM_CFG_ISET_GET

#define CSR_MICM_CFG_ISET_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT)

◆ CSR_MICM_CFG_ISET_MASK

#define CSR_MICM_CFG_ISET_MASK   (0x7U)

◆ CSR_MICM_CFG_ISET_SHIFT

#define CSR_MICM_CFG_ISET_SHIFT   (0U)

◆ CSR_MICM_CFG_ISZ_GET

#define CSR_MICM_CFG_ISZ_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT)

◆ CSR_MICM_CFG_ISZ_MASK

#define CSR_MICM_CFG_ISZ_MASK   (0x1C0U)

◆ CSR_MICM_CFG_ISZ_SHIFT

#define CSR_MICM_CFG_ISZ_SHIFT   (6U)

◆ CSR_MICM_CFG_IWAY_GET

#define CSR_MICM_CFG_IWAY_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT)

◆ CSR_MICM_CFG_IWAY_MASK

#define CSR_MICM_CFG_IWAY_MASK   (0x38U)

◆ CSR_MICM_CFG_IWAY_SHIFT

#define CSR_MICM_CFG_IWAY_SHIFT   (3U)

◆ CSR_MICM_CFG_SETH_GET

#define CSR_MICM_CFG_SETH_GET (   x)    (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT)

◆ CSR_MICM_CFG_SETH_MASK

#define CSR_MICM_CFG_SETH_MASK   (0x1000000UL)

◆ CSR_MICM_CFG_SETH_SHIFT

#define CSR_MICM_CFG_SETH_SHIFT   (24U)

◆ CSR_MIE

#define CSR_MIE   (0x304)

◆ CSR_MIE_BWEI_GET

#define CSR_MIE_BWEI_GET (   x)    (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT)

◆ CSR_MIE_BWEI_MASK

#define CSR_MIE_BWEI_MASK   (0x20000UL)

◆ CSR_MIE_BWEI_SET

#define CSR_MIE_BWEI_SET (   x)    (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK)

◆ CSR_MIE_BWEI_SHIFT

#define CSR_MIE_BWEI_SHIFT   (17U)

◆ CSR_MIE_IMECCI_GET

#define CSR_MIE_IMECCI_GET (   x)    (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT)

◆ CSR_MIE_IMECCI_MASK

#define CSR_MIE_IMECCI_MASK   (0x10000UL)

◆ CSR_MIE_IMECCI_SET

#define CSR_MIE_IMECCI_SET (   x)    (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK)

◆ CSR_MIE_IMECCI_SHIFT

#define CSR_MIE_IMECCI_SHIFT   (16U)

◆ CSR_MIE_MEIE_GET

#define CSR_MIE_MEIE_GET (   x)    (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT)

◆ CSR_MIE_MEIE_MASK

#define CSR_MIE_MEIE_MASK   (0x800U)

◆ CSR_MIE_MEIE_SET

#define CSR_MIE_MEIE_SET (   x)    (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK)

◆ CSR_MIE_MEIE_SHIFT

#define CSR_MIE_MEIE_SHIFT   (11U)

◆ CSR_MIE_MSIE_GET

#define CSR_MIE_MSIE_GET (   x)    (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT)

◆ CSR_MIE_MSIE_MASK

#define CSR_MIE_MSIE_MASK   (0x8U)

◆ CSR_MIE_MSIE_SET

#define CSR_MIE_MSIE_SET (   x)    (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK)

◆ CSR_MIE_MSIE_SHIFT

#define CSR_MIE_MSIE_SHIFT   (3U)

◆ CSR_MIE_MTIE_GET

#define CSR_MIE_MTIE_GET (   x)    (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT)

◆ CSR_MIE_MTIE_MASK

#define CSR_MIE_MTIE_MASK   (0x80U)

◆ CSR_MIE_MTIE_SET

#define CSR_MIE_MTIE_SET (   x)    (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK)

◆ CSR_MIE_MTIE_SHIFT

#define CSR_MIE_MTIE_SHIFT   (7U)

◆ CSR_MIE_PMOVI_GET

#define CSR_MIE_PMOVI_GET (   x)    (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT)

◆ CSR_MIE_PMOVI_MASK

#define CSR_MIE_PMOVI_MASK   (0x40000UL)

◆ CSR_MIE_PMOVI_SET

#define CSR_MIE_PMOVI_SET (   x)    (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK)

◆ CSR_MIE_PMOVI_SHIFT

#define CSR_MIE_PMOVI_SHIFT   (18U)

◆ CSR_MIE_UEIE_GET

#define CSR_MIE_UEIE_GET (   x)    (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT)

◆ CSR_MIE_UEIE_MASK

#define CSR_MIE_UEIE_MASK   (0x100U)

◆ CSR_MIE_UEIE_SET

#define CSR_MIE_UEIE_SET (   x)    (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK)

◆ CSR_MIE_UEIE_SHIFT

#define CSR_MIE_UEIE_SHIFT   (8U)

◆ CSR_MIE_USIE_GET

#define CSR_MIE_USIE_GET (   x)    (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT)

◆ CSR_MIE_USIE_MASK

#define CSR_MIE_USIE_MASK   (0x1U)

◆ CSR_MIE_USIE_SET

#define CSR_MIE_USIE_SET (   x)    (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK)

◆ CSR_MIE_USIE_SHIFT

#define CSR_MIE_USIE_SHIFT   (0U)

◆ CSR_MIE_UTIE_GET

#define CSR_MIE_UTIE_GET (   x)    (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT)

◆ CSR_MIE_UTIE_MASK

#define CSR_MIE_UTIE_MASK   (0x10U)

◆ CSR_MIE_UTIE_SET

#define CSR_MIE_UTIE_SET (   x)    (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK)

◆ CSR_MIE_UTIE_SHIFT

#define CSR_MIE_UTIE_SHIFT   (4U)

◆ CSR_MILMB

#define CSR_MILMB   (0x7C0)

◆ CSR_MILMB_ECCEN_GET

#define CSR_MILMB_ECCEN_GET (   x)    (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT)

◆ CSR_MILMB_ECCEN_MASK

#define CSR_MILMB_ECCEN_MASK   (0x6U)

◆ CSR_MILMB_ECCEN_SET

#define CSR_MILMB_ECCEN_SET (   x)    (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK)

◆ CSR_MILMB_ECCEN_SHIFT

#define CSR_MILMB_ECCEN_SHIFT   (1U)

◆ CSR_MILMB_IBPA_GET

#define CSR_MILMB_IBPA_GET (   x)    (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT)

◆ CSR_MILMB_IBPA_MASK

#define CSR_MILMB_IBPA_MASK   (0xFFFFFC00UL)

◆ CSR_MILMB_IBPA_SHIFT

#define CSR_MILMB_IBPA_SHIFT   (10U)

◆ CSR_MILMB_IEN_GET

#define CSR_MILMB_IEN_GET (   x)    (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT)

◆ CSR_MILMB_IEN_MASK

#define CSR_MILMB_IEN_MASK   (0x1U)

◆ CSR_MILMB_IEN_SHIFT

#define CSR_MILMB_IEN_SHIFT   (0U)

◆ CSR_MILMB_RWECC_GET

#define CSR_MILMB_RWECC_GET (   x)    (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT)

◆ CSR_MILMB_RWECC_MASK

#define CSR_MILMB_RWECC_MASK   (0x8U)

◆ CSR_MILMB_RWECC_SET

#define CSR_MILMB_RWECC_SET (   x)    (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK)

◆ CSR_MILMB_RWECC_SHIFT

#define CSR_MILMB_RWECC_SHIFT   (3U)

◆ CSR_MIMPID

#define CSR_MIMPID   (0xF13)

◆ CSR_MIMPID_EXTENSION_GET

#define CSR_MIMPID_EXTENSION_GET (   x)    (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT)

◆ CSR_MIMPID_EXTENSION_MASK

#define CSR_MIMPID_EXTENSION_MASK   (0xFU)

◆ CSR_MIMPID_EXTENSION_SHIFT

#define CSR_MIMPID_EXTENSION_SHIFT   (0U)

◆ CSR_MIMPID_MAJOR_GET

#define CSR_MIMPID_MAJOR_GET (   x)    (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT)

◆ CSR_MIMPID_MAJOR_MASK

#define CSR_MIMPID_MAJOR_MASK   (0xFFFFFF00UL)

◆ CSR_MIMPID_MAJOR_SHIFT

#define CSR_MIMPID_MAJOR_SHIFT   (8U)

◆ CSR_MIMPID_MINOR_GET

#define CSR_MIMPID_MINOR_GET (   x)    (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT)

◆ CSR_MIMPID_MINOR_MASK

#define CSR_MIMPID_MINOR_MASK   (0xF0U)

◆ CSR_MIMPID_MINOR_SHIFT

#define CSR_MIMPID_MINOR_SHIFT   (4U)

◆ CSR_MINSTRET

#define CSR_MINSTRET   (0xB02)

◆ CSR_MINSTRET_COUNTER_GET

#define CSR_MINSTRET_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT)

◆ CSR_MINSTRET_COUNTER_MASK

#define CSR_MINSTRET_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MINSTRET_COUNTER_SET

#define CSR_MINSTRET_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK)

◆ CSR_MINSTRET_COUNTER_SHIFT

#define CSR_MINSTRET_COUNTER_SHIFT   (0U)

◆ CSR_MINSTRETH

#define CSR_MINSTRETH   (0xB82)

◆ CSR_MINSTRETH_COUNTER_GET

#define CSR_MINSTRETH_COUNTER_GET (   x)    (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT)

◆ CSR_MINSTRETH_COUNTER_MASK

#define CSR_MINSTRETH_COUNTER_MASK   (0xFFFFFFFFUL)

◆ CSR_MINSTRETH_COUNTER_SET

#define CSR_MINSTRETH_COUNTER_SET (   x)    (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK)

◆ CSR_MINSTRETH_COUNTER_SHIFT

#define CSR_MINSTRETH_COUNTER_SHIFT   (0U)

◆ CSR_MIP

#define CSR_MIP   (0x344)

◆ CSR_MIP_BWEI_GET

#define CSR_MIP_BWEI_GET (   x)    (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT)

◆ CSR_MIP_BWEI_MASK

#define CSR_MIP_BWEI_MASK   (0x20000UL)

◆ CSR_MIP_BWEI_SET

#define CSR_MIP_BWEI_SET (   x)    (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK)

◆ CSR_MIP_BWEI_SHIFT

#define CSR_MIP_BWEI_SHIFT   (17U)

◆ CSR_MIP_IMECCI_GET

#define CSR_MIP_IMECCI_GET (   x)    (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT)

◆ CSR_MIP_IMECCI_MASK

#define CSR_MIP_IMECCI_MASK   (0x10000UL)

◆ CSR_MIP_IMECCI_SET

#define CSR_MIP_IMECCI_SET (   x)    (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK)

◆ CSR_MIP_IMECCI_SHIFT

#define CSR_MIP_IMECCI_SHIFT   (16U)

◆ CSR_MIP_MEIP_GET

#define CSR_MIP_MEIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT)

◆ CSR_MIP_MEIP_MASK

#define CSR_MIP_MEIP_MASK   (0x800U)

◆ CSR_MIP_MEIP_SET

#define CSR_MIP_MEIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK)

◆ CSR_MIP_MEIP_SHIFT

#define CSR_MIP_MEIP_SHIFT   (11U)

◆ CSR_MIP_MSIP_GET

#define CSR_MIP_MSIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT)

◆ CSR_MIP_MSIP_MASK

#define CSR_MIP_MSIP_MASK   (0x8U)

◆ CSR_MIP_MSIP_SET

#define CSR_MIP_MSIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK)

◆ CSR_MIP_MSIP_SHIFT

#define CSR_MIP_MSIP_SHIFT   (3U)

◆ CSR_MIP_MTIP_GET

#define CSR_MIP_MTIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT)

◆ CSR_MIP_MTIP_MASK

#define CSR_MIP_MTIP_MASK   (0x80U)

◆ CSR_MIP_MTIP_SET

#define CSR_MIP_MTIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK)

◆ CSR_MIP_MTIP_SHIFT

#define CSR_MIP_MTIP_SHIFT   (7U)

◆ CSR_MIP_PMOVI_GET

#define CSR_MIP_PMOVI_GET (   x)    (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT)

◆ CSR_MIP_PMOVI_MASK

#define CSR_MIP_PMOVI_MASK   (0x40000UL)

◆ CSR_MIP_PMOVI_SET

#define CSR_MIP_PMOVI_SET (   x)    (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK)

◆ CSR_MIP_PMOVI_SHIFT

#define CSR_MIP_PMOVI_SHIFT   (18U)

◆ CSR_MIP_SEIP_GET

#define CSR_MIP_SEIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT)

◆ CSR_MIP_SEIP_MASK

#define CSR_MIP_SEIP_MASK   (0x200U)

◆ CSR_MIP_SEIP_SET

#define CSR_MIP_SEIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK)

◆ CSR_MIP_SEIP_SHIFT

#define CSR_MIP_SEIP_SHIFT   (9U)

◆ CSR_MIP_SSIP_GET

#define CSR_MIP_SSIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT)

◆ CSR_MIP_SSIP_MASK

#define CSR_MIP_SSIP_MASK   (0x2U)

◆ CSR_MIP_SSIP_SET

#define CSR_MIP_SSIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK)

◆ CSR_MIP_SSIP_SHIFT

#define CSR_MIP_SSIP_SHIFT   (1U)

◆ CSR_MIP_STIP_GET

#define CSR_MIP_STIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT)

◆ CSR_MIP_STIP_MASK

#define CSR_MIP_STIP_MASK   (0x20U)

◆ CSR_MIP_STIP_SET

#define CSR_MIP_STIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK)

◆ CSR_MIP_STIP_SHIFT

#define CSR_MIP_STIP_SHIFT   (5U)

◆ CSR_MIP_UEIP_GET

#define CSR_MIP_UEIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT)

◆ CSR_MIP_UEIP_MASK

#define CSR_MIP_UEIP_MASK   (0x100U)

◆ CSR_MIP_UEIP_SET

#define CSR_MIP_UEIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK)

◆ CSR_MIP_UEIP_SHIFT

#define CSR_MIP_UEIP_SHIFT   (8U)

◆ CSR_MIP_USIP_GET

#define CSR_MIP_USIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT)

◆ CSR_MIP_USIP_MASK

#define CSR_MIP_USIP_MASK   (0x1U)

◆ CSR_MIP_USIP_SET

#define CSR_MIP_USIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK)

◆ CSR_MIP_USIP_SHIFT

#define CSR_MIP_USIP_SHIFT   (0U)

◆ CSR_MIP_UTIP_GET

#define CSR_MIP_UTIP_GET (   x)    (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT)

◆ CSR_MIP_UTIP_MASK

#define CSR_MIP_UTIP_MASK   (0x10U)

◆ CSR_MIP_UTIP_SET

#define CSR_MIP_UTIP_SET (   x)    (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK)

◆ CSR_MIP_UTIP_SHIFT

#define CSR_MIP_UTIP_SHIFT   (4U)

◆ CSR_MISA

#define CSR_MISA   (0x301)

◆ CSR_MISA_A_GET

#define CSR_MISA_A_GET (   x)    (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT)

◆ CSR_MISA_A_MASK

#define CSR_MISA_A_MASK   (0x1U)

◆ CSR_MISA_A_SHIFT

#define CSR_MISA_A_SHIFT   (0U)

◆ CSR_MISA_B_GET

#define CSR_MISA_B_GET (   x)    (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT)

◆ CSR_MISA_B_MASK

#define CSR_MISA_B_MASK   (0x2U)

◆ CSR_MISA_B_SHIFT

#define CSR_MISA_B_SHIFT   (1U)

◆ CSR_MISA_BASE_GET

#define CSR_MISA_BASE_GET (   x)    (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT)

◆ CSR_MISA_BASE_MASK

#define CSR_MISA_BASE_MASK   (0xC0000000UL)

◆ CSR_MISA_BASE_SHIFT

#define CSR_MISA_BASE_SHIFT   (30U)

◆ CSR_MISA_C_GET

#define CSR_MISA_C_GET (   x)    (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT)

◆ CSR_MISA_C_MASK

#define CSR_MISA_C_MASK   (0x4U)

◆ CSR_MISA_C_SHIFT

#define CSR_MISA_C_SHIFT   (2U)

◆ CSR_MISA_D_GET

#define CSR_MISA_D_GET (   x)    (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT)

◆ CSR_MISA_D_MASK

#define CSR_MISA_D_MASK   (0x8U)

◆ CSR_MISA_D_SHIFT

#define CSR_MISA_D_SHIFT   (3U)

◆ CSR_MISA_E_GET

#define CSR_MISA_E_GET (   x)    (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT)

◆ CSR_MISA_E_MASK

#define CSR_MISA_E_MASK   (0x10U)

◆ CSR_MISA_E_SHIFT

#define CSR_MISA_E_SHIFT   (4U)

◆ CSR_MISA_F_GET

#define CSR_MISA_F_GET (   x)    (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT)

◆ CSR_MISA_F_MASK

#define CSR_MISA_F_MASK   (0x20U)

◆ CSR_MISA_F_SHIFT

#define CSR_MISA_F_SHIFT   (5U)

◆ CSR_MISA_G_GET

#define CSR_MISA_G_GET (   x)    (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT)

◆ CSR_MISA_G_MASK

#define CSR_MISA_G_MASK   (0x40U)

◆ CSR_MISA_G_SHIFT

#define CSR_MISA_G_SHIFT   (6U)

◆ CSR_MISA_H_GET

#define CSR_MISA_H_GET (   x)    (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT)

◆ CSR_MISA_H_MASK

#define CSR_MISA_H_MASK   (0x80U)

◆ CSR_MISA_H_SHIFT

#define CSR_MISA_H_SHIFT   (7U)

◆ CSR_MISA_I_GET

#define CSR_MISA_I_GET (   x)    (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT)

◆ CSR_MISA_I_MASK

#define CSR_MISA_I_MASK   (0x100U)

◆ CSR_MISA_I_SHIFT

#define CSR_MISA_I_SHIFT   (8U)

◆ CSR_MISA_J_GET

#define CSR_MISA_J_GET (   x)    (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT)

◆ CSR_MISA_J_MASK

#define CSR_MISA_J_MASK   (0x200U)

◆ CSR_MISA_J_SHIFT

#define CSR_MISA_J_SHIFT   (9U)

◆ CSR_MISA_K_GET

#define CSR_MISA_K_GET (   x)    (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT)

◆ CSR_MISA_K_MASK

#define CSR_MISA_K_MASK   (0x400U)

◆ CSR_MISA_K_SHIFT

#define CSR_MISA_K_SHIFT   (10U)

◆ CSR_MISA_L_GET

#define CSR_MISA_L_GET (   x)    (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT)

◆ CSR_MISA_L_MASK

#define CSR_MISA_L_MASK   (0x800U)

◆ CSR_MISA_L_SHIFT

#define CSR_MISA_L_SHIFT   (11U)

◆ CSR_MISA_M_GET

#define CSR_MISA_M_GET (   x)    (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT)

◆ CSR_MISA_M_MASK

#define CSR_MISA_M_MASK   (0x1000U)

◆ CSR_MISA_M_SHIFT

#define CSR_MISA_M_SHIFT   (12U)

◆ CSR_MISA_N_GET

#define CSR_MISA_N_GET (   x)    (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT)

◆ CSR_MISA_N_MASK

#define CSR_MISA_N_MASK   (0x2000U)

◆ CSR_MISA_N_SHIFT

#define CSR_MISA_N_SHIFT   (13U)

◆ CSR_MISA_O_GET

#define CSR_MISA_O_GET (   x)    (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT)

◆ CSR_MISA_O_MASK

#define CSR_MISA_O_MASK   (0x4000U)

◆ CSR_MISA_O_SHIFT

#define CSR_MISA_O_SHIFT   (14U)

◆ CSR_MISA_P_GET

#define CSR_MISA_P_GET (   x)    (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT)

◆ CSR_MISA_P_MASK

#define CSR_MISA_P_MASK   (0x8000U)

◆ CSR_MISA_P_SHIFT

#define CSR_MISA_P_SHIFT   (15U)

◆ CSR_MISA_Q_GET

#define CSR_MISA_Q_GET (   x)    (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT)

◆ CSR_MISA_Q_MASK

#define CSR_MISA_Q_MASK   (0x10000UL)

◆ CSR_MISA_Q_SHIFT

#define CSR_MISA_Q_SHIFT   (16U)

◆ CSR_MISA_R_GET

#define CSR_MISA_R_GET (   x)    (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT)

◆ CSR_MISA_R_MASK

#define CSR_MISA_R_MASK   (0x20000UL)

◆ CSR_MISA_R_SHIFT

#define CSR_MISA_R_SHIFT   (17U)

◆ CSR_MISA_S_GET

#define CSR_MISA_S_GET (   x)    (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT)

◆ CSR_MISA_S_MASK

#define CSR_MISA_S_MASK   (0x40000UL)

◆ CSR_MISA_S_SHIFT

#define CSR_MISA_S_SHIFT   (18U)

◆ CSR_MISA_T_GET

#define CSR_MISA_T_GET (   x)    (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT)

◆ CSR_MISA_T_MASK

#define CSR_MISA_T_MASK   (0x80000UL)

◆ CSR_MISA_T_SHIFT

#define CSR_MISA_T_SHIFT   (19U)

◆ CSR_MISA_U_GET

#define CSR_MISA_U_GET (   x)    (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT)

◆ CSR_MISA_U_MASK

#define CSR_MISA_U_MASK   (0x100000UL)

◆ CSR_MISA_U_SHIFT

#define CSR_MISA_U_SHIFT   (20U)

◆ CSR_MISA_V_GET

#define CSR_MISA_V_GET (   x)    (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT)

◆ CSR_MISA_V_MASK

#define CSR_MISA_V_MASK   (0x200000UL)

◆ CSR_MISA_V_SHIFT

#define CSR_MISA_V_SHIFT   (21U)

◆ CSR_MISA_W_GET

#define CSR_MISA_W_GET (   x)    (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT)

◆ CSR_MISA_W_MASK

#define CSR_MISA_W_MASK   (0x400000UL)

◆ CSR_MISA_W_SHIFT

#define CSR_MISA_W_SHIFT   (22U)

◆ CSR_MISA_X_GET

#define CSR_MISA_X_GET (   x)    (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT)

◆ CSR_MISA_X_MASK

#define CSR_MISA_X_MASK   (0x800000UL)

◆ CSR_MISA_X_SHIFT

#define CSR_MISA_X_SHIFT   (23U)

◆ CSR_MISA_Y_GET

#define CSR_MISA_Y_GET (   x)    (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT)

◆ CSR_MISA_Y_MASK

#define CSR_MISA_Y_MASK   (0x1000000UL)

◆ CSR_MISA_Y_SHIFT

#define CSR_MISA_Y_SHIFT   (24U)

◆ CSR_MISA_Z_GET

#define CSR_MISA_Z_GET (   x)    (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT)

◆ CSR_MISA_Z_MASK

#define CSR_MISA_Z_MASK   (0x2000000UL)

◆ CSR_MISA_Z_SHIFT

#define CSR_MISA_Z_SHIFT   (25U)

◆ CSR_MMISC_CTL

#define CSR_MMISC_CTL   (0x7D0)

◆ CSR_MMISC_CTL_BRPE_GET

#define CSR_MMISC_CTL_BRPE_GET (   x)    (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT)

◆ CSR_MMISC_CTL_BRPE_MASK

#define CSR_MMISC_CTL_BRPE_MASK   (0x8U)

◆ CSR_MMISC_CTL_BRPE_SET

#define CSR_MMISC_CTL_BRPE_SET (   x)    (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK)

◆ CSR_MMISC_CTL_BRPE_SHIFT

#define CSR_MMISC_CTL_BRPE_SHIFT   (3U)

◆ CSR_MMISC_CTL_MSA_UNA_GET

#define CSR_MMISC_CTL_MSA_UNA_GET (   x)    (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT)

◆ CSR_MMISC_CTL_MSA_UNA_MASK

#define CSR_MMISC_CTL_MSA_UNA_MASK   (0x40U)

◆ CSR_MMISC_CTL_MSA_UNA_SET

#define CSR_MMISC_CTL_MSA_UNA_SET (   x)    (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK)

◆ CSR_MMISC_CTL_MSA_UNA_SHIFT

#define CSR_MMISC_CTL_MSA_UNA_SHIFT   (6U)

◆ CSR_MMISC_CTL_RVCOMPM_GET

#define CSR_MMISC_CTL_RVCOMPM_GET (   x)    (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT)

◆ CSR_MMISC_CTL_RVCOMPM_MASK

#define CSR_MMISC_CTL_RVCOMPM_MASK   (0x4U)

◆ CSR_MMISC_CTL_RVCOMPM_SET

#define CSR_MMISC_CTL_RVCOMPM_SET (   x)    (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK)

◆ CSR_MMISC_CTL_RVCOMPM_SHIFT

#define CSR_MMISC_CTL_RVCOMPM_SHIFT   (2U)

◆ CSR_MMISC_CTL_VEC_PLIC_GET

#define CSR_MMISC_CTL_VEC_PLIC_GET (   x)    (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT)

◆ CSR_MMISC_CTL_VEC_PLIC_MASK

#define CSR_MMISC_CTL_VEC_PLIC_MASK   (0x2U)

◆ CSR_MMISC_CTL_VEC_PLIC_SET

#define CSR_MMISC_CTL_VEC_PLIC_SET (   x)    (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK)

◆ CSR_MMISC_CTL_VEC_PLIC_SHIFT

#define CSR_MMISC_CTL_VEC_PLIC_SHIFT   (1U)

◆ CSR_MMSC_CFG

#define CSR_MMSC_CFG   (0xFC2)

◆ CSR_MMSC_CFG2

#define CSR_MMSC_CFG2   (0xFC3)

◆ CSR_MMSC_CFG2_BF16CVT_GET

#define CSR_MMSC_CFG2_BF16CVT_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT)

◆ CSR_MMSC_CFG2_BF16CVT_MASK

#define CSR_MMSC_CFG2_BF16CVT_MASK   (0x1U)

◆ CSR_MMSC_CFG2_BF16CVT_SHIFT

#define CSR_MMSC_CFG2_BF16CVT_SHIFT   (0U)

◆ CSR_MMSC_CFG2_FINV_GET

#define CSR_MMSC_CFG2_FINV_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT)

◆ CSR_MMSC_CFG2_FINV_MASK

#define CSR_MMSC_CFG2_FINV_MASK   (0x20U)

◆ CSR_MMSC_CFG2_FINV_SHIFT

#define CSR_MMSC_CFG2_FINV_SHIFT   (5U)

◆ CSR_MMSC_CFG2_ZFH_GET

#define CSR_MMSC_CFG2_ZFH_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT)

◆ CSR_MMSC_CFG2_ZFH_MASK

#define CSR_MMSC_CFG2_ZFH_MASK   (0x2U)

◆ CSR_MMSC_CFG2_ZFH_SHIFT

#define CSR_MMSC_CFG2_ZFH_SHIFT   (1U)

◆ CSR_MMSC_CFG_ACE_GET

#define CSR_MMSC_CFG_ACE_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT)

◆ CSR_MMSC_CFG_ACE_MASK

#define CSR_MMSC_CFG_ACE_MASK   (0x40U)

◆ CSR_MMSC_CFG_ACE_SHIFT

#define CSR_MMSC_CFG_ACE_SHIFT   (6U)

◆ CSR_MMSC_CFG_CCTLCSR_GET

#define CSR_MMSC_CFG_CCTLCSR_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT)

◆ CSR_MMSC_CFG_CCTLCSR_MASK

#define CSR_MMSC_CFG_CCTLCSR_MASK   (0x10000UL)

◆ CSR_MMSC_CFG_CCTLCSR_SHIFT

#define CSR_MMSC_CFG_CCTLCSR_SHIFT   (16U)

◆ CSR_MMSC_CFG_ECC_GET

#define CSR_MMSC_CFG_ECC_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT)

◆ CSR_MMSC_CFG_ECC_MASK

#define CSR_MMSC_CFG_ECC_MASK   (0x1U)

◆ CSR_MMSC_CFG_ECC_SHIFT

#define CSR_MMSC_CFG_ECC_SHIFT   (0U)

◆ CSR_MMSC_CFG_ECD_GET

#define CSR_MMSC_CFG_ECD_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT)

◆ CSR_MMSC_CFG_ECD_MASK

#define CSR_MMSC_CFG_ECD_MASK   (0x8U)

◆ CSR_MMSC_CFG_ECD_SHIFT

#define CSR_MMSC_CFG_ECD_SHIFT   (3U)

◆ CSR_MMSC_CFG_EDSP_GET

#define CSR_MMSC_CFG_EDSP_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT)

◆ CSR_MMSC_CFG_EDSP_MASK

#define CSR_MMSC_CFG_EDSP_MASK   (0x20000000UL)

◆ CSR_MMSC_CFG_EDSP_SHIFT

#define CSR_MMSC_CFG_EDSP_SHIFT   (29U)

◆ CSR_MMSC_CFG_EFHW_GET

#define CSR_MMSC_CFG_EFHW_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT)

◆ CSR_MMSC_CFG_EFHW_MASK

#define CSR_MMSC_CFG_EFHW_MASK   (0x20000UL)

◆ CSR_MMSC_CFG_EFHW_SHIFT

#define CSR_MMSC_CFG_EFHW_SHIFT   (17U)

◆ CSR_MMSC_CFG_EV5PE_GET

#define CSR_MMSC_CFG_EV5PE_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT)

◆ CSR_MMSC_CFG_EV5PE_MASK

#define CSR_MMSC_CFG_EV5PE_MASK   (0x2000U)

◆ CSR_MMSC_CFG_EV5PE_SHIFT

#define CSR_MMSC_CFG_EV5PE_SHIFT   (13U)

◆ CSR_MMSC_CFG_HSP_GET

#define CSR_MMSC_CFG_HSP_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT)

◆ CSR_MMSC_CFG_HSP_MASK

#define CSR_MMSC_CFG_HSP_MASK   (0x20U)

◆ CSR_MMSC_CFG_HSP_SHIFT

#define CSR_MMSC_CFG_HSP_SHIFT   (5U)

◆ CSR_MMSC_CFG_LMSLVP_GET

#define CSR_MMSC_CFG_LMSLVP_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT)

◆ CSR_MMSC_CFG_LMSLVP_MASK

#define CSR_MMSC_CFG_LMSLVP_MASK   (0x4000U)

◆ CSR_MMSC_CFG_LMSLVP_SHIFT

#define CSR_MMSC_CFG_LMSLVP_SHIFT   (14U)

◆ CSR_MMSC_CFG_MSC_EXT_GET

#define CSR_MMSC_CFG_MSC_EXT_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT)

◆ CSR_MMSC_CFG_MSC_EXT_MASK

#define CSR_MMSC_CFG_MSC_EXT_MASK   (0x80000000UL)

◆ CSR_MMSC_CFG_MSC_EXT_SHIFT

#define CSR_MMSC_CFG_MSC_EXT_SHIFT   (31U)

◆ CSR_MMSC_CFG_PFT_GET

#define CSR_MMSC_CFG_PFT_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT)

◆ CSR_MMSC_CFG_PFT_MASK

#define CSR_MMSC_CFG_PFT_MASK   (0x10U)

◆ CSR_MMSC_CFG_PFT_SHIFT

#define CSR_MMSC_CFG_PFT_SHIFT   (4U)

◆ CSR_MMSC_CFG_PMNDS_GET

#define CSR_MMSC_CFG_PMNDS_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT)

◆ CSR_MMSC_CFG_PMNDS_MASK

#define CSR_MMSC_CFG_PMNDS_MASK   (0x8000U)

◆ CSR_MMSC_CFG_PMNDS_SHIFT

#define CSR_MMSC_CFG_PMNDS_SHIFT   (15U)

◆ CSR_MMSC_CFG_PPMA_GET

#define CSR_MMSC_CFG_PPMA_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT)

◆ CSR_MMSC_CFG_PPMA_MASK

#define CSR_MMSC_CFG_PPMA_MASK   (0x40000000UL)

◆ CSR_MMSC_CFG_PPMA_SHIFT

#define CSR_MMSC_CFG_PPMA_SHIFT   (30U)

◆ CSR_MMSC_CFG_TLB_ECC_GET

#define CSR_MMSC_CFG_TLB_ECC_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT)

◆ CSR_MMSC_CFG_TLB_ECC_MASK

#define CSR_MMSC_CFG_TLB_ECC_MASK   (0x6U)

◆ CSR_MMSC_CFG_TLB_ECC_SHIFT

#define CSR_MMSC_CFG_TLB_ECC_SHIFT   (1U)

◆ CSR_MMSC_CFG_VCCTL_GET

#define CSR_MMSC_CFG_VCCTL_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT)

◆ CSR_MMSC_CFG_VCCTL_MASK

#define CSR_MMSC_CFG_VCCTL_MASK   (0xC0000UL)

◆ CSR_MMSC_CFG_VCCTL_SHIFT

#define CSR_MMSC_CFG_VCCTL_SHIFT   (18U)

◆ CSR_MMSC_CFG_VPLIC_GET

#define CSR_MMSC_CFG_VPLIC_GET (   x)    (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT)

◆ CSR_MMSC_CFG_VPLIC_MASK

#define CSR_MMSC_CFG_VPLIC_MASK   (0x1000U)

◆ CSR_MMSC_CFG_VPLIC_SHIFT

#define CSR_MMSC_CFG_VPLIC_SHIFT   (12U)

◆ CSR_MNVEC

#define CSR_MNVEC   (0x7C3)

◆ CSR_MNVEC_MNVEC_GET

#define CSR_MNVEC_MNVEC_GET (   x)    (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT)

◆ CSR_MNVEC_MNVEC_MASK

#define CSR_MNVEC_MNVEC_MASK   (0xFFFFFFFFUL)

◆ CSR_MNVEC_MNVEC_SHIFT

#define CSR_MNVEC_MNVEC_SHIFT   (0U)

◆ CSR_MPFT_CTL

#define CSR_MPFT_CTL   (0x7C5)

◆ CSR_MPFT_CTL_FAST_INT_GET

#define CSR_MPFT_CTL_FAST_INT_GET (   x)    (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT)

◆ CSR_MPFT_CTL_FAST_INT_MASK

#define CSR_MPFT_CTL_FAST_INT_MASK   (0x100U)

◆ CSR_MPFT_CTL_FAST_INT_SET

#define CSR_MPFT_CTL_FAST_INT_SET (   x)    (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK)

◆ CSR_MPFT_CTL_FAST_INT_SHIFT

#define CSR_MPFT_CTL_FAST_INT_SHIFT   (8U)

◆ CSR_MPFT_CTL_T_LEVEL_GET

#define CSR_MPFT_CTL_T_LEVEL_GET (   x)    (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT)

◆ CSR_MPFT_CTL_T_LEVEL_MASK

#define CSR_MPFT_CTL_T_LEVEL_MASK   (0xF0U)

◆ CSR_MPFT_CTL_T_LEVEL_SET

#define CSR_MPFT_CTL_T_LEVEL_SET (   x)    (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK)

◆ CSR_MPFT_CTL_T_LEVEL_SHIFT

#define CSR_MPFT_CTL_T_LEVEL_SHIFT   (4U)

◆ CSR_MSCRATCH

#define CSR_MSCRATCH   (0x340)

◆ CSR_MSCRATCH_MSCRATCH_GET

#define CSR_MSCRATCH_MSCRATCH_GET (   x)    (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT)

◆ CSR_MSCRATCH_MSCRATCH_MASK

#define CSR_MSCRATCH_MSCRATCH_MASK   (0xFFFFFFFFUL)

◆ CSR_MSCRATCH_MSCRATCH_SET

#define CSR_MSCRATCH_MSCRATCH_SET (   x)    (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK)

◆ CSR_MSCRATCH_MSCRATCH_SHIFT

#define CSR_MSCRATCH_MSCRATCH_SHIFT   (0U)

◆ CSR_MSP_BASE

#define CSR_MSP_BASE   (0x7C8)

◆ CSR_MSP_BASE_SP_BASE_GET

#define CSR_MSP_BASE_SP_BASE_GET (   x)    (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT)

◆ CSR_MSP_BASE_SP_BASE_MASK

#define CSR_MSP_BASE_SP_BASE_MASK   (0xFFFFFFFFUL)

◆ CSR_MSP_BASE_SP_BASE_SET

#define CSR_MSP_BASE_SP_BASE_SET (   x)    (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK)

◆ CSR_MSP_BASE_SP_BASE_SHIFT

#define CSR_MSP_BASE_SP_BASE_SHIFT   (0U)

◆ CSR_MSP_BOUND

#define CSR_MSP_BOUND   (0x7C7)

◆ CSR_MSP_BOUND_MSP_BOUND_GET

#define CSR_MSP_BOUND_MSP_BOUND_GET (   x)    (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT)

◆ CSR_MSP_BOUND_MSP_BOUND_MASK

#define CSR_MSP_BOUND_MSP_BOUND_MASK   (0xFFFFFFFFUL)

◆ CSR_MSP_BOUND_MSP_BOUND_SET

#define CSR_MSP_BOUND_MSP_BOUND_SET (   x)    (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK)

◆ CSR_MSP_BOUND_MSP_BOUND_SHIFT

#define CSR_MSP_BOUND_MSP_BOUND_SHIFT   (0U)

◆ CSR_MSTATUS

#define CSR_MSTATUS   (0x300)

◆ CSR_MSTATUS_FS_GET

#define CSR_MSTATUS_FS_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT)

◆ CSR_MSTATUS_FS_MASK

#define CSR_MSTATUS_FS_MASK   (0x6000U)

◆ CSR_MSTATUS_FS_SET

#define CSR_MSTATUS_FS_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK)

◆ CSR_MSTATUS_FS_SHIFT

#define CSR_MSTATUS_FS_SHIFT   (13U)

◆ CSR_MSTATUS_MIE_GET

#define CSR_MSTATUS_MIE_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT)

◆ CSR_MSTATUS_MIE_MASK

#define CSR_MSTATUS_MIE_MASK   (0x8U)

◆ CSR_MSTATUS_MIE_SET

#define CSR_MSTATUS_MIE_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK)

◆ CSR_MSTATUS_MIE_SHIFT

#define CSR_MSTATUS_MIE_SHIFT   (3U)

◆ CSR_MSTATUS_MPIE_GET

#define CSR_MSTATUS_MPIE_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT)

◆ CSR_MSTATUS_MPIE_MASK

#define CSR_MSTATUS_MPIE_MASK   (0x80U)

◆ CSR_MSTATUS_MPIE_SET

#define CSR_MSTATUS_MPIE_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK)

◆ CSR_MSTATUS_MPIE_SHIFT

#define CSR_MSTATUS_MPIE_SHIFT   (7U)

◆ CSR_MSTATUS_MPP_GET

#define CSR_MSTATUS_MPP_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT)

◆ CSR_MSTATUS_MPP_MASK

#define CSR_MSTATUS_MPP_MASK   (0x1800U)

◆ CSR_MSTATUS_MPP_SET

#define CSR_MSTATUS_MPP_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK)

◆ CSR_MSTATUS_MPP_SHIFT

#define CSR_MSTATUS_MPP_SHIFT   (11U)

◆ CSR_MSTATUS_MPRV_GET

#define CSR_MSTATUS_MPRV_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT)

◆ CSR_MSTATUS_MPRV_MASK

#define CSR_MSTATUS_MPRV_MASK   (0x20000UL)

◆ CSR_MSTATUS_MPRV_SET

#define CSR_MSTATUS_MPRV_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK)

◆ CSR_MSTATUS_MPRV_SHIFT

#define CSR_MSTATUS_MPRV_SHIFT   (17U)

◆ CSR_MSTATUS_MXR_GET

#define CSR_MSTATUS_MXR_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT)

◆ CSR_MSTATUS_MXR_MASK

#define CSR_MSTATUS_MXR_MASK   (0x80000UL)

◆ CSR_MSTATUS_MXR_SET

#define CSR_MSTATUS_MXR_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK)

◆ CSR_MSTATUS_MXR_SHIFT

#define CSR_MSTATUS_MXR_SHIFT   (19U)

◆ CSR_MSTATUS_SD_GET

#define CSR_MSTATUS_SD_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT)

◆ CSR_MSTATUS_SD_MASK

#define CSR_MSTATUS_SD_MASK   (0x80000000UL)

◆ CSR_MSTATUS_SD_SHIFT

#define CSR_MSTATUS_SD_SHIFT   (31U)

◆ CSR_MSTATUS_UIE_GET

#define CSR_MSTATUS_UIE_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT)

◆ CSR_MSTATUS_UIE_MASK

#define CSR_MSTATUS_UIE_MASK   (0x1U)

◆ CSR_MSTATUS_UIE_SET

#define CSR_MSTATUS_UIE_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK)

◆ CSR_MSTATUS_UIE_SHIFT

#define CSR_MSTATUS_UIE_SHIFT   (0U)

◆ CSR_MSTATUS_UPIE_GET

#define CSR_MSTATUS_UPIE_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT)

◆ CSR_MSTATUS_UPIE_MASK

#define CSR_MSTATUS_UPIE_MASK   (0x10U)

◆ CSR_MSTATUS_UPIE_SET

#define CSR_MSTATUS_UPIE_SET (   x)    (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK)

◆ CSR_MSTATUS_UPIE_SHIFT

#define CSR_MSTATUS_UPIE_SHIFT   (4U)

◆ CSR_MSTATUS_XS_GET

#define CSR_MSTATUS_XS_GET (   x)    (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT)

◆ CSR_MSTATUS_XS_MASK

#define CSR_MSTATUS_XS_MASK   (0x18000UL)

◆ CSR_MSTATUS_XS_SHIFT

#define CSR_MSTATUS_XS_SHIFT   (15U)

◆ CSR_MTVAL

#define CSR_MTVAL   (0x343)

◆ CSR_MTVAL_MTVAL_GET

#define CSR_MTVAL_MTVAL_GET (   x)    (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT)

◆ CSR_MTVAL_MTVAL_MASK

#define CSR_MTVAL_MTVAL_MASK   (0xFFFFFFFFUL)

◆ CSR_MTVAL_MTVAL_SET

#define CSR_MTVAL_MTVAL_SET (   x)    (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK)

◆ CSR_MTVAL_MTVAL_SHIFT

#define CSR_MTVAL_MTVAL_SHIFT   (0U)

◆ CSR_MTVEC

#define CSR_MTVEC   (0x305)

◆ CSR_MTVEC_BASE_31_2_GET

#define CSR_MTVEC_BASE_31_2_GET (   x)    (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT)

◆ CSR_MTVEC_BASE_31_2_MASK

#define CSR_MTVEC_BASE_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_MTVEC_BASE_31_2_SET

#define CSR_MTVEC_BASE_31_2_SET (   x)    (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK)

◆ CSR_MTVEC_BASE_31_2_SHIFT

#define CSR_MTVEC_BASE_31_2_SHIFT   (2U)

◆ CSR_MVENDORID

#define CSR_MVENDORID   (0xF11)

◆ CSR_MVENDORID_MVENDORID_GET

#define CSR_MVENDORID_MVENDORID_GET (   x)    (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT)

◆ CSR_MVENDORID_MVENDORID_MASK

#define CSR_MVENDORID_MVENDORID_MASK   (0xFFFFFFFFUL)

◆ CSR_MVENDORID_MVENDORID_SHIFT

#define CSR_MVENDORID_MVENDORID_SHIFT   (0U)

◆ CSR_MXSTATUS

#define CSR_MXSTATUS   (0x7C4)

◆ CSR_MXSTATUS_DME_GET

#define CSR_MXSTATUS_DME_GET (   x)    (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT)

◆ CSR_MXSTATUS_DME_MASK

#define CSR_MXSTATUS_DME_MASK   (0x10U)

◆ CSR_MXSTATUS_DME_SET

#define CSR_MXSTATUS_DME_SET (   x)    (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK)

◆ CSR_MXSTATUS_DME_SHIFT

#define CSR_MXSTATUS_DME_SHIFT   (4U)

◆ CSR_MXSTATUS_IME_GET

#define CSR_MXSTATUS_IME_GET (   x)    (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT)

◆ CSR_MXSTATUS_IME_MASK

#define CSR_MXSTATUS_IME_MASK   (0x4U)

◆ CSR_MXSTATUS_IME_SET

#define CSR_MXSTATUS_IME_SET (   x)    (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK)

◆ CSR_MXSTATUS_IME_SHIFT

#define CSR_MXSTATUS_IME_SHIFT   (2U)

◆ CSR_MXSTATUS_PDME_GET

#define CSR_MXSTATUS_PDME_GET (   x)    (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT)

◆ CSR_MXSTATUS_PDME_MASK

#define CSR_MXSTATUS_PDME_MASK   (0x20U)

◆ CSR_MXSTATUS_PDME_SET

#define CSR_MXSTATUS_PDME_SET (   x)    (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK)

◆ CSR_MXSTATUS_PDME_SHIFT

#define CSR_MXSTATUS_PDME_SHIFT   (5U)

◆ CSR_MXSTATUS_PFT_EN_GET

#define CSR_MXSTATUS_PFT_EN_GET (   x)    (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT)

◆ CSR_MXSTATUS_PFT_EN_MASK

#define CSR_MXSTATUS_PFT_EN_MASK   (0x1U)

◆ CSR_MXSTATUS_PFT_EN_SET

#define CSR_MXSTATUS_PFT_EN_SET (   x)    (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK)

◆ CSR_MXSTATUS_PFT_EN_SHIFT

#define CSR_MXSTATUS_PFT_EN_SHIFT   (0U)

◆ CSR_MXSTATUS_PIME_GET

#define CSR_MXSTATUS_PIME_GET (   x)    (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT)

◆ CSR_MXSTATUS_PIME_MASK

#define CSR_MXSTATUS_PIME_MASK   (0x8U)

◆ CSR_MXSTATUS_PIME_SET

#define CSR_MXSTATUS_PIME_SET (   x)    (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK)

◆ CSR_MXSTATUS_PIME_SHIFT

#define CSR_MXSTATUS_PIME_SHIFT   (3U)

◆ CSR_MXSTATUS_PPFT_EN_GET

#define CSR_MXSTATUS_PPFT_EN_GET (   x)    (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT)

◆ CSR_MXSTATUS_PPFT_EN_MASK

#define CSR_MXSTATUS_PPFT_EN_MASK   (0x2U)

◆ CSR_MXSTATUS_PPFT_EN_SET

#define CSR_MXSTATUS_PPFT_EN_SET (   x)    (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK)

◆ CSR_MXSTATUS_PPFT_EN_SHIFT

#define CSR_MXSTATUS_PPFT_EN_SHIFT   (1U)

◆ CSR_PMPADDR0

#define CSR_PMPADDR0   (0x3B0)

◆ CSR_PMPADDR0_PMPADDR_31_2_GET

#define CSR_PMPADDR0_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR0_PMPADDR_31_2_MASK

#define CSR_PMPADDR0_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR0_PMPADDR_31_2_SET

#define CSR_PMPADDR0_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR0_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR1

#define CSR_PMPADDR1   (0x3B1)

◆ CSR_PMPADDR10

#define CSR_PMPADDR10   (0x3BA)

◆ CSR_PMPADDR10_PMPADDR_31_2_GET

#define CSR_PMPADDR10_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR10_PMPADDR_31_2_MASK

#define CSR_PMPADDR10_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR10_PMPADDR_31_2_SET

#define CSR_PMPADDR10_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR10_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR11

#define CSR_PMPADDR11   (0x3BB)

◆ CSR_PMPADDR11_PMPADDR_31_2_GET

#define CSR_PMPADDR11_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR11_PMPADDR_31_2_MASK

#define CSR_PMPADDR11_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR11_PMPADDR_31_2_SET

#define CSR_PMPADDR11_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR11_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR12

#define CSR_PMPADDR12   (0x3BC)

◆ CSR_PMPADDR12_PMPADDR_31_2_GET

#define CSR_PMPADDR12_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR12_PMPADDR_31_2_MASK

#define CSR_PMPADDR12_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR12_PMPADDR_31_2_SET

#define CSR_PMPADDR12_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR12_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR13

#define CSR_PMPADDR13   (0x3BD)

◆ CSR_PMPADDR13_PMPADDR_31_2_GET

#define CSR_PMPADDR13_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR13_PMPADDR_31_2_MASK

#define CSR_PMPADDR13_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR13_PMPADDR_31_2_SET

#define CSR_PMPADDR13_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR13_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR14

#define CSR_PMPADDR14   (0x3BE)

◆ CSR_PMPADDR14_PMPADDR_31_2_GET

#define CSR_PMPADDR14_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR14_PMPADDR_31_2_MASK

#define CSR_PMPADDR14_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR14_PMPADDR_31_2_SET

#define CSR_PMPADDR14_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR14_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR15

#define CSR_PMPADDR15   (0x3BF)

◆ CSR_PMPADDR15_PMPADDR_31_2_GET

#define CSR_PMPADDR15_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR15_PMPADDR_31_2_MASK

#define CSR_PMPADDR15_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR15_PMPADDR_31_2_SET

#define CSR_PMPADDR15_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR15_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR1_PMPADDR_31_2_GET

#define CSR_PMPADDR1_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR1_PMPADDR_31_2_MASK

#define CSR_PMPADDR1_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR1_PMPADDR_31_2_SET

#define CSR_PMPADDR1_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR1_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR2

#define CSR_PMPADDR2   (0x3B2)

◆ CSR_PMPADDR2_PMPADDR_31_2_GET

#define CSR_PMPADDR2_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR2_PMPADDR_31_2_MASK

#define CSR_PMPADDR2_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR2_PMPADDR_31_2_SET

#define CSR_PMPADDR2_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR2_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR3

#define CSR_PMPADDR3   (0x3B3)

◆ CSR_PMPADDR3_PMPADDR_31_2_GET

#define CSR_PMPADDR3_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR3_PMPADDR_31_2_MASK

#define CSR_PMPADDR3_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR3_PMPADDR_31_2_SET

#define CSR_PMPADDR3_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR3_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR4

#define CSR_PMPADDR4   (0x3B4)

◆ CSR_PMPADDR4_PMPADDR_31_2_GET

#define CSR_PMPADDR4_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR4_PMPADDR_31_2_MASK

#define CSR_PMPADDR4_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR4_PMPADDR_31_2_SET

#define CSR_PMPADDR4_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR4_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR5

#define CSR_PMPADDR5   (0x3B5)

◆ CSR_PMPADDR5_PMPADDR_31_2_GET

#define CSR_PMPADDR5_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR5_PMPADDR_31_2_MASK

#define CSR_PMPADDR5_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR5_PMPADDR_31_2_SET

#define CSR_PMPADDR5_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR5_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR6

#define CSR_PMPADDR6   (0x3B6)

◆ CSR_PMPADDR6_PMPADDR_31_2_GET

#define CSR_PMPADDR6_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR6_PMPADDR_31_2_MASK

#define CSR_PMPADDR6_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR6_PMPADDR_31_2_SET

#define CSR_PMPADDR6_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR6_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR7

#define CSR_PMPADDR7   (0x3B7)

◆ CSR_PMPADDR7_PMPADDR_31_2_GET

#define CSR_PMPADDR7_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR7_PMPADDR_31_2_MASK

#define CSR_PMPADDR7_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR7_PMPADDR_31_2_SET

#define CSR_PMPADDR7_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR7_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR8

#define CSR_PMPADDR8   (0x3B8)

◆ CSR_PMPADDR8_PMPADDR_31_2_GET

#define CSR_PMPADDR8_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR8_PMPADDR_31_2_MASK

#define CSR_PMPADDR8_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR8_PMPADDR_31_2_SET

#define CSR_PMPADDR8_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR8_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPADDR9

#define CSR_PMPADDR9   (0x3B9)

◆ CSR_PMPADDR9_PMPADDR_31_2_GET

#define CSR_PMPADDR9_PMPADDR_31_2_GET (   x)    (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT)

◆ CSR_PMPADDR9_PMPADDR_31_2_MASK

#define CSR_PMPADDR9_PMPADDR_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_PMPADDR9_PMPADDR_31_2_SET

#define CSR_PMPADDR9_PMPADDR_31_2_SET (   x)    (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK)

◆ CSR_PMPADDR9_PMPADDR_31_2_SHIFT

#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT   (2U)

◆ CSR_PMPCFG0

#define CSR_PMPCFG0   (0x3A0)

◆ CSR_PMPCFG0_PMP0CFG_GET

#define CSR_PMPCFG0_PMP0CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT)

◆ CSR_PMPCFG0_PMP0CFG_MASK

#define CSR_PMPCFG0_PMP0CFG_MASK   (0xFFU)

◆ CSR_PMPCFG0_PMP0CFG_SET

#define CSR_PMPCFG0_PMP0CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK)

◆ CSR_PMPCFG0_PMP0CFG_SHIFT

#define CSR_PMPCFG0_PMP0CFG_SHIFT   (0U)

◆ CSR_PMPCFG0_PMP1CFG_GET

#define CSR_PMPCFG0_PMP1CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT)

◆ CSR_PMPCFG0_PMP1CFG_MASK

#define CSR_PMPCFG0_PMP1CFG_MASK   (0xFF00U)

◆ CSR_PMPCFG0_PMP1CFG_SET

#define CSR_PMPCFG0_PMP1CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK)

◆ CSR_PMPCFG0_PMP1CFG_SHIFT

#define CSR_PMPCFG0_PMP1CFG_SHIFT   (8U)

◆ CSR_PMPCFG0_PMP2CFG_GET

#define CSR_PMPCFG0_PMP2CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT)

◆ CSR_PMPCFG0_PMP2CFG_MASK

#define CSR_PMPCFG0_PMP2CFG_MASK   (0xFF0000UL)

◆ CSR_PMPCFG0_PMP2CFG_SET

#define CSR_PMPCFG0_PMP2CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK)

◆ CSR_PMPCFG0_PMP2CFG_SHIFT

#define CSR_PMPCFG0_PMP2CFG_SHIFT   (16U)

◆ CSR_PMPCFG0_PMP3CFG_GET

#define CSR_PMPCFG0_PMP3CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT)

◆ CSR_PMPCFG0_PMP3CFG_MASK

#define CSR_PMPCFG0_PMP3CFG_MASK   (0xFF000000UL)

◆ CSR_PMPCFG0_PMP3CFG_SET

#define CSR_PMPCFG0_PMP3CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK)

◆ CSR_PMPCFG0_PMP3CFG_SHIFT

#define CSR_PMPCFG0_PMP3CFG_SHIFT   (24U)

◆ CSR_PMPCFG1

#define CSR_PMPCFG1   (0x3A1)

◆ CSR_PMPCFG1_PMP4CFG_GET

#define CSR_PMPCFG1_PMP4CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT)

◆ CSR_PMPCFG1_PMP4CFG_MASK

#define CSR_PMPCFG1_PMP4CFG_MASK   (0xFFU)

◆ CSR_PMPCFG1_PMP4CFG_SET

#define CSR_PMPCFG1_PMP4CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK)

◆ CSR_PMPCFG1_PMP4CFG_SHIFT

#define CSR_PMPCFG1_PMP4CFG_SHIFT   (0U)

◆ CSR_PMPCFG1_PMP5CFG_GET

#define CSR_PMPCFG1_PMP5CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT)

◆ CSR_PMPCFG1_PMP5CFG_MASK

#define CSR_PMPCFG1_PMP5CFG_MASK   (0xFF00U)

◆ CSR_PMPCFG1_PMP5CFG_SET

#define CSR_PMPCFG1_PMP5CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK)

◆ CSR_PMPCFG1_PMP5CFG_SHIFT

#define CSR_PMPCFG1_PMP5CFG_SHIFT   (8U)

◆ CSR_PMPCFG1_PMP6CFG_GET

#define CSR_PMPCFG1_PMP6CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT)

◆ CSR_PMPCFG1_PMP6CFG_MASK

#define CSR_PMPCFG1_PMP6CFG_MASK   (0xFF0000UL)

◆ CSR_PMPCFG1_PMP6CFG_SET

#define CSR_PMPCFG1_PMP6CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK)

◆ CSR_PMPCFG1_PMP6CFG_SHIFT

#define CSR_PMPCFG1_PMP6CFG_SHIFT   (16U)

◆ CSR_PMPCFG1_PMP7CFG_GET

#define CSR_PMPCFG1_PMP7CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT)

◆ CSR_PMPCFG1_PMP7CFG_MASK

#define CSR_PMPCFG1_PMP7CFG_MASK   (0xFF000000UL)

◆ CSR_PMPCFG1_PMP7CFG_SET

#define CSR_PMPCFG1_PMP7CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK)

◆ CSR_PMPCFG1_PMP7CFG_SHIFT

#define CSR_PMPCFG1_PMP7CFG_SHIFT   (24U)

◆ CSR_PMPCFG2

#define CSR_PMPCFG2   (0x3A2)

◆ CSR_PMPCFG2_PMP10CFG_GET

#define CSR_PMPCFG2_PMP10CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT)

◆ CSR_PMPCFG2_PMP10CFG_MASK

#define CSR_PMPCFG2_PMP10CFG_MASK   (0xFF0000UL)

◆ CSR_PMPCFG2_PMP10CFG_SET

#define CSR_PMPCFG2_PMP10CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK)

◆ CSR_PMPCFG2_PMP10CFG_SHIFT

#define CSR_PMPCFG2_PMP10CFG_SHIFT   (16U)

◆ CSR_PMPCFG2_PMP11CFG_GET

#define CSR_PMPCFG2_PMP11CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT)

◆ CSR_PMPCFG2_PMP11CFG_MASK

#define CSR_PMPCFG2_PMP11CFG_MASK   (0xFF000000UL)

◆ CSR_PMPCFG2_PMP11CFG_SET

#define CSR_PMPCFG2_PMP11CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK)

◆ CSR_PMPCFG2_PMP11CFG_SHIFT

#define CSR_PMPCFG2_PMP11CFG_SHIFT   (24U)

◆ CSR_PMPCFG2_PMP8CFG_GET

#define CSR_PMPCFG2_PMP8CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT)

◆ CSR_PMPCFG2_PMP8CFG_MASK

#define CSR_PMPCFG2_PMP8CFG_MASK   (0xFFU)

◆ CSR_PMPCFG2_PMP8CFG_SET

#define CSR_PMPCFG2_PMP8CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK)

◆ CSR_PMPCFG2_PMP8CFG_SHIFT

#define CSR_PMPCFG2_PMP8CFG_SHIFT   (0U)

◆ CSR_PMPCFG2_PMP9CFG_GET

#define CSR_PMPCFG2_PMP9CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT)

◆ CSR_PMPCFG2_PMP9CFG_MASK

#define CSR_PMPCFG2_PMP9CFG_MASK   (0xFF00U)

◆ CSR_PMPCFG2_PMP9CFG_SET

#define CSR_PMPCFG2_PMP9CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK)

◆ CSR_PMPCFG2_PMP9CFG_SHIFT

#define CSR_PMPCFG2_PMP9CFG_SHIFT   (8U)

◆ CSR_PMPCFG3

#define CSR_PMPCFG3   (0x3A3)

◆ CSR_PMPCFG3_PMP12CFG_GET

#define CSR_PMPCFG3_PMP12CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT)

◆ CSR_PMPCFG3_PMP12CFG_MASK

#define CSR_PMPCFG3_PMP12CFG_MASK   (0xFFU)

◆ CSR_PMPCFG3_PMP12CFG_SET

#define CSR_PMPCFG3_PMP12CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK)

◆ CSR_PMPCFG3_PMP12CFG_SHIFT

#define CSR_PMPCFG3_PMP12CFG_SHIFT   (0U)

◆ CSR_PMPCFG3_PMP13CFG_GET

#define CSR_PMPCFG3_PMP13CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT)

◆ CSR_PMPCFG3_PMP13CFG_MASK

#define CSR_PMPCFG3_PMP13CFG_MASK   (0xFF00U)

◆ CSR_PMPCFG3_PMP13CFG_SET

#define CSR_PMPCFG3_PMP13CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK)

◆ CSR_PMPCFG3_PMP13CFG_SHIFT

#define CSR_PMPCFG3_PMP13CFG_SHIFT   (8U)

◆ CSR_PMPCFG3_PMP14CFG_GET

#define CSR_PMPCFG3_PMP14CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT)

◆ CSR_PMPCFG3_PMP14CFG_MASK

#define CSR_PMPCFG3_PMP14CFG_MASK   (0xFF0000UL)

◆ CSR_PMPCFG3_PMP14CFG_SET

#define CSR_PMPCFG3_PMP14CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK)

◆ CSR_PMPCFG3_PMP14CFG_SHIFT

#define CSR_PMPCFG3_PMP14CFG_SHIFT   (16U)

◆ CSR_PMPCFG3_PMP15CFG_GET

#define CSR_PMPCFG3_PMP15CFG_GET (   x)    (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT)

◆ CSR_PMPCFG3_PMP15CFG_MASK

#define CSR_PMPCFG3_PMP15CFG_MASK   (0xFF000000UL)

◆ CSR_PMPCFG3_PMP15CFG_SET

#define CSR_PMPCFG3_PMP15CFG_SET (   x)    (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK)

◆ CSR_PMPCFG3_PMP15CFG_SHIFT

#define CSR_PMPCFG3_PMP15CFG_SHIFT   (24U)

◆ CSR_SCONTEXT

#define CSR_SCONTEXT   (0x7AA)

◆ CSR_SCONTEXT_SCONTEXT_GET

#define CSR_SCONTEXT_SCONTEXT_GET (   x)    (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT)

◆ CSR_SCONTEXT_SCONTEXT_MASK

#define CSR_SCONTEXT_SCONTEXT_MASK   (0x1FFU)

◆ CSR_SCONTEXT_SCONTEXT_SET

#define CSR_SCONTEXT_SCONTEXT_SET (   x)    (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK)

◆ CSR_SCONTEXT_SCONTEXT_SHIFT

#define CSR_SCONTEXT_SCONTEXT_SHIFT   (0U)

◆ CSR_TCONTROL

#define CSR_TCONTROL   (0x7A5)

◆ CSR_TCONTROL_MPTE_GET

#define CSR_TCONTROL_MPTE_GET (   x)    (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT)

◆ CSR_TCONTROL_MPTE_MASK

#define CSR_TCONTROL_MPTE_MASK   (0x80U)

◆ CSR_TCONTROL_MPTE_SET

#define CSR_TCONTROL_MPTE_SET (   x)    (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK)

◆ CSR_TCONTROL_MPTE_SHIFT

#define CSR_TCONTROL_MPTE_SHIFT   (7U)

◆ CSR_TCONTROL_MTE_GET

#define CSR_TCONTROL_MTE_GET (   x)    (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT)

◆ CSR_TCONTROL_MTE_MASK

#define CSR_TCONTROL_MTE_MASK   (0x8U)

◆ CSR_TCONTROL_MTE_SET

#define CSR_TCONTROL_MTE_SET (   x)    (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK)

◆ CSR_TCONTROL_MTE_SHIFT

#define CSR_TCONTROL_MTE_SHIFT   (3U)

◆ CSR_TDATA1

#define CSR_TDATA1   (0x7A1)

◆ CSR_TDATA1_DATA_GET

#define CSR_TDATA1_DATA_GET (   x)    (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT)

◆ CSR_TDATA1_DATA_MASK

#define CSR_TDATA1_DATA_MASK   (0x7FFFFFFUL)

◆ CSR_TDATA1_DATA_SET

#define CSR_TDATA1_DATA_SET (   x)    (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK)

◆ CSR_TDATA1_DATA_SHIFT

#define CSR_TDATA1_DATA_SHIFT   (0U)

◆ CSR_TDATA1_DMODE_GET

#define CSR_TDATA1_DMODE_GET (   x)    (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT)

◆ CSR_TDATA1_DMODE_MASK

#define CSR_TDATA1_DMODE_MASK   (0x8000000UL)

◆ CSR_TDATA1_DMODE_SET

#define CSR_TDATA1_DMODE_SET (   x)    (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK)

◆ CSR_TDATA1_DMODE_SHIFT

#define CSR_TDATA1_DMODE_SHIFT   (27U)

◆ CSR_TDATA1_TYPE_GET

#define CSR_TDATA1_TYPE_GET (   x)    (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT)

◆ CSR_TDATA1_TYPE_MASK

#define CSR_TDATA1_TYPE_MASK   (0xF0000000UL)

◆ CSR_TDATA1_TYPE_SET

#define CSR_TDATA1_TYPE_SET (   x)    (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK)

◆ CSR_TDATA1_TYPE_SHIFT

#define CSR_TDATA1_TYPE_SHIFT   (28U)

◆ CSR_TDATA2

#define CSR_TDATA2   (0x7A2)

◆ CSR_TDATA2_DATA_GET

#define CSR_TDATA2_DATA_GET (   x)    (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT)

◆ CSR_TDATA2_DATA_MASK

#define CSR_TDATA2_DATA_MASK   (0xFFFFFFFFUL)

◆ CSR_TDATA2_DATA_SET

#define CSR_TDATA2_DATA_SET (   x)    (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK)

◆ CSR_TDATA2_DATA_SHIFT

#define CSR_TDATA2_DATA_SHIFT   (0U)

◆ CSR_TDATA3

#define CSR_TDATA3   (0x7A3)

◆ CSR_TDATA3_DATA_GET

#define CSR_TDATA3_DATA_GET (   x)    (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT)

◆ CSR_TDATA3_DATA_MASK

#define CSR_TDATA3_DATA_MASK   (0xFFFFFFFFUL)

◆ CSR_TDATA3_DATA_SET

#define CSR_TDATA3_DATA_SET (   x)    (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK)

◆ CSR_TDATA3_DATA_SHIFT

#define CSR_TDATA3_DATA_SHIFT   (0U)

◆ CSR_TEXTRA

#define CSR_TEXTRA   (0x7A3)

◆ CSR_TEXTRA_MSELECT_GET

#define CSR_TEXTRA_MSELECT_GET (   x)    (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT)

◆ CSR_TEXTRA_MSELECT_MASK

#define CSR_TEXTRA_MSELECT_MASK   (0x2000000UL)

◆ CSR_TEXTRA_MSELECT_SET

#define CSR_TEXTRA_MSELECT_SET (   x)    (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK)

◆ CSR_TEXTRA_MSELECT_SHIFT

#define CSR_TEXTRA_MSELECT_SHIFT   (25U)

◆ CSR_TEXTRA_MVALUE_GET

#define CSR_TEXTRA_MVALUE_GET (   x)    (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT)

◆ CSR_TEXTRA_MVALUE_MASK

#define CSR_TEXTRA_MVALUE_MASK   (0xFC000000UL)

◆ CSR_TEXTRA_MVALUE_SET

#define CSR_TEXTRA_MVALUE_SET (   x)    (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK)

◆ CSR_TEXTRA_MVALUE_SHIFT

#define CSR_TEXTRA_MVALUE_SHIFT   (26U)

◆ CSR_TEXTRA_SSELECT_GET

#define CSR_TEXTRA_SSELECT_GET (   x)    (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT)

◆ CSR_TEXTRA_SSELECT_MASK

#define CSR_TEXTRA_SSELECT_MASK   (0x3U)

◆ CSR_TEXTRA_SSELECT_SET

#define CSR_TEXTRA_SSELECT_SET (   x)    (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK)

◆ CSR_TEXTRA_SSELECT_SHIFT

#define CSR_TEXTRA_SSELECT_SHIFT   (0U)

◆ CSR_TEXTRA_SVALUE_GET

#define CSR_TEXTRA_SVALUE_GET (   x)    (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT)

◆ CSR_TEXTRA_SVALUE_MASK

#define CSR_TEXTRA_SVALUE_MASK   (0x7FCU)

◆ CSR_TEXTRA_SVALUE_SET

#define CSR_TEXTRA_SVALUE_SET (   x)    (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK)

◆ CSR_TEXTRA_SVALUE_SHIFT

#define CSR_TEXTRA_SVALUE_SHIFT   (2U)

◆ CSR_TINFO

#define CSR_TINFO   (0x7A4)

◆ CSR_TINFO_INFO_GET

#define CSR_TINFO_INFO_GET (   x)    (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT)

◆ CSR_TINFO_INFO_MASK

#define CSR_TINFO_INFO_MASK   (0xFFFFU)

◆ CSR_TINFO_INFO_SHIFT

#define CSR_TINFO_INFO_SHIFT   (0U)

◆ CSR_TSELECT

#define CSR_TSELECT   (0x7A0)

◆ CSR_TSELECT_TRIGGER_INDEX_GET

#define CSR_TSELECT_TRIGGER_INDEX_GET (   x)    (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT)

◆ CSR_TSELECT_TRIGGER_INDEX_MASK

#define CSR_TSELECT_TRIGGER_INDEX_MASK   (0xFFFFFFFFUL)

◆ CSR_TSELECT_TRIGGER_INDEX_SET

#define CSR_TSELECT_TRIGGER_INDEX_SET (   x)    (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK)

◆ CSR_TSELECT_TRIGGER_INDEX_SHIFT

#define CSR_TSELECT_TRIGGER_INDEX_SHIFT   (0U)

◆ CSR_UCAUSE

#define CSR_UCAUSE   (0x42)

◆ CSR_UCAUSE_EXCEPTION_CODE_GET

#define CSR_UCAUSE_EXCEPTION_CODE_GET (   x)    (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT)

◆ CSR_UCAUSE_EXCEPTION_CODE_MASK

#define CSR_UCAUSE_EXCEPTION_CODE_MASK   (0x3FFU)

◆ CSR_UCAUSE_EXCEPTION_CODE_SET

#define CSR_UCAUSE_EXCEPTION_CODE_SET (   x)    (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK)

◆ CSR_UCAUSE_EXCEPTION_CODE_SHIFT

#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT   (0U)

◆ CSR_UCAUSE_INTERRUPT_GET

#define CSR_UCAUSE_INTERRUPT_GET (   x)    (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT)

◆ CSR_UCAUSE_INTERRUPT_MASK

#define CSR_UCAUSE_INTERRUPT_MASK   (0x80000000UL)

◆ CSR_UCAUSE_INTERRUPT_SET

#define CSR_UCAUSE_INTERRUPT_SET (   x)    (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK)

◆ CSR_UCAUSE_INTERRUPT_SHIFT

#define CSR_UCAUSE_INTERRUPT_SHIFT   (31U)

◆ CSR_UCCTLBEGINADDR

#define CSR_UCCTLBEGINADDR   (0x80B)

◆ CSR_UCCTLBEGINADDR_VA_GET

#define CSR_UCCTLBEGINADDR_VA_GET (   x)    (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT)

◆ CSR_UCCTLBEGINADDR_VA_MASK

#define CSR_UCCTLBEGINADDR_VA_MASK   (0xFFFFFFFFUL)

◆ CSR_UCCTLBEGINADDR_VA_SET

#define CSR_UCCTLBEGINADDR_VA_SET (   x)    (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK)

◆ CSR_UCCTLBEGINADDR_VA_SHIFT

#define CSR_UCCTLBEGINADDR_VA_SHIFT   (0U)

◆ CSR_UCCTLCOMMAND

#define CSR_UCCTLCOMMAND   (0x80C)

◆ CSR_UCCTLCOMMAND_VA_GET

#define CSR_UCCTLCOMMAND_VA_GET (   x)    (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT)

◆ CSR_UCCTLCOMMAND_VA_MASK

#define CSR_UCCTLCOMMAND_VA_MASK   (0x1FU)

◆ CSR_UCCTLCOMMAND_VA_SET

#define CSR_UCCTLCOMMAND_VA_SET (   x)    (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK)

◆ CSR_UCCTLCOMMAND_VA_SHIFT

#define CSR_UCCTLCOMMAND_VA_SHIFT   (0U)

◆ CSR_UCODE

#define CSR_UCODE   (0x801)

◆ CSR_UCODE_OV_GET

#define CSR_UCODE_OV_GET (   x)    (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT)

◆ CSR_UCODE_OV_MASK

#define CSR_UCODE_OV_MASK   (0x1U)

◆ CSR_UCODE_OV_SET

#define CSR_UCODE_OV_SET (   x)    (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK)

◆ CSR_UCODE_OV_SHIFT

#define CSR_UCODE_OV_SHIFT   (0U)

◆ CSR_UDCAUSE

#define CSR_UDCAUSE   (0x809)

◆ CSR_UDCAUSE_UDCAUSE_GET

#define CSR_UDCAUSE_UDCAUSE_GET (   x)    (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT)

◆ CSR_UDCAUSE_UDCAUSE_MASK

#define CSR_UDCAUSE_UDCAUSE_MASK   (0x7U)

◆ CSR_UDCAUSE_UDCAUSE_SET

#define CSR_UDCAUSE_UDCAUSE_SET (   x)    (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK)

◆ CSR_UDCAUSE_UDCAUSE_SHIFT

#define CSR_UDCAUSE_UDCAUSE_SHIFT   (0U)

◆ CSR_UEPC

#define CSR_UEPC   (0x41)

◆ CSR_UEPC_EPC_GET

#define CSR_UEPC_EPC_GET (   x)    (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT)

◆ CSR_UEPC_EPC_MASK

#define CSR_UEPC_EPC_MASK   (0xFFFFFFFEUL)

◆ CSR_UEPC_EPC_SET

#define CSR_UEPC_EPC_SET (   x)    (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK)

◆ CSR_UEPC_EPC_SHIFT

#define CSR_UEPC_EPC_SHIFT   (1U)

◆ CSR_UIE

#define CSR_UIE   (0x4)

◆ CSR_UIE_UEIE_GET

#define CSR_UIE_UEIE_GET (   x)    (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT)

◆ CSR_UIE_UEIE_MASK

#define CSR_UIE_UEIE_MASK   (0x100U)

◆ CSR_UIE_UEIE_SET

#define CSR_UIE_UEIE_SET (   x)    (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK)

◆ CSR_UIE_UEIE_SHIFT

#define CSR_UIE_UEIE_SHIFT   (8U)

◆ CSR_UIE_USIE_GET

#define CSR_UIE_USIE_GET (   x)    (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT)

◆ CSR_UIE_USIE_MASK

#define CSR_UIE_USIE_MASK   (0x1U)

◆ CSR_UIE_USIE_SET

#define CSR_UIE_USIE_SET (   x)    (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK)

◆ CSR_UIE_USIE_SHIFT

#define CSR_UIE_USIE_SHIFT   (0U)

◆ CSR_UIE_UTIE_GET

#define CSR_UIE_UTIE_GET (   x)    (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT)

◆ CSR_UIE_UTIE_MASK

#define CSR_UIE_UTIE_MASK   (0x10U)

◆ CSR_UIE_UTIE_SET

#define CSR_UIE_UTIE_SET (   x)    (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK)

◆ CSR_UIE_UTIE_SHIFT

#define CSR_UIE_UTIE_SHIFT   (4U)

◆ CSR_UIP

#define CSR_UIP   (0x44)

◆ CSR_UIP_UEIP_GET

#define CSR_UIP_UEIP_GET (   x)    (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT)

◆ CSR_UIP_UEIP_MASK

#define CSR_UIP_UEIP_MASK   (0x100U)

◆ CSR_UIP_UEIP_SET

#define CSR_UIP_UEIP_SET (   x)    (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK)

◆ CSR_UIP_UEIP_SHIFT

#define CSR_UIP_UEIP_SHIFT   (8U)

◆ CSR_UIP_USIP_GET

#define CSR_UIP_USIP_GET (   x)    (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT)

◆ CSR_UIP_USIP_MASK

#define CSR_UIP_USIP_MASK   (0x1U)

◆ CSR_UIP_USIP_SET

#define CSR_UIP_USIP_SET (   x)    (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK)

◆ CSR_UIP_USIP_SHIFT

#define CSR_UIP_USIP_SHIFT   (0U)

◆ CSR_UIP_UTIP_GET

#define CSR_UIP_UTIP_GET (   x)    (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT)

◆ CSR_UIP_UTIP_MASK

#define CSR_UIP_UTIP_MASK   (0x10U)

◆ CSR_UIP_UTIP_SET

#define CSR_UIP_UTIP_SET (   x)    (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK)

◆ CSR_UIP_UTIP_SHIFT

#define CSR_UIP_UTIP_SHIFT   (4U)

◆ CSR_UITB

#define CSR_UITB   (0x800)

◆ CSR_UITB_ADDR_GET

#define CSR_UITB_ADDR_GET (   x)    (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT)

◆ CSR_UITB_ADDR_MASK

#define CSR_UITB_ADDR_MASK   (0xFFFFFFFCUL)

◆ CSR_UITB_ADDR_SET

#define CSR_UITB_ADDR_SET (   x)    (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK)

◆ CSR_UITB_ADDR_SHIFT

#define CSR_UITB_ADDR_SHIFT   (2U)

◆ CSR_UITB_HW_GET

#define CSR_UITB_HW_GET (   x)    (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT)

◆ CSR_UITB_HW_MASK

#define CSR_UITB_HW_MASK   (0x1U)

◆ CSR_UITB_HW_SHIFT

#define CSR_UITB_HW_SHIFT   (0U)

◆ CSR_USCRATCH

#define CSR_USCRATCH   (0x40)

◆ CSR_USCRATCH_USCRATCH_GET

#define CSR_USCRATCH_USCRATCH_GET (   x)    (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT)

◆ CSR_USCRATCH_USCRATCH_MASK

#define CSR_USCRATCH_USCRATCH_MASK   (0xFFFFFFFFUL)

◆ CSR_USCRATCH_USCRATCH_SET

#define CSR_USCRATCH_USCRATCH_SET (   x)    (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK)

◆ CSR_USCRATCH_USCRATCH_SHIFT

#define CSR_USCRATCH_USCRATCH_SHIFT   (0U)

◆ CSR_USTATUS

#define CSR_USTATUS   (0x0)

◆ CSR_USTATUS_UIE_GET

#define CSR_USTATUS_UIE_GET (   x)    (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT)

◆ CSR_USTATUS_UIE_MASK

#define CSR_USTATUS_UIE_MASK   (0x1U)

◆ CSR_USTATUS_UIE_SET

#define CSR_USTATUS_UIE_SET (   x)    (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK)

◆ CSR_USTATUS_UIE_SHIFT

#define CSR_USTATUS_UIE_SHIFT   (0U)

◆ CSR_USTATUS_UPIE_GET

#define CSR_USTATUS_UPIE_GET (   x)    (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT)

◆ CSR_USTATUS_UPIE_MASK

#define CSR_USTATUS_UPIE_MASK   (0x10U)

◆ CSR_USTATUS_UPIE_SET

#define CSR_USTATUS_UPIE_SET (   x)    (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK)

◆ CSR_USTATUS_UPIE_SHIFT

#define CSR_USTATUS_UPIE_SHIFT   (4U)

◆ CSR_UTVAL

#define CSR_UTVAL   (0x43)

◆ CSR_UTVAL_UTVAL_GET

#define CSR_UTVAL_UTVAL_GET (   x)    (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT)

◆ CSR_UTVAL_UTVAL_MASK

#define CSR_UTVAL_UTVAL_MASK   (0xFFFFFFFFUL)

◆ CSR_UTVAL_UTVAL_SET

#define CSR_UTVAL_UTVAL_SET (   x)    (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK)

◆ CSR_UTVAL_UTVAL_SHIFT

#define CSR_UTVAL_UTVAL_SHIFT   (0U)

◆ CSR_UTVEC

#define CSR_UTVEC   (0x5)

◆ CSR_UTVEC_BASE_31_2_GET

#define CSR_UTVEC_BASE_31_2_GET (   x)    (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT)

◆ CSR_UTVEC_BASE_31_2_MASK

#define CSR_UTVEC_BASE_31_2_MASK   (0xFFFFFFFCUL)

◆ CSR_UTVEC_BASE_31_2_SET

#define CSR_UTVEC_BASE_31_2_SET (   x)    (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK)

◆ CSR_UTVEC_BASE_31_2_SHIFT

#define CSR_UTVEC_BASE_31_2_SHIFT   (2U)