HPM SDK
HPMicro Software Development Kit
hpm_acmp_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_ACMP_H
10 #define HPM_ACMP_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t CFG; /* 0x0: Configure Register */
15  __RW uint32_t DACCFG; /* 0x4: DAC configure register */
16  __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */
17  __RW uint32_t SR; /* 0x10: Status register */
18  __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */
19  __RW uint32_t DMAEN; /* 0x18: DMA request enable register */
20  __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */
21  } CHANNEL[2];
22 } ACMP_Type;
23 
24 
25 /* Bitfield definition for register of struct array CHANNEL: CFG */
26 /*
27  * HYST (RW)
28  *
29  * This bitfield configure the comparator hysteresis.
30  * 00: Hysteresis level 0
31  * 01: Hysteresis level 1
32  * 10: Hysteresis level 2
33  * 11: Hysteresis level 3
34  */
35 #define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL)
36 #define ACMP_CHANNEL_CFG_HYST_SHIFT (30U)
37 #define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK)
38 #define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT)
39 
40 /*
41  * DACEN (RW)
42  *
43  * This bit enable the comparator internal DAC
44  * 0: DAC disabled
45  * 1: DAC enabled
46  */
47 #define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL)
48 #define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U)
49 #define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK)
50 #define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT)
51 
52 /*
53  * HPMODE (RW)
54  *
55  * This bit enable the comparator high performance mode.
56  * 0: HP mode disabled
57  * 1: HP mode enabled
58  */
59 #define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL)
60 #define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U)
61 #define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK)
62 #define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT)
63 
64 /*
65  * CMPEN (RW)
66  *
67  * This bit enable the comparator.
68  * 0: ACMP disabled
69  * 1: ACMP enabled
70  */
71 #define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL)
72 #define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U)
73 #define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK)
74 #define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT)
75 
76 /*
77  * MINSEL (RW)
78  *
79  * PIN select, from pad_ai_acmp[7:1] and dac_out
80  */
81 #define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL)
82 #define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U)
83 #define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK)
84 #define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT)
85 
86 /*
87  * DAC_TRIG_EN (RW)
88  *
89  * if set, the dac value is from moto system when valid
90  * if clr, use dac_cfg value
91  */
92 #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK (0x800000UL)
93 #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT (23U)
94 #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK)
95 #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) >> ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT)
96 
97 /*
98  * PINSEL (RW)
99  *
100  * MIN select, from pad_ai_acmp[7:1] and dac_out
101  */
102 #define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL)
103 #define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U)
104 #define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK)
105 #define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT)
106 
107 /*
108  * CMPOEN (RW)
109  *
110  * This bit enable the comparator output on pad.
111  * 0: ACMP output disabled
112  * 1: ACMP output enabled
113  */
114 #define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL)
115 #define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U)
116 #define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK)
117 #define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT)
118 
119 /*
120  * FLTBYPS (RW)
121  *
122  * This bit bypass the comparator output digital filter.
123  * 0: The ACMP output need pass digital filter
124  * 1: The ACMP output digital filter is bypassed.
125  */
126 #define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL)
127 #define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U)
128 #define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK)
129 #define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT)
130 
131 /*
132  * WINEN (RW)
133  *
134  * This bit enable the comparator window mode.
135  * 0: Window mode is disabled
136  * 1: Window mode is enabled
137  */
138 #define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL)
139 #define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U)
140 #define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK)
141 #define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT)
142 
143 /*
144  * OPOL (RW)
145  *
146  * The output polarity control bit.
147  * 0: The ACMP output remain un-changed.
148  * 1: The ACMP output is inverted.
149  */
150 #define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL)
151 #define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U)
152 #define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK)
153 #define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT)
154 
155 /*
156  * FLTMODE (RW)
157  *
158  * This bitfield define the ACMP output digital filter mode:
159  * 000-bypass
160  * 100-change immediately;
161  * 101-change after filter;
162  * 110-stalbe low;
163  * 111-stable high
164  */
165 #define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U)
166 #define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U)
167 #define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK)
168 #define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT)
169 
170 /*
171  * SYNCEN (RW)
172  *
173  * This bit enable the comparator output synchronization.
174  * 0: ACMP output not synchronized with ACMP clock.
175  * 1: ACMP output synchronized with ACMP clock.
176  */
177 #define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U)
178 #define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U)
179 #define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK)
180 #define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT)
181 
182 /*
183  * FLTLEN (RW)
184  *
185  * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle.
186  */
187 #define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU)
188 #define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U)
189 #define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK)
190 #define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT)
191 
192 /* Bitfield definition for register of struct array CHANNEL: DACCFG */
193 /*
194  * DACCFG (RW)
195  *
196  * 8bit DAC digital value output to analog block
197  */
198 #define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU)
199 #define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U)
200 #define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK)
201 #define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT)
202 
203 /* Bitfield definition for register of struct array CHANNEL: SR */
204 /*
205  * FEDGF (RW)
206  *
207  * Output falling edge flag. Write 1 to clear this flag.
208  */
209 #define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U)
210 #define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U)
211 #define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK)
212 #define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT)
213 
214 /*
215  * REDGF (RW)
216  *
217  * Output rising edge flag. Write 1 to clear this flag.
218  */
219 #define ACMP_CHANNEL_SR_REDGF_MASK (0x1U)
220 #define ACMP_CHANNEL_SR_REDGF_SHIFT (0U)
221 #define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK)
222 #define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT)
223 
224 /* Bitfield definition for register of struct array CHANNEL: IRQEN */
225 /*
226  * FEDGEN (RW)
227  *
228  * Output falling edge flag interrupt enable bit.
229  */
230 #define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U)
231 #define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U)
232 #define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK)
233 #define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT)
234 
235 /*
236  * REDGEN (RW)
237  *
238  * Output rising edge flag interrupt enable bit.
239  */
240 #define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U)
241 #define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U)
242 #define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK)
243 #define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT)
244 
245 /* Bitfield definition for register of struct array CHANNEL: DMAEN */
246 /*
247  * FEDGEN (RW)
248  *
249  * Output falling edge flag DMA request enable bit.
250  */
251 #define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U)
252 #define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U)
253 #define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK)
254 #define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT)
255 
256 /*
257  * REDGEN (RW)
258  *
259  * Output rising edge flag DMA request enable bit.
260  */
261 #define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U)
262 #define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U)
263 #define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK)
264 #define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT)
265 
266 
267 
268 /* CHANNEL register group index macro definition */
269 #define ACMP_CHANNEL_CHN0 (0UL)
270 #define ACMP_CHANNEL_CHN1 (1UL)
271 
272 
273 #endif /* HPM_ACMP_H */
ACMP_Type
Definition: hpm_acmp_regs.h:12