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Data Structures | |
| struct | ACMP_Type |
| #define ACMP_CHANNEL_CFG_CMPEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) |
| #define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) |
| #define ACMP_CHANNEL_CFG_CMPEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) |
| #define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) |
| #define ACMP_CHANNEL_CFG_CMPOEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) |
| #define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) |
| #define ACMP_CHANNEL_CFG_CMPOEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) |
| #define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) |
| #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) >> ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) |
| #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK (0x800000UL) |
| #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) |
| #define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT (23U) |
| #define ACMP_CHANNEL_CFG_DACEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) |
| #define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) |
| #define ACMP_CHANNEL_CFG_DACEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) |
| #define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) |
| #define ACMP_CHANNEL_CFG_FLTBYPS_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) |
| #define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) |
| #define ACMP_CHANNEL_CFG_FLTBYPS_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) |
| #define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) |
| #define ACMP_CHANNEL_CFG_FLTLEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) |
| #define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) |
| #define ACMP_CHANNEL_CFG_FLTLEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) |
| #define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) |
| #define ACMP_CHANNEL_CFG_FLTMODE_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) |
| #define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) |
| #define ACMP_CHANNEL_CFG_FLTMODE_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) |
| #define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) |
| #define ACMP_CHANNEL_CFG_HPMODE_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) |
| #define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) |
| #define ACMP_CHANNEL_CFG_HPMODE_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) |
| #define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) |
| #define ACMP_CHANNEL_CFG_HYST_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) |
| #define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) |
| #define ACMP_CHANNEL_CFG_HYST_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) |
| #define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) |
| #define ACMP_CHANNEL_CFG_MINSEL_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) |
| #define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) |
| #define ACMP_CHANNEL_CFG_MINSEL_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) |
| #define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) |
| #define ACMP_CHANNEL_CFG_OPOL_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) |
| #define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) |
| #define ACMP_CHANNEL_CFG_OPOL_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) |
| #define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) |
| #define ACMP_CHANNEL_CFG_PINSEL_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) |
| #define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) |
| #define ACMP_CHANNEL_CFG_PINSEL_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) |
| #define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) |
| #define ACMP_CHANNEL_CFG_SYNCEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) |
| #define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) |
| #define ACMP_CHANNEL_CFG_SYNCEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) |
| #define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) |
| #define ACMP_CHANNEL_CFG_WINEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) |
| #define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) |
| #define ACMP_CHANNEL_CFG_WINEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) |
| #define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) |
| #define ACMP_CHANNEL_CHN0 (0UL) |
| #define ACMP_CHANNEL_CHN1 (1UL) |
| #define ACMP_CHANNEL_DACCFG_DACCFG_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) |
| #define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) |
| #define ACMP_CHANNEL_DACCFG_DACCFG_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) |
| #define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) |
| #define ACMP_CHANNEL_DMAEN_FEDGEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) |
| #define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) |
| #define ACMP_CHANNEL_DMAEN_FEDGEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) |
| #define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) |
| #define ACMP_CHANNEL_DMAEN_REDGEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) |
| #define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) |
| #define ACMP_CHANNEL_DMAEN_REDGEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) |
| #define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) |
| #define ACMP_CHANNEL_IRQEN_FEDGEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) |
| #define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) |
| #define ACMP_CHANNEL_IRQEN_FEDGEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) |
| #define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) |
| #define ACMP_CHANNEL_IRQEN_REDGEN_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) |
| #define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) |
| #define ACMP_CHANNEL_IRQEN_REDGEN_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) |
| #define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) |
| #define ACMP_CHANNEL_SR_FEDGF_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) |
| #define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) |
| #define ACMP_CHANNEL_SR_FEDGF_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) |
| #define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) |
| #define ACMP_CHANNEL_SR_REDGF_GET | ( | x | ) | (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) |
| #define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) |
| #define ACMP_CHANNEL_SR_REDGF_SET | ( | x | ) | (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) |
| #define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) |