hpm_ewdg_regs.h File Reference

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Data Structures
struct	EWDG_Type

Macros
#define	EWDG_CTRL0_CLK_SEL_MASK   (0x20000000UL)
#define	EWDG_CTRL0_CLK_SEL_SHIFT   (29U)
#define	EWDG_CTRL0_CLK_SEL_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK)
#define	EWDG_CTRL0_CLK_SEL_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT)
#define	EWDG_CTRL0_DIV_VALUE_MASK   (0xE000000UL)
#define	EWDG_CTRL0_DIV_VALUE_SHIFT   (25U)
#define	EWDG_CTRL0_DIV_VALUE_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK)
#define	EWDG_CTRL0_DIV_VALUE_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT)
#define	EWDG_CTRL0_WIN_EN_MASK   (0x1000000UL)
#define	EWDG_CTRL0_WIN_EN_SHIFT   (24U)
#define	EWDG_CTRL0_WIN_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK)
#define	EWDG_CTRL0_WIN_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT)
#define	EWDG_CTRL0_WIN_LOWER_MASK   (0xC00000UL)
#define	EWDG_CTRL0_WIN_LOWER_SHIFT   (22U)
#define	EWDG_CTRL0_WIN_LOWER_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK)
#define	EWDG_CTRL0_WIN_LOWER_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT)
#define	EWDG_CTRL0_CFG_LOCK_MASK   (0x200000UL)
#define	EWDG_CTRL0_CFG_LOCK_SHIFT   (21U)
#define	EWDG_CTRL0_CFG_LOCK_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK)
#define	EWDG_CTRL0_CFG_LOCK_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT)
#define	EWDG_CTRL0_OT_SELF_CLEAR_MASK   (0x20000UL)
#define	EWDG_CTRL0_OT_SELF_CLEAR_SHIFT   (17U)
#define	EWDG_CTRL0_OT_SELF_CLEAR_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK)
#define	EWDG_CTRL0_OT_SELF_CLEAR_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT)
#define	EWDG_CTRL0_REF_OT_REQ_MASK   (0x8000U)
#define	EWDG_CTRL0_REF_OT_REQ_SHIFT   (15U)
#define	EWDG_CTRL0_REF_OT_REQ_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK)
#define	EWDG_CTRL0_REF_OT_REQ_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT)
#define	EWDG_CTRL0_WIN_UPPER_MASK   (0x7000U)
#define	EWDG_CTRL0_WIN_UPPER_SHIFT   (12U)
#define	EWDG_CTRL0_WIN_UPPER_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK)
#define	EWDG_CTRL0_WIN_UPPER_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT)
#define	EWDG_CTRL0_REF_LOCK_MASK   (0x20U)
#define	EWDG_CTRL0_REF_LOCK_SHIFT   (5U)
#define	EWDG_CTRL0_REF_LOCK_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK)
#define	EWDG_CTRL0_REF_LOCK_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT)
#define	EWDG_CTRL0_REF_UNLOCK_MEC_MASK   (0x18U)
#define	EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT   (3U)
#define	EWDG_CTRL0_REF_UNLOCK_MEC_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK)
#define	EWDG_CTRL0_REF_UNLOCK_MEC_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT)
#define	EWDG_CTRL0_EN_DBG_MASK   (0x4U)
#define	EWDG_CTRL0_EN_DBG_SHIFT   (2U)
#define	EWDG_CTRL0_EN_DBG_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK)
#define	EWDG_CTRL0_EN_DBG_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT)
#define	EWDG_CTRL0_EN_LP_MASK   (0x3U)
#define	EWDG_CTRL0_EN_LP_SHIFT   (0U)
#define	EWDG_CTRL0_EN_LP_SET(x)   (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK)
#define	EWDG_CTRL0_EN_LP_GET(x)   (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT)
#define	EWDG_CTRL1_REF_FAIL_RST_EN_MASK   (0x800000UL)
#define	EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT   (23U)
#define	EWDG_CTRL1_REF_FAIL_RST_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK)
#define	EWDG_CTRL1_REF_FAIL_RST_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT)
#define	EWDG_CTRL1_REF_FAIL_INT_EN_MASK   (0x400000UL)
#define	EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT   (22U)
#define	EWDG_CTRL1_REF_FAIL_INT_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK)
#define	EWDG_CTRL1_REF_FAIL_INT_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT)
#define	EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK   (0x200000UL)
#define	EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT   (21U)
#define	EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK)
#define	EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT)
#define	EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK   (0x100000UL)
#define	EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT   (20U)
#define	EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK)
#define	EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT)
#define	EWDG_CTRL1_OT_RST_EN_MASK   (0x20000UL)
#define	EWDG_CTRL1_OT_RST_EN_SHIFT   (17U)
#define	EWDG_CTRL1_OT_RST_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK)
#define	EWDG_CTRL1_OT_RST_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT)
#define	EWDG_CTRL1_OT_INT_EN_MASK   (0x10000UL)
#define	EWDG_CTRL1_OT_INT_EN_SHIFT   (16U)
#define	EWDG_CTRL1_OT_INT_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK)
#define	EWDG_CTRL1_OT_INT_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT)
#define	EWDG_CTRL1_CTL_VIO_RST_EN_MASK   (0x80U)
#define	EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT   (7U)
#define	EWDG_CTRL1_CTL_VIO_RST_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK)
#define	EWDG_CTRL1_CTL_VIO_RST_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT)
#define	EWDG_CTRL1_CTL_VIO_INT_EN_MASK   (0x40U)
#define	EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT   (6U)
#define	EWDG_CTRL1_CTL_VIO_INT_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK)
#define	EWDG_CTRL1_CTL_VIO_INT_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT)
#define	EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK   (0x20U)
#define	EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT   (5U)
#define	EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK)
#define	EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT)
#define	EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK   (0x10U)
#define	EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT   (4U)
#define	EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK)
#define	EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT)
#define	EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK   (0x8U)
#define	EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT   (3U)
#define	EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK)
#define	EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT)
#define	EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK   (0x4U)
#define	EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT   (2U)
#define	EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x)   (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK)
#define	EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x)   (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT)
#define	EWDG_OT_INT_VAL_OT_INT_VAL_MASK   (0xFFFFU)
#define	EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT   (0U)
#define	EWDG_OT_INT_VAL_OT_INT_VAL_SET(x)   (((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK)
#define	EWDG_OT_INT_VAL_OT_INT_VAL_GET(x)   (((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT)
#define	EWDG_OT_RST_VAL_OT_RST_VAL_MASK   (0xFFFFU)
#define	EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT   (0U)
#define	EWDG_OT_RST_VAL_OT_RST_VAL_SET(x)   (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK)
#define	EWDG_OT_RST_VAL_OT_RST_VAL_GET(x)   (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT)
#define	EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK   (0xFFFFFFFFUL)
#define	EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT   (0U)
#define	EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x)   (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK)
#define	EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x)   (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT)
#define	EWDG_WDT_STATUS_PARITY_ERROR_MASK   (0x40U)
#define	EWDG_WDT_STATUS_PARITY_ERROR_SHIFT   (6U)
#define	EWDG_WDT_STATUS_PARITY_ERROR_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK)
#define	EWDG_WDT_STATUS_PARITY_ERROR_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT)
#define	EWDG_WDT_STATUS_OT_RST_MASK   (0x20U)
#define	EWDG_WDT_STATUS_OT_RST_SHIFT   (5U)
#define	EWDG_WDT_STATUS_OT_RST_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_OT_RST_SHIFT) & EWDG_WDT_STATUS_OT_RST_MASK)
#define	EWDG_WDT_STATUS_OT_RST_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT)
#define	EWDG_WDT_STATUS_OT_INT_MASK   (0x10U)
#define	EWDG_WDT_STATUS_OT_INT_SHIFT   (4U)
#define	EWDG_WDT_STATUS_OT_INT_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_OT_INT_SHIFT) & EWDG_WDT_STATUS_OT_INT_MASK)
#define	EWDG_WDT_STATUS_OT_INT_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT)
#define	EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK   (0x8U)
#define	EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT   (3U)
#define	EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK)
#define	EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT)
#define	EWDG_WDT_STATUS_CTL_VIO_MASK   (0x4U)
#define	EWDG_WDT_STATUS_CTL_VIO_SHIFT   (2U)
#define	EWDG_WDT_STATUS_CTL_VIO_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK)
#define	EWDG_WDT_STATUS_CTL_VIO_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT)
#define	EWDG_WDT_STATUS_REF_UNL_FAIL_MASK   (0x2U)
#define	EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT   (1U)
#define	EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK)
#define	EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT)
#define	EWDG_WDT_STATUS_REF_VIO_MASK   (0x1U)
#define	EWDG_WDT_STATUS_REF_VIO_SHIFT   (0U)
#define	EWDG_WDT_STATUS_REF_VIO_SET(x)   (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK)
#define	EWDG_WDT_STATUS_REF_VIO_GET(x)   (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT)
#define	EWDG_CFG_PROT_UPD_OT_TIME_MASK   (0xF0000UL)
#define	EWDG_CFG_PROT_UPD_OT_TIME_SHIFT   (16U)
#define	EWDG_CFG_PROT_UPD_OT_TIME_SET(x)   (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK)
#define	EWDG_CFG_PROT_UPD_OT_TIME_GET(x)   (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT)
#define	EWDG_CFG_PROT_UPD_PSD_MASK   (0xFFFFU)
#define	EWDG_CFG_PROT_UPD_PSD_SHIFT   (0U)
#define	EWDG_CFG_PROT_UPD_PSD_SET(x)   (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK)
#define	EWDG_CFG_PROT_UPD_PSD_GET(x)   (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT)
#define	EWDG_REF_PROT_REF_UNL_PSD_MASK   (0xFFFFU)
#define	EWDG_REF_PROT_REF_UNL_PSD_SHIFT   (0U)
#define	EWDG_REF_PROT_REF_UNL_PSD_SET(x)   (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK)
#define	EWDG_REF_PROT_REF_UNL_PSD_GET(x)   (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT)
#define	EWDG_WDT_EN_WDOG_EN_MASK   (0x1U)
#define	EWDG_WDT_EN_WDOG_EN_SHIFT   (0U)
#define	EWDG_WDT_EN_WDOG_EN_SET(x)   (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK)
#define	EWDG_WDT_EN_WDOG_EN_GET(x)   (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT)
#define	EWDG_REF_TIME_REFRESH_PERIOD_MASK   (0xFFFFU)
#define	EWDG_REF_TIME_REFRESH_PERIOD_SHIFT   (0U)
#define	EWDG_REF_TIME_REFRESH_PERIOD_SET(x)   (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK)
#define	EWDG_REF_TIME_REFRESH_PERIOD_GET(x)   (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT)

Macro Definition Documentation

EWDG_CFG_PROT_UPD_OT_TIME_GET

#define EWDG_CFG_PROT_UPD_OT_TIME_GET

(

x

)

(((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT)

EWDG_CFG_PROT_UPD_OT_TIME_MASK

#define EWDG_CFG_PROT_UPD_OT_TIME_MASK   (0xF0000UL)

EWDG_CFG_PROT_UPD_OT_TIME_SET

#define EWDG_CFG_PROT_UPD_OT_TIME_SET

(

x

)

(((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK)

EWDG_CFG_PROT_UPD_OT_TIME_SHIFT

#define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT   (16U)

EWDG_CFG_PROT_UPD_PSD_GET

#define EWDG_CFG_PROT_UPD_PSD_GET

(

x

)

(((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT)

EWDG_CFG_PROT_UPD_PSD_MASK

#define EWDG_CFG_PROT_UPD_PSD_MASK   (0xFFFFU)

EWDG_CFG_PROT_UPD_PSD_SET

#define EWDG_CFG_PROT_UPD_PSD_SET

(

x

)

(((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK)

EWDG_CFG_PROT_UPD_PSD_SHIFT

#define EWDG_CFG_PROT_UPD_PSD_SHIFT   (0U)

EWDG_CTRL0_CFG_LOCK_GET

#define EWDG_CTRL0_CFG_LOCK_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT)

EWDG_CTRL0_CFG_LOCK_MASK

#define EWDG_CTRL0_CFG_LOCK_MASK   (0x200000UL)

EWDG_CTRL0_CFG_LOCK_SET

#define EWDG_CTRL0_CFG_LOCK_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK)

EWDG_CTRL0_CFG_LOCK_SHIFT

#define EWDG_CTRL0_CFG_LOCK_SHIFT   (21U)

EWDG_CTRL0_CLK_SEL_GET

#define EWDG_CTRL0_CLK_SEL_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT)

EWDG_CTRL0_CLK_SEL_MASK

#define EWDG_CTRL0_CLK_SEL_MASK   (0x20000000UL)

EWDG_CTRL0_CLK_SEL_SET

#define EWDG_CTRL0_CLK_SEL_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK)

EWDG_CTRL0_CLK_SEL_SHIFT

#define EWDG_CTRL0_CLK_SEL_SHIFT   (29U)

EWDG_CTRL0_DIV_VALUE_GET

#define EWDG_CTRL0_DIV_VALUE_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT)

EWDG_CTRL0_DIV_VALUE_MASK

#define EWDG_CTRL0_DIV_VALUE_MASK   (0xE000000UL)

EWDG_CTRL0_DIV_VALUE_SET

#define EWDG_CTRL0_DIV_VALUE_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK)

EWDG_CTRL0_DIV_VALUE_SHIFT

#define EWDG_CTRL0_DIV_VALUE_SHIFT   (25U)

EWDG_CTRL0_EN_DBG_GET

#define EWDG_CTRL0_EN_DBG_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT)

EWDG_CTRL0_EN_DBG_MASK

#define EWDG_CTRL0_EN_DBG_MASK   (0x4U)

EWDG_CTRL0_EN_DBG_SET

#define EWDG_CTRL0_EN_DBG_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK)

EWDG_CTRL0_EN_DBG_SHIFT

#define EWDG_CTRL0_EN_DBG_SHIFT   (2U)

EWDG_CTRL0_EN_LP_GET

#define EWDG_CTRL0_EN_LP_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT)

EWDG_CTRL0_EN_LP_MASK

#define EWDG_CTRL0_EN_LP_MASK   (0x3U)

EWDG_CTRL0_EN_LP_SET

#define EWDG_CTRL0_EN_LP_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK)

EWDG_CTRL0_EN_LP_SHIFT

#define EWDG_CTRL0_EN_LP_SHIFT   (0U)

EWDG_CTRL0_OT_SELF_CLEAR_GET

#define EWDG_CTRL0_OT_SELF_CLEAR_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT)

EWDG_CTRL0_OT_SELF_CLEAR_MASK

#define EWDG_CTRL0_OT_SELF_CLEAR_MASK   (0x20000UL)

EWDG_CTRL0_OT_SELF_CLEAR_SET

#define EWDG_CTRL0_OT_SELF_CLEAR_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK)

EWDG_CTRL0_OT_SELF_CLEAR_SHIFT

#define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT   (17U)

EWDG_CTRL0_REF_LOCK_GET

#define EWDG_CTRL0_REF_LOCK_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT)

EWDG_CTRL0_REF_LOCK_MASK

#define EWDG_CTRL0_REF_LOCK_MASK   (0x20U)

EWDG_CTRL0_REF_LOCK_SET

#define EWDG_CTRL0_REF_LOCK_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK)

EWDG_CTRL0_REF_LOCK_SHIFT

#define EWDG_CTRL0_REF_LOCK_SHIFT   (5U)

EWDG_CTRL0_REF_OT_REQ_GET

#define EWDG_CTRL0_REF_OT_REQ_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT)

EWDG_CTRL0_REF_OT_REQ_MASK

#define EWDG_CTRL0_REF_OT_REQ_MASK   (0x8000U)

EWDG_CTRL0_REF_OT_REQ_SET

#define EWDG_CTRL0_REF_OT_REQ_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK)

EWDG_CTRL0_REF_OT_REQ_SHIFT

#define EWDG_CTRL0_REF_OT_REQ_SHIFT   (15U)

EWDG_CTRL0_REF_UNLOCK_MEC_GET

#define EWDG_CTRL0_REF_UNLOCK_MEC_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT)

EWDG_CTRL0_REF_UNLOCK_MEC_MASK

#define EWDG_CTRL0_REF_UNLOCK_MEC_MASK   (0x18U)

EWDG_CTRL0_REF_UNLOCK_MEC_SET

#define EWDG_CTRL0_REF_UNLOCK_MEC_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK)

EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT

#define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT   (3U)

EWDG_CTRL0_WIN_EN_GET

#define EWDG_CTRL0_WIN_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT)

EWDG_CTRL0_WIN_EN_MASK

#define EWDG_CTRL0_WIN_EN_MASK   (0x1000000UL)

EWDG_CTRL0_WIN_EN_SET

#define EWDG_CTRL0_WIN_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK)

EWDG_CTRL0_WIN_EN_SHIFT

#define EWDG_CTRL0_WIN_EN_SHIFT   (24U)

EWDG_CTRL0_WIN_LOWER_GET

#define EWDG_CTRL0_WIN_LOWER_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT)

EWDG_CTRL0_WIN_LOWER_MASK

#define EWDG_CTRL0_WIN_LOWER_MASK   (0xC00000UL)

EWDG_CTRL0_WIN_LOWER_SET

#define EWDG_CTRL0_WIN_LOWER_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK)

EWDG_CTRL0_WIN_LOWER_SHIFT

#define EWDG_CTRL0_WIN_LOWER_SHIFT   (22U)

EWDG_CTRL0_WIN_UPPER_GET

#define EWDG_CTRL0_WIN_UPPER_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT)

EWDG_CTRL0_WIN_UPPER_MASK

#define EWDG_CTRL0_WIN_UPPER_MASK   (0x7000U)

EWDG_CTRL0_WIN_UPPER_SET

#define EWDG_CTRL0_WIN_UPPER_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK)

EWDG_CTRL0_WIN_UPPER_SHIFT

#define EWDG_CTRL0_WIN_UPPER_SHIFT   (12U)

EWDG_CTRL1_CTL_VIO_INT_EN_GET

#define EWDG_CTRL1_CTL_VIO_INT_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT)

EWDG_CTRL1_CTL_VIO_INT_EN_MASK

#define EWDG_CTRL1_CTL_VIO_INT_EN_MASK   (0x40U)

EWDG_CTRL1_CTL_VIO_INT_EN_SET

#define EWDG_CTRL1_CTL_VIO_INT_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK)

EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT

#define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT   (6U)

EWDG_CTRL1_CTL_VIO_RST_EN_GET

#define EWDG_CTRL1_CTL_VIO_RST_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT)

EWDG_CTRL1_CTL_VIO_RST_EN_MASK

#define EWDG_CTRL1_CTL_VIO_RST_EN_MASK   (0x80U)

EWDG_CTRL1_CTL_VIO_RST_EN_SET

#define EWDG_CTRL1_CTL_VIO_RST_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK)

EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT

#define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT   (7U)

EWDG_CTRL1_OT_INT_EN_GET

#define EWDG_CTRL1_OT_INT_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT)

EWDG_CTRL1_OT_INT_EN_MASK

#define EWDG_CTRL1_OT_INT_EN_MASK   (0x10000UL)

EWDG_CTRL1_OT_INT_EN_SET

#define EWDG_CTRL1_OT_INT_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK)

EWDG_CTRL1_OT_INT_EN_SHIFT

#define EWDG_CTRL1_OT_INT_EN_SHIFT   (16U)

EWDG_CTRL1_OT_RST_EN_GET

#define EWDG_CTRL1_OT_RST_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT)

EWDG_CTRL1_OT_RST_EN_MASK

#define EWDG_CTRL1_OT_RST_EN_MASK   (0x20000UL)

EWDG_CTRL1_OT_RST_EN_SET

#define EWDG_CTRL1_OT_RST_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK)

EWDG_CTRL1_OT_RST_EN_SHIFT

#define EWDG_CTRL1_OT_RST_EN_SHIFT   (17U)

EWDG_CTRL1_PARITY_FAIL_INT_EN_GET

#define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT)

EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK

#define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK   (0x4U)

EWDG_CTRL1_PARITY_FAIL_INT_EN_SET

#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK)

EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT

#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT   (2U)

EWDG_CTRL1_PARITY_FAIL_RST_EN_GET

#define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT)

EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK

#define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK   (0x8U)

EWDG_CTRL1_PARITY_FAIL_RST_EN_SET

#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK)

EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT

#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT   (3U)

EWDG_CTRL1_REF_FAIL_INT_EN_GET

#define EWDG_CTRL1_REF_FAIL_INT_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT)

EWDG_CTRL1_REF_FAIL_INT_EN_MASK

#define EWDG_CTRL1_REF_FAIL_INT_EN_MASK   (0x400000UL)

EWDG_CTRL1_REF_FAIL_INT_EN_SET

#define EWDG_CTRL1_REF_FAIL_INT_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK)

EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT

#define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT   (22U)

EWDG_CTRL1_REF_FAIL_RST_EN_GET

#define EWDG_CTRL1_REF_FAIL_RST_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT)

EWDG_CTRL1_REF_FAIL_RST_EN_MASK

#define EWDG_CTRL1_REF_FAIL_RST_EN_MASK   (0x800000UL)

EWDG_CTRL1_REF_FAIL_RST_EN_SET

#define EWDG_CTRL1_REF_FAIL_RST_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK)

EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT

#define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT   (23U)

EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET

#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT)

EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK

#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK   (0x10U)

EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET

#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK)

EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT

#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT   (4U)

EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET

#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT)

EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK

#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK   (0x20U)

EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET

#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK)

EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT

#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT   (5U)

EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET

#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT)

EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK

#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK   (0x100000UL)

EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET

#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK)

EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT

#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT   (20U)

EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET

#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT)

EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK

#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK   (0x200000UL)

EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET

#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK)

EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT

#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT   (21U)

EWDG_OT_INT_VAL_OT_INT_VAL_GET

#define EWDG_OT_INT_VAL_OT_INT_VAL_GET

(

x

)

(((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT)

EWDG_OT_INT_VAL_OT_INT_VAL_MASK

#define EWDG_OT_INT_VAL_OT_INT_VAL_MASK   (0xFFFFU)

EWDG_OT_INT_VAL_OT_INT_VAL_SET

#define EWDG_OT_INT_VAL_OT_INT_VAL_SET

(

x

)

(((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK)

EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT

#define EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT   (0U)

EWDG_OT_RST_VAL_OT_RST_VAL_GET

#define EWDG_OT_RST_VAL_OT_RST_VAL_GET

(

x

)

(((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT)

EWDG_OT_RST_VAL_OT_RST_VAL_MASK

#define EWDG_OT_RST_VAL_OT_RST_VAL_MASK   (0xFFFFU)

EWDG_OT_RST_VAL_OT_RST_VAL_SET

#define EWDG_OT_RST_VAL_OT_RST_VAL_SET

(

x

)

(((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK)

EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT

#define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT   (0U)

EWDG_REF_PROT_REF_UNL_PSD_GET

#define EWDG_REF_PROT_REF_UNL_PSD_GET

(

x

)

(((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT)

EWDG_REF_PROT_REF_UNL_PSD_MASK

#define EWDG_REF_PROT_REF_UNL_PSD_MASK   (0xFFFFU)

EWDG_REF_PROT_REF_UNL_PSD_SET

#define EWDG_REF_PROT_REF_UNL_PSD_SET

(

x

)

(((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK)

EWDG_REF_PROT_REF_UNL_PSD_SHIFT

#define EWDG_REF_PROT_REF_UNL_PSD_SHIFT   (0U)

EWDG_REF_TIME_REFRESH_PERIOD_GET

#define EWDG_REF_TIME_REFRESH_PERIOD_GET

(

x

)

(((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT)

EWDG_REF_TIME_REFRESH_PERIOD_MASK

#define EWDG_REF_TIME_REFRESH_PERIOD_MASK   (0xFFFFU)

EWDG_REF_TIME_REFRESH_PERIOD_SET

#define EWDG_REF_TIME_REFRESH_PERIOD_SET

(

x

)

(((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK)

EWDG_REF_TIME_REFRESH_PERIOD_SHIFT

#define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT   (0U)

EWDG_WDT_EN_WDOG_EN_GET

#define EWDG_WDT_EN_WDOG_EN_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT)

EWDG_WDT_EN_WDOG_EN_MASK

#define EWDG_WDT_EN_WDOG_EN_MASK   (0x1U)

EWDG_WDT_EN_WDOG_EN_SET

#define EWDG_WDT_EN_WDOG_EN_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK)

EWDG_WDT_EN_WDOG_EN_SHIFT

#define EWDG_WDT_EN_WDOG_EN_SHIFT   (0U)

EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET

#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT)

EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK

#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK   (0xFFFFFFFFUL)

EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET

#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK)

EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT

#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT   (0U)

EWDG_WDT_STATUS_CTL_UNL_FAIL_GET

#define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT)

EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK

#define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK   (0x8U)

EWDG_WDT_STATUS_CTL_UNL_FAIL_SET

#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK)

EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT

#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT   (3U)

EWDG_WDT_STATUS_CTL_VIO_GET

#define EWDG_WDT_STATUS_CTL_VIO_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT)

EWDG_WDT_STATUS_CTL_VIO_MASK

#define EWDG_WDT_STATUS_CTL_VIO_MASK   (0x4U)

EWDG_WDT_STATUS_CTL_VIO_SET

#define EWDG_WDT_STATUS_CTL_VIO_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK)

EWDG_WDT_STATUS_CTL_VIO_SHIFT

#define EWDG_WDT_STATUS_CTL_VIO_SHIFT   (2U)

EWDG_WDT_STATUS_OT_INT_GET

#define EWDG_WDT_STATUS_OT_INT_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT)

EWDG_WDT_STATUS_OT_INT_MASK

#define EWDG_WDT_STATUS_OT_INT_MASK   (0x10U)

EWDG_WDT_STATUS_OT_INT_SET

#define EWDG_WDT_STATUS_OT_INT_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_OT_INT_SHIFT) & EWDG_WDT_STATUS_OT_INT_MASK)

EWDG_WDT_STATUS_OT_INT_SHIFT

#define EWDG_WDT_STATUS_OT_INT_SHIFT   (4U)

EWDG_WDT_STATUS_OT_RST_GET

#define EWDG_WDT_STATUS_OT_RST_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT)

EWDG_WDT_STATUS_OT_RST_MASK

#define EWDG_WDT_STATUS_OT_RST_MASK   (0x20U)

EWDG_WDT_STATUS_OT_RST_SET

#define EWDG_WDT_STATUS_OT_RST_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_OT_RST_SHIFT) & EWDG_WDT_STATUS_OT_RST_MASK)

EWDG_WDT_STATUS_OT_RST_SHIFT

#define EWDG_WDT_STATUS_OT_RST_SHIFT   (5U)

EWDG_WDT_STATUS_PARITY_ERROR_GET

#define EWDG_WDT_STATUS_PARITY_ERROR_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT)

EWDG_WDT_STATUS_PARITY_ERROR_MASK

#define EWDG_WDT_STATUS_PARITY_ERROR_MASK   (0x40U)

EWDG_WDT_STATUS_PARITY_ERROR_SET

#define EWDG_WDT_STATUS_PARITY_ERROR_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK)

EWDG_WDT_STATUS_PARITY_ERROR_SHIFT

#define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT   (6U)

EWDG_WDT_STATUS_REF_UNL_FAIL_GET

#define EWDG_WDT_STATUS_REF_UNL_FAIL_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT)

EWDG_WDT_STATUS_REF_UNL_FAIL_MASK

#define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK   (0x2U)

EWDG_WDT_STATUS_REF_UNL_FAIL_SET

#define EWDG_WDT_STATUS_REF_UNL_FAIL_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK)

EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT

#define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT   (1U)

EWDG_WDT_STATUS_REF_VIO_GET

#define EWDG_WDT_STATUS_REF_VIO_GET

(

x

)

(((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT)

EWDG_WDT_STATUS_REF_VIO_MASK

#define EWDG_WDT_STATUS_REF_VIO_MASK   (0x1U)

EWDG_WDT_STATUS_REF_VIO_SET

#define EWDG_WDT_STATUS_REF_VIO_SET

(

x

)

(((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK)

EWDG_WDT_STATUS_REF_VIO_SHIFT

#define EWDG_WDT_STATUS_REF_VIO_SHIFT   (0U)