hpm_pdgo_regs.h File Reference

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Data Structures
struct	PDGO_Type

Macros
#define	PDGO_DGO_TURNOFF_COUNTER_MASK   (0xFFFFFFFFUL)
#define	PDGO_DGO_TURNOFF_COUNTER_SHIFT   (0U)
#define	PDGO_DGO_TURNOFF_COUNTER_SET(x)   (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK)
#define	PDGO_DGO_TURNOFF_COUNTER_GET(x)   (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT)
#define	PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK   (0x80000000UL)
#define	PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT   (31U)
#define	PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x)   (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK)
#define	PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x)   (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT)
#define	PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK   (0x800000UL)
#define	PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT   (23U)
#define	PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x)   (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK)
#define	PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x)   (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT)
#define	PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK   (0x400000UL)
#define	PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT   (22U)
#define	PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x)   (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK)
#define	PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x)   (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT)
#define	PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK   (0x1FFU)
#define	PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT   (0U)
#define	PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x)   (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK)
#define	PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x)   (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT)
#define	PDGO_DGO_GPR00_GPR_MASK   (0xFFFFFFFFUL)
#define	PDGO_DGO_GPR00_GPR_SHIFT   (0U)
#define	PDGO_DGO_GPR00_GPR_SET(x)   (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK)
#define	PDGO_DGO_GPR00_GPR_GET(x)   (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT)
#define	PDGO_DGO_GPR01_GPR_MASK   (0xFFFFFFFFUL)
#define	PDGO_DGO_GPR01_GPR_SHIFT   (0U)
#define	PDGO_DGO_GPR01_GPR_SET(x)   (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK)
#define	PDGO_DGO_GPR01_GPR_GET(x)   (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT)
#define	PDGO_DGO_GPR02_GPR_MASK   (0xFFFFFFFFUL)
#define	PDGO_DGO_GPR02_GPR_SHIFT   (0U)
#define	PDGO_DGO_GPR02_GPR_SET(x)   (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK)
#define	PDGO_DGO_GPR02_GPR_GET(x)   (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT)
#define	PDGO_DGO_GPR03_GPR_MASK   (0xFFFFFFFFUL)
#define	PDGO_DGO_GPR03_GPR_SHIFT   (0U)
#define	PDGO_DGO_GPR03_GPR_SET(x)   (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK)
#define	PDGO_DGO_GPR03_GPR_GET(x)   (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT)
#define	PDGO_DGO_CTR0_RETENTION_MASK   (0x10000UL)
#define	PDGO_DGO_CTR0_RETENTION_SHIFT   (16U)
#define	PDGO_DGO_CTR0_RETENTION_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK)
#define	PDGO_DGO_CTR0_RETENTION_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT)
#define	PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK   (0x80000000UL)
#define	PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT   (31U)
#define	PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK)
#define	PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT)
#define	PDGO_DGO_CTR1_WAKEUP_EN_MASK   (0x10000UL)
#define	PDGO_DGO_CTR1_WAKEUP_EN_SHIFT   (16U)
#define	PDGO_DGO_CTR1_WAKEUP_EN_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK)
#define	PDGO_DGO_CTR1_WAKEUP_EN_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT)
#define	PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK   (0x1U)
#define	PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT   (0U)
#define	PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT)
#define	PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK   (0x1000000UL)
#define	PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT   (24U)
#define	PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK)
#define	PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT)
#define	PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK   (0x10000UL)
#define	PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT   (16U)
#define	PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK)
#define	PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT)
#define	PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK   (0xFFFFFFFFUL)
#define	PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT   (0U)
#define	PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK)
#define	PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT)
#define	PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK   (0x2U)
#define	PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT   (1U)
#define	PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK)
#define	PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT)
#define	PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK   (0x1U)
#define	PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT   (0U)
#define	PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x)   (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK)
#define	PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x)   (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT)

Macro Definition Documentation

PDGO_DGO_CTR0_RETENTION_GET

#define PDGO_DGO_CTR0_RETENTION_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT)

PDGO_DGO_CTR0_RETENTION_MASK

#define PDGO_DGO_CTR0_RETENTION_MASK   (0x10000UL)

PDGO_DGO_CTR0_RETENTION_SET

#define PDGO_DGO_CTR0_RETENTION_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK)

PDGO_DGO_CTR0_RETENTION_SHIFT

#define PDGO_DGO_CTR0_RETENTION_SHIFT   (16U)

PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET

#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT)

PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK

#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK   (0x80000000UL)

PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET

#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK)

PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT

#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT   (31U)

PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET

#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT)

PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK

#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK   (0x1U)

PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT

#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT   (0U)

PDGO_DGO_CTR1_WAKEUP_EN_GET

#define PDGO_DGO_CTR1_WAKEUP_EN_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT)

PDGO_DGO_CTR1_WAKEUP_EN_MASK

#define PDGO_DGO_CTR1_WAKEUP_EN_MASK   (0x10000UL)

PDGO_DGO_CTR1_WAKEUP_EN_SET

#define PDGO_DGO_CTR1_WAKEUP_EN_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK)

PDGO_DGO_CTR1_WAKEUP_EN_SHIFT

#define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT   (16U)

PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET

#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT)

PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK

#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK   (0x1000000UL)

PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET

#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK)

PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT

#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT   (24U)

PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET

#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT)

PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK

#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK   (0x10000UL)

PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET

#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK)

PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT

#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT   (16U)

PDGO_DGO_CTR3_WAKEUP_COUNTER_GET

#define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT)

PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK

#define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK   (0xFFFFFFFFUL)

PDGO_DGO_CTR3_WAKEUP_COUNTER_SET

#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK)

PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT

#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT   (0U)

PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET

#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT)

PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK

#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK   (0x2U)

PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET

#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK)

PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT

#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT   (1U)

PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET

#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT)

PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK

#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK   (0x1U)

PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET

#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK)

PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT

#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT   (0U)

PDGO_DGO_GPR00_GPR_GET

#define PDGO_DGO_GPR00_GPR_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT)

PDGO_DGO_GPR00_GPR_MASK

#define PDGO_DGO_GPR00_GPR_MASK   (0xFFFFFFFFUL)

PDGO_DGO_GPR00_GPR_SET

#define PDGO_DGO_GPR00_GPR_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK)

PDGO_DGO_GPR00_GPR_SHIFT

#define PDGO_DGO_GPR00_GPR_SHIFT   (0U)

PDGO_DGO_GPR01_GPR_GET

#define PDGO_DGO_GPR01_GPR_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT)

PDGO_DGO_GPR01_GPR_MASK

#define PDGO_DGO_GPR01_GPR_MASK   (0xFFFFFFFFUL)

PDGO_DGO_GPR01_GPR_SET

#define PDGO_DGO_GPR01_GPR_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK)

PDGO_DGO_GPR01_GPR_SHIFT

#define PDGO_DGO_GPR01_GPR_SHIFT   (0U)

PDGO_DGO_GPR02_GPR_GET

#define PDGO_DGO_GPR02_GPR_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT)

PDGO_DGO_GPR02_GPR_MASK

#define PDGO_DGO_GPR02_GPR_MASK   (0xFFFFFFFFUL)

PDGO_DGO_GPR02_GPR_SET

#define PDGO_DGO_GPR02_GPR_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK)

PDGO_DGO_GPR02_GPR_SHIFT

#define PDGO_DGO_GPR02_GPR_SHIFT   (0U)

PDGO_DGO_GPR03_GPR_GET

#define PDGO_DGO_GPR03_GPR_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT)

PDGO_DGO_GPR03_GPR_MASK

#define PDGO_DGO_GPR03_GPR_MASK   (0xFFFFFFFFUL)

PDGO_DGO_GPR03_GPR_SET

#define PDGO_DGO_GPR03_GPR_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK)

PDGO_DGO_GPR03_GPR_SHIFT

#define PDGO_DGO_GPR03_GPR_SHIFT   (0U)

PDGO_DGO_RC32K_CFG_CAP_TRIM_GET

#define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT)

PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK

#define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK   (0x1FFU)

PDGO_DGO_RC32K_CFG_CAP_TRIM_SET

#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK)

PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT

#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT   (0U)

PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET

#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT)

PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK

#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK   (0x400000UL)

PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET

#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK)

PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT

#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT   (22U)

PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET

#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT)

PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK

#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK   (0x800000UL)

PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET

#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK)

PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT

#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT   (23U)

PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET

#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT)

PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK

#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK   (0x80000000UL)

PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET

#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK)

PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT

#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT   (31U)

PDGO_DGO_TURNOFF_COUNTER_GET

#define PDGO_DGO_TURNOFF_COUNTER_GET

(

x

)

(((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT)

PDGO_DGO_TURNOFF_COUNTER_MASK

#define PDGO_DGO_TURNOFF_COUNTER_MASK   (0xFFFFFFFFUL)

PDGO_DGO_TURNOFF_COUNTER_SET

#define PDGO_DGO_TURNOFF_COUNTER_SET

(

x

)

(((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK)

PDGO_DGO_TURNOFF_COUNTER_SHIFT

#define PDGO_DGO_TURNOFF_COUNTER_SHIFT   (0U)