HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_pwm_regs.h File Reference

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Data Structures

struct  PWM_Type
 

Macros

#define PWM_UNLK_SHUNLK_MASK   (0xFFFFFFFFUL)
 
#define PWM_UNLK_SHUNLK_SHIFT   (0U)
 
#define PWM_UNLK_SHUNLK_SET(x)   (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK)
 
#define PWM_UNLK_SHUNLK_GET(x)   (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT)
 
#define PWM_STA_XSTA_MASK   (0xF0000000UL)
 
#define PWM_STA_XSTA_SHIFT   (28U)
 
#define PWM_STA_XSTA_SET(x)   (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK)
 
#define PWM_STA_XSTA_GET(x)   (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT)
 
#define PWM_STA_STA_MASK   (0xFFFFFF0UL)
 
#define PWM_STA_STA_SHIFT   (4U)
 
#define PWM_STA_STA_SET(x)   (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK)
 
#define PWM_STA_STA_GET(x)   (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT)
 
#define PWM_RLD_XRLD_MASK   (0xF0000000UL)
 
#define PWM_RLD_XRLD_SHIFT   (28U)
 
#define PWM_RLD_XRLD_SET(x)   (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK)
 
#define PWM_RLD_XRLD_GET(x)   (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT)
 
#define PWM_RLD_RLD_MASK   (0xFFFFFF0UL)
 
#define PWM_RLD_RLD_SHIFT   (4U)
 
#define PWM_RLD_RLD_SET(x)   (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK)
 
#define PWM_RLD_RLD_GET(x)   (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT)
 
#define PWM_CMP_XCMP_MASK   (0xF0000000UL)
 
#define PWM_CMP_XCMP_SHIFT   (28U)
 
#define PWM_CMP_XCMP_SET(x)   (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK)
 
#define PWM_CMP_XCMP_GET(x)   (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT)
 
#define PWM_CMP_CMP_MASK   (0xFFFFFF0UL)
 
#define PWM_CMP_CMP_SHIFT   (4U)
 
#define PWM_CMP_CMP_SET(x)   (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK)
 
#define PWM_CMP_CMP_GET(x)   (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT)
 
#define PWM_CMP_CMPHLF_MASK   (0x8U)
 
#define PWM_CMP_CMPHLF_SHIFT   (3U)
 
#define PWM_CMP_CMPHLF_SET(x)   (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK)
 
#define PWM_CMP_CMPHLF_GET(x)   (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT)
 
#define PWM_CMP_CMPJIT_MASK   (0x7U)
 
#define PWM_CMP_CMPJIT_SHIFT   (0U)
 
#define PWM_CMP_CMPJIT_SET(x)   (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK)
 
#define PWM_CMP_CMPJIT_GET(x)   (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT)
 
#define PWM_FRCMD_FRCMD_MASK   (0xFFFFU)
 
#define PWM_FRCMD_FRCMD_SHIFT   (0U)
 
#define PWM_FRCMD_FRCMD_SET(x)   (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK)
 
#define PWM_FRCMD_FRCMD_GET(x)   (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT)
 
#define PWM_SHLK_SHLK_MASK   (0x80000000UL)
 
#define PWM_SHLK_SHLK_SHIFT   (31U)
 
#define PWM_SHLK_SHLK_SET(x)   (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK)
 
#define PWM_SHLK_SHLK_GET(x)   (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT)
 
#define PWM_CHCFG_CMPSELEND_MASK   (0x1F000000UL)
 
#define PWM_CHCFG_CMPSELEND_SHIFT   (24U)
 
#define PWM_CHCFG_CMPSELEND_SET(x)   (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK)
 
#define PWM_CHCFG_CMPSELEND_GET(x)   (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT)
 
#define PWM_CHCFG_CMPSELBEG_MASK   (0x1F0000UL)
 
#define PWM_CHCFG_CMPSELBEG_SHIFT   (16U)
 
#define PWM_CHCFG_CMPSELBEG_SET(x)   (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK)
 
#define PWM_CHCFG_CMPSELBEG_GET(x)   (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT)
 
#define PWM_CHCFG_OUTPOL_MASK   (0x2U)
 
#define PWM_CHCFG_OUTPOL_SHIFT   (1U)
 
#define PWM_CHCFG_OUTPOL_SET(x)   (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK)
 
#define PWM_CHCFG_OUTPOL_GET(x)   (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT)
 
#define PWM_GCR_FAULTI3EN_MASK   (0x80000000UL)
 
#define PWM_GCR_FAULTI3EN_SHIFT   (31U)
 
#define PWM_GCR_FAULTI3EN_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK)
 
#define PWM_GCR_FAULTI3EN_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT)
 
#define PWM_GCR_FAULTI2EN_MASK   (0x40000000UL)
 
#define PWM_GCR_FAULTI2EN_SHIFT   (30U)
 
#define PWM_GCR_FAULTI2EN_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK)
 
#define PWM_GCR_FAULTI2EN_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT)
 
#define PWM_GCR_FAULTI1EN_MASK   (0x20000000UL)
 
#define PWM_GCR_FAULTI1EN_SHIFT   (29U)
 
#define PWM_GCR_FAULTI1EN_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK)
 
#define PWM_GCR_FAULTI1EN_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT)
 
#define PWM_GCR_FAULTI0EN_MASK   (0x10000000UL)
 
#define PWM_GCR_FAULTI0EN_SHIFT   (28U)
 
#define PWM_GCR_FAULTI0EN_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK)
 
#define PWM_GCR_FAULTI0EN_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT)
 
#define PWM_GCR_DEBUGFAULT_MASK   (0x8000000UL)
 
#define PWM_GCR_DEBUGFAULT_SHIFT   (27U)
 
#define PWM_GCR_DEBUGFAULT_SET(x)   (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK)
 
#define PWM_GCR_DEBUGFAULT_GET(x)   (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT)
 
#define PWM_GCR_FRCPOL_MASK   (0x4000000UL)
 
#define PWM_GCR_FRCPOL_SHIFT   (26U)
 
#define PWM_GCR_FRCPOL_SET(x)   (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK)
 
#define PWM_GCR_FRCPOL_GET(x)   (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT)
 
#define PWM_GCR_HWSHDWEDG_MASK   (0x1000000UL)
 
#define PWM_GCR_HWSHDWEDG_SHIFT   (24U)
 
#define PWM_GCR_HWSHDWEDG_SET(x)   (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK)
 
#define PWM_GCR_HWSHDWEDG_GET(x)   (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT)
 
#define PWM_GCR_CMPSHDWSEL_MASK   (0xF80000UL)
 
#define PWM_GCR_CMPSHDWSEL_SHIFT   (19U)
 
#define PWM_GCR_CMPSHDWSEL_SET(x)   (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK)
 
#define PWM_GCR_CMPSHDWSEL_GET(x)   (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT)
 
#define PWM_GCR_FAULTRECEDG_MASK   (0x40000UL)
 
#define PWM_GCR_FAULTRECEDG_SHIFT   (18U)
 
#define PWM_GCR_FAULTRECEDG_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK)
 
#define PWM_GCR_FAULTRECEDG_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT)
 
#define PWM_GCR_FAULTRECHWSEL_MASK   (0x3E000UL)
 
#define PWM_GCR_FAULTRECHWSEL_SHIFT   (13U)
 
#define PWM_GCR_FAULTRECHWSEL_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK)
 
#define PWM_GCR_FAULTRECHWSEL_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT)
 
#define PWM_GCR_FAULTE1EN_MASK   (0x1000U)
 
#define PWM_GCR_FAULTE1EN_SHIFT   (12U)
 
#define PWM_GCR_FAULTE1EN_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK)
 
#define PWM_GCR_FAULTE1EN_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT)
 
#define PWM_GCR_FAULTE0EN_MASK   (0x800U)
 
#define PWM_GCR_FAULTE0EN_SHIFT   (11U)
 
#define PWM_GCR_FAULTE0EN_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK)
 
#define PWM_GCR_FAULTE0EN_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT)
 
#define PWM_GCR_FAULTEXPOL_MASK   (0x600U)
 
#define PWM_GCR_FAULTEXPOL_SHIFT   (9U)
 
#define PWM_GCR_FAULTEXPOL_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK)
 
#define PWM_GCR_FAULTEXPOL_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT)
 
#define PWM_GCR_RLDSYNCEN_MASK   (0x100U)
 
#define PWM_GCR_RLDSYNCEN_SHIFT   (8U)
 
#define PWM_GCR_RLDSYNCEN_SET(x)   (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK)
 
#define PWM_GCR_RLDSYNCEN_GET(x)   (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT)
 
#define PWM_GCR_CEN_MASK   (0x80U)
 
#define PWM_GCR_CEN_SHIFT   (7U)
 
#define PWM_GCR_CEN_SET(x)   (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK)
 
#define PWM_GCR_CEN_GET(x)   (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT)
 
#define PWM_GCR_FAULTCLR_MASK   (0x40U)
 
#define PWM_GCR_FAULTCLR_SHIFT   (6U)
 
#define PWM_GCR_FAULTCLR_SET(x)   (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK)
 
#define PWM_GCR_FAULTCLR_GET(x)   (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT)
 
#define PWM_GCR_XRLDSYNCEN_MASK   (0x20U)
 
#define PWM_GCR_XRLDSYNCEN_SHIFT   (5U)
 
#define PWM_GCR_XRLDSYNCEN_SET(x)   (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK)
 
#define PWM_GCR_XRLDSYNCEN_GET(x)   (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT)
 
#define PWM_GCR_TIMERRESET_MASK   (0x8U)
 
#define PWM_GCR_TIMERRESET_SHIFT   (3U)
 
#define PWM_GCR_TIMERRESET_SET(x)   (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK)
 
#define PWM_GCR_TIMERRESET_GET(x)   (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT)
 
#define PWM_GCR_FRCTIME_MASK   (0x6U)
 
#define PWM_GCR_FRCTIME_SHIFT   (1U)
 
#define PWM_GCR_FRCTIME_SET(x)   (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK)
 
#define PWM_GCR_FRCTIME_GET(x)   (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT)
 
#define PWM_GCR_SWFRC_MASK   (0x1U)
 
#define PWM_GCR_SWFRC_SHIFT   (0U)
 
#define PWM_GCR_SWFRC_SET(x)   (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK)
 
#define PWM_GCR_SWFRC_GET(x)   (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT)
 
#define PWM_SHCR_FRCSHDWSEL_MASK   (0x1F00U)
 
#define PWM_SHCR_FRCSHDWSEL_SHIFT   (8U)
 
#define PWM_SHCR_FRCSHDWSEL_SET(x)   (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK)
 
#define PWM_SHCR_FRCSHDWSEL_GET(x)   (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT)
 
#define PWM_SHCR_CNTSHDWSEL_MASK   (0xF8U)
 
#define PWM_SHCR_CNTSHDWSEL_SHIFT   (3U)
 
#define PWM_SHCR_CNTSHDWSEL_SET(x)   (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK)
 
#define PWM_SHCR_CNTSHDWSEL_GET(x)   (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT)
 
#define PWM_SHCR_CNTSHDWUPT_MASK   (0x6U)
 
#define PWM_SHCR_CNTSHDWUPT_SHIFT   (1U)
 
#define PWM_SHCR_CNTSHDWUPT_SET(x)   (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK)
 
#define PWM_SHCR_CNTSHDWUPT_GET(x)   (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT)
 
#define PWM_SHCR_SHLKEN_MASK   (0x1U)
 
#define PWM_SHCR_SHLKEN_SHIFT   (0U)
 
#define PWM_SHCR_SHLKEN_SET(x)   (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK)
 
#define PWM_SHCR_SHLKEN_GET(x)   (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT)
 
#define PWM_CAPPOS_CAPPOS_MASK   (0xFFFFFFF0UL)
 
#define PWM_CAPPOS_CAPPOS_SHIFT   (4U)
 
#define PWM_CAPPOS_CAPPOS_GET(x)   (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT)
 
#define PWM_CNT_XCNT_MASK   (0xF0000000UL)
 
#define PWM_CNT_XCNT_SHIFT   (28U)
 
#define PWM_CNT_XCNT_GET(x)   (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT)
 
#define PWM_CNT_CNT_MASK   (0xFFFFFF0UL)
 
#define PWM_CNT_CNT_SHIFT   (4U)
 
#define PWM_CNT_CNT_GET(x)   (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT)
 
#define PWM_CAPNEG_CAPNEG_MASK   (0xFFFFFFFFUL)
 
#define PWM_CAPNEG_CAPNEG_SHIFT   (0U)
 
#define PWM_CAPNEG_CAPNEG_GET(x)   (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT)
 
#define PWM_CNTCOPY_XCNT_MASK   (0xF0000000UL)
 
#define PWM_CNTCOPY_XCNT_SHIFT   (28U)
 
#define PWM_CNTCOPY_XCNT_GET(x)   (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT)
 
#define PWM_CNTCOPY_CNT_MASK   (0xFFFFFF0UL)
 
#define PWM_CNTCOPY_CNT_SHIFT   (4U)
 
#define PWM_CNTCOPY_CNT_GET(x)   (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT)
 
#define PWM_PWMCFG_OEN_MASK   (0x10000000UL)
 
#define PWM_PWMCFG_OEN_SHIFT   (28U)
 
#define PWM_PWMCFG_OEN_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK)
 
#define PWM_PWMCFG_OEN_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT)
 
#define PWM_PWMCFG_FRCSHDWUPT_MASK   (0xC000000UL)
 
#define PWM_PWMCFG_FRCSHDWUPT_SHIFT   (26U)
 
#define PWM_PWMCFG_FRCSHDWUPT_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK)
 
#define PWM_PWMCFG_FRCSHDWUPT_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT)
 
#define PWM_PWMCFG_FAULTMODE_MASK   (0x3000000UL)
 
#define PWM_PWMCFG_FAULTMODE_SHIFT   (24U)
 
#define PWM_PWMCFG_FAULTMODE_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK)
 
#define PWM_PWMCFG_FAULTMODE_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT)
 
#define PWM_PWMCFG_FAULTRECTIME_MASK   (0xC00000UL)
 
#define PWM_PWMCFG_FAULTRECTIME_SHIFT   (22U)
 
#define PWM_PWMCFG_FAULTRECTIME_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK)
 
#define PWM_PWMCFG_FAULTRECTIME_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT)
 
#define PWM_PWMCFG_FRCSRCSEL_MASK   (0x200000UL)
 
#define PWM_PWMCFG_FRCSRCSEL_SHIFT   (21U)
 
#define PWM_PWMCFG_FRCSRCSEL_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK)
 
#define PWM_PWMCFG_FRCSRCSEL_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT)
 
#define PWM_PWMCFG_PAIR_MASK   (0x100000UL)
 
#define PWM_PWMCFG_PAIR_SHIFT   (20U)
 
#define PWM_PWMCFG_PAIR_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK)
 
#define PWM_PWMCFG_PAIR_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT)
 
#define PWM_PWMCFG_DEADAREA_MASK   (0xFFFFFUL)
 
#define PWM_PWMCFG_DEADAREA_SHIFT   (0U)
 
#define PWM_PWMCFG_DEADAREA_SET(x)   (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK)
 
#define PWM_PWMCFG_DEADAREA_GET(x)   (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT)
 
#define PWM_SR_FAULTF_MASK   (0x8000000UL)
 
#define PWM_SR_FAULTF_SHIFT   (27U)
 
#define PWM_SR_FAULTF_SET(x)   (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK)
 
#define PWM_SR_FAULTF_GET(x)   (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT)
 
#define PWM_SR_XRLDF_MASK   (0x4000000UL)
 
#define PWM_SR_XRLDF_SHIFT   (26U)
 
#define PWM_SR_XRLDF_SET(x)   (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK)
 
#define PWM_SR_XRLDF_GET(x)   (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT)
 
#define PWM_SR_HALFRLDF_MASK   (0x2000000UL)
 
#define PWM_SR_HALFRLDF_SHIFT   (25U)
 
#define PWM_SR_HALFRLDF_SET(x)   (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK)
 
#define PWM_SR_HALFRLDF_GET(x)   (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT)
 
#define PWM_SR_RLDF_MASK   (0x1000000UL)
 
#define PWM_SR_RLDF_SHIFT   (24U)
 
#define PWM_SR_RLDF_SET(x)   (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK)
 
#define PWM_SR_RLDF_GET(x)   (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT)
 
#define PWM_SR_CMPFX_MASK   (0xFFFFFFUL)
 
#define PWM_SR_CMPFX_SHIFT   (0U)
 
#define PWM_SR_CMPFX_SET(x)   (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK)
 
#define PWM_SR_CMPFX_GET(x)   (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT)
 
#define PWM_IRQEN_FAULTIRQE_MASK   (0x8000000UL)
 
#define PWM_IRQEN_FAULTIRQE_SHIFT   (27U)
 
#define PWM_IRQEN_FAULTIRQE_SET(x)   (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK)
 
#define PWM_IRQEN_FAULTIRQE_GET(x)   (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT)
 
#define PWM_IRQEN_XRLDIRQE_MASK   (0x4000000UL)
 
#define PWM_IRQEN_XRLDIRQE_SHIFT   (26U)
 
#define PWM_IRQEN_XRLDIRQE_SET(x)   (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK)
 
#define PWM_IRQEN_XRLDIRQE_GET(x)   (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT)
 
#define PWM_IRQEN_HALFRLDIRQE_MASK   (0x2000000UL)
 
#define PWM_IRQEN_HALFRLDIRQE_SHIFT   (25U)
 
#define PWM_IRQEN_HALFRLDIRQE_SET(x)   (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK)
 
#define PWM_IRQEN_HALFRLDIRQE_GET(x)   (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT)
 
#define PWM_IRQEN_RLDIRQE_MASK   (0x1000000UL)
 
#define PWM_IRQEN_RLDIRQE_SHIFT   (24U)
 
#define PWM_IRQEN_RLDIRQE_SET(x)   (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK)
 
#define PWM_IRQEN_RLDIRQE_GET(x)   (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT)
 
#define PWM_IRQEN_CMPIRQEX_MASK   (0xFFFFFFUL)
 
#define PWM_IRQEN_CMPIRQEX_SHIFT   (0U)
 
#define PWM_IRQEN_CMPIRQEX_SET(x)   (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK)
 
#define PWM_IRQEN_CMPIRQEX_GET(x)   (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT)
 
#define PWM_DMAEN_FAULTEN_MASK   (0x8000000UL)
 
#define PWM_DMAEN_FAULTEN_SHIFT   (27U)
 
#define PWM_DMAEN_FAULTEN_SET(x)   (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK)
 
#define PWM_DMAEN_FAULTEN_GET(x)   (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT)
 
#define PWM_DMAEN_XRLDEN_MASK   (0x4000000UL)
 
#define PWM_DMAEN_XRLDEN_SHIFT   (26U)
 
#define PWM_DMAEN_XRLDEN_SET(x)   (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK)
 
#define PWM_DMAEN_XRLDEN_GET(x)   (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT)
 
#define PWM_DMAEN_HALFRLDEN_MASK   (0x2000000UL)
 
#define PWM_DMAEN_HALFRLDEN_SHIFT   (25U)
 
#define PWM_DMAEN_HALFRLDEN_SET(x)   (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK)
 
#define PWM_DMAEN_HALFRLDEN_GET(x)   (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT)
 
#define PWM_DMAEN_RLDEN_MASK   (0x1000000UL)
 
#define PWM_DMAEN_RLDEN_SHIFT   (24U)
 
#define PWM_DMAEN_RLDEN_SET(x)   (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK)
 
#define PWM_DMAEN_RLDEN_GET(x)   (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT)
 
#define PWM_DMAEN_CMPENX_MASK   (0xFFFFFFUL)
 
#define PWM_DMAEN_CMPENX_SHIFT   (0U)
 
#define PWM_DMAEN_CMPENX_SET(x)   (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK)
 
#define PWM_DMAEN_CMPENX_GET(x)   (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT)
 
#define PWM_CMPCFG_XCNTCMPEN_MASK   (0xF0U)
 
#define PWM_CMPCFG_XCNTCMPEN_SHIFT   (4U)
 
#define PWM_CMPCFG_XCNTCMPEN_SET(x)   (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK)
 
#define PWM_CMPCFG_XCNTCMPEN_GET(x)   (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT)
 
#define PWM_CMPCFG_CMPSHDWUPT_MASK   (0xCU)
 
#define PWM_CMPCFG_CMPSHDWUPT_SHIFT   (2U)
 
#define PWM_CMPCFG_CMPSHDWUPT_SET(x)   (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK)
 
#define PWM_CMPCFG_CMPSHDWUPT_GET(x)   (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT)
 
#define PWM_CMPCFG_CMPMODE_MASK   (0x2U)
 
#define PWM_CMPCFG_CMPMODE_SHIFT   (1U)
 
#define PWM_CMPCFG_CMPMODE_SET(x)   (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK)
 
#define PWM_CMPCFG_CMPMODE_GET(x)   (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT)
 
#define PWM_CMP_0   (0UL)
 
#define PWM_CMP_1   (1UL)
 
#define PWM_CMP_2   (2UL)
 
#define PWM_CMP_3   (3UL)
 
#define PWM_CMP_4   (4UL)
 
#define PWM_CMP_5   (5UL)
 
#define PWM_CMP_6   (6UL)
 
#define PWM_CMP_7   (7UL)
 
#define PWM_CMP_8   (8UL)
 
#define PWM_CMP_9   (9UL)
 
#define PWM_CMP_10   (10UL)
 
#define PWM_CMP_11   (11UL)
 
#define PWM_CMP_12   (12UL)
 
#define PWM_CMP_13   (13UL)
 
#define PWM_CMP_14   (14UL)
 
#define PWM_CMP_15   (15UL)
 
#define PWM_CMP_16   (16UL)
 
#define PWM_CMP_17   (17UL)
 
#define PWM_CMP_18   (18UL)
 
#define PWM_CMP_19   (19UL)
 
#define PWM_CMP_20   (20UL)
 
#define PWM_CMP_21   (21UL)
 
#define PWM_CMP_22   (22UL)
 
#define PWM_CMP_23   (23UL)
 
#define PWM_CHCFG_0   (0UL)
 
#define PWM_CHCFG_1   (1UL)
 
#define PWM_CHCFG_2   (2UL)
 
#define PWM_CHCFG_3   (3UL)
 
#define PWM_CHCFG_4   (4UL)
 
#define PWM_CHCFG_5   (5UL)
 
#define PWM_CHCFG_6   (6UL)
 
#define PWM_CHCFG_7   (7UL)
 
#define PWM_CHCFG_8   (8UL)
 
#define PWM_CHCFG_9   (9UL)
 
#define PWM_CHCFG_10   (10UL)
 
#define PWM_CHCFG_11   (11UL)
 
#define PWM_CHCFG_12   (12UL)
 
#define PWM_CHCFG_13   (13UL)
 
#define PWM_CHCFG_14   (14UL)
 
#define PWM_CHCFG_15   (15UL)
 
#define PWM_CHCFG_16   (16UL)
 
#define PWM_CHCFG_17   (17UL)
 
#define PWM_CHCFG_18   (18UL)
 
#define PWM_CHCFG_19   (19UL)
 
#define PWM_CHCFG_20   (20UL)
 
#define PWM_CHCFG_21   (21UL)
 
#define PWM_CHCFG_22   (22UL)
 
#define PWM_CHCFG_23   (23UL)
 
#define PWM_CAPPOS_0   (0UL)
 
#define PWM_CAPPOS_1   (1UL)
 
#define PWM_CAPPOS_2   (2UL)
 
#define PWM_CAPPOS_3   (3UL)
 
#define PWM_CAPPOS_4   (4UL)
 
#define PWM_CAPPOS_5   (5UL)
 
#define PWM_CAPPOS_6   (6UL)
 
#define PWM_CAPPOS_7   (7UL)
 
#define PWM_CAPPOS_8   (8UL)
 
#define PWM_CAPPOS_9   (9UL)
 
#define PWM_CAPPOS_10   (10UL)
 
#define PWM_CAPPOS_11   (11UL)
 
#define PWM_CAPPOS_12   (12UL)
 
#define PWM_CAPPOS_13   (13UL)
 
#define PWM_CAPPOS_14   (14UL)
 
#define PWM_CAPPOS_15   (15UL)
 
#define PWM_CAPPOS_16   (16UL)
 
#define PWM_CAPPOS_17   (17UL)
 
#define PWM_CAPPOS_18   (18UL)
 
#define PWM_CAPPOS_19   (19UL)
 
#define PWM_CAPPOS_20   (20UL)
 
#define PWM_CAPPOS_21   (21UL)
 
#define PWM_CAPPOS_22   (22UL)
 
#define PWM_CAPPOS_23   (23UL)
 
#define PWM_CAPNEG_0   (0UL)
 
#define PWM_CAPNEG_1   (1UL)
 
#define PWM_CAPNEG_2   (2UL)
 
#define PWM_CAPNEG_3   (3UL)
 
#define PWM_CAPNEG_4   (4UL)
 
#define PWM_CAPNEG_5   (5UL)
 
#define PWM_CAPNEG_6   (6UL)
 
#define PWM_CAPNEG_7   (7UL)
 
#define PWM_CAPNEG_8   (8UL)
 
#define PWM_CAPNEG_9   (9UL)
 
#define PWM_CAPNEG_10   (10UL)
 
#define PWM_CAPNEG_11   (11UL)
 
#define PWM_CAPNEG_12   (12UL)
 
#define PWM_CAPNEG_13   (13UL)
 
#define PWM_CAPNEG_14   (14UL)
 
#define PWM_CAPNEG_15   (15UL)
 
#define PWM_CAPNEG_16   (16UL)
 
#define PWM_CAPNEG_17   (17UL)
 
#define PWM_CAPNEG_18   (18UL)
 
#define PWM_CAPNEG_19   (19UL)
 
#define PWM_CAPNEG_20   (20UL)
 
#define PWM_CAPNEG_21   (21UL)
 
#define PWM_CAPNEG_22   (22UL)
 
#define PWM_CAPNEG_23   (23UL)
 
#define PWM_PWMCFG_0   (0UL)
 
#define PWM_PWMCFG_1   (1UL)
 
#define PWM_PWMCFG_2   (2UL)
 
#define PWM_PWMCFG_3   (3UL)
 
#define PWM_PWMCFG_4   (4UL)
 
#define PWM_PWMCFG_5   (5UL)
 
#define PWM_PWMCFG_6   (6UL)
 
#define PWM_PWMCFG_7   (7UL)
 
#define PWM_CMPCFG_CMPCFG0   (0UL)
 
#define PWM_CMPCFG_1   (1UL)
 
#define PWM_CMPCFG_2   (2UL)
 
#define PWM_CMPCFG_3   (3UL)
 
#define PWM_CMPCFG_4   (4UL)
 
#define PWM_CMPCFG_5   (5UL)
 
#define PWM_CMPCFG_6   (6UL)
 
#define PWM_CMPCFG_7   (7UL)
 
#define PWM_CMPCFG_8   (8UL)
 
#define PWM_CMPCFG_9   (9UL)
 
#define PWM_CMPCFG_10   (10UL)
 
#define PWM_CMPCFG_11   (11UL)
 
#define PWM_CMPCFG_12   (12UL)
 
#define PWM_CMPCFG_13   (13UL)
 
#define PWM_CMPCFG_14   (14UL)
 
#define PWM_CMPCFG_15   (15UL)
 
#define PWM_CMPCFG_16   (16UL)
 
#define PWM_CMPCFG_17   (17UL)
 
#define PWM_CMPCFG_18   (18UL)
 
#define PWM_CMPCFG_19   (19UL)
 
#define PWM_CMPCFG_20   (20UL)
 
#define PWM_CMPCFG_21   (21UL)
 
#define PWM_CMPCFG_22   (22UL)
 
#define PWM_CMPCFG_23   (23UL)
 

Macro Definition Documentation

◆ PWM_CAPNEG_0

#define PWM_CAPNEG_0   (0UL)

◆ PWM_CAPNEG_1

#define PWM_CAPNEG_1   (1UL)

◆ PWM_CAPNEG_10

#define PWM_CAPNEG_10   (10UL)

◆ PWM_CAPNEG_11

#define PWM_CAPNEG_11   (11UL)

◆ PWM_CAPNEG_12

#define PWM_CAPNEG_12   (12UL)

◆ PWM_CAPNEG_13

#define PWM_CAPNEG_13   (13UL)

◆ PWM_CAPNEG_14

#define PWM_CAPNEG_14   (14UL)

◆ PWM_CAPNEG_15

#define PWM_CAPNEG_15   (15UL)

◆ PWM_CAPNEG_16

#define PWM_CAPNEG_16   (16UL)

◆ PWM_CAPNEG_17

#define PWM_CAPNEG_17   (17UL)

◆ PWM_CAPNEG_18

#define PWM_CAPNEG_18   (18UL)

◆ PWM_CAPNEG_19

#define PWM_CAPNEG_19   (19UL)

◆ PWM_CAPNEG_2

#define PWM_CAPNEG_2   (2UL)

◆ PWM_CAPNEG_20

#define PWM_CAPNEG_20   (20UL)

◆ PWM_CAPNEG_21

#define PWM_CAPNEG_21   (21UL)

◆ PWM_CAPNEG_22

#define PWM_CAPNEG_22   (22UL)

◆ PWM_CAPNEG_23

#define PWM_CAPNEG_23   (23UL)

◆ PWM_CAPNEG_3

#define PWM_CAPNEG_3   (3UL)

◆ PWM_CAPNEG_4

#define PWM_CAPNEG_4   (4UL)

◆ PWM_CAPNEG_5

#define PWM_CAPNEG_5   (5UL)

◆ PWM_CAPNEG_6

#define PWM_CAPNEG_6   (6UL)

◆ PWM_CAPNEG_7

#define PWM_CAPNEG_7   (7UL)

◆ PWM_CAPNEG_8

#define PWM_CAPNEG_8   (8UL)

◆ PWM_CAPNEG_9

#define PWM_CAPNEG_9   (9UL)

◆ PWM_CAPNEG_CAPNEG_GET

#define PWM_CAPNEG_CAPNEG_GET (   x)    (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT)

◆ PWM_CAPNEG_CAPNEG_MASK

#define PWM_CAPNEG_CAPNEG_MASK   (0xFFFFFFFFUL)

◆ PWM_CAPNEG_CAPNEG_SHIFT

#define PWM_CAPNEG_CAPNEG_SHIFT   (0U)

◆ PWM_CAPPOS_0

#define PWM_CAPPOS_0   (0UL)

◆ PWM_CAPPOS_1

#define PWM_CAPPOS_1   (1UL)

◆ PWM_CAPPOS_10

#define PWM_CAPPOS_10   (10UL)

◆ PWM_CAPPOS_11

#define PWM_CAPPOS_11   (11UL)

◆ PWM_CAPPOS_12

#define PWM_CAPPOS_12   (12UL)

◆ PWM_CAPPOS_13

#define PWM_CAPPOS_13   (13UL)

◆ PWM_CAPPOS_14

#define PWM_CAPPOS_14   (14UL)

◆ PWM_CAPPOS_15

#define PWM_CAPPOS_15   (15UL)

◆ PWM_CAPPOS_16

#define PWM_CAPPOS_16   (16UL)

◆ PWM_CAPPOS_17

#define PWM_CAPPOS_17   (17UL)

◆ PWM_CAPPOS_18

#define PWM_CAPPOS_18   (18UL)

◆ PWM_CAPPOS_19

#define PWM_CAPPOS_19   (19UL)

◆ PWM_CAPPOS_2

#define PWM_CAPPOS_2   (2UL)

◆ PWM_CAPPOS_20

#define PWM_CAPPOS_20   (20UL)

◆ PWM_CAPPOS_21

#define PWM_CAPPOS_21   (21UL)

◆ PWM_CAPPOS_22

#define PWM_CAPPOS_22   (22UL)

◆ PWM_CAPPOS_23

#define PWM_CAPPOS_23   (23UL)

◆ PWM_CAPPOS_3

#define PWM_CAPPOS_3   (3UL)

◆ PWM_CAPPOS_4

#define PWM_CAPPOS_4   (4UL)

◆ PWM_CAPPOS_5

#define PWM_CAPPOS_5   (5UL)

◆ PWM_CAPPOS_6

#define PWM_CAPPOS_6   (6UL)

◆ PWM_CAPPOS_7

#define PWM_CAPPOS_7   (7UL)

◆ PWM_CAPPOS_8

#define PWM_CAPPOS_8   (8UL)

◆ PWM_CAPPOS_9

#define PWM_CAPPOS_9   (9UL)

◆ PWM_CAPPOS_CAPPOS_GET

#define PWM_CAPPOS_CAPPOS_GET (   x)    (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT)

◆ PWM_CAPPOS_CAPPOS_MASK

#define PWM_CAPPOS_CAPPOS_MASK   (0xFFFFFFF0UL)

◆ PWM_CAPPOS_CAPPOS_SHIFT

#define PWM_CAPPOS_CAPPOS_SHIFT   (4U)

◆ PWM_CHCFG_0

#define PWM_CHCFG_0   (0UL)

◆ PWM_CHCFG_1

#define PWM_CHCFG_1   (1UL)

◆ PWM_CHCFG_10

#define PWM_CHCFG_10   (10UL)

◆ PWM_CHCFG_11

#define PWM_CHCFG_11   (11UL)

◆ PWM_CHCFG_12

#define PWM_CHCFG_12   (12UL)

◆ PWM_CHCFG_13

#define PWM_CHCFG_13   (13UL)

◆ PWM_CHCFG_14

#define PWM_CHCFG_14   (14UL)

◆ PWM_CHCFG_15

#define PWM_CHCFG_15   (15UL)

◆ PWM_CHCFG_16

#define PWM_CHCFG_16   (16UL)

◆ PWM_CHCFG_17

#define PWM_CHCFG_17   (17UL)

◆ PWM_CHCFG_18

#define PWM_CHCFG_18   (18UL)

◆ PWM_CHCFG_19

#define PWM_CHCFG_19   (19UL)

◆ PWM_CHCFG_2

#define PWM_CHCFG_2   (2UL)

◆ PWM_CHCFG_20

#define PWM_CHCFG_20   (20UL)

◆ PWM_CHCFG_21

#define PWM_CHCFG_21   (21UL)

◆ PWM_CHCFG_22

#define PWM_CHCFG_22   (22UL)

◆ PWM_CHCFG_23

#define PWM_CHCFG_23   (23UL)

◆ PWM_CHCFG_3

#define PWM_CHCFG_3   (3UL)

◆ PWM_CHCFG_4

#define PWM_CHCFG_4   (4UL)

◆ PWM_CHCFG_5

#define PWM_CHCFG_5   (5UL)

◆ PWM_CHCFG_6

#define PWM_CHCFG_6   (6UL)

◆ PWM_CHCFG_7

#define PWM_CHCFG_7   (7UL)

◆ PWM_CHCFG_8

#define PWM_CHCFG_8   (8UL)

◆ PWM_CHCFG_9

#define PWM_CHCFG_9   (9UL)

◆ PWM_CHCFG_CMPSELBEG_GET

#define PWM_CHCFG_CMPSELBEG_GET (   x)    (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT)

◆ PWM_CHCFG_CMPSELBEG_MASK

#define PWM_CHCFG_CMPSELBEG_MASK   (0x1F0000UL)

◆ PWM_CHCFG_CMPSELBEG_SET

#define PWM_CHCFG_CMPSELBEG_SET (   x)    (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK)

◆ PWM_CHCFG_CMPSELBEG_SHIFT

#define PWM_CHCFG_CMPSELBEG_SHIFT   (16U)

◆ PWM_CHCFG_CMPSELEND_GET

#define PWM_CHCFG_CMPSELEND_GET (   x)    (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT)

◆ PWM_CHCFG_CMPSELEND_MASK

#define PWM_CHCFG_CMPSELEND_MASK   (0x1F000000UL)

◆ PWM_CHCFG_CMPSELEND_SET

#define PWM_CHCFG_CMPSELEND_SET (   x)    (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK)

◆ PWM_CHCFG_CMPSELEND_SHIFT

#define PWM_CHCFG_CMPSELEND_SHIFT   (24U)

◆ PWM_CHCFG_OUTPOL_GET

#define PWM_CHCFG_OUTPOL_GET (   x)    (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT)

◆ PWM_CHCFG_OUTPOL_MASK

#define PWM_CHCFG_OUTPOL_MASK   (0x2U)

◆ PWM_CHCFG_OUTPOL_SET

#define PWM_CHCFG_OUTPOL_SET (   x)    (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK)

◆ PWM_CHCFG_OUTPOL_SHIFT

#define PWM_CHCFG_OUTPOL_SHIFT   (1U)

◆ PWM_CMP_0

#define PWM_CMP_0   (0UL)

◆ PWM_CMP_1

#define PWM_CMP_1   (1UL)

◆ PWM_CMP_10

#define PWM_CMP_10   (10UL)

◆ PWM_CMP_11

#define PWM_CMP_11   (11UL)

◆ PWM_CMP_12

#define PWM_CMP_12   (12UL)

◆ PWM_CMP_13

#define PWM_CMP_13   (13UL)

◆ PWM_CMP_14

#define PWM_CMP_14   (14UL)

◆ PWM_CMP_15

#define PWM_CMP_15   (15UL)

◆ PWM_CMP_16

#define PWM_CMP_16   (16UL)

◆ PWM_CMP_17

#define PWM_CMP_17   (17UL)

◆ PWM_CMP_18

#define PWM_CMP_18   (18UL)

◆ PWM_CMP_19

#define PWM_CMP_19   (19UL)

◆ PWM_CMP_2

#define PWM_CMP_2   (2UL)

◆ PWM_CMP_20

#define PWM_CMP_20   (20UL)

◆ PWM_CMP_21

#define PWM_CMP_21   (21UL)

◆ PWM_CMP_22

#define PWM_CMP_22   (22UL)

◆ PWM_CMP_23

#define PWM_CMP_23   (23UL)

◆ PWM_CMP_3

#define PWM_CMP_3   (3UL)

◆ PWM_CMP_4

#define PWM_CMP_4   (4UL)

◆ PWM_CMP_5

#define PWM_CMP_5   (5UL)

◆ PWM_CMP_6

#define PWM_CMP_6   (6UL)

◆ PWM_CMP_7

#define PWM_CMP_7   (7UL)

◆ PWM_CMP_8

#define PWM_CMP_8   (8UL)

◆ PWM_CMP_9

#define PWM_CMP_9   (9UL)

◆ PWM_CMP_CMP_GET

#define PWM_CMP_CMP_GET (   x)    (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT)

◆ PWM_CMP_CMP_MASK

#define PWM_CMP_CMP_MASK   (0xFFFFFF0UL)

◆ PWM_CMP_CMP_SET

#define PWM_CMP_CMP_SET (   x)    (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK)

◆ PWM_CMP_CMP_SHIFT

#define PWM_CMP_CMP_SHIFT   (4U)

◆ PWM_CMP_CMPHLF_GET

#define PWM_CMP_CMPHLF_GET (   x)    (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT)

◆ PWM_CMP_CMPHLF_MASK

#define PWM_CMP_CMPHLF_MASK   (0x8U)

◆ PWM_CMP_CMPHLF_SET

#define PWM_CMP_CMPHLF_SET (   x)    (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK)

◆ PWM_CMP_CMPHLF_SHIFT

#define PWM_CMP_CMPHLF_SHIFT   (3U)

◆ PWM_CMP_CMPJIT_GET

#define PWM_CMP_CMPJIT_GET (   x)    (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT)

◆ PWM_CMP_CMPJIT_MASK

#define PWM_CMP_CMPJIT_MASK   (0x7U)

◆ PWM_CMP_CMPJIT_SET

#define PWM_CMP_CMPJIT_SET (   x)    (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK)

◆ PWM_CMP_CMPJIT_SHIFT

#define PWM_CMP_CMPJIT_SHIFT   (0U)

◆ PWM_CMP_XCMP_GET

#define PWM_CMP_XCMP_GET (   x)    (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT)

◆ PWM_CMP_XCMP_MASK

#define PWM_CMP_XCMP_MASK   (0xF0000000UL)

◆ PWM_CMP_XCMP_SET

#define PWM_CMP_XCMP_SET (   x)    (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK)

◆ PWM_CMP_XCMP_SHIFT

#define PWM_CMP_XCMP_SHIFT   (28U)

◆ PWM_CMPCFG_1

#define PWM_CMPCFG_1   (1UL)

◆ PWM_CMPCFG_10

#define PWM_CMPCFG_10   (10UL)

◆ PWM_CMPCFG_11

#define PWM_CMPCFG_11   (11UL)

◆ PWM_CMPCFG_12

#define PWM_CMPCFG_12   (12UL)

◆ PWM_CMPCFG_13

#define PWM_CMPCFG_13   (13UL)

◆ PWM_CMPCFG_14

#define PWM_CMPCFG_14   (14UL)

◆ PWM_CMPCFG_15

#define PWM_CMPCFG_15   (15UL)

◆ PWM_CMPCFG_16

#define PWM_CMPCFG_16   (16UL)

◆ PWM_CMPCFG_17

#define PWM_CMPCFG_17   (17UL)

◆ PWM_CMPCFG_18

#define PWM_CMPCFG_18   (18UL)

◆ PWM_CMPCFG_19

#define PWM_CMPCFG_19   (19UL)

◆ PWM_CMPCFG_2

#define PWM_CMPCFG_2   (2UL)

◆ PWM_CMPCFG_20

#define PWM_CMPCFG_20   (20UL)

◆ PWM_CMPCFG_21

#define PWM_CMPCFG_21   (21UL)

◆ PWM_CMPCFG_22

#define PWM_CMPCFG_22   (22UL)

◆ PWM_CMPCFG_23

#define PWM_CMPCFG_23   (23UL)

◆ PWM_CMPCFG_3

#define PWM_CMPCFG_3   (3UL)

◆ PWM_CMPCFG_4

#define PWM_CMPCFG_4   (4UL)

◆ PWM_CMPCFG_5

#define PWM_CMPCFG_5   (5UL)

◆ PWM_CMPCFG_6

#define PWM_CMPCFG_6   (6UL)

◆ PWM_CMPCFG_7

#define PWM_CMPCFG_7   (7UL)

◆ PWM_CMPCFG_8

#define PWM_CMPCFG_8   (8UL)

◆ PWM_CMPCFG_9

#define PWM_CMPCFG_9   (9UL)

◆ PWM_CMPCFG_CMPCFG0

#define PWM_CMPCFG_CMPCFG0   (0UL)

◆ PWM_CMPCFG_CMPMODE_GET

#define PWM_CMPCFG_CMPMODE_GET (   x)    (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT)

◆ PWM_CMPCFG_CMPMODE_MASK

#define PWM_CMPCFG_CMPMODE_MASK   (0x2U)

◆ PWM_CMPCFG_CMPMODE_SET

#define PWM_CMPCFG_CMPMODE_SET (   x)    (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK)

◆ PWM_CMPCFG_CMPMODE_SHIFT

#define PWM_CMPCFG_CMPMODE_SHIFT   (1U)

◆ PWM_CMPCFG_CMPSHDWUPT_GET

#define PWM_CMPCFG_CMPSHDWUPT_GET (   x)    (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT)

◆ PWM_CMPCFG_CMPSHDWUPT_MASK

#define PWM_CMPCFG_CMPSHDWUPT_MASK   (0xCU)

◆ PWM_CMPCFG_CMPSHDWUPT_SET

#define PWM_CMPCFG_CMPSHDWUPT_SET (   x)    (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK)

◆ PWM_CMPCFG_CMPSHDWUPT_SHIFT

#define PWM_CMPCFG_CMPSHDWUPT_SHIFT   (2U)

◆ PWM_CMPCFG_XCNTCMPEN_GET

#define PWM_CMPCFG_XCNTCMPEN_GET (   x)    (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT)

◆ PWM_CMPCFG_XCNTCMPEN_MASK

#define PWM_CMPCFG_XCNTCMPEN_MASK   (0xF0U)

◆ PWM_CMPCFG_XCNTCMPEN_SET

#define PWM_CMPCFG_XCNTCMPEN_SET (   x)    (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK)

◆ PWM_CMPCFG_XCNTCMPEN_SHIFT

#define PWM_CMPCFG_XCNTCMPEN_SHIFT   (4U)

◆ PWM_CNT_CNT_GET

#define PWM_CNT_CNT_GET (   x)    (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT)

◆ PWM_CNT_CNT_MASK

#define PWM_CNT_CNT_MASK   (0xFFFFFF0UL)

◆ PWM_CNT_CNT_SHIFT

#define PWM_CNT_CNT_SHIFT   (4U)

◆ PWM_CNT_XCNT_GET

#define PWM_CNT_XCNT_GET (   x)    (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT)

◆ PWM_CNT_XCNT_MASK

#define PWM_CNT_XCNT_MASK   (0xF0000000UL)

◆ PWM_CNT_XCNT_SHIFT

#define PWM_CNT_XCNT_SHIFT   (28U)

◆ PWM_CNTCOPY_CNT_GET

#define PWM_CNTCOPY_CNT_GET (   x)    (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT)

◆ PWM_CNTCOPY_CNT_MASK

#define PWM_CNTCOPY_CNT_MASK   (0xFFFFFF0UL)

◆ PWM_CNTCOPY_CNT_SHIFT

#define PWM_CNTCOPY_CNT_SHIFT   (4U)

◆ PWM_CNTCOPY_XCNT_GET

#define PWM_CNTCOPY_XCNT_GET (   x)    (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT)

◆ PWM_CNTCOPY_XCNT_MASK

#define PWM_CNTCOPY_XCNT_MASK   (0xF0000000UL)

◆ PWM_CNTCOPY_XCNT_SHIFT

#define PWM_CNTCOPY_XCNT_SHIFT   (28U)

◆ PWM_DMAEN_CMPENX_GET

#define PWM_DMAEN_CMPENX_GET (   x)    (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT)

◆ PWM_DMAEN_CMPENX_MASK

#define PWM_DMAEN_CMPENX_MASK   (0xFFFFFFUL)

◆ PWM_DMAEN_CMPENX_SET

#define PWM_DMAEN_CMPENX_SET (   x)    (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK)

◆ PWM_DMAEN_CMPENX_SHIFT

#define PWM_DMAEN_CMPENX_SHIFT   (0U)

◆ PWM_DMAEN_FAULTEN_GET

#define PWM_DMAEN_FAULTEN_GET (   x)    (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT)

◆ PWM_DMAEN_FAULTEN_MASK

#define PWM_DMAEN_FAULTEN_MASK   (0x8000000UL)

◆ PWM_DMAEN_FAULTEN_SET

#define PWM_DMAEN_FAULTEN_SET (   x)    (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK)

◆ PWM_DMAEN_FAULTEN_SHIFT

#define PWM_DMAEN_FAULTEN_SHIFT   (27U)

◆ PWM_DMAEN_HALFRLDEN_GET

#define PWM_DMAEN_HALFRLDEN_GET (   x)    (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT)

◆ PWM_DMAEN_HALFRLDEN_MASK

#define PWM_DMAEN_HALFRLDEN_MASK   (0x2000000UL)

◆ PWM_DMAEN_HALFRLDEN_SET

#define PWM_DMAEN_HALFRLDEN_SET (   x)    (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK)

◆ PWM_DMAEN_HALFRLDEN_SHIFT

#define PWM_DMAEN_HALFRLDEN_SHIFT   (25U)

◆ PWM_DMAEN_RLDEN_GET

#define PWM_DMAEN_RLDEN_GET (   x)    (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT)

◆ PWM_DMAEN_RLDEN_MASK

#define PWM_DMAEN_RLDEN_MASK   (0x1000000UL)

◆ PWM_DMAEN_RLDEN_SET

#define PWM_DMAEN_RLDEN_SET (   x)    (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK)

◆ PWM_DMAEN_RLDEN_SHIFT

#define PWM_DMAEN_RLDEN_SHIFT   (24U)

◆ PWM_DMAEN_XRLDEN_GET

#define PWM_DMAEN_XRLDEN_GET (   x)    (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT)

◆ PWM_DMAEN_XRLDEN_MASK

#define PWM_DMAEN_XRLDEN_MASK   (0x4000000UL)

◆ PWM_DMAEN_XRLDEN_SET

#define PWM_DMAEN_XRLDEN_SET (   x)    (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK)

◆ PWM_DMAEN_XRLDEN_SHIFT

#define PWM_DMAEN_XRLDEN_SHIFT   (26U)

◆ PWM_FRCMD_FRCMD_GET

#define PWM_FRCMD_FRCMD_GET (   x)    (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT)

◆ PWM_FRCMD_FRCMD_MASK

#define PWM_FRCMD_FRCMD_MASK   (0xFFFFU)

◆ PWM_FRCMD_FRCMD_SET

#define PWM_FRCMD_FRCMD_SET (   x)    (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK)

◆ PWM_FRCMD_FRCMD_SHIFT

#define PWM_FRCMD_FRCMD_SHIFT   (0U)

◆ PWM_GCR_CEN_GET

#define PWM_GCR_CEN_GET (   x)    (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT)

◆ PWM_GCR_CEN_MASK

#define PWM_GCR_CEN_MASK   (0x80U)

◆ PWM_GCR_CEN_SET

#define PWM_GCR_CEN_SET (   x)    (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK)

◆ PWM_GCR_CEN_SHIFT

#define PWM_GCR_CEN_SHIFT   (7U)

◆ PWM_GCR_CMPSHDWSEL_GET

#define PWM_GCR_CMPSHDWSEL_GET (   x)    (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT)

◆ PWM_GCR_CMPSHDWSEL_MASK

#define PWM_GCR_CMPSHDWSEL_MASK   (0xF80000UL)

◆ PWM_GCR_CMPSHDWSEL_SET

#define PWM_GCR_CMPSHDWSEL_SET (   x)    (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK)

◆ PWM_GCR_CMPSHDWSEL_SHIFT

#define PWM_GCR_CMPSHDWSEL_SHIFT   (19U)

◆ PWM_GCR_DEBUGFAULT_GET

#define PWM_GCR_DEBUGFAULT_GET (   x)    (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT)

◆ PWM_GCR_DEBUGFAULT_MASK

#define PWM_GCR_DEBUGFAULT_MASK   (0x8000000UL)

◆ PWM_GCR_DEBUGFAULT_SET

#define PWM_GCR_DEBUGFAULT_SET (   x)    (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK)

◆ PWM_GCR_DEBUGFAULT_SHIFT

#define PWM_GCR_DEBUGFAULT_SHIFT   (27U)

◆ PWM_GCR_FAULTCLR_GET

#define PWM_GCR_FAULTCLR_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT)

◆ PWM_GCR_FAULTCLR_MASK

#define PWM_GCR_FAULTCLR_MASK   (0x40U)

◆ PWM_GCR_FAULTCLR_SET

#define PWM_GCR_FAULTCLR_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK)

◆ PWM_GCR_FAULTCLR_SHIFT

#define PWM_GCR_FAULTCLR_SHIFT   (6U)

◆ PWM_GCR_FAULTE0EN_GET

#define PWM_GCR_FAULTE0EN_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT)

◆ PWM_GCR_FAULTE0EN_MASK

#define PWM_GCR_FAULTE0EN_MASK   (0x800U)

◆ PWM_GCR_FAULTE0EN_SET

#define PWM_GCR_FAULTE0EN_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK)

◆ PWM_GCR_FAULTE0EN_SHIFT

#define PWM_GCR_FAULTE0EN_SHIFT   (11U)

◆ PWM_GCR_FAULTE1EN_GET

#define PWM_GCR_FAULTE1EN_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT)

◆ PWM_GCR_FAULTE1EN_MASK

#define PWM_GCR_FAULTE1EN_MASK   (0x1000U)

◆ PWM_GCR_FAULTE1EN_SET

#define PWM_GCR_FAULTE1EN_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK)

◆ PWM_GCR_FAULTE1EN_SHIFT

#define PWM_GCR_FAULTE1EN_SHIFT   (12U)

◆ PWM_GCR_FAULTEXPOL_GET

#define PWM_GCR_FAULTEXPOL_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT)

◆ PWM_GCR_FAULTEXPOL_MASK

#define PWM_GCR_FAULTEXPOL_MASK   (0x600U)

◆ PWM_GCR_FAULTEXPOL_SET

#define PWM_GCR_FAULTEXPOL_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK)

◆ PWM_GCR_FAULTEXPOL_SHIFT

#define PWM_GCR_FAULTEXPOL_SHIFT   (9U)

◆ PWM_GCR_FAULTI0EN_GET

#define PWM_GCR_FAULTI0EN_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT)

◆ PWM_GCR_FAULTI0EN_MASK

#define PWM_GCR_FAULTI0EN_MASK   (0x10000000UL)

◆ PWM_GCR_FAULTI0EN_SET

#define PWM_GCR_FAULTI0EN_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK)

◆ PWM_GCR_FAULTI0EN_SHIFT

#define PWM_GCR_FAULTI0EN_SHIFT   (28U)

◆ PWM_GCR_FAULTI1EN_GET

#define PWM_GCR_FAULTI1EN_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT)

◆ PWM_GCR_FAULTI1EN_MASK

#define PWM_GCR_FAULTI1EN_MASK   (0x20000000UL)

◆ PWM_GCR_FAULTI1EN_SET

#define PWM_GCR_FAULTI1EN_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK)

◆ PWM_GCR_FAULTI1EN_SHIFT

#define PWM_GCR_FAULTI1EN_SHIFT   (29U)

◆ PWM_GCR_FAULTI2EN_GET

#define PWM_GCR_FAULTI2EN_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT)

◆ PWM_GCR_FAULTI2EN_MASK

#define PWM_GCR_FAULTI2EN_MASK   (0x40000000UL)

◆ PWM_GCR_FAULTI2EN_SET

#define PWM_GCR_FAULTI2EN_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK)

◆ PWM_GCR_FAULTI2EN_SHIFT

#define PWM_GCR_FAULTI2EN_SHIFT   (30U)

◆ PWM_GCR_FAULTI3EN_GET

#define PWM_GCR_FAULTI3EN_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT)

◆ PWM_GCR_FAULTI3EN_MASK

#define PWM_GCR_FAULTI3EN_MASK   (0x80000000UL)

◆ PWM_GCR_FAULTI3EN_SET

#define PWM_GCR_FAULTI3EN_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK)

◆ PWM_GCR_FAULTI3EN_SHIFT

#define PWM_GCR_FAULTI3EN_SHIFT   (31U)

◆ PWM_GCR_FAULTRECEDG_GET

#define PWM_GCR_FAULTRECEDG_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT)

◆ PWM_GCR_FAULTRECEDG_MASK

#define PWM_GCR_FAULTRECEDG_MASK   (0x40000UL)

◆ PWM_GCR_FAULTRECEDG_SET

#define PWM_GCR_FAULTRECEDG_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK)

◆ PWM_GCR_FAULTRECEDG_SHIFT

#define PWM_GCR_FAULTRECEDG_SHIFT   (18U)

◆ PWM_GCR_FAULTRECHWSEL_GET

#define PWM_GCR_FAULTRECHWSEL_GET (   x)    (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT)

◆ PWM_GCR_FAULTRECHWSEL_MASK

#define PWM_GCR_FAULTRECHWSEL_MASK   (0x3E000UL)

◆ PWM_GCR_FAULTRECHWSEL_SET

#define PWM_GCR_FAULTRECHWSEL_SET (   x)    (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK)

◆ PWM_GCR_FAULTRECHWSEL_SHIFT

#define PWM_GCR_FAULTRECHWSEL_SHIFT   (13U)

◆ PWM_GCR_FRCPOL_GET

#define PWM_GCR_FRCPOL_GET (   x)    (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT)

◆ PWM_GCR_FRCPOL_MASK

#define PWM_GCR_FRCPOL_MASK   (0x4000000UL)

◆ PWM_GCR_FRCPOL_SET

#define PWM_GCR_FRCPOL_SET (   x)    (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK)

◆ PWM_GCR_FRCPOL_SHIFT

#define PWM_GCR_FRCPOL_SHIFT   (26U)

◆ PWM_GCR_FRCTIME_GET

#define PWM_GCR_FRCTIME_GET (   x)    (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT)

◆ PWM_GCR_FRCTIME_MASK

#define PWM_GCR_FRCTIME_MASK   (0x6U)

◆ PWM_GCR_FRCTIME_SET

#define PWM_GCR_FRCTIME_SET (   x)    (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK)

◆ PWM_GCR_FRCTIME_SHIFT

#define PWM_GCR_FRCTIME_SHIFT   (1U)

◆ PWM_GCR_HWSHDWEDG_GET

#define PWM_GCR_HWSHDWEDG_GET (   x)    (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT)

◆ PWM_GCR_HWSHDWEDG_MASK

#define PWM_GCR_HWSHDWEDG_MASK   (0x1000000UL)

◆ PWM_GCR_HWSHDWEDG_SET

#define PWM_GCR_HWSHDWEDG_SET (   x)    (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK)

◆ PWM_GCR_HWSHDWEDG_SHIFT

#define PWM_GCR_HWSHDWEDG_SHIFT   (24U)

◆ PWM_GCR_RLDSYNCEN_GET

#define PWM_GCR_RLDSYNCEN_GET (   x)    (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT)

◆ PWM_GCR_RLDSYNCEN_MASK

#define PWM_GCR_RLDSYNCEN_MASK   (0x100U)

◆ PWM_GCR_RLDSYNCEN_SET

#define PWM_GCR_RLDSYNCEN_SET (   x)    (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK)

◆ PWM_GCR_RLDSYNCEN_SHIFT

#define PWM_GCR_RLDSYNCEN_SHIFT   (8U)

◆ PWM_GCR_SWFRC_GET

#define PWM_GCR_SWFRC_GET (   x)    (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT)

◆ PWM_GCR_SWFRC_MASK

#define PWM_GCR_SWFRC_MASK   (0x1U)

◆ PWM_GCR_SWFRC_SET

#define PWM_GCR_SWFRC_SET (   x)    (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK)

◆ PWM_GCR_SWFRC_SHIFT

#define PWM_GCR_SWFRC_SHIFT   (0U)

◆ PWM_GCR_TIMERRESET_GET

#define PWM_GCR_TIMERRESET_GET (   x)    (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT)

◆ PWM_GCR_TIMERRESET_MASK

#define PWM_GCR_TIMERRESET_MASK   (0x8U)

◆ PWM_GCR_TIMERRESET_SET

#define PWM_GCR_TIMERRESET_SET (   x)    (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK)

◆ PWM_GCR_TIMERRESET_SHIFT

#define PWM_GCR_TIMERRESET_SHIFT   (3U)

◆ PWM_GCR_XRLDSYNCEN_GET

#define PWM_GCR_XRLDSYNCEN_GET (   x)    (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT)

◆ PWM_GCR_XRLDSYNCEN_MASK

#define PWM_GCR_XRLDSYNCEN_MASK   (0x20U)

◆ PWM_GCR_XRLDSYNCEN_SET

#define PWM_GCR_XRLDSYNCEN_SET (   x)    (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK)

◆ PWM_GCR_XRLDSYNCEN_SHIFT

#define PWM_GCR_XRLDSYNCEN_SHIFT   (5U)

◆ PWM_IRQEN_CMPIRQEX_GET

#define PWM_IRQEN_CMPIRQEX_GET (   x)    (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT)

◆ PWM_IRQEN_CMPIRQEX_MASK

#define PWM_IRQEN_CMPIRQEX_MASK   (0xFFFFFFUL)

◆ PWM_IRQEN_CMPIRQEX_SET

#define PWM_IRQEN_CMPIRQEX_SET (   x)    (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK)

◆ PWM_IRQEN_CMPIRQEX_SHIFT

#define PWM_IRQEN_CMPIRQEX_SHIFT   (0U)

◆ PWM_IRQEN_FAULTIRQE_GET

#define PWM_IRQEN_FAULTIRQE_GET (   x)    (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT)

◆ PWM_IRQEN_FAULTIRQE_MASK

#define PWM_IRQEN_FAULTIRQE_MASK   (0x8000000UL)

◆ PWM_IRQEN_FAULTIRQE_SET

#define PWM_IRQEN_FAULTIRQE_SET (   x)    (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK)

◆ PWM_IRQEN_FAULTIRQE_SHIFT

#define PWM_IRQEN_FAULTIRQE_SHIFT   (27U)

◆ PWM_IRQEN_HALFRLDIRQE_GET

#define PWM_IRQEN_HALFRLDIRQE_GET (   x)    (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT)

◆ PWM_IRQEN_HALFRLDIRQE_MASK

#define PWM_IRQEN_HALFRLDIRQE_MASK   (0x2000000UL)

◆ PWM_IRQEN_HALFRLDIRQE_SET

#define PWM_IRQEN_HALFRLDIRQE_SET (   x)    (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK)

◆ PWM_IRQEN_HALFRLDIRQE_SHIFT

#define PWM_IRQEN_HALFRLDIRQE_SHIFT   (25U)

◆ PWM_IRQEN_RLDIRQE_GET

#define PWM_IRQEN_RLDIRQE_GET (   x)    (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT)

◆ PWM_IRQEN_RLDIRQE_MASK

#define PWM_IRQEN_RLDIRQE_MASK   (0x1000000UL)

◆ PWM_IRQEN_RLDIRQE_SET

#define PWM_IRQEN_RLDIRQE_SET (   x)    (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK)

◆ PWM_IRQEN_RLDIRQE_SHIFT

#define PWM_IRQEN_RLDIRQE_SHIFT   (24U)

◆ PWM_IRQEN_XRLDIRQE_GET

#define PWM_IRQEN_XRLDIRQE_GET (   x)    (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT)

◆ PWM_IRQEN_XRLDIRQE_MASK

#define PWM_IRQEN_XRLDIRQE_MASK   (0x4000000UL)

◆ PWM_IRQEN_XRLDIRQE_SET

#define PWM_IRQEN_XRLDIRQE_SET (   x)    (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK)

◆ PWM_IRQEN_XRLDIRQE_SHIFT

#define PWM_IRQEN_XRLDIRQE_SHIFT   (26U)

◆ PWM_PWMCFG_0

#define PWM_PWMCFG_0   (0UL)

◆ PWM_PWMCFG_1

#define PWM_PWMCFG_1   (1UL)

◆ PWM_PWMCFG_2

#define PWM_PWMCFG_2   (2UL)

◆ PWM_PWMCFG_3

#define PWM_PWMCFG_3   (3UL)

◆ PWM_PWMCFG_4

#define PWM_PWMCFG_4   (4UL)

◆ PWM_PWMCFG_5

#define PWM_PWMCFG_5   (5UL)

◆ PWM_PWMCFG_6

#define PWM_PWMCFG_6   (6UL)

◆ PWM_PWMCFG_7

#define PWM_PWMCFG_7   (7UL)

◆ PWM_PWMCFG_DEADAREA_GET

#define PWM_PWMCFG_DEADAREA_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT)

◆ PWM_PWMCFG_DEADAREA_MASK

#define PWM_PWMCFG_DEADAREA_MASK   (0xFFFFFUL)

◆ PWM_PWMCFG_DEADAREA_SET

#define PWM_PWMCFG_DEADAREA_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK)

◆ PWM_PWMCFG_DEADAREA_SHIFT

#define PWM_PWMCFG_DEADAREA_SHIFT   (0U)

◆ PWM_PWMCFG_FAULTMODE_GET

#define PWM_PWMCFG_FAULTMODE_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT)

◆ PWM_PWMCFG_FAULTMODE_MASK

#define PWM_PWMCFG_FAULTMODE_MASK   (0x3000000UL)

◆ PWM_PWMCFG_FAULTMODE_SET

#define PWM_PWMCFG_FAULTMODE_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK)

◆ PWM_PWMCFG_FAULTMODE_SHIFT

#define PWM_PWMCFG_FAULTMODE_SHIFT   (24U)

◆ PWM_PWMCFG_FAULTRECTIME_GET

#define PWM_PWMCFG_FAULTRECTIME_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT)

◆ PWM_PWMCFG_FAULTRECTIME_MASK

#define PWM_PWMCFG_FAULTRECTIME_MASK   (0xC00000UL)

◆ PWM_PWMCFG_FAULTRECTIME_SET

#define PWM_PWMCFG_FAULTRECTIME_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK)

◆ PWM_PWMCFG_FAULTRECTIME_SHIFT

#define PWM_PWMCFG_FAULTRECTIME_SHIFT   (22U)

◆ PWM_PWMCFG_FRCSHDWUPT_GET

#define PWM_PWMCFG_FRCSHDWUPT_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT)

◆ PWM_PWMCFG_FRCSHDWUPT_MASK

#define PWM_PWMCFG_FRCSHDWUPT_MASK   (0xC000000UL)

◆ PWM_PWMCFG_FRCSHDWUPT_SET

#define PWM_PWMCFG_FRCSHDWUPT_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK)

◆ PWM_PWMCFG_FRCSHDWUPT_SHIFT

#define PWM_PWMCFG_FRCSHDWUPT_SHIFT   (26U)

◆ PWM_PWMCFG_FRCSRCSEL_GET

#define PWM_PWMCFG_FRCSRCSEL_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT)

◆ PWM_PWMCFG_FRCSRCSEL_MASK

#define PWM_PWMCFG_FRCSRCSEL_MASK   (0x200000UL)

◆ PWM_PWMCFG_FRCSRCSEL_SET

#define PWM_PWMCFG_FRCSRCSEL_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK)

◆ PWM_PWMCFG_FRCSRCSEL_SHIFT

#define PWM_PWMCFG_FRCSRCSEL_SHIFT   (21U)

◆ PWM_PWMCFG_OEN_GET

#define PWM_PWMCFG_OEN_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT)

◆ PWM_PWMCFG_OEN_MASK

#define PWM_PWMCFG_OEN_MASK   (0x10000000UL)

◆ PWM_PWMCFG_OEN_SET

#define PWM_PWMCFG_OEN_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK)

◆ PWM_PWMCFG_OEN_SHIFT

#define PWM_PWMCFG_OEN_SHIFT   (28U)

◆ PWM_PWMCFG_PAIR_GET

#define PWM_PWMCFG_PAIR_GET (   x)    (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT)

◆ PWM_PWMCFG_PAIR_MASK

#define PWM_PWMCFG_PAIR_MASK   (0x100000UL)

◆ PWM_PWMCFG_PAIR_SET

#define PWM_PWMCFG_PAIR_SET (   x)    (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK)

◆ PWM_PWMCFG_PAIR_SHIFT

#define PWM_PWMCFG_PAIR_SHIFT   (20U)

◆ PWM_RLD_RLD_GET

#define PWM_RLD_RLD_GET (   x)    (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT)

◆ PWM_RLD_RLD_MASK

#define PWM_RLD_RLD_MASK   (0xFFFFFF0UL)

◆ PWM_RLD_RLD_SET

#define PWM_RLD_RLD_SET (   x)    (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK)

◆ PWM_RLD_RLD_SHIFT

#define PWM_RLD_RLD_SHIFT   (4U)

◆ PWM_RLD_XRLD_GET

#define PWM_RLD_XRLD_GET (   x)    (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT)

◆ PWM_RLD_XRLD_MASK

#define PWM_RLD_XRLD_MASK   (0xF0000000UL)

◆ PWM_RLD_XRLD_SET

#define PWM_RLD_XRLD_SET (   x)    (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK)

◆ PWM_RLD_XRLD_SHIFT

#define PWM_RLD_XRLD_SHIFT   (28U)

◆ PWM_SHCR_CNTSHDWSEL_GET

#define PWM_SHCR_CNTSHDWSEL_GET (   x)    (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT)

◆ PWM_SHCR_CNTSHDWSEL_MASK

#define PWM_SHCR_CNTSHDWSEL_MASK   (0xF8U)

◆ PWM_SHCR_CNTSHDWSEL_SET

#define PWM_SHCR_CNTSHDWSEL_SET (   x)    (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK)

◆ PWM_SHCR_CNTSHDWSEL_SHIFT

#define PWM_SHCR_CNTSHDWSEL_SHIFT   (3U)

◆ PWM_SHCR_CNTSHDWUPT_GET

#define PWM_SHCR_CNTSHDWUPT_GET (   x)    (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT)

◆ PWM_SHCR_CNTSHDWUPT_MASK

#define PWM_SHCR_CNTSHDWUPT_MASK   (0x6U)

◆ PWM_SHCR_CNTSHDWUPT_SET

#define PWM_SHCR_CNTSHDWUPT_SET (   x)    (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK)

◆ PWM_SHCR_CNTSHDWUPT_SHIFT

#define PWM_SHCR_CNTSHDWUPT_SHIFT   (1U)

◆ PWM_SHCR_FRCSHDWSEL_GET

#define PWM_SHCR_FRCSHDWSEL_GET (   x)    (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT)

◆ PWM_SHCR_FRCSHDWSEL_MASK

#define PWM_SHCR_FRCSHDWSEL_MASK   (0x1F00U)

◆ PWM_SHCR_FRCSHDWSEL_SET

#define PWM_SHCR_FRCSHDWSEL_SET (   x)    (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK)

◆ PWM_SHCR_FRCSHDWSEL_SHIFT

#define PWM_SHCR_FRCSHDWSEL_SHIFT   (8U)

◆ PWM_SHCR_SHLKEN_GET

#define PWM_SHCR_SHLKEN_GET (   x)    (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT)

◆ PWM_SHCR_SHLKEN_MASK

#define PWM_SHCR_SHLKEN_MASK   (0x1U)

◆ PWM_SHCR_SHLKEN_SET

#define PWM_SHCR_SHLKEN_SET (   x)    (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK)

◆ PWM_SHCR_SHLKEN_SHIFT

#define PWM_SHCR_SHLKEN_SHIFT   (0U)

◆ PWM_SHLK_SHLK_GET

#define PWM_SHLK_SHLK_GET (   x)    (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT)

◆ PWM_SHLK_SHLK_MASK

#define PWM_SHLK_SHLK_MASK   (0x80000000UL)

◆ PWM_SHLK_SHLK_SET

#define PWM_SHLK_SHLK_SET (   x)    (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK)

◆ PWM_SHLK_SHLK_SHIFT

#define PWM_SHLK_SHLK_SHIFT   (31U)

◆ PWM_SR_CMPFX_GET

#define PWM_SR_CMPFX_GET (   x)    (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT)

◆ PWM_SR_CMPFX_MASK

#define PWM_SR_CMPFX_MASK   (0xFFFFFFUL)

◆ PWM_SR_CMPFX_SET

#define PWM_SR_CMPFX_SET (   x)    (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK)

◆ PWM_SR_CMPFX_SHIFT

#define PWM_SR_CMPFX_SHIFT   (0U)

◆ PWM_SR_FAULTF_GET

#define PWM_SR_FAULTF_GET (   x)    (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT)

◆ PWM_SR_FAULTF_MASK

#define PWM_SR_FAULTF_MASK   (0x8000000UL)

◆ PWM_SR_FAULTF_SET

#define PWM_SR_FAULTF_SET (   x)    (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK)

◆ PWM_SR_FAULTF_SHIFT

#define PWM_SR_FAULTF_SHIFT   (27U)

◆ PWM_SR_HALFRLDF_GET

#define PWM_SR_HALFRLDF_GET (   x)    (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT)

◆ PWM_SR_HALFRLDF_MASK

#define PWM_SR_HALFRLDF_MASK   (0x2000000UL)

◆ PWM_SR_HALFRLDF_SET

#define PWM_SR_HALFRLDF_SET (   x)    (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK)

◆ PWM_SR_HALFRLDF_SHIFT

#define PWM_SR_HALFRLDF_SHIFT   (25U)

◆ PWM_SR_RLDF_GET

#define PWM_SR_RLDF_GET (   x)    (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT)

◆ PWM_SR_RLDF_MASK

#define PWM_SR_RLDF_MASK   (0x1000000UL)

◆ PWM_SR_RLDF_SET

#define PWM_SR_RLDF_SET (   x)    (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK)

◆ PWM_SR_RLDF_SHIFT

#define PWM_SR_RLDF_SHIFT   (24U)

◆ PWM_SR_XRLDF_GET

#define PWM_SR_XRLDF_GET (   x)    (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT)

◆ PWM_SR_XRLDF_MASK

#define PWM_SR_XRLDF_MASK   (0x4000000UL)

◆ PWM_SR_XRLDF_SET

#define PWM_SR_XRLDF_SET (   x)    (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK)

◆ PWM_SR_XRLDF_SHIFT

#define PWM_SR_XRLDF_SHIFT   (26U)

◆ PWM_STA_STA_GET

#define PWM_STA_STA_GET (   x)    (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT)

◆ PWM_STA_STA_MASK

#define PWM_STA_STA_MASK   (0xFFFFFF0UL)

◆ PWM_STA_STA_SET

#define PWM_STA_STA_SET (   x)    (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK)

◆ PWM_STA_STA_SHIFT

#define PWM_STA_STA_SHIFT   (4U)

◆ PWM_STA_XSTA_GET

#define PWM_STA_XSTA_GET (   x)    (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT)

◆ PWM_STA_XSTA_MASK

#define PWM_STA_XSTA_MASK   (0xF0000000UL)

◆ PWM_STA_XSTA_SET

#define PWM_STA_XSTA_SET (   x)    (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK)

◆ PWM_STA_XSTA_SHIFT

#define PWM_STA_XSTA_SHIFT   (28U)

◆ PWM_UNLK_SHUNLK_GET

#define PWM_UNLK_SHUNLK_GET (   x)    (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT)

◆ PWM_UNLK_SHUNLK_MASK

#define PWM_UNLK_SHUNLK_MASK   (0xFFFFFFFFUL)

◆ PWM_UNLK_SHUNLK_SET

#define PWM_UNLK_SHUNLK_SET (   x)    (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK)

◆ PWM_UNLK_SHUNLK_SHIFT

#define PWM_UNLK_SHUNLK_SHIFT   (0U)