hpm_ptpc_regs.h File Reference

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Data Structures
struct	PTPC_Type

Macros
#define	PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK   (0x200U)
#define	PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT   (9U)
#define	PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK)
#define	PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK   (0x100U)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT   (8U)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK   (0x80U)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT   (7U)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK   (0x40U)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT   (6U)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK)
#define	PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT)
#define	PTPC_PTPC_CTRL0_COMP_EN_MASK   (0x10U)
#define	PTPC_PTPC_CTRL0_COMP_EN_SHIFT   (4U)
#define	PTPC_PTPC_CTRL0_COMP_EN_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK)
#define	PTPC_PTPC_CTRL0_COMP_EN_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT)
#define	PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK   (0x8U)
#define	PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT   (3U)
#define	PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK)
#define	PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT)
#define	PTPC_PTPC_CTRL0_INIT_TIMER_MASK   (0x4U)
#define	PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT   (2U)
#define	PTPC_PTPC_CTRL0_INIT_TIMER_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK)
#define	PTPC_PTPC_CTRL0_INIT_TIMER_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT)
#define	PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK   (0x2U)
#define	PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT   (1U)
#define	PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK)
#define	PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT)
#define	PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK   (0x1U)
#define	PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT   (0U)
#define	PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK)
#define	PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT)
#define	PTPC_PTPC_CTRL1_SS_INCR_MASK   (0xFFU)
#define	PTPC_PTPC_CTRL1_SS_INCR_SHIFT   (0U)
#define	PTPC_PTPC_CTRL1_SS_INCR_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK)
#define	PTPC_PTPC_CTRL1_SS_INCR_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT)
#define	PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT   (0U)
#define	PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT)
#define	PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT   (0U)
#define	PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT)
#define	PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT   (0U)
#define	PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x)   (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK)
#define	PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT)
#define	PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK   (0x80000000UL)
#define	PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT   (31U)
#define	PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x)   (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK)
#define	PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT)
#define	PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK   (0x7FFFFFFFUL)
#define	PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT   (0U)
#define	PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x)   (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK)
#define	PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT)
#define	PTPC_PTPC_ADDEND_ADDEND_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_ADDEND_ADDEND_SHIFT   (0U)
#define	PTPC_PTPC_ADDEND_ADDEND_SET(x)   (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK)
#define	PTPC_PTPC_ADDEND_ADDEND_GET(x)   (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT)
#define	PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT   (0U)
#define	PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x)   (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK)
#define	PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT)
#define	PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT   (0U)
#define	PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x)   (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK)
#define	PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x)   (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT)
#define	PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK   (0xFU)
#define	PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT   (0U)
#define	PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x)   (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK)
#define	PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x)   (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT)
#define	PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT   (0U)
#define	PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT)
#define	PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK   (0xFFFFFFFFUL)
#define	PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT   (0U)
#define	PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK)
#define	PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT)
#define	PTPC_TIME_SEL_CAN3_TIME_SEL_MASK   (0x8U)
#define	PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT   (3U)
#define	PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x)   (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK)
#define	PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x)   (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT)
#define	PTPC_TIME_SEL_CAN2_TIME_SEL_MASK   (0x4U)
#define	PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT   (2U)
#define	PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x)   (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK)
#define	PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x)   (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT)
#define	PTPC_TIME_SEL_CAN1_TIME_SEL_MASK   (0x2U)
#define	PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT   (1U)
#define	PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x)   (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK)
#define	PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x)   (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT)
#define	PTPC_TIME_SEL_CAN0_TIME_SEL_MASK   (0x1U)
#define	PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT   (0U)
#define	PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x)   (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK)
#define	PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x)   (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT)
#define	PTPC_INT_STS_COMP_INT_STS1_MASK   (0x40000UL)
#define	PTPC_INT_STS_COMP_INT_STS1_SHIFT   (18U)
#define	PTPC_INT_STS_COMP_INT_STS1_SET(x)   (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK)
#define	PTPC_INT_STS_COMP_INT_STS1_GET(x)   (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT)
#define	PTPC_INT_STS_CAPTURE_INT_STS1_MASK   (0x20000UL)
#define	PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT   (17U)
#define	PTPC_INT_STS_CAPTURE_INT_STS1_SET(x)   (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK)
#define	PTPC_INT_STS_CAPTURE_INT_STS1_GET(x)   (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT)
#define	PTPC_INT_STS_PPS_INT_STS1_MASK   (0x10000UL)
#define	PTPC_INT_STS_PPS_INT_STS1_SHIFT   (16U)
#define	PTPC_INT_STS_PPS_INT_STS1_SET(x)   (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK)
#define	PTPC_INT_STS_PPS_INT_STS1_GET(x)   (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT)
#define	PTPC_INT_STS_COMP_INT_STS0_MASK   (0x4U)
#define	PTPC_INT_STS_COMP_INT_STS0_SHIFT   (2U)
#define	PTPC_INT_STS_COMP_INT_STS0_SET(x)   (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK)
#define	PTPC_INT_STS_COMP_INT_STS0_GET(x)   (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT)
#define	PTPC_INT_STS_CAPTURE_INT_STS0_MASK   (0x2U)
#define	PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT   (1U)
#define	PTPC_INT_STS_CAPTURE_INT_STS0_SET(x)   (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK)
#define	PTPC_INT_STS_CAPTURE_INT_STS0_GET(x)   (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT)
#define	PTPC_INT_STS_PPS_INT_STS0_MASK   (0x1U)
#define	PTPC_INT_STS_PPS_INT_STS0_SHIFT   (0U)
#define	PTPC_INT_STS_PPS_INT_STS0_SET(x)   (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK)
#define	PTPC_INT_STS_PPS_INT_STS0_GET(x)   (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT)
#define	PTPC_INT_EN_COMP_INT_STS1_MASK   (0x40000UL)
#define	PTPC_INT_EN_COMP_INT_STS1_SHIFT   (18U)
#define	PTPC_INT_EN_COMP_INT_STS1_SET(x)   (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK)
#define	PTPC_INT_EN_COMP_INT_STS1_GET(x)   (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT)
#define	PTPC_INT_EN_CAPTURE_INT_STS1_MASK   (0x20000UL)
#define	PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT   (17U)
#define	PTPC_INT_EN_CAPTURE_INT_STS1_SET(x)   (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK)
#define	PTPC_INT_EN_CAPTURE_INT_STS1_GET(x)   (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT)
#define	PTPC_INT_EN_PPS_INT_STS1_MASK   (0x10000UL)
#define	PTPC_INT_EN_PPS_INT_STS1_SHIFT   (16U)
#define	PTPC_INT_EN_PPS_INT_STS1_SET(x)   (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK)
#define	PTPC_INT_EN_PPS_INT_STS1_GET(x)   (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT)
#define	PTPC_INT_EN_COMP_INT_STS0_MASK   (0x4U)
#define	PTPC_INT_EN_COMP_INT_STS0_SHIFT   (2U)
#define	PTPC_INT_EN_COMP_INT_STS0_SET(x)   (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK)
#define	PTPC_INT_EN_COMP_INT_STS0_GET(x)   (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT)
#define	PTPC_INT_EN_CAPTURE_INT_STS0_MASK   (0x2U)
#define	PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT   (1U)
#define	PTPC_INT_EN_CAPTURE_INT_STS0_SET(x)   (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK)
#define	PTPC_INT_EN_CAPTURE_INT_STS0_GET(x)   (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT)
#define	PTPC_INT_EN_PPS_INT_STS0_MASK   (0x1U)
#define	PTPC_INT_EN_PPS_INT_STS0_SHIFT   (0U)
#define	PTPC_INT_EN_PPS_INT_STS0_SET(x)   (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK)
#define	PTPC_INT_EN_PPS_INT_STS0_GET(x)   (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK   (0xFC000000UL)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT   (26U)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK   (0x3F00000UL)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT   (20U)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK   (0xFC000UL)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT   (14U)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK   (0x3F00U)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT   (8U)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x)   (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK)
#define	PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x)   (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT)
#define	PTPC_PTPC_0   (0UL)
#define	PTPC_PTPC_1   (1UL)

Macro Definition Documentation

PTPC_INT_EN_CAPTURE_INT_STS0_GET

#define PTPC_INT_EN_CAPTURE_INT_STS0_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT)

PTPC_INT_EN_CAPTURE_INT_STS0_MASK

#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK   (0x2U)

PTPC_INT_EN_CAPTURE_INT_STS0_SET

#define PTPC_INT_EN_CAPTURE_INT_STS0_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK)

PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT

#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT   (1U)

PTPC_INT_EN_CAPTURE_INT_STS1_GET

#define PTPC_INT_EN_CAPTURE_INT_STS1_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT)

PTPC_INT_EN_CAPTURE_INT_STS1_MASK

#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK   (0x20000UL)

PTPC_INT_EN_CAPTURE_INT_STS1_SET

#define PTPC_INT_EN_CAPTURE_INT_STS1_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK)

PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT

#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT   (17U)

PTPC_INT_EN_COMP_INT_STS0_GET

#define PTPC_INT_EN_COMP_INT_STS0_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT)

PTPC_INT_EN_COMP_INT_STS0_MASK

#define PTPC_INT_EN_COMP_INT_STS0_MASK   (0x4U)

PTPC_INT_EN_COMP_INT_STS0_SET

#define PTPC_INT_EN_COMP_INT_STS0_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK)

PTPC_INT_EN_COMP_INT_STS0_SHIFT

#define PTPC_INT_EN_COMP_INT_STS0_SHIFT   (2U)

PTPC_INT_EN_COMP_INT_STS1_GET

#define PTPC_INT_EN_COMP_INT_STS1_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT)

PTPC_INT_EN_COMP_INT_STS1_MASK

#define PTPC_INT_EN_COMP_INT_STS1_MASK   (0x40000UL)

PTPC_INT_EN_COMP_INT_STS1_SET

#define PTPC_INT_EN_COMP_INT_STS1_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK)

PTPC_INT_EN_COMP_INT_STS1_SHIFT

#define PTPC_INT_EN_COMP_INT_STS1_SHIFT   (18U)

PTPC_INT_EN_PPS_INT_STS0_GET

#define PTPC_INT_EN_PPS_INT_STS0_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT)

PTPC_INT_EN_PPS_INT_STS0_MASK

#define PTPC_INT_EN_PPS_INT_STS0_MASK   (0x1U)

PTPC_INT_EN_PPS_INT_STS0_SET

#define PTPC_INT_EN_PPS_INT_STS0_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK)

PTPC_INT_EN_PPS_INT_STS0_SHIFT

#define PTPC_INT_EN_PPS_INT_STS0_SHIFT   (0U)

PTPC_INT_EN_PPS_INT_STS1_GET

#define PTPC_INT_EN_PPS_INT_STS1_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT)

PTPC_INT_EN_PPS_INT_STS1_MASK

#define PTPC_INT_EN_PPS_INT_STS1_MASK   (0x10000UL)

PTPC_INT_EN_PPS_INT_STS1_SET

#define PTPC_INT_EN_PPS_INT_STS1_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK)

PTPC_INT_EN_PPS_INT_STS1_SHIFT

#define PTPC_INT_EN_PPS_INT_STS1_SHIFT   (16U)

PTPC_INT_STS_CAPTURE_INT_STS0_GET

#define PTPC_INT_STS_CAPTURE_INT_STS0_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT)

PTPC_INT_STS_CAPTURE_INT_STS0_MASK

#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK   (0x2U)

PTPC_INT_STS_CAPTURE_INT_STS0_SET

#define PTPC_INT_STS_CAPTURE_INT_STS0_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK)

PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT

#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT   (1U)

PTPC_INT_STS_CAPTURE_INT_STS1_GET

#define PTPC_INT_STS_CAPTURE_INT_STS1_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT)

PTPC_INT_STS_CAPTURE_INT_STS1_MASK

#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK   (0x20000UL)

PTPC_INT_STS_CAPTURE_INT_STS1_SET

#define PTPC_INT_STS_CAPTURE_INT_STS1_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK)

PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT

#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT   (17U)

PTPC_INT_STS_COMP_INT_STS0_GET

#define PTPC_INT_STS_COMP_INT_STS0_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT)

PTPC_INT_STS_COMP_INT_STS0_MASK

#define PTPC_INT_STS_COMP_INT_STS0_MASK   (0x4U)

PTPC_INT_STS_COMP_INT_STS0_SET

#define PTPC_INT_STS_COMP_INT_STS0_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK)

PTPC_INT_STS_COMP_INT_STS0_SHIFT

#define PTPC_INT_STS_COMP_INT_STS0_SHIFT   (2U)

PTPC_INT_STS_COMP_INT_STS1_GET

#define PTPC_INT_STS_COMP_INT_STS1_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT)

PTPC_INT_STS_COMP_INT_STS1_MASK

#define PTPC_INT_STS_COMP_INT_STS1_MASK   (0x40000UL)

PTPC_INT_STS_COMP_INT_STS1_SET

#define PTPC_INT_STS_COMP_INT_STS1_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK)

PTPC_INT_STS_COMP_INT_STS1_SHIFT

#define PTPC_INT_STS_COMP_INT_STS1_SHIFT   (18U)

PTPC_INT_STS_PPS_INT_STS0_GET

#define PTPC_INT_STS_PPS_INT_STS0_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT)

PTPC_INT_STS_PPS_INT_STS0_MASK

#define PTPC_INT_STS_PPS_INT_STS0_MASK   (0x1U)

PTPC_INT_STS_PPS_INT_STS0_SET

#define PTPC_INT_STS_PPS_INT_STS0_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK)

PTPC_INT_STS_PPS_INT_STS0_SHIFT

#define PTPC_INT_STS_PPS_INT_STS0_SHIFT   (0U)

PTPC_INT_STS_PPS_INT_STS1_GET

#define PTPC_INT_STS_PPS_INT_STS1_GET

(

x

)

(((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT)

PTPC_INT_STS_PPS_INT_STS1_MASK

#define PTPC_INT_STS_PPS_INT_STS1_MASK   (0x10000UL)

PTPC_INT_STS_PPS_INT_STS1_SET

#define PTPC_INT_STS_PPS_INT_STS1_SET

(

x

)

(((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK)

PTPC_INT_STS_PPS_INT_STS1_SHIFT

#define PTPC_INT_STS_PPS_INT_STS1_SHIFT   (16U)

PTPC_PTPC_0

#define PTPC_PTPC_0   (0UL)

PTPC_PTPC_1

#define PTPC_PTPC_1   (1UL)

PTPC_PTPC_ADDEND_ADDEND_GET

#define PTPC_PTPC_ADDEND_ADDEND_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT)

PTPC_PTPC_ADDEND_ADDEND_MASK

#define PTPC_PTPC_ADDEND_ADDEND_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_ADDEND_ADDEND_SET

#define PTPC_PTPC_ADDEND_ADDEND_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK)

PTPC_PTPC_ADDEND_ADDEND_SHIFT

#define PTPC_PTPC_ADDEND_ADDEND_SHIFT   (0U)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK   (0x3F00U)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT   (8U)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK   (0xFC000UL)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT   (14U)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK   (0x3F00000UL)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT   (20U)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK   (0xFC000000UL)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK)

PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT

#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT   (26U)

PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET

#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT)

PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK

#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT

#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT   (0U)

PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET

#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT)

PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK

#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET

#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK)

PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT

#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT   (0U)

PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET

#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT)

PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK

#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK   (0x100U)

PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET

#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK)

PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT

#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT   (8U)

PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET

#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT)

PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK

#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK   (0x40U)

PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET

#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK)

PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT

#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT   (6U)

PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET

#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT)

PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK

#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK   (0x80U)

PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET

#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK)

PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT

#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT   (7U)

PTPC_PTPC_CTRL0_COMP_EN_GET

#define PTPC_PTPC_CTRL0_COMP_EN_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT)

PTPC_PTPC_CTRL0_COMP_EN_MASK

#define PTPC_PTPC_CTRL0_COMP_EN_MASK   (0x10U)

PTPC_PTPC_CTRL0_COMP_EN_SET

#define PTPC_PTPC_CTRL0_COMP_EN_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK)

PTPC_PTPC_CTRL0_COMP_EN_SHIFT

#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT   (4U)

PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET

#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT)

PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK

#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK   (0x2U)

PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET

#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK)

PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT

#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT   (1U)

PTPC_PTPC_CTRL0_INIT_TIMER_GET

#define PTPC_PTPC_CTRL0_INIT_TIMER_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT)

PTPC_PTPC_CTRL0_INIT_TIMER_MASK

#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK   (0x4U)

PTPC_PTPC_CTRL0_INIT_TIMER_SET

#define PTPC_PTPC_CTRL0_INIT_TIMER_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK)

PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT

#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT   (2U)

PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET

#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT)

PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK

#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK   (0x200U)

PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET

#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK)

PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT

#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT   (9U)

PTPC_PTPC_CTRL0_TIMER_ENABLE_GET

#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT)

PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK

#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK   (0x1U)

PTPC_PTPC_CTRL0_TIMER_ENABLE_SET

#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK)

PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT

#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT   (0U)

PTPC_PTPC_CTRL0_UPDATE_TIMER_GET

#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT)

PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK

#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK   (0x8U)

PTPC_PTPC_CTRL0_UPDATE_TIMER_SET

#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK)

PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT

#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT   (3U)

PTPC_PTPC_CTRL1_SS_INCR_GET

#define PTPC_PTPC_CTRL1_SS_INCR_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT)

PTPC_PTPC_CTRL1_SS_INCR_MASK

#define PTPC_PTPC_CTRL1_SS_INCR_MASK   (0xFFU)

PTPC_PTPC_CTRL1_SS_INCR_SET

#define PTPC_PTPC_CTRL1_SS_INCR_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK)

PTPC_PTPC_CTRL1_SS_INCR_SHIFT

#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT   (0U)

PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET

#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT)

PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK

#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK   (0xFU)

PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET

#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK)

PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT

#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT   (0U)

PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET

#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT)

PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK

#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET

#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK)

PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT

#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT   (0U)

PTPC_PTPC_TARL_TARGET_TIME_LOW_GET

#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT)

PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK

#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_TARL_TARGET_TIME_LOW_SET

#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK)

PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT

#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT   (0U)

PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET

#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT)

PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK

#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT

#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT   (0U)

PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET

#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT)

PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK

#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT

#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT   (0U)

PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET

#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT)

PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK

#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK   (0xFFFFFFFFUL)

PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET

#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK)

PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT

#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT   (0U)

PTPC_PTPC_TS_UPDTL_ADD_SUB_GET

#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT)

PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK

#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK   (0x80000000UL)

PTPC_PTPC_TS_UPDTL_ADD_SUB_SET

#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK)

PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT

#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT   (31U)

PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET

#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET

(

x

)

(((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT)

PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK

#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK   (0x7FFFFFFFUL)

PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET

#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET

(

x

)

(((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK)

PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT

#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT   (0U)

PTPC_TIME_SEL_CAN0_TIME_SEL_GET

#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT)

PTPC_TIME_SEL_CAN0_TIME_SEL_MASK

#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK   (0x1U)

PTPC_TIME_SEL_CAN0_TIME_SEL_SET

#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK)

PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT

#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT   (0U)

PTPC_TIME_SEL_CAN1_TIME_SEL_GET

#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT)

PTPC_TIME_SEL_CAN1_TIME_SEL_MASK

#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK   (0x2U)

PTPC_TIME_SEL_CAN1_TIME_SEL_SET

#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK)

PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT

#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT   (1U)

PTPC_TIME_SEL_CAN2_TIME_SEL_GET

#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT)

PTPC_TIME_SEL_CAN2_TIME_SEL_MASK

#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK   (0x4U)

PTPC_TIME_SEL_CAN2_TIME_SEL_SET

#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK)

PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT

#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT   (2U)

PTPC_TIME_SEL_CAN3_TIME_SEL_GET

#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET

(

x

)

(((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT)

PTPC_TIME_SEL_CAN3_TIME_SEL_MASK

#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK   (0x8U)

PTPC_TIME_SEL_CAN3_TIME_SEL_SET

#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET

(

x

)

(((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK)

PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT

#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT   (3U)