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Data Structures | |
| struct | HALL_Type |
| #define HALL_COUNT_CURRENT (0UL) |
| #define HALL_COUNT_READ (1UL) |
| #define HALL_COUNT_SNAP0 (2UL) |
| #define HALL_COUNT_SNAP1 (3UL) |
| #define HALL_COUNT_TMR_TIMER_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_TMR_TIMER_MASK) >> HALL_COUNT_TMR_TIMER_SHIFT) |
| #define HALL_COUNT_TMR_TIMER_MASK (0xFFFFFFFFUL) |
| #define HALL_COUNT_TMR_TIMER_SHIFT (0U) |
| #define HALL_COUNT_U_DIR_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_U_DIR_MASK) >> HALL_COUNT_U_DIR_SHIFT) |
| #define HALL_COUNT_U_DIR_MASK (0x80000000UL) |
| #define HALL_COUNT_U_DIR_SHIFT (31U) |
| #define HALL_COUNT_U_UCNT_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_U_UCNT_MASK) >> HALL_COUNT_U_UCNT_SHIFT) |
| #define HALL_COUNT_U_UCNT_MASK (0xFFFFFFFUL) |
| #define HALL_COUNT_U_UCNT_SHIFT (0U) |
| #define HALL_COUNT_U_USTAT_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_U_USTAT_MASK) >> HALL_COUNT_U_USTAT_SHIFT) |
| #define HALL_COUNT_U_USTAT_MASK (0x40000000UL) |
| #define HALL_COUNT_U_USTAT_SHIFT (30U) |
| #define HALL_COUNT_U_VSTAT_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_U_VSTAT_MASK) >> HALL_COUNT_U_VSTAT_SHIFT) |
| #define HALL_COUNT_U_VSTAT_MASK (0x20000000UL) |
| #define HALL_COUNT_U_VSTAT_SHIFT (29U) |
| #define HALL_COUNT_U_WSTAT_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_U_WSTAT_MASK) >> HALL_COUNT_U_WSTAT_SHIFT) |
| #define HALL_COUNT_U_WSTAT_MASK (0x10000000UL) |
| #define HALL_COUNT_U_WSTAT_SHIFT (28U) |
| #define HALL_COUNT_V_VCNT_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_V_VCNT_MASK) >> HALL_COUNT_V_VCNT_SHIFT) |
| #define HALL_COUNT_V_VCNT_MASK (0xFFFFFFFUL) |
| #define HALL_COUNT_V_VCNT_SHIFT (0U) |
| #define HALL_COUNT_W_WCNT_GET | ( | x | ) | (((uint32_t)(x) & HALL_COUNT_W_WCNT_MASK) >> HALL_COUNT_W_WCNT_SHIFT) |
| #define HALL_COUNT_W_WCNT_MASK (0xFFFFFFFUL) |
| #define HALL_COUNT_W_WCNT_SHIFT (0U) |
| #define HALL_CR_READ_GET | ( | x | ) | (((uint32_t)(x) & HALL_CR_READ_MASK) >> HALL_CR_READ_SHIFT) |
| #define HALL_CR_READ_MASK (0x80000000UL) |
| #define HALL_CR_READ_SET | ( | x | ) | (((uint32_t)(x) << HALL_CR_READ_SHIFT) & HALL_CR_READ_MASK) |
| #define HALL_CR_READ_SHIFT (31U) |
| #define HALL_CR_RSTCNT_GET | ( | x | ) | (((uint32_t)(x) & HALL_CR_RSTCNT_MASK) >> HALL_CR_RSTCNT_SHIFT) |
| #define HALL_CR_RSTCNT_MASK (0x10U) |
| #define HALL_CR_RSTCNT_SET | ( | x | ) | (((uint32_t)(x) << HALL_CR_RSTCNT_SHIFT) & HALL_CR_RSTCNT_MASK) |
| #define HALL_CR_RSTCNT_SHIFT (4U) |
| #define HALL_CR_SNAPEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_CR_SNAPEN_MASK) >> HALL_CR_SNAPEN_SHIFT) |
| #define HALL_CR_SNAPEN_MASK (0x800U) |
| #define HALL_CR_SNAPEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_CR_SNAPEN_SHIFT) & HALL_CR_SNAPEN_MASK) |
| #define HALL_CR_SNAPEN_SHIFT (11U) |
| #define HALL_DMAEN_PHDLYEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_PHDLYEN_MASK) >> HALL_DMAEN_PHDLYEN_SHIFT) |
| #define HALL_DMAEN_PHDLYEN_MASK (0x10000000UL) |
| #define HALL_DMAEN_PHDLYEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_PHDLYEN_SHIFT) & HALL_DMAEN_PHDLYEN_MASK) |
| #define HALL_DMAEN_PHDLYEN_SHIFT (28U) |
| #define HALL_DMAEN_PHPREEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_PHPREEN_MASK) >> HALL_DMAEN_PHPREEN_SHIFT) |
| #define HALL_DMAEN_PHPREEN_MASK (0x20000000UL) |
| #define HALL_DMAEN_PHPREEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_PHPREEN_SHIFT) & HALL_DMAEN_PHPREEN_MASK) |
| #define HALL_DMAEN_PHPREEN_SHIFT (29U) |
| #define HALL_DMAEN_PHUPTEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_PHUPTEN_MASK) >> HALL_DMAEN_PHUPTEN_SHIFT) |
| #define HALL_DMAEN_PHUPTEN_MASK (0x40000000UL) |
| #define HALL_DMAEN_PHUPTEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_PHUPTEN_SHIFT) & HALL_DMAEN_PHUPTEN_MASK) |
| #define HALL_DMAEN_PHUPTEN_SHIFT (30U) |
| #define HALL_DMAEN_UFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_UFEN_MASK) >> HALL_DMAEN_UFEN_SHIFT) |
| #define HALL_DMAEN_UFEN_MASK (0x800000UL) |
| #define HALL_DMAEN_UFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_UFEN_SHIFT) & HALL_DMAEN_UFEN_MASK) |
| #define HALL_DMAEN_UFEN_SHIFT (23U) |
| #define HALL_DMAEN_VFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_VFEN_MASK) >> HALL_DMAEN_VFEN_SHIFT) |
| #define HALL_DMAEN_VFEN_MASK (0x400000UL) |
| #define HALL_DMAEN_VFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_VFEN_SHIFT) & HALL_DMAEN_VFEN_MASK) |
| #define HALL_DMAEN_VFEN_SHIFT (22U) |
| #define HALL_DMAEN_WDGEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_WDGEN_MASK) >> HALL_DMAEN_WDGEN_SHIFT) |
| #define HALL_DMAEN_WDGEN_MASK (0x80000000UL) |
| #define HALL_DMAEN_WDGEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_WDGEN_SHIFT) & HALL_DMAEN_WDGEN_MASK) |
| #define HALL_DMAEN_WDGEN_SHIFT (31U) |
| #define HALL_DMAEN_WFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_DMAEN_WFEN_MASK) >> HALL_DMAEN_WFEN_SHIFT) |
| #define HALL_DMAEN_WFEN_MASK (0x200000UL) |
| #define HALL_DMAEN_WFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_DMAEN_WFEN_SHIFT) & HALL_DMAEN_WFEN_MASK) |
| #define HALL_DMAEN_WFEN_SHIFT (21U) |
| #define HALL_HIS_HIS0_UHIS0_GET | ( | x | ) | (((uint32_t)(x) & HALL_HIS_HIS0_UHIS0_MASK) >> HALL_HIS_HIS0_UHIS0_SHIFT) |
| #define HALL_HIS_HIS0_UHIS0_MASK (0xFFFFFFFFUL) |
| #define HALL_HIS_HIS0_UHIS0_SHIFT (0U) |
| #define HALL_HIS_HIS1_UHIS1_GET | ( | x | ) | (((uint32_t)(x) & HALL_HIS_HIS1_UHIS1_MASK) >> HALL_HIS_HIS1_UHIS1_SHIFT) |
| #define HALL_HIS_HIS1_UHIS1_MASK (0xFFFFFFFFUL) |
| #define HALL_HIS_HIS1_UHIS1_SHIFT (0U) |
| #define HALL_HIS_U (0UL) |
| #define HALL_HIS_V (1UL) |
| #define HALL_HIS_W (2UL) |
| #define HALL_IRQEN_PHDLYIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_PHDLYIE_MASK) >> HALL_IRQEN_PHDLYIE_SHIFT) |
| #define HALL_IRQEN_PHDLYIE_MASK (0x10000000UL) |
| #define HALL_IRQEN_PHDLYIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_PHDLYIE_SHIFT) & HALL_IRQEN_PHDLYIE_MASK) |
| #define HALL_IRQEN_PHDLYIE_SHIFT (28U) |
| #define HALL_IRQEN_PHPREIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_PHPREIE_MASK) >> HALL_IRQEN_PHPREIE_SHIFT) |
| #define HALL_IRQEN_PHPREIE_MASK (0x20000000UL) |
| #define HALL_IRQEN_PHPREIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_PHPREIE_SHIFT) & HALL_IRQEN_PHPREIE_MASK) |
| #define HALL_IRQEN_PHPREIE_SHIFT (29U) |
| #define HALL_IRQEN_PHUPTIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_PHUPTIE_MASK) >> HALL_IRQEN_PHUPTIE_SHIFT) |
| #define HALL_IRQEN_PHUPTIE_MASK (0x40000000UL) |
| #define HALL_IRQEN_PHUPTIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_PHUPTIE_SHIFT) & HALL_IRQEN_PHUPTIE_MASK) |
| #define HALL_IRQEN_PHUPTIE_SHIFT (30U) |
| #define HALL_IRQEN_UFIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_UFIE_MASK) >> HALL_IRQEN_UFIE_SHIFT) |
| #define HALL_IRQEN_UFIE_MASK (0x800000UL) |
| #define HALL_IRQEN_UFIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_UFIE_SHIFT) & HALL_IRQEN_UFIE_MASK) |
| #define HALL_IRQEN_UFIE_SHIFT (23U) |
| #define HALL_IRQEN_VFIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_VFIE_MASK) >> HALL_IRQEN_VFIE_SHIFT) |
| #define HALL_IRQEN_VFIE_MASK (0x400000UL) |
| #define HALL_IRQEN_VFIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_VFIE_SHIFT) & HALL_IRQEN_VFIE_MASK) |
| #define HALL_IRQEN_VFIE_SHIFT (22U) |
| #define HALL_IRQEN_WDGIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_WDGIE_MASK) >> HALL_IRQEN_WDGIE_SHIFT) |
| #define HALL_IRQEN_WDGIE_MASK (0x80000000UL) |
| #define HALL_IRQEN_WDGIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_WDGIE_SHIFT) & HALL_IRQEN_WDGIE_MASK) |
| #define HALL_IRQEN_WDGIE_SHIFT (31U) |
| #define HALL_IRQEN_WFIE_GET | ( | x | ) | (((uint32_t)(x) & HALL_IRQEN_WFIE_MASK) >> HALL_IRQEN_WFIE_SHIFT) |
| #define HALL_IRQEN_WFIE_MASK (0x200000UL) |
| #define HALL_IRQEN_WFIE_SET | ( | x | ) | (((uint32_t)(x) << HALL_IRQEN_WFIE_SHIFT) & HALL_IRQEN_WFIE_MASK) |
| #define HALL_IRQEN_WFIE_SHIFT (21U) |
| #define HALL_PHCFG_DLYCNT_GET | ( | x | ) | (((uint32_t)(x) & HALL_PHCFG_DLYCNT_MASK) >> HALL_PHCFG_DLYCNT_SHIFT) |
| #define HALL_PHCFG_DLYCNT_MASK (0xFFFFFFUL) |
| #define HALL_PHCFG_DLYCNT_SET | ( | x | ) | (((uint32_t)(x) << HALL_PHCFG_DLYCNT_SHIFT) & HALL_PHCFG_DLYCNT_MASK) |
| #define HALL_PHCFG_DLYCNT_SHIFT (0U) |
| #define HALL_PHCFG_DLYSEL_GET | ( | x | ) | (((uint32_t)(x) & HALL_PHCFG_DLYSEL_MASK) >> HALL_PHCFG_DLYSEL_SHIFT) |
| #define HALL_PHCFG_DLYSEL_MASK (0x80000000UL) |
| #define HALL_PHCFG_DLYSEL_SET | ( | x | ) | (((uint32_t)(x) << HALL_PHCFG_DLYSEL_SHIFT) & HALL_PHCFG_DLYSEL_MASK) |
| #define HALL_PHCFG_DLYSEL_SHIFT (31U) |
| #define HALL_READEN_PHDLYEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_PHDLYEN_MASK) >> HALL_READEN_PHDLYEN_SHIFT) |
| #define HALL_READEN_PHDLYEN_MASK (0x10000000UL) |
| #define HALL_READEN_PHDLYEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_PHDLYEN_SHIFT) & HALL_READEN_PHDLYEN_MASK) |
| #define HALL_READEN_PHDLYEN_SHIFT (28U) |
| #define HALL_READEN_PHPREEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_PHPREEN_MASK) >> HALL_READEN_PHPREEN_SHIFT) |
| #define HALL_READEN_PHPREEN_MASK (0x20000000UL) |
| #define HALL_READEN_PHPREEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_PHPREEN_SHIFT) & HALL_READEN_PHPREEN_MASK) |
| #define HALL_READEN_PHPREEN_SHIFT (29U) |
| #define HALL_READEN_PHUPTEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_PHUPTEN_MASK) >> HALL_READEN_PHUPTEN_SHIFT) |
| #define HALL_READEN_PHUPTEN_MASK (0x40000000UL) |
| #define HALL_READEN_PHUPTEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_PHUPTEN_SHIFT) & HALL_READEN_PHUPTEN_MASK) |
| #define HALL_READEN_PHUPTEN_SHIFT (30U) |
| #define HALL_READEN_UFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_UFEN_MASK) >> HALL_READEN_UFEN_SHIFT) |
| #define HALL_READEN_UFEN_MASK (0x800000UL) |
| #define HALL_READEN_UFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_UFEN_SHIFT) & HALL_READEN_UFEN_MASK) |
| #define HALL_READEN_UFEN_SHIFT (23U) |
| #define HALL_READEN_VFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_VFEN_MASK) >> HALL_READEN_VFEN_SHIFT) |
| #define HALL_READEN_VFEN_MASK (0x400000UL) |
| #define HALL_READEN_VFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_VFEN_SHIFT) & HALL_READEN_VFEN_MASK) |
| #define HALL_READEN_VFEN_SHIFT (22U) |
| #define HALL_READEN_WDGEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_WDGEN_MASK) >> HALL_READEN_WDGEN_SHIFT) |
| #define HALL_READEN_WDGEN_MASK (0x80000000UL) |
| #define HALL_READEN_WDGEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_WDGEN_SHIFT) & HALL_READEN_WDGEN_MASK) |
| #define HALL_READEN_WDGEN_SHIFT (31U) |
| #define HALL_READEN_WFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_READEN_WFEN_MASK) >> HALL_READEN_WFEN_SHIFT) |
| #define HALL_READEN_WFEN_MASK (0x200000UL) |
| #define HALL_READEN_WFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_READEN_WFEN_SHIFT) & HALL_READEN_WFEN_MASK) |
| #define HALL_READEN_WFEN_SHIFT (21U) |
| #define HALL_SR_PHDLYF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_PHDLYF_MASK) >> HALL_SR_PHDLYF_SHIFT) |
| #define HALL_SR_PHDLYF_MASK (0x10000000UL) |
| #define HALL_SR_PHDLYF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_PHDLYF_SHIFT) & HALL_SR_PHDLYF_MASK) |
| #define HALL_SR_PHDLYF_SHIFT (28U) |
| #define HALL_SR_PHPREF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_PHPREF_MASK) >> HALL_SR_PHPREF_SHIFT) |
| #define HALL_SR_PHPREF_MASK (0x20000000UL) |
| #define HALL_SR_PHPREF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_PHPREF_SHIFT) & HALL_SR_PHPREF_MASK) |
| #define HALL_SR_PHPREF_SHIFT (29U) |
| #define HALL_SR_PHUPTF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_PHUPTF_MASK) >> HALL_SR_PHUPTF_SHIFT) |
| #define HALL_SR_PHUPTF_MASK (0x40000000UL) |
| #define HALL_SR_PHUPTF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_PHUPTF_SHIFT) & HALL_SR_PHUPTF_MASK) |
| #define HALL_SR_PHUPTF_SHIFT (30U) |
| #define HALL_SR_UF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_UF_MASK) >> HALL_SR_UF_SHIFT) |
| #define HALL_SR_UF_MASK (0x800000UL) |
| #define HALL_SR_UF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_UF_SHIFT) & HALL_SR_UF_MASK) |
| #define HALL_SR_UF_SHIFT (23U) |
| #define HALL_SR_VF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_VF_MASK) >> HALL_SR_VF_SHIFT) |
| #define HALL_SR_VF_MASK (0x400000UL) |
| #define HALL_SR_VF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_VF_SHIFT) & HALL_SR_VF_MASK) |
| #define HALL_SR_VF_SHIFT (22U) |
| #define HALL_SR_WDGF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_WDGF_MASK) >> HALL_SR_WDGF_SHIFT) |
| #define HALL_SR_WDGF_MASK (0x80000000UL) |
| #define HALL_SR_WDGF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_WDGF_SHIFT) & HALL_SR_WDGF_MASK) |
| #define HALL_SR_WDGF_SHIFT (31U) |
| #define HALL_SR_WF_GET | ( | x | ) | (((uint32_t)(x) & HALL_SR_WF_MASK) >> HALL_SR_WF_SHIFT) |
| #define HALL_SR_WF_MASK (0x200000UL) |
| #define HALL_SR_WF_SET | ( | x | ) | (((uint32_t)(x) << HALL_SR_WF_SHIFT) & HALL_SR_WF_MASK) |
| #define HALL_SR_WF_SHIFT (21U) |
| #define HALL_TRGOEN_PHDLYEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_PHDLYEN_MASK) >> HALL_TRGOEN_PHDLYEN_SHIFT) |
| #define HALL_TRGOEN_PHDLYEN_MASK (0x10000000UL) |
| #define HALL_TRGOEN_PHDLYEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_PHDLYEN_SHIFT) & HALL_TRGOEN_PHDLYEN_MASK) |
| #define HALL_TRGOEN_PHDLYEN_SHIFT (28U) |
| #define HALL_TRGOEN_PHPREEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_PHPREEN_MASK) >> HALL_TRGOEN_PHPREEN_SHIFT) |
| #define HALL_TRGOEN_PHPREEN_MASK (0x20000000UL) |
| #define HALL_TRGOEN_PHPREEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_PHPREEN_SHIFT) & HALL_TRGOEN_PHPREEN_MASK) |
| #define HALL_TRGOEN_PHPREEN_SHIFT (29U) |
| #define HALL_TRGOEN_PHUPTEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_PHUPTEN_MASK) >> HALL_TRGOEN_PHUPTEN_SHIFT) |
| #define HALL_TRGOEN_PHUPTEN_MASK (0x40000000UL) |
| #define HALL_TRGOEN_PHUPTEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_PHUPTEN_SHIFT) & HALL_TRGOEN_PHUPTEN_MASK) |
| #define HALL_TRGOEN_PHUPTEN_SHIFT (30U) |
| #define HALL_TRGOEN_UFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_UFEN_MASK) >> HALL_TRGOEN_UFEN_SHIFT) |
| #define HALL_TRGOEN_UFEN_MASK (0x800000UL) |
| #define HALL_TRGOEN_UFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_UFEN_SHIFT) & HALL_TRGOEN_UFEN_MASK) |
| #define HALL_TRGOEN_UFEN_SHIFT (23U) |
| #define HALL_TRGOEN_VFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_VFEN_MASK) >> HALL_TRGOEN_VFEN_SHIFT) |
| #define HALL_TRGOEN_VFEN_MASK (0x400000UL) |
| #define HALL_TRGOEN_VFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_VFEN_SHIFT) & HALL_TRGOEN_VFEN_MASK) |
| #define HALL_TRGOEN_VFEN_SHIFT (22U) |
| #define HALL_TRGOEN_WDGEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_WDGEN_MASK) >> HALL_TRGOEN_WDGEN_SHIFT) |
| #define HALL_TRGOEN_WDGEN_MASK (0x80000000UL) |
| #define HALL_TRGOEN_WDGEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_WDGEN_SHIFT) & HALL_TRGOEN_WDGEN_MASK) |
| #define HALL_TRGOEN_WDGEN_SHIFT (31U) |
| #define HALL_TRGOEN_WFEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_TRGOEN_WFEN_MASK) >> HALL_TRGOEN_WFEN_SHIFT) |
| #define HALL_TRGOEN_WFEN_MASK (0x200000UL) |
| #define HALL_TRGOEN_WFEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_TRGOEN_WFEN_SHIFT) & HALL_TRGOEN_WFEN_MASK) |
| #define HALL_TRGOEN_WFEN_SHIFT (21U) |
| #define HALL_UVWCFG_PRECNT_GET | ( | x | ) | (((uint32_t)(x) & HALL_UVWCFG_PRECNT_MASK) >> HALL_UVWCFG_PRECNT_SHIFT) |
| #define HALL_UVWCFG_PRECNT_MASK (0xFFFFFFUL) |
| #define HALL_UVWCFG_PRECNT_SET | ( | x | ) | (((uint32_t)(x) << HALL_UVWCFG_PRECNT_SHIFT) & HALL_UVWCFG_PRECNT_MASK) |
| #define HALL_UVWCFG_PRECNT_SHIFT (0U) |
| #define HALL_WDGCFG_WDGEN_GET | ( | x | ) | (((uint32_t)(x) & HALL_WDGCFG_WDGEN_MASK) >> HALL_WDGCFG_WDGEN_SHIFT) |
| #define HALL_WDGCFG_WDGEN_MASK (0x80000000UL) |
| #define HALL_WDGCFG_WDGEN_SET | ( | x | ) | (((uint32_t)(x) << HALL_WDGCFG_WDGEN_SHIFT) & HALL_WDGCFG_WDGEN_MASK) |
| #define HALL_WDGCFG_WDGEN_SHIFT (31U) |
| #define HALL_WDGCFG_WDGTO_GET | ( | x | ) | (((uint32_t)(x) & HALL_WDGCFG_WDGTO_MASK) >> HALL_WDGCFG_WDGTO_SHIFT) |
| #define HALL_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) |
| #define HALL_WDGCFG_WDGTO_SET | ( | x | ) | (((uint32_t)(x) << HALL_WDGCFG_WDGTO_SHIFT) & HALL_WDGCFG_WDGTO_MASK) |
| #define HALL_WDGCFG_WDGTO_SHIFT (0U) |