hpm_pllctlv2_regs.h File Reference

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Data Structures
struct	PLLCTLV2_Type

Macros
#define	PLLCTLV2_XTAL_BUSY_MASK   (0x80000000UL)
#define	PLLCTLV2_XTAL_BUSY_SHIFT   (31U)
#define	PLLCTLV2_XTAL_BUSY_GET(x)   (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT)
#define	PLLCTLV2_XTAL_RESPONSE_MASK   (0x20000000UL)
#define	PLLCTLV2_XTAL_RESPONSE_SHIFT   (29U)
#define	PLLCTLV2_XTAL_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT)
#define	PLLCTLV2_XTAL_ENABLE_MASK   (0x10000000UL)
#define	PLLCTLV2_XTAL_ENABLE_SHIFT   (28U)
#define	PLLCTLV2_XTAL_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT)
#define	PLLCTLV2_XTAL_RAMP_TIME_MASK   (0xFFFFFUL)
#define	PLLCTLV2_XTAL_RAMP_TIME_SHIFT   (0U)
#define	PLLCTLV2_XTAL_RAMP_TIME_SET(x)   (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK)
#define	PLLCTLV2_XTAL_RAMP_TIME_GET(x)   (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT)
#define	PLLCTLV2_PLL_MFI_BUSY_MASK   (0x80000000UL)
#define	PLLCTLV2_PLL_MFI_BUSY_SHIFT   (31U)
#define	PLLCTLV2_PLL_MFI_BUSY_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT)
#define	PLLCTLV2_PLL_MFI_RESPONSE_MASK   (0x20000000UL)
#define	PLLCTLV2_PLL_MFI_RESPONSE_SHIFT   (29U)
#define	PLLCTLV2_PLL_MFI_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT)
#define	PLLCTLV2_PLL_MFI_ENABLE_MASK   (0x10000000UL)
#define	PLLCTLV2_PLL_MFI_ENABLE_SHIFT   (28U)
#define	PLLCTLV2_PLL_MFI_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT)
#define	PLLCTLV2_PLL_MFI_MFI_MASK   (0x7FU)
#define	PLLCTLV2_PLL_MFI_MFI_SHIFT   (0U)
#define	PLLCTLV2_PLL_MFI_MFI_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK)
#define	PLLCTLV2_PLL_MFI_MFI_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT)
#define	PLLCTLV2_PLL_MFN_MFN_MASK   (0x3FFFFFFFUL)
#define	PLLCTLV2_PLL_MFN_MFN_SHIFT   (0U)
#define	PLLCTLV2_PLL_MFN_MFN_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK)
#define	PLLCTLV2_PLL_MFN_MFN_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT)
#define	PLLCTLV2_PLL_MFD_MFD_MASK   (0x3FFFFFFFUL)
#define	PLLCTLV2_PLL_MFD_MFD_SHIFT   (0U)
#define	PLLCTLV2_PLL_MFD_MFD_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK)
#define	PLLCTLV2_PLL_MFD_MFD_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT)
#define	PLLCTLV2_PLL_SS_STEP_STEP_MASK   (0x3FFFFFFFUL)
#define	PLLCTLV2_PLL_SS_STEP_STEP_SHIFT   (0U)
#define	PLLCTLV2_PLL_SS_STEP_STEP_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK)
#define	PLLCTLV2_PLL_SS_STEP_STEP_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT)
#define	PLLCTLV2_PLL_SS_STOP_STOP_MASK   (0x3FFFFFFFUL)
#define	PLLCTLV2_PLL_SS_STOP_STOP_SHIFT   (0U)
#define	PLLCTLV2_PLL_SS_STOP_STOP_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK)
#define	PLLCTLV2_PLL_SS_STOP_STOP_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT)
#define	PLLCTLV2_PLL_CONFIG_SPREAD_MASK   (0x100U)
#define	PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT   (8U)
#define	PLLCTLV2_PLL_CONFIG_SPREAD_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK)
#define	PLLCTLV2_PLL_CONFIG_SPREAD_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT)
#define	PLLCTLV2_PLL_CONFIG_REFSEL_MASK   (0x1U)
#define	PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT   (0U)
#define	PLLCTLV2_PLL_CONFIG_REFSEL_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK)
#define	PLLCTLV2_PLL_CONFIG_REFSEL_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT)
#define	PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK   (0xFFFFU)
#define	PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT   (0U)
#define	PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK)
#define	PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT)
#define	PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK   (0xFFFFU)
#define	PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT   (0U)
#define	PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK)
#define	PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT)
#define	PLLCTLV2_PLL_ADVANCED_SLOW_MASK   (0x10000000UL)
#define	PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT   (28U)
#define	PLLCTLV2_PLL_ADVANCED_SLOW_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK)
#define	PLLCTLV2_PLL_ADVANCED_SLOW_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT)
#define	PLLCTLV2_PLL_ADVANCED_DITHER_MASK   (0x1000000UL)
#define	PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT   (24U)
#define	PLLCTLV2_PLL_ADVANCED_DITHER_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK)
#define	PLLCTLV2_PLL_ADVANCED_DITHER_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT)
#define	PLLCTLV2_PLL_DIV_BUSY_MASK   (0x80000000UL)
#define	PLLCTLV2_PLL_DIV_BUSY_SHIFT   (31U)
#define	PLLCTLV2_PLL_DIV_BUSY_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT)
#define	PLLCTLV2_PLL_DIV_RESPONSE_MASK   (0x20000000UL)
#define	PLLCTLV2_PLL_DIV_RESPONSE_SHIFT   (29U)
#define	PLLCTLV2_PLL_DIV_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT)
#define	PLLCTLV2_PLL_DIV_ENABLE_MASK   (0x10000000UL)
#define	PLLCTLV2_PLL_DIV_ENABLE_SHIFT   (28U)
#define	PLLCTLV2_PLL_DIV_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT)
#define	PLLCTLV2_PLL_DIV_DIV_MASK   (0x3FU)
#define	PLLCTLV2_PLL_DIV_DIV_SHIFT   (0U)
#define	PLLCTLV2_PLL_DIV_DIV_SET(x)   (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK)
#define	PLLCTLV2_PLL_DIV_DIV_GET(x)   (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT)
#define	PLLCTLV2_PLL_DIV_DIV0   (0UL)
#define	PLLCTLV2_PLL_DIV_DIV1   (1UL)
#define	PLLCTLV2_PLL_DIV_DIV2   (2UL)
#define	PLLCTLV2_PLL_PLL0   (0UL)
#define	PLLCTLV2_PLL_PLL1   (1UL)
#define	PLLCTLV2_PLL_PLL2   (2UL)

Macro Definition Documentation

PLLCTLV2_PLL_ADVANCED_DITHER_GET

#define PLLCTLV2_PLL_ADVANCED_DITHER_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT)

PLLCTLV2_PLL_ADVANCED_DITHER_MASK

#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK   (0x1000000UL)

PLLCTLV2_PLL_ADVANCED_DITHER_SET

#define PLLCTLV2_PLL_ADVANCED_DITHER_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK)

PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT

#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT   (24U)

PLLCTLV2_PLL_ADVANCED_SLOW_GET

#define PLLCTLV2_PLL_ADVANCED_SLOW_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT)

PLLCTLV2_PLL_ADVANCED_SLOW_MASK

#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK   (0x10000000UL)

PLLCTLV2_PLL_ADVANCED_SLOW_SET

#define PLLCTLV2_PLL_ADVANCED_SLOW_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK)

PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT

#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT   (28U)

PLLCTLV2_PLL_CONFIG_REFSEL_GET

#define PLLCTLV2_PLL_CONFIG_REFSEL_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT)

PLLCTLV2_PLL_CONFIG_REFSEL_MASK

#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK   (0x1U)

PLLCTLV2_PLL_CONFIG_REFSEL_SET

#define PLLCTLV2_PLL_CONFIG_REFSEL_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK)

PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT

#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT   (0U)

PLLCTLV2_PLL_CONFIG_SPREAD_GET

#define PLLCTLV2_PLL_CONFIG_SPREAD_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT)

PLLCTLV2_PLL_CONFIG_SPREAD_MASK

#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK   (0x100U)

PLLCTLV2_PLL_CONFIG_SPREAD_SET

#define PLLCTLV2_PLL_CONFIG_SPREAD_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK)

PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT

#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT   (8U)

PLLCTLV2_PLL_DIV_BUSY_GET

#define PLLCTLV2_PLL_DIV_BUSY_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT)

PLLCTLV2_PLL_DIV_BUSY_MASK

#define PLLCTLV2_PLL_DIV_BUSY_MASK   (0x80000000UL)

PLLCTLV2_PLL_DIV_BUSY_SHIFT

#define PLLCTLV2_PLL_DIV_BUSY_SHIFT   (31U)

PLLCTLV2_PLL_DIV_DIV0

#define PLLCTLV2_PLL_DIV_DIV0   (0UL)

PLLCTLV2_PLL_DIV_DIV1

#define PLLCTLV2_PLL_DIV_DIV1   (1UL)

PLLCTLV2_PLL_DIV_DIV2

#define PLLCTLV2_PLL_DIV_DIV2   (2UL)

PLLCTLV2_PLL_DIV_DIV_GET

#define PLLCTLV2_PLL_DIV_DIV_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT)

PLLCTLV2_PLL_DIV_DIV_MASK

#define PLLCTLV2_PLL_DIV_DIV_MASK   (0x3FU)

PLLCTLV2_PLL_DIV_DIV_SET

#define PLLCTLV2_PLL_DIV_DIV_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK)

PLLCTLV2_PLL_DIV_DIV_SHIFT

#define PLLCTLV2_PLL_DIV_DIV_SHIFT   (0U)

PLLCTLV2_PLL_DIV_ENABLE_GET

#define PLLCTLV2_PLL_DIV_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT)

PLLCTLV2_PLL_DIV_ENABLE_MASK

#define PLLCTLV2_PLL_DIV_ENABLE_MASK   (0x10000000UL)

PLLCTLV2_PLL_DIV_ENABLE_SHIFT

#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT   (28U)

PLLCTLV2_PLL_DIV_RESPONSE_GET

#define PLLCTLV2_PLL_DIV_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT)

PLLCTLV2_PLL_DIV_RESPONSE_MASK

#define PLLCTLV2_PLL_DIV_RESPONSE_MASK   (0x20000000UL)

PLLCTLV2_PLL_DIV_RESPONSE_SHIFT

#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT   (29U)

PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET

#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT)

PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK

#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK   (0xFFFFU)

PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET

#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK)

PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT

#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT   (0U)

PLLCTLV2_PLL_MFD_MFD_GET

#define PLLCTLV2_PLL_MFD_MFD_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT)

PLLCTLV2_PLL_MFD_MFD_MASK

#define PLLCTLV2_PLL_MFD_MFD_MASK   (0x3FFFFFFFUL)

PLLCTLV2_PLL_MFD_MFD_SET

#define PLLCTLV2_PLL_MFD_MFD_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK)

PLLCTLV2_PLL_MFD_MFD_SHIFT

#define PLLCTLV2_PLL_MFD_MFD_SHIFT   (0U)

PLLCTLV2_PLL_MFI_BUSY_GET

#define PLLCTLV2_PLL_MFI_BUSY_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT)

PLLCTLV2_PLL_MFI_BUSY_MASK

#define PLLCTLV2_PLL_MFI_BUSY_MASK   (0x80000000UL)

PLLCTLV2_PLL_MFI_BUSY_SHIFT

#define PLLCTLV2_PLL_MFI_BUSY_SHIFT   (31U)

PLLCTLV2_PLL_MFI_ENABLE_GET

#define PLLCTLV2_PLL_MFI_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT)

PLLCTLV2_PLL_MFI_ENABLE_MASK

#define PLLCTLV2_PLL_MFI_ENABLE_MASK   (0x10000000UL)

PLLCTLV2_PLL_MFI_ENABLE_SHIFT

#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT   (28U)

PLLCTLV2_PLL_MFI_MFI_GET

#define PLLCTLV2_PLL_MFI_MFI_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT)

PLLCTLV2_PLL_MFI_MFI_MASK

#define PLLCTLV2_PLL_MFI_MFI_MASK   (0x7FU)

PLLCTLV2_PLL_MFI_MFI_SET

#define PLLCTLV2_PLL_MFI_MFI_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK)

PLLCTLV2_PLL_MFI_MFI_SHIFT

#define PLLCTLV2_PLL_MFI_MFI_SHIFT   (0U)

PLLCTLV2_PLL_MFI_RESPONSE_GET

#define PLLCTLV2_PLL_MFI_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT)

PLLCTLV2_PLL_MFI_RESPONSE_MASK

#define PLLCTLV2_PLL_MFI_RESPONSE_MASK   (0x20000000UL)

PLLCTLV2_PLL_MFI_RESPONSE_SHIFT

#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT   (29U)

PLLCTLV2_PLL_MFN_MFN_GET

#define PLLCTLV2_PLL_MFN_MFN_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT)

PLLCTLV2_PLL_MFN_MFN_MASK

#define PLLCTLV2_PLL_MFN_MFN_MASK   (0x3FFFFFFFUL)

PLLCTLV2_PLL_MFN_MFN_SET

#define PLLCTLV2_PLL_MFN_MFN_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK)

PLLCTLV2_PLL_MFN_MFN_SHIFT

#define PLLCTLV2_PLL_MFN_MFN_SHIFT   (0U)

PLLCTLV2_PLL_PLL0

#define PLLCTLV2_PLL_PLL0   (0UL)

PLLCTLV2_PLL_PLL1

#define PLLCTLV2_PLL_PLL1   (1UL)

PLLCTLV2_PLL_PLL2

#define PLLCTLV2_PLL_PLL2   (2UL)

PLLCTLV2_PLL_SS_STEP_STEP_GET

#define PLLCTLV2_PLL_SS_STEP_STEP_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT)

PLLCTLV2_PLL_SS_STEP_STEP_MASK

#define PLLCTLV2_PLL_SS_STEP_STEP_MASK   (0x3FFFFFFFUL)

PLLCTLV2_PLL_SS_STEP_STEP_SET

#define PLLCTLV2_PLL_SS_STEP_STEP_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK)

PLLCTLV2_PLL_SS_STEP_STEP_SHIFT

#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT   (0U)

PLLCTLV2_PLL_SS_STOP_STOP_GET

#define PLLCTLV2_PLL_SS_STOP_STOP_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT)

PLLCTLV2_PLL_SS_STOP_STOP_MASK

#define PLLCTLV2_PLL_SS_STOP_STOP_MASK   (0x3FFFFFFFUL)

PLLCTLV2_PLL_SS_STOP_STOP_SET

#define PLLCTLV2_PLL_SS_STOP_STOP_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK)

PLLCTLV2_PLL_SS_STOP_STOP_SHIFT

#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT   (0U)

PLLCTLV2_PLL_STEPTIME_STEPTIME_GET

#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT)

PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK

#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK   (0xFFFFU)

PLLCTLV2_PLL_STEPTIME_STEPTIME_SET

#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK)

PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT

#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT   (0U)

PLLCTLV2_XTAL_BUSY_GET

#define PLLCTLV2_XTAL_BUSY_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT)

PLLCTLV2_XTAL_BUSY_MASK

#define PLLCTLV2_XTAL_BUSY_MASK   (0x80000000UL)

PLLCTLV2_XTAL_BUSY_SHIFT

#define PLLCTLV2_XTAL_BUSY_SHIFT   (31U)

PLLCTLV2_XTAL_ENABLE_GET

#define PLLCTLV2_XTAL_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT)

PLLCTLV2_XTAL_ENABLE_MASK

#define PLLCTLV2_XTAL_ENABLE_MASK   (0x10000000UL)

PLLCTLV2_XTAL_ENABLE_SHIFT

#define PLLCTLV2_XTAL_ENABLE_SHIFT   (28U)

PLLCTLV2_XTAL_RAMP_TIME_GET

#define PLLCTLV2_XTAL_RAMP_TIME_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT)

PLLCTLV2_XTAL_RAMP_TIME_MASK

#define PLLCTLV2_XTAL_RAMP_TIME_MASK   (0xFFFFFUL)

PLLCTLV2_XTAL_RAMP_TIME_SET

#define PLLCTLV2_XTAL_RAMP_TIME_SET

(

x

)

(((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK)

PLLCTLV2_XTAL_RAMP_TIME_SHIFT

#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT   (0U)

PLLCTLV2_XTAL_RESPONSE_GET

#define PLLCTLV2_XTAL_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT)

PLLCTLV2_XTAL_RESPONSE_MASK

#define PLLCTLV2_XTAL_RESPONSE_MASK   (0x20000000UL)

PLLCTLV2_XTAL_RESPONSE_SHIFT

#define PLLCTLV2_XTAL_RESPONSE_SHIFT   (29U)