HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_qei_regs.h File Reference

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Data Structures

struct  QEI_Type
 

Macros

#define QEI_CR_READ_MASK   (0x80000000UL)
 
#define QEI_CR_READ_SHIFT   (31U)
 
#define QEI_CR_READ_SET(x)   (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK)
 
#define QEI_CR_READ_GET(x)   (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT)
 
#define QEI_CR_HRSTSPD_MASK   (0x40000UL)
 
#define QEI_CR_HRSTSPD_SHIFT   (18U)
 
#define QEI_CR_HRSTSPD_SET(x)   (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK)
 
#define QEI_CR_HRSTSPD_GET(x)   (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT)
 
#define QEI_CR_HRSTPH_MASK   (0x20000UL)
 
#define QEI_CR_HRSTPH_SHIFT   (17U)
 
#define QEI_CR_HRSTPH_SET(x)   (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK)
 
#define QEI_CR_HRSTPH_GET(x)   (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT)
 
#define QEI_CR_HRSTZ_MASK   (0x10000UL)
 
#define QEI_CR_HRSTZ_SHIFT   (16U)
 
#define QEI_CR_HRSTZ_SET(x)   (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK)
 
#define QEI_CR_HRSTZ_GET(x)   (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT)
 
#define QEI_CR_PAUSESPD_MASK   (0x4000U)
 
#define QEI_CR_PAUSESPD_SHIFT   (14U)
 
#define QEI_CR_PAUSESPD_SET(x)   (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK)
 
#define QEI_CR_PAUSESPD_GET(x)   (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT)
 
#define QEI_CR_PAUSEPH_MASK   (0x2000U)
 
#define QEI_CR_PAUSEPH_SHIFT   (13U)
 
#define QEI_CR_PAUSEPH_SET(x)   (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK)
 
#define QEI_CR_PAUSEPH_GET(x)   (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT)
 
#define QEI_CR_PAUSEZ_MASK   (0x1000U)
 
#define QEI_CR_PAUSEZ_SHIFT   (12U)
 
#define QEI_CR_PAUSEZ_SET(x)   (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK)
 
#define QEI_CR_PAUSEZ_GET(x)   (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT)
 
#define QEI_CR_HRDIR1_MASK   (0x800U)
 
#define QEI_CR_HRDIR1_SHIFT   (11U)
 
#define QEI_CR_HRDIR1_SET(x)   (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK)
 
#define QEI_CR_HRDIR1_GET(x)   (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT)
 
#define QEI_CR_HRDIR0_MASK   (0x400U)
 
#define QEI_CR_HRDIR0_SHIFT   (10U)
 
#define QEI_CR_HRDIR0_SET(x)   (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK)
 
#define QEI_CR_HRDIR0_GET(x)   (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT)
 
#define QEI_CR_HFDIR1_MASK   (0x200U)
 
#define QEI_CR_HFDIR1_SHIFT   (9U)
 
#define QEI_CR_HFDIR1_SET(x)   (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK)
 
#define QEI_CR_HFDIR1_GET(x)   (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT)
 
#define QEI_CR_HFDIR0_MASK   (0x100U)
 
#define QEI_CR_HFDIR0_SHIFT   (8U)
 
#define QEI_CR_HFDIR0_SET(x)   (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK)
 
#define QEI_CR_HFDIR0_GET(x)   (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT)
 
#define QEI_CR_SNAPEN_MASK   (0x20U)
 
#define QEI_CR_SNAPEN_SHIFT   (5U)
 
#define QEI_CR_SNAPEN_SET(x)   (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK)
 
#define QEI_CR_SNAPEN_GET(x)   (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT)
 
#define QEI_CR_RSTCNT_MASK   (0x10U)
 
#define QEI_CR_RSTCNT_SHIFT   (4U)
 
#define QEI_CR_RSTCNT_SET(x)   (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK)
 
#define QEI_CR_RSTCNT_GET(x)   (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT)
 
#define QEI_CR_ENCTYP_MASK   (0x3U)
 
#define QEI_CR_ENCTYP_SHIFT   (0U)
 
#define QEI_CR_ENCTYP_SET(x)   (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK)
 
#define QEI_CR_ENCTYP_GET(x)   (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT)
 
#define QEI_PHCFG_ZCNTCFG_MASK   (0x400000UL)
 
#define QEI_PHCFG_ZCNTCFG_SHIFT   (22U)
 
#define QEI_PHCFG_ZCNTCFG_SET(x)   (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK)
 
#define QEI_PHCFG_ZCNTCFG_GET(x)   (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT)
 
#define QEI_PHCFG_PHCALIZ_MASK   (0x200000UL)
 
#define QEI_PHCFG_PHCALIZ_SHIFT   (21U)
 
#define QEI_PHCFG_PHCALIZ_SET(x)   (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK)
 
#define QEI_PHCFG_PHCALIZ_GET(x)   (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT)
 
#define QEI_PHCFG_PHMAX_MASK   (0x1FFFFFUL)
 
#define QEI_PHCFG_PHMAX_SHIFT   (0U)
 
#define QEI_PHCFG_PHMAX_SET(x)   (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK)
 
#define QEI_PHCFG_PHMAX_GET(x)   (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT)
 
#define QEI_WDGCFG_WDGEN_MASK   (0x80000000UL)
 
#define QEI_WDGCFG_WDGEN_SHIFT   (31U)
 
#define QEI_WDGCFG_WDGEN_SET(x)   (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK)
 
#define QEI_WDGCFG_WDGEN_GET(x)   (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT)
 
#define QEI_WDGCFG_WDGTO_MASK   (0x7FFFFFFFUL)
 
#define QEI_WDGCFG_WDGTO_SHIFT   (0U)
 
#define QEI_WDGCFG_WDGTO_SET(x)   (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK)
 
#define QEI_WDGCFG_WDGTO_GET(x)   (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT)
 
#define QEI_PHIDX_PHIDX_MASK   (0x1FFFFFUL)
 
#define QEI_PHIDX_PHIDX_SHIFT   (0U)
 
#define QEI_PHIDX_PHIDX_SET(x)   (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK)
 
#define QEI_PHIDX_PHIDX_GET(x)   (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT)
 
#define QEI_TRGOEN_WDGFEN_MASK   (0x80000000UL)
 
#define QEI_TRGOEN_WDGFEN_SHIFT   (31U)
 
#define QEI_TRGOEN_WDGFEN_SET(x)   (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK)
 
#define QEI_TRGOEN_WDGFEN_GET(x)   (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT)
 
#define QEI_TRGOEN_HOMEFEN_MASK   (0x40000000UL)
 
#define QEI_TRGOEN_HOMEFEN_SHIFT   (30U)
 
#define QEI_TRGOEN_HOMEFEN_SET(x)   (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK)
 
#define QEI_TRGOEN_HOMEFEN_GET(x)   (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT)
 
#define QEI_TRGOEN_POSCMPFEN_MASK   (0x20000000UL)
 
#define QEI_TRGOEN_POSCMPFEN_SHIFT   (29U)
 
#define QEI_TRGOEN_POSCMPFEN_SET(x)   (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK)
 
#define QEI_TRGOEN_POSCMPFEN_GET(x)   (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT)
 
#define QEI_TRGOEN_ZPHFEN_MASK   (0x10000000UL)
 
#define QEI_TRGOEN_ZPHFEN_SHIFT   (28U)
 
#define QEI_TRGOEN_ZPHFEN_SET(x)   (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK)
 
#define QEI_TRGOEN_ZPHFEN_GET(x)   (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT)
 
#define QEI_READEN_WDGFEN_MASK   (0x80000000UL)
 
#define QEI_READEN_WDGFEN_SHIFT   (31U)
 
#define QEI_READEN_WDGFEN_SET(x)   (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK)
 
#define QEI_READEN_WDGFEN_GET(x)   (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT)
 
#define QEI_READEN_HOMEFEN_MASK   (0x40000000UL)
 
#define QEI_READEN_HOMEFEN_SHIFT   (30U)
 
#define QEI_READEN_HOMEFEN_SET(x)   (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK)
 
#define QEI_READEN_HOMEFEN_GET(x)   (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT)
 
#define QEI_READEN_POSCMPFEN_MASK   (0x20000000UL)
 
#define QEI_READEN_POSCMPFEN_SHIFT   (29U)
 
#define QEI_READEN_POSCMPFEN_SET(x)   (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK)
 
#define QEI_READEN_POSCMPFEN_GET(x)   (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT)
 
#define QEI_READEN_ZPHFEN_MASK   (0x10000000UL)
 
#define QEI_READEN_ZPHFEN_SHIFT   (28U)
 
#define QEI_READEN_ZPHFEN_SET(x)   (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK)
 
#define QEI_READEN_ZPHFEN_GET(x)   (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT)
 
#define QEI_ZCMP_ZCMP_MASK   (0xFFFFFFFFUL)
 
#define QEI_ZCMP_ZCMP_SHIFT   (0U)
 
#define QEI_ZCMP_ZCMP_SET(x)   (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK)
 
#define QEI_ZCMP_ZCMP_GET(x)   (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT)
 
#define QEI_PHCMP_ZCMPDIS_MASK   (0x80000000UL)
 
#define QEI_PHCMP_ZCMPDIS_SHIFT   (31U)
 
#define QEI_PHCMP_ZCMPDIS_SET(x)   (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK)
 
#define QEI_PHCMP_ZCMPDIS_GET(x)   (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT)
 
#define QEI_PHCMP_DIRCMPDIS_MASK   (0x40000000UL)
 
#define QEI_PHCMP_DIRCMPDIS_SHIFT   (30U)
 
#define QEI_PHCMP_DIRCMPDIS_SET(x)   (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK)
 
#define QEI_PHCMP_DIRCMPDIS_GET(x)   (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT)
 
#define QEI_PHCMP_DIRCMP_MASK   (0x20000000UL)
 
#define QEI_PHCMP_DIRCMP_SHIFT   (29U)
 
#define QEI_PHCMP_DIRCMP_SET(x)   (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK)
 
#define QEI_PHCMP_DIRCMP_GET(x)   (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT)
 
#define QEI_PHCMP_PHCMP_MASK   (0x1FFFFFUL)
 
#define QEI_PHCMP_PHCMP_SHIFT   (0U)
 
#define QEI_PHCMP_PHCMP_SET(x)   (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK)
 
#define QEI_PHCMP_PHCMP_GET(x)   (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT)
 
#define QEI_SPDCMP_SPDCMP_MASK   (0xFFFFFFFFUL)
 
#define QEI_SPDCMP_SPDCMP_SHIFT   (0U)
 
#define QEI_SPDCMP_SPDCMP_SET(x)   (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK)
 
#define QEI_SPDCMP_SPDCMP_GET(x)   (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT)
 
#define QEI_DMAEN_WDGFEN_MASK   (0x80000000UL)
 
#define QEI_DMAEN_WDGFEN_SHIFT   (31U)
 
#define QEI_DMAEN_WDGFEN_SET(x)   (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK)
 
#define QEI_DMAEN_WDGFEN_GET(x)   (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT)
 
#define QEI_DMAEN_HOMEFEN_MASK   (0x40000000UL)
 
#define QEI_DMAEN_HOMEFEN_SHIFT   (30U)
 
#define QEI_DMAEN_HOMEFEN_SET(x)   (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK)
 
#define QEI_DMAEN_HOMEFEN_GET(x)   (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT)
 
#define QEI_DMAEN_POSCMPFEN_MASK   (0x20000000UL)
 
#define QEI_DMAEN_POSCMPFEN_SHIFT   (29U)
 
#define QEI_DMAEN_POSCMPFEN_SET(x)   (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK)
 
#define QEI_DMAEN_POSCMPFEN_GET(x)   (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT)
 
#define QEI_DMAEN_ZPHFEN_MASK   (0x10000000UL)
 
#define QEI_DMAEN_ZPHFEN_SHIFT   (28U)
 
#define QEI_DMAEN_ZPHFEN_SET(x)   (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK)
 
#define QEI_DMAEN_ZPHFEN_GET(x)   (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT)
 
#define QEI_SR_WDGF_MASK   (0x80000000UL)
 
#define QEI_SR_WDGF_SHIFT   (31U)
 
#define QEI_SR_WDGF_SET(x)   (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK)
 
#define QEI_SR_WDGF_GET(x)   (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT)
 
#define QEI_SR_HOMEF_MASK   (0x40000000UL)
 
#define QEI_SR_HOMEF_SHIFT   (30U)
 
#define QEI_SR_HOMEF_SET(x)   (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK)
 
#define QEI_SR_HOMEF_GET(x)   (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT)
 
#define QEI_SR_POSCMPF_MASK   (0x20000000UL)
 
#define QEI_SR_POSCMPF_SHIFT   (29U)
 
#define QEI_SR_POSCMPF_SET(x)   (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK)
 
#define QEI_SR_POSCMPF_GET(x)   (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT)
 
#define QEI_SR_ZPHF_MASK   (0x10000000UL)
 
#define QEI_SR_ZPHF_SHIFT   (28U)
 
#define QEI_SR_ZPHF_SET(x)   (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK)
 
#define QEI_SR_ZPHF_GET(x)   (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT)
 
#define QEI_IRQEN_WDGIE_MASK   (0x80000000UL)
 
#define QEI_IRQEN_WDGIE_SHIFT   (31U)
 
#define QEI_IRQEN_WDGIE_SET(x)   (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK)
 
#define QEI_IRQEN_WDGIE_GET(x)   (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT)
 
#define QEI_IRQEN_HOMEIE_MASK   (0x40000000UL)
 
#define QEI_IRQEN_HOMEIE_SHIFT   (30U)
 
#define QEI_IRQEN_HOMEIE_SET(x)   (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK)
 
#define QEI_IRQEN_HOMEIE_GET(x)   (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT)
 
#define QEI_IRQEN_POSCMPIE_MASK   (0x20000000UL)
 
#define QEI_IRQEN_POSCMPIE_SHIFT   (29U)
 
#define QEI_IRQEN_POSCMPIE_SET(x)   (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK)
 
#define QEI_IRQEN_POSCMPIE_GET(x)   (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT)
 
#define QEI_IRQEN_ZPHIE_MASK   (0x10000000UL)
 
#define QEI_IRQEN_ZPHIE_SHIFT   (28U)
 
#define QEI_IRQEN_ZPHIE_SET(x)   (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK)
 
#define QEI_IRQEN_ZPHIE_GET(x)   (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT)
 
#define QEI_COUNT_Z_ZCNT_MASK   (0xFFFFFFFFUL)
 
#define QEI_COUNT_Z_ZCNT_SHIFT   (0U)
 
#define QEI_COUNT_Z_ZCNT_SET(x)   (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK)
 
#define QEI_COUNT_Z_ZCNT_GET(x)   (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT)
 
#define QEI_COUNT_PH_DIR_MASK   (0x40000000UL)
 
#define QEI_COUNT_PH_DIR_SHIFT   (30U)
 
#define QEI_COUNT_PH_DIR_GET(x)   (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT)
 
#define QEI_COUNT_PH_ASTAT_MASK   (0x4000000UL)
 
#define QEI_COUNT_PH_ASTAT_SHIFT   (26U)
 
#define QEI_COUNT_PH_ASTAT_GET(x)   (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT)
 
#define QEI_COUNT_PH_BSTAT_MASK   (0x2000000UL)
 
#define QEI_COUNT_PH_BSTAT_SHIFT   (25U)
 
#define QEI_COUNT_PH_BSTAT_GET(x)   (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT)
 
#define QEI_COUNT_PH_PHCNT_MASK   (0x1FFFFFUL)
 
#define QEI_COUNT_PH_PHCNT_SHIFT   (0U)
 
#define QEI_COUNT_PH_PHCNT_GET(x)   (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT)
 
#define QEI_COUNT_SPD_DIR_MASK   (0x80000000UL)
 
#define QEI_COUNT_SPD_DIR_SHIFT   (31U)
 
#define QEI_COUNT_SPD_DIR_GET(x)   (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT)
 
#define QEI_COUNT_SPD_ASTAT_MASK   (0x40000000UL)
 
#define QEI_COUNT_SPD_ASTAT_SHIFT   (30U)
 
#define QEI_COUNT_SPD_ASTAT_GET(x)   (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT)
 
#define QEI_COUNT_SPD_BSTAT_MASK   (0x20000000UL)
 
#define QEI_COUNT_SPD_BSTAT_SHIFT   (29U)
 
#define QEI_COUNT_SPD_BSTAT_SET(x)   (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK)
 
#define QEI_COUNT_SPD_BSTAT_GET(x)   (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT)
 
#define QEI_COUNT_SPD_SPDCNT_MASK   (0xFFFFFFFUL)
 
#define QEI_COUNT_SPD_SPDCNT_SHIFT   (0U)
 
#define QEI_COUNT_SPD_SPDCNT_GET(x)   (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT)
 
#define QEI_COUNT_TMR_TMRCNT_MASK   (0xFFFFFFFFUL)
 
#define QEI_COUNT_TMR_TMRCNT_SHIFT   (0U)
 
#define QEI_COUNT_TMR_TMRCNT_GET(x)   (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT)
 
#define QEI_SPDHIS_SPDHIS0_MASK   (0xFFFFFFFFUL)
 
#define QEI_SPDHIS_SPDHIS0_SHIFT   (0U)
 
#define QEI_SPDHIS_SPDHIS0_GET(x)   (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT)
 
#define QEI_COUNT_CURRENT   (0UL)
 
#define QEI_COUNT_READ   (1UL)
 
#define QEI_COUNT_SNAP0   (2UL)
 
#define QEI_COUNT_SNAP1   (3UL)
 
#define QEI_SPDHIS_SPDHIS0   (0UL)
 
#define QEI_SPDHIS_SPDHIS1   (1UL)
 
#define QEI_SPDHIS_SPDHIS2   (2UL)
 
#define QEI_SPDHIS_SPDHIS3   (3UL)
 

Macro Definition Documentation

◆ QEI_COUNT_CURRENT

#define QEI_COUNT_CURRENT   (0UL)

◆ QEI_COUNT_PH_ASTAT_GET

#define QEI_COUNT_PH_ASTAT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT)

◆ QEI_COUNT_PH_ASTAT_MASK

#define QEI_COUNT_PH_ASTAT_MASK   (0x4000000UL)

◆ QEI_COUNT_PH_ASTAT_SHIFT

#define QEI_COUNT_PH_ASTAT_SHIFT   (26U)

◆ QEI_COUNT_PH_BSTAT_GET

#define QEI_COUNT_PH_BSTAT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT)

◆ QEI_COUNT_PH_BSTAT_MASK

#define QEI_COUNT_PH_BSTAT_MASK   (0x2000000UL)

◆ QEI_COUNT_PH_BSTAT_SHIFT

#define QEI_COUNT_PH_BSTAT_SHIFT   (25U)

◆ QEI_COUNT_PH_DIR_GET

#define QEI_COUNT_PH_DIR_GET (   x)    (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT)

◆ QEI_COUNT_PH_DIR_MASK

#define QEI_COUNT_PH_DIR_MASK   (0x40000000UL)

◆ QEI_COUNT_PH_DIR_SHIFT

#define QEI_COUNT_PH_DIR_SHIFT   (30U)

◆ QEI_COUNT_PH_PHCNT_GET

#define QEI_COUNT_PH_PHCNT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT)

◆ QEI_COUNT_PH_PHCNT_MASK

#define QEI_COUNT_PH_PHCNT_MASK   (0x1FFFFFUL)

◆ QEI_COUNT_PH_PHCNT_SHIFT

#define QEI_COUNT_PH_PHCNT_SHIFT   (0U)

◆ QEI_COUNT_READ

#define QEI_COUNT_READ   (1UL)

◆ QEI_COUNT_SNAP0

#define QEI_COUNT_SNAP0   (2UL)

◆ QEI_COUNT_SNAP1

#define QEI_COUNT_SNAP1   (3UL)

◆ QEI_COUNT_SPD_ASTAT_GET

#define QEI_COUNT_SPD_ASTAT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT)

◆ QEI_COUNT_SPD_ASTAT_MASK

#define QEI_COUNT_SPD_ASTAT_MASK   (0x40000000UL)

◆ QEI_COUNT_SPD_ASTAT_SHIFT

#define QEI_COUNT_SPD_ASTAT_SHIFT   (30U)

◆ QEI_COUNT_SPD_BSTAT_GET

#define QEI_COUNT_SPD_BSTAT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT)

◆ QEI_COUNT_SPD_BSTAT_MASK

#define QEI_COUNT_SPD_BSTAT_MASK   (0x20000000UL)

◆ QEI_COUNT_SPD_BSTAT_SET

#define QEI_COUNT_SPD_BSTAT_SET (   x)    (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK)

◆ QEI_COUNT_SPD_BSTAT_SHIFT

#define QEI_COUNT_SPD_BSTAT_SHIFT   (29U)

◆ QEI_COUNT_SPD_DIR_GET

#define QEI_COUNT_SPD_DIR_GET (   x)    (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT)

◆ QEI_COUNT_SPD_DIR_MASK

#define QEI_COUNT_SPD_DIR_MASK   (0x80000000UL)

◆ QEI_COUNT_SPD_DIR_SHIFT

#define QEI_COUNT_SPD_DIR_SHIFT   (31U)

◆ QEI_COUNT_SPD_SPDCNT_GET

#define QEI_COUNT_SPD_SPDCNT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT)

◆ QEI_COUNT_SPD_SPDCNT_MASK

#define QEI_COUNT_SPD_SPDCNT_MASK   (0xFFFFFFFUL)

◆ QEI_COUNT_SPD_SPDCNT_SHIFT

#define QEI_COUNT_SPD_SPDCNT_SHIFT   (0U)

◆ QEI_COUNT_TMR_TMRCNT_GET

#define QEI_COUNT_TMR_TMRCNT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT)

◆ QEI_COUNT_TMR_TMRCNT_MASK

#define QEI_COUNT_TMR_TMRCNT_MASK   (0xFFFFFFFFUL)

◆ QEI_COUNT_TMR_TMRCNT_SHIFT

#define QEI_COUNT_TMR_TMRCNT_SHIFT   (0U)

◆ QEI_COUNT_Z_ZCNT_GET

#define QEI_COUNT_Z_ZCNT_GET (   x)    (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT)

◆ QEI_COUNT_Z_ZCNT_MASK

#define QEI_COUNT_Z_ZCNT_MASK   (0xFFFFFFFFUL)

◆ QEI_COUNT_Z_ZCNT_SET

#define QEI_COUNT_Z_ZCNT_SET (   x)    (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK)

◆ QEI_COUNT_Z_ZCNT_SHIFT

#define QEI_COUNT_Z_ZCNT_SHIFT   (0U)

◆ QEI_CR_ENCTYP_GET

#define QEI_CR_ENCTYP_GET (   x)    (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT)

◆ QEI_CR_ENCTYP_MASK

#define QEI_CR_ENCTYP_MASK   (0x3U)

◆ QEI_CR_ENCTYP_SET

#define QEI_CR_ENCTYP_SET (   x)    (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK)

◆ QEI_CR_ENCTYP_SHIFT

#define QEI_CR_ENCTYP_SHIFT   (0U)

◆ QEI_CR_HFDIR0_GET

#define QEI_CR_HFDIR0_GET (   x)    (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT)

◆ QEI_CR_HFDIR0_MASK

#define QEI_CR_HFDIR0_MASK   (0x100U)

◆ QEI_CR_HFDIR0_SET

#define QEI_CR_HFDIR0_SET (   x)    (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK)

◆ QEI_CR_HFDIR0_SHIFT

#define QEI_CR_HFDIR0_SHIFT   (8U)

◆ QEI_CR_HFDIR1_GET

#define QEI_CR_HFDIR1_GET (   x)    (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT)

◆ QEI_CR_HFDIR1_MASK

#define QEI_CR_HFDIR1_MASK   (0x200U)

◆ QEI_CR_HFDIR1_SET

#define QEI_CR_HFDIR1_SET (   x)    (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK)

◆ QEI_CR_HFDIR1_SHIFT

#define QEI_CR_HFDIR1_SHIFT   (9U)

◆ QEI_CR_HRDIR0_GET

#define QEI_CR_HRDIR0_GET (   x)    (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT)

◆ QEI_CR_HRDIR0_MASK

#define QEI_CR_HRDIR0_MASK   (0x400U)

◆ QEI_CR_HRDIR0_SET

#define QEI_CR_HRDIR0_SET (   x)    (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK)

◆ QEI_CR_HRDIR0_SHIFT

#define QEI_CR_HRDIR0_SHIFT   (10U)

◆ QEI_CR_HRDIR1_GET

#define QEI_CR_HRDIR1_GET (   x)    (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT)

◆ QEI_CR_HRDIR1_MASK

#define QEI_CR_HRDIR1_MASK   (0x800U)

◆ QEI_CR_HRDIR1_SET

#define QEI_CR_HRDIR1_SET (   x)    (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK)

◆ QEI_CR_HRDIR1_SHIFT

#define QEI_CR_HRDIR1_SHIFT   (11U)

◆ QEI_CR_HRSTPH_GET

#define QEI_CR_HRSTPH_GET (   x)    (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT)

◆ QEI_CR_HRSTPH_MASK

#define QEI_CR_HRSTPH_MASK   (0x20000UL)

◆ QEI_CR_HRSTPH_SET

#define QEI_CR_HRSTPH_SET (   x)    (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK)

◆ QEI_CR_HRSTPH_SHIFT

#define QEI_CR_HRSTPH_SHIFT   (17U)

◆ QEI_CR_HRSTSPD_GET

#define QEI_CR_HRSTSPD_GET (   x)    (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT)

◆ QEI_CR_HRSTSPD_MASK

#define QEI_CR_HRSTSPD_MASK   (0x40000UL)

◆ QEI_CR_HRSTSPD_SET

#define QEI_CR_HRSTSPD_SET (   x)    (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK)

◆ QEI_CR_HRSTSPD_SHIFT

#define QEI_CR_HRSTSPD_SHIFT   (18U)

◆ QEI_CR_HRSTZ_GET

#define QEI_CR_HRSTZ_GET (   x)    (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT)

◆ QEI_CR_HRSTZ_MASK

#define QEI_CR_HRSTZ_MASK   (0x10000UL)

◆ QEI_CR_HRSTZ_SET

#define QEI_CR_HRSTZ_SET (   x)    (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK)

◆ QEI_CR_HRSTZ_SHIFT

#define QEI_CR_HRSTZ_SHIFT   (16U)

◆ QEI_CR_PAUSEPH_GET

#define QEI_CR_PAUSEPH_GET (   x)    (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT)

◆ QEI_CR_PAUSEPH_MASK

#define QEI_CR_PAUSEPH_MASK   (0x2000U)

◆ QEI_CR_PAUSEPH_SET

#define QEI_CR_PAUSEPH_SET (   x)    (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK)

◆ QEI_CR_PAUSEPH_SHIFT

#define QEI_CR_PAUSEPH_SHIFT   (13U)

◆ QEI_CR_PAUSESPD_GET

#define QEI_CR_PAUSESPD_GET (   x)    (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT)

◆ QEI_CR_PAUSESPD_MASK

#define QEI_CR_PAUSESPD_MASK   (0x4000U)

◆ QEI_CR_PAUSESPD_SET

#define QEI_CR_PAUSESPD_SET (   x)    (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK)

◆ QEI_CR_PAUSESPD_SHIFT

#define QEI_CR_PAUSESPD_SHIFT   (14U)

◆ QEI_CR_PAUSEZ_GET

#define QEI_CR_PAUSEZ_GET (   x)    (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT)

◆ QEI_CR_PAUSEZ_MASK

#define QEI_CR_PAUSEZ_MASK   (0x1000U)

◆ QEI_CR_PAUSEZ_SET

#define QEI_CR_PAUSEZ_SET (   x)    (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK)

◆ QEI_CR_PAUSEZ_SHIFT

#define QEI_CR_PAUSEZ_SHIFT   (12U)

◆ QEI_CR_READ_GET

#define QEI_CR_READ_GET (   x)    (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT)

◆ QEI_CR_READ_MASK

#define QEI_CR_READ_MASK   (0x80000000UL)

◆ QEI_CR_READ_SET

#define QEI_CR_READ_SET (   x)    (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK)

◆ QEI_CR_READ_SHIFT

#define QEI_CR_READ_SHIFT   (31U)

◆ QEI_CR_RSTCNT_GET

#define QEI_CR_RSTCNT_GET (   x)    (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT)

◆ QEI_CR_RSTCNT_MASK

#define QEI_CR_RSTCNT_MASK   (0x10U)

◆ QEI_CR_RSTCNT_SET

#define QEI_CR_RSTCNT_SET (   x)    (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK)

◆ QEI_CR_RSTCNT_SHIFT

#define QEI_CR_RSTCNT_SHIFT   (4U)

◆ QEI_CR_SNAPEN_GET

#define QEI_CR_SNAPEN_GET (   x)    (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT)

◆ QEI_CR_SNAPEN_MASK

#define QEI_CR_SNAPEN_MASK   (0x20U)

◆ QEI_CR_SNAPEN_SET

#define QEI_CR_SNAPEN_SET (   x)    (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK)

◆ QEI_CR_SNAPEN_SHIFT

#define QEI_CR_SNAPEN_SHIFT   (5U)

◆ QEI_DMAEN_HOMEFEN_GET

#define QEI_DMAEN_HOMEFEN_GET (   x)    (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT)

◆ QEI_DMAEN_HOMEFEN_MASK

#define QEI_DMAEN_HOMEFEN_MASK   (0x40000000UL)

◆ QEI_DMAEN_HOMEFEN_SET

#define QEI_DMAEN_HOMEFEN_SET (   x)    (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK)

◆ QEI_DMAEN_HOMEFEN_SHIFT

#define QEI_DMAEN_HOMEFEN_SHIFT   (30U)

◆ QEI_DMAEN_POSCMPFEN_GET

#define QEI_DMAEN_POSCMPFEN_GET (   x)    (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT)

◆ QEI_DMAEN_POSCMPFEN_MASK

#define QEI_DMAEN_POSCMPFEN_MASK   (0x20000000UL)

◆ QEI_DMAEN_POSCMPFEN_SET

#define QEI_DMAEN_POSCMPFEN_SET (   x)    (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK)

◆ QEI_DMAEN_POSCMPFEN_SHIFT

#define QEI_DMAEN_POSCMPFEN_SHIFT   (29U)

◆ QEI_DMAEN_WDGFEN_GET

#define QEI_DMAEN_WDGFEN_GET (   x)    (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT)

◆ QEI_DMAEN_WDGFEN_MASK

#define QEI_DMAEN_WDGFEN_MASK   (0x80000000UL)

◆ QEI_DMAEN_WDGFEN_SET

#define QEI_DMAEN_WDGFEN_SET (   x)    (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK)

◆ QEI_DMAEN_WDGFEN_SHIFT

#define QEI_DMAEN_WDGFEN_SHIFT   (31U)

◆ QEI_DMAEN_ZPHFEN_GET

#define QEI_DMAEN_ZPHFEN_GET (   x)    (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT)

◆ QEI_DMAEN_ZPHFEN_MASK

#define QEI_DMAEN_ZPHFEN_MASK   (0x10000000UL)

◆ QEI_DMAEN_ZPHFEN_SET

#define QEI_DMAEN_ZPHFEN_SET (   x)    (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK)

◆ QEI_DMAEN_ZPHFEN_SHIFT

#define QEI_DMAEN_ZPHFEN_SHIFT   (28U)

◆ QEI_IRQEN_HOMEIE_GET

#define QEI_IRQEN_HOMEIE_GET (   x)    (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT)

◆ QEI_IRQEN_HOMEIE_MASK

#define QEI_IRQEN_HOMEIE_MASK   (0x40000000UL)

◆ QEI_IRQEN_HOMEIE_SET

#define QEI_IRQEN_HOMEIE_SET (   x)    (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK)

◆ QEI_IRQEN_HOMEIE_SHIFT

#define QEI_IRQEN_HOMEIE_SHIFT   (30U)

◆ QEI_IRQEN_POSCMPIE_GET

#define QEI_IRQEN_POSCMPIE_GET (   x)    (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT)

◆ QEI_IRQEN_POSCMPIE_MASK

#define QEI_IRQEN_POSCMPIE_MASK   (0x20000000UL)

◆ QEI_IRQEN_POSCMPIE_SET

#define QEI_IRQEN_POSCMPIE_SET (   x)    (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK)

◆ QEI_IRQEN_POSCMPIE_SHIFT

#define QEI_IRQEN_POSCMPIE_SHIFT   (29U)

◆ QEI_IRQEN_WDGIE_GET

#define QEI_IRQEN_WDGIE_GET (   x)    (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT)

◆ QEI_IRQEN_WDGIE_MASK

#define QEI_IRQEN_WDGIE_MASK   (0x80000000UL)

◆ QEI_IRQEN_WDGIE_SET

#define QEI_IRQEN_WDGIE_SET (   x)    (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK)

◆ QEI_IRQEN_WDGIE_SHIFT

#define QEI_IRQEN_WDGIE_SHIFT   (31U)

◆ QEI_IRQEN_ZPHIE_GET

#define QEI_IRQEN_ZPHIE_GET (   x)    (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT)

◆ QEI_IRQEN_ZPHIE_MASK

#define QEI_IRQEN_ZPHIE_MASK   (0x10000000UL)

◆ QEI_IRQEN_ZPHIE_SET

#define QEI_IRQEN_ZPHIE_SET (   x)    (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK)

◆ QEI_IRQEN_ZPHIE_SHIFT

#define QEI_IRQEN_ZPHIE_SHIFT   (28U)

◆ QEI_PHCFG_PHCALIZ_GET

#define QEI_PHCFG_PHCALIZ_GET (   x)    (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT)

◆ QEI_PHCFG_PHCALIZ_MASK

#define QEI_PHCFG_PHCALIZ_MASK   (0x200000UL)

◆ QEI_PHCFG_PHCALIZ_SET

#define QEI_PHCFG_PHCALIZ_SET (   x)    (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK)

◆ QEI_PHCFG_PHCALIZ_SHIFT

#define QEI_PHCFG_PHCALIZ_SHIFT   (21U)

◆ QEI_PHCFG_PHMAX_GET

#define QEI_PHCFG_PHMAX_GET (   x)    (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT)

◆ QEI_PHCFG_PHMAX_MASK

#define QEI_PHCFG_PHMAX_MASK   (0x1FFFFFUL)

◆ QEI_PHCFG_PHMAX_SET

#define QEI_PHCFG_PHMAX_SET (   x)    (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK)

◆ QEI_PHCFG_PHMAX_SHIFT

#define QEI_PHCFG_PHMAX_SHIFT   (0U)

◆ QEI_PHCFG_ZCNTCFG_GET

#define QEI_PHCFG_ZCNTCFG_GET (   x)    (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT)

◆ QEI_PHCFG_ZCNTCFG_MASK

#define QEI_PHCFG_ZCNTCFG_MASK   (0x400000UL)

◆ QEI_PHCFG_ZCNTCFG_SET

#define QEI_PHCFG_ZCNTCFG_SET (   x)    (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK)

◆ QEI_PHCFG_ZCNTCFG_SHIFT

#define QEI_PHCFG_ZCNTCFG_SHIFT   (22U)

◆ QEI_PHCMP_DIRCMP_GET

#define QEI_PHCMP_DIRCMP_GET (   x)    (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT)

◆ QEI_PHCMP_DIRCMP_MASK

#define QEI_PHCMP_DIRCMP_MASK   (0x20000000UL)

◆ QEI_PHCMP_DIRCMP_SET

#define QEI_PHCMP_DIRCMP_SET (   x)    (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK)

◆ QEI_PHCMP_DIRCMP_SHIFT

#define QEI_PHCMP_DIRCMP_SHIFT   (29U)

◆ QEI_PHCMP_DIRCMPDIS_GET

#define QEI_PHCMP_DIRCMPDIS_GET (   x)    (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT)

◆ QEI_PHCMP_DIRCMPDIS_MASK

#define QEI_PHCMP_DIRCMPDIS_MASK   (0x40000000UL)

◆ QEI_PHCMP_DIRCMPDIS_SET

#define QEI_PHCMP_DIRCMPDIS_SET (   x)    (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK)

◆ QEI_PHCMP_DIRCMPDIS_SHIFT

#define QEI_PHCMP_DIRCMPDIS_SHIFT   (30U)

◆ QEI_PHCMP_PHCMP_GET

#define QEI_PHCMP_PHCMP_GET (   x)    (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT)

◆ QEI_PHCMP_PHCMP_MASK

#define QEI_PHCMP_PHCMP_MASK   (0x1FFFFFUL)

◆ QEI_PHCMP_PHCMP_SET

#define QEI_PHCMP_PHCMP_SET (   x)    (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK)

◆ QEI_PHCMP_PHCMP_SHIFT

#define QEI_PHCMP_PHCMP_SHIFT   (0U)

◆ QEI_PHCMP_ZCMPDIS_GET

#define QEI_PHCMP_ZCMPDIS_GET (   x)    (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT)

◆ QEI_PHCMP_ZCMPDIS_MASK

#define QEI_PHCMP_ZCMPDIS_MASK   (0x80000000UL)

◆ QEI_PHCMP_ZCMPDIS_SET

#define QEI_PHCMP_ZCMPDIS_SET (   x)    (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK)

◆ QEI_PHCMP_ZCMPDIS_SHIFT

#define QEI_PHCMP_ZCMPDIS_SHIFT   (31U)

◆ QEI_PHIDX_PHIDX_GET

#define QEI_PHIDX_PHIDX_GET (   x)    (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT)

◆ QEI_PHIDX_PHIDX_MASK

#define QEI_PHIDX_PHIDX_MASK   (0x1FFFFFUL)

◆ QEI_PHIDX_PHIDX_SET

#define QEI_PHIDX_PHIDX_SET (   x)    (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK)

◆ QEI_PHIDX_PHIDX_SHIFT

#define QEI_PHIDX_PHIDX_SHIFT   (0U)

◆ QEI_READEN_HOMEFEN_GET

#define QEI_READEN_HOMEFEN_GET (   x)    (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT)

◆ QEI_READEN_HOMEFEN_MASK

#define QEI_READEN_HOMEFEN_MASK   (0x40000000UL)

◆ QEI_READEN_HOMEFEN_SET

#define QEI_READEN_HOMEFEN_SET (   x)    (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK)

◆ QEI_READEN_HOMEFEN_SHIFT

#define QEI_READEN_HOMEFEN_SHIFT   (30U)

◆ QEI_READEN_POSCMPFEN_GET

#define QEI_READEN_POSCMPFEN_GET (   x)    (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT)

◆ QEI_READEN_POSCMPFEN_MASK

#define QEI_READEN_POSCMPFEN_MASK   (0x20000000UL)

◆ QEI_READEN_POSCMPFEN_SET

#define QEI_READEN_POSCMPFEN_SET (   x)    (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK)

◆ QEI_READEN_POSCMPFEN_SHIFT

#define QEI_READEN_POSCMPFEN_SHIFT   (29U)

◆ QEI_READEN_WDGFEN_GET

#define QEI_READEN_WDGFEN_GET (   x)    (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT)

◆ QEI_READEN_WDGFEN_MASK

#define QEI_READEN_WDGFEN_MASK   (0x80000000UL)

◆ QEI_READEN_WDGFEN_SET

#define QEI_READEN_WDGFEN_SET (   x)    (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK)

◆ QEI_READEN_WDGFEN_SHIFT

#define QEI_READEN_WDGFEN_SHIFT   (31U)

◆ QEI_READEN_ZPHFEN_GET

#define QEI_READEN_ZPHFEN_GET (   x)    (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT)

◆ QEI_READEN_ZPHFEN_MASK

#define QEI_READEN_ZPHFEN_MASK   (0x10000000UL)

◆ QEI_READEN_ZPHFEN_SET

#define QEI_READEN_ZPHFEN_SET (   x)    (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK)

◆ QEI_READEN_ZPHFEN_SHIFT

#define QEI_READEN_ZPHFEN_SHIFT   (28U)

◆ QEI_SPDCMP_SPDCMP_GET

#define QEI_SPDCMP_SPDCMP_GET (   x)    (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT)

◆ QEI_SPDCMP_SPDCMP_MASK

#define QEI_SPDCMP_SPDCMP_MASK   (0xFFFFFFFFUL)

◆ QEI_SPDCMP_SPDCMP_SET

#define QEI_SPDCMP_SPDCMP_SET (   x)    (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK)

◆ QEI_SPDCMP_SPDCMP_SHIFT

#define QEI_SPDCMP_SPDCMP_SHIFT   (0U)

◆ QEI_SPDHIS_SPDHIS0

#define QEI_SPDHIS_SPDHIS0   (0UL)

◆ QEI_SPDHIS_SPDHIS0_GET

#define QEI_SPDHIS_SPDHIS0_GET (   x)    (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT)

◆ QEI_SPDHIS_SPDHIS0_MASK

#define QEI_SPDHIS_SPDHIS0_MASK   (0xFFFFFFFFUL)

◆ QEI_SPDHIS_SPDHIS0_SHIFT

#define QEI_SPDHIS_SPDHIS0_SHIFT   (0U)

◆ QEI_SPDHIS_SPDHIS1

#define QEI_SPDHIS_SPDHIS1   (1UL)

◆ QEI_SPDHIS_SPDHIS2

#define QEI_SPDHIS_SPDHIS2   (2UL)

◆ QEI_SPDHIS_SPDHIS3

#define QEI_SPDHIS_SPDHIS3   (3UL)

◆ QEI_SR_HOMEF_GET

#define QEI_SR_HOMEF_GET (   x)    (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT)

◆ QEI_SR_HOMEF_MASK

#define QEI_SR_HOMEF_MASK   (0x40000000UL)

◆ QEI_SR_HOMEF_SET

#define QEI_SR_HOMEF_SET (   x)    (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK)

◆ QEI_SR_HOMEF_SHIFT

#define QEI_SR_HOMEF_SHIFT   (30U)

◆ QEI_SR_POSCMPF_GET

#define QEI_SR_POSCMPF_GET (   x)    (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT)

◆ QEI_SR_POSCMPF_MASK

#define QEI_SR_POSCMPF_MASK   (0x20000000UL)

◆ QEI_SR_POSCMPF_SET

#define QEI_SR_POSCMPF_SET (   x)    (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK)

◆ QEI_SR_POSCMPF_SHIFT

#define QEI_SR_POSCMPF_SHIFT   (29U)

◆ QEI_SR_WDGF_GET

#define QEI_SR_WDGF_GET (   x)    (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT)

◆ QEI_SR_WDGF_MASK

#define QEI_SR_WDGF_MASK   (0x80000000UL)

◆ QEI_SR_WDGF_SET

#define QEI_SR_WDGF_SET (   x)    (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK)

◆ QEI_SR_WDGF_SHIFT

#define QEI_SR_WDGF_SHIFT   (31U)

◆ QEI_SR_ZPHF_GET

#define QEI_SR_ZPHF_GET (   x)    (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT)

◆ QEI_SR_ZPHF_MASK

#define QEI_SR_ZPHF_MASK   (0x10000000UL)

◆ QEI_SR_ZPHF_SET

#define QEI_SR_ZPHF_SET (   x)    (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK)

◆ QEI_SR_ZPHF_SHIFT

#define QEI_SR_ZPHF_SHIFT   (28U)

◆ QEI_TRGOEN_HOMEFEN_GET

#define QEI_TRGOEN_HOMEFEN_GET (   x)    (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT)

◆ QEI_TRGOEN_HOMEFEN_MASK

#define QEI_TRGOEN_HOMEFEN_MASK   (0x40000000UL)

◆ QEI_TRGOEN_HOMEFEN_SET

#define QEI_TRGOEN_HOMEFEN_SET (   x)    (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK)

◆ QEI_TRGOEN_HOMEFEN_SHIFT

#define QEI_TRGOEN_HOMEFEN_SHIFT   (30U)

◆ QEI_TRGOEN_POSCMPFEN_GET

#define QEI_TRGOEN_POSCMPFEN_GET (   x)    (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT)

◆ QEI_TRGOEN_POSCMPFEN_MASK

#define QEI_TRGOEN_POSCMPFEN_MASK   (0x20000000UL)

◆ QEI_TRGOEN_POSCMPFEN_SET

#define QEI_TRGOEN_POSCMPFEN_SET (   x)    (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK)

◆ QEI_TRGOEN_POSCMPFEN_SHIFT

#define QEI_TRGOEN_POSCMPFEN_SHIFT   (29U)

◆ QEI_TRGOEN_WDGFEN_GET

#define QEI_TRGOEN_WDGFEN_GET (   x)    (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT)

◆ QEI_TRGOEN_WDGFEN_MASK

#define QEI_TRGOEN_WDGFEN_MASK   (0x80000000UL)

◆ QEI_TRGOEN_WDGFEN_SET

#define QEI_TRGOEN_WDGFEN_SET (   x)    (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK)

◆ QEI_TRGOEN_WDGFEN_SHIFT

#define QEI_TRGOEN_WDGFEN_SHIFT   (31U)

◆ QEI_TRGOEN_ZPHFEN_GET

#define QEI_TRGOEN_ZPHFEN_GET (   x)    (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT)

◆ QEI_TRGOEN_ZPHFEN_MASK

#define QEI_TRGOEN_ZPHFEN_MASK   (0x10000000UL)

◆ QEI_TRGOEN_ZPHFEN_SET

#define QEI_TRGOEN_ZPHFEN_SET (   x)    (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK)

◆ QEI_TRGOEN_ZPHFEN_SHIFT

#define QEI_TRGOEN_ZPHFEN_SHIFT   (28U)

◆ QEI_WDGCFG_WDGEN_GET

#define QEI_WDGCFG_WDGEN_GET (   x)    (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT)

◆ QEI_WDGCFG_WDGEN_MASK

#define QEI_WDGCFG_WDGEN_MASK   (0x80000000UL)

◆ QEI_WDGCFG_WDGEN_SET

#define QEI_WDGCFG_WDGEN_SET (   x)    (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK)

◆ QEI_WDGCFG_WDGEN_SHIFT

#define QEI_WDGCFG_WDGEN_SHIFT   (31U)

◆ QEI_WDGCFG_WDGTO_GET

#define QEI_WDGCFG_WDGTO_GET (   x)    (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT)

◆ QEI_WDGCFG_WDGTO_MASK

#define QEI_WDGCFG_WDGTO_MASK   (0x7FFFFFFFUL)

◆ QEI_WDGCFG_WDGTO_SET

#define QEI_WDGCFG_WDGTO_SET (   x)    (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK)

◆ QEI_WDGCFG_WDGTO_SHIFT

#define QEI_WDGCFG_WDGTO_SHIFT   (0U)

◆ QEI_ZCMP_ZCMP_GET

#define QEI_ZCMP_ZCMP_GET (   x)    (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT)

◆ QEI_ZCMP_ZCMP_MASK

#define QEI_ZCMP_ZCMP_MASK   (0xFFFFFFFFUL)

◆ QEI_ZCMP_ZCMP_SET

#define QEI_ZCMP_ZCMP_SET (   x)    (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK)

◆ QEI_ZCMP_ZCMP_SHIFT

#define QEI_ZCMP_ZCMP_SHIFT   (0U)