Go to the source code of this file.
Data Structures | |
| struct | RTC_Type |
| #define RTC_ALARM0_ALARM_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) |
| #define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) |
| #define RTC_ALARM0_ALARM_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) |
| #define RTC_ALARM0_ALARM_SHIFT (0U) |
| #define RTC_ALARM0_INC_INCREASE_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) |
| #define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) |
| #define RTC_ALARM0_INC_INCREASE_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) |
| #define RTC_ALARM0_INC_INCREASE_SHIFT (0U) |
| #define RTC_ALARM1_ALARM_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) |
| #define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) |
| #define RTC_ALARM1_ALARM_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) |
| #define RTC_ALARM1_ALARM_SHIFT (0U) |
| #define RTC_ALARM1_INC_INCREASE_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) |
| #define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) |
| #define RTC_ALARM1_INC_INCREASE_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) |
| #define RTC_ALARM1_INC_INCREASE_SHIFT (0U) |
| #define RTC_ALARM_EN_ENABLE0_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) |
| #define RTC_ALARM_EN_ENABLE0_MASK (0x1U) |
| #define RTC_ALARM_EN_ENABLE0_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) |
| #define RTC_ALARM_EN_ENABLE0_SHIFT (0U) |
| #define RTC_ALARM_EN_ENABLE1_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) |
| #define RTC_ALARM_EN_ENABLE1_MASK (0x2U) |
| #define RTC_ALARM_EN_ENABLE1_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) |
| #define RTC_ALARM_EN_ENABLE1_SHIFT (1U) |
| #define RTC_ALARM_FLAG_ALARM0_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) |
| #define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) |
| #define RTC_ALARM_FLAG_ALARM0_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) |
| #define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) |
| #define RTC_ALARM_FLAG_ALARM1_GET | ( | x | ) | (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) |
| #define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) |
| #define RTC_ALARM_FLAG_ALARM1_SET | ( | x | ) | (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) |
| #define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) |
| #define RTC_SEC_SNAP_SEC_SNAP_GET | ( | x | ) | (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) |
| #define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) |
| #define RTC_SEC_SNAP_SEC_SNAP_SET | ( | x | ) | (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) |
| #define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) |
| #define RTC_SECOND_SECOND_GET | ( | x | ) | (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) |
| #define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) |
| #define RTC_SECOND_SECOND_SET | ( | x | ) | (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) |
| #define RTC_SECOND_SECOND_SHIFT (0U) |
| #define RTC_SUB_SNAP_SUB_SNAP_GET | ( | x | ) | (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) |
| #define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) |
| #define RTC_SUB_SNAP_SUB_SNAP_SET | ( | x | ) | (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) |
| #define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) |
| #define RTC_SUBSEC_SUBSEC_GET | ( | x | ) | (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) |
| #define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) |
| #define RTC_SUBSEC_SUBSEC_SHIFT (0U) |