HPM SDK
HPMicro Software Development Kit
hpm_wdg_regs.h File Reference

Go to the source code of this file.

Data Structures

struct  WDG_Type
 

Macros

#define WDG_CTRL_RSTTIME_MASK   (0x700U)
 
#define WDG_CTRL_RSTTIME_SHIFT   (8U)
 
#define WDG_CTRL_RSTTIME_SET(x)   (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK)
 
#define WDG_CTRL_RSTTIME_GET(x)   (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT)
 
#define WDG_CTRL_INTTIME_MASK   (0xF0U)
 
#define WDG_CTRL_INTTIME_SHIFT   (4U)
 
#define WDG_CTRL_INTTIME_SET(x)   (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK)
 
#define WDG_CTRL_INTTIME_GET(x)   (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT)
 
#define WDG_CTRL_RSTEN_MASK   (0x8U)
 
#define WDG_CTRL_RSTEN_SHIFT   (3U)
 
#define WDG_CTRL_RSTEN_SET(x)   (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK)
 
#define WDG_CTRL_RSTEN_GET(x)   (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT)
 
#define WDG_CTRL_INTEN_MASK   (0x4U)
 
#define WDG_CTRL_INTEN_SHIFT   (2U)
 
#define WDG_CTRL_INTEN_SET(x)   (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK)
 
#define WDG_CTRL_INTEN_GET(x)   (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT)
 
#define WDG_CTRL_CLKSEL_MASK   (0x2U)
 
#define WDG_CTRL_CLKSEL_SHIFT   (1U)
 
#define WDG_CTRL_CLKSEL_SET(x)   (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK)
 
#define WDG_CTRL_CLKSEL_GET(x)   (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT)
 
#define WDG_CTRL_EN_MASK   (0x1U)
 
#define WDG_CTRL_EN_SHIFT   (0U)
 
#define WDG_CTRL_EN_SET(x)   (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK)
 
#define WDG_CTRL_EN_GET(x)   (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT)
 
#define WDG_RESTART_RESTART_MASK   (0xFFFFU)
 
#define WDG_RESTART_RESTART_SHIFT   (0U)
 
#define WDG_RESTART_RESTART_SET(x)   (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK)
 
#define WDG_RESTART_RESTART_GET(x)   (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT)
 
#define WDG_WREN_WEN_MASK   (0xFFFFU)
 
#define WDG_WREN_WEN_SHIFT   (0U)
 
#define WDG_WREN_WEN_SET(x)   (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK)
 
#define WDG_WREN_WEN_GET(x)   (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT)
 
#define WDG_ST_INTEXPIRED_MASK   (0x1U)
 
#define WDG_ST_INTEXPIRED_SHIFT   (0U)
 
#define WDG_ST_INTEXPIRED_SET(x)   (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK)
 
#define WDG_ST_INTEXPIRED_GET(x)   (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT)
 

Macro Definition Documentation

◆ WDG_CTRL_CLKSEL_GET

#define WDG_CTRL_CLKSEL_GET (   x)    (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT)

◆ WDG_CTRL_CLKSEL_MASK

#define WDG_CTRL_CLKSEL_MASK   (0x2U)

◆ WDG_CTRL_CLKSEL_SET

#define WDG_CTRL_CLKSEL_SET (   x)    (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK)

◆ WDG_CTRL_CLKSEL_SHIFT

#define WDG_CTRL_CLKSEL_SHIFT   (1U)

◆ WDG_CTRL_EN_GET

#define WDG_CTRL_EN_GET (   x)    (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT)

◆ WDG_CTRL_EN_MASK

#define WDG_CTRL_EN_MASK   (0x1U)

◆ WDG_CTRL_EN_SET

#define WDG_CTRL_EN_SET (   x)    (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK)

◆ WDG_CTRL_EN_SHIFT

#define WDG_CTRL_EN_SHIFT   (0U)

◆ WDG_CTRL_INTEN_GET

#define WDG_CTRL_INTEN_GET (   x)    (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT)

◆ WDG_CTRL_INTEN_MASK

#define WDG_CTRL_INTEN_MASK   (0x4U)

◆ WDG_CTRL_INTEN_SET

#define WDG_CTRL_INTEN_SET (   x)    (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK)

◆ WDG_CTRL_INTEN_SHIFT

#define WDG_CTRL_INTEN_SHIFT   (2U)

◆ WDG_CTRL_INTTIME_GET

#define WDG_CTRL_INTTIME_GET (   x)    (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT)

◆ WDG_CTRL_INTTIME_MASK

#define WDG_CTRL_INTTIME_MASK   (0xF0U)

◆ WDG_CTRL_INTTIME_SET

#define WDG_CTRL_INTTIME_SET (   x)    (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK)

◆ WDG_CTRL_INTTIME_SHIFT

#define WDG_CTRL_INTTIME_SHIFT   (4U)

◆ WDG_CTRL_RSTEN_GET

#define WDG_CTRL_RSTEN_GET (   x)    (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT)

◆ WDG_CTRL_RSTEN_MASK

#define WDG_CTRL_RSTEN_MASK   (0x8U)

◆ WDG_CTRL_RSTEN_SET

#define WDG_CTRL_RSTEN_SET (   x)    (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK)

◆ WDG_CTRL_RSTEN_SHIFT

#define WDG_CTRL_RSTEN_SHIFT   (3U)

◆ WDG_CTRL_RSTTIME_GET

#define WDG_CTRL_RSTTIME_GET (   x)    (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT)

◆ WDG_CTRL_RSTTIME_MASK

#define WDG_CTRL_RSTTIME_MASK   (0x700U)

◆ WDG_CTRL_RSTTIME_SET

#define WDG_CTRL_RSTTIME_SET (   x)    (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK)

◆ WDG_CTRL_RSTTIME_SHIFT

#define WDG_CTRL_RSTTIME_SHIFT   (8U)

◆ WDG_RESTART_RESTART_GET

#define WDG_RESTART_RESTART_GET (   x)    (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT)

◆ WDG_RESTART_RESTART_MASK

#define WDG_RESTART_RESTART_MASK   (0xFFFFU)

◆ WDG_RESTART_RESTART_SET

#define WDG_RESTART_RESTART_SET (   x)    (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK)

◆ WDG_RESTART_RESTART_SHIFT

#define WDG_RESTART_RESTART_SHIFT   (0U)

◆ WDG_ST_INTEXPIRED_GET

#define WDG_ST_INTEXPIRED_GET (   x)    (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT)

◆ WDG_ST_INTEXPIRED_MASK

#define WDG_ST_INTEXPIRED_MASK   (0x1U)

◆ WDG_ST_INTEXPIRED_SET

#define WDG_ST_INTEXPIRED_SET (   x)    (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK)

◆ WDG_ST_INTEXPIRED_SHIFT

#define WDG_ST_INTEXPIRED_SHIFT   (0U)

◆ WDG_WREN_WEN_GET

#define WDG_WREN_WEN_GET (   x)    (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT)

◆ WDG_WREN_WEN_MASK

#define WDG_WREN_WEN_MASK   (0xFFFFU)

◆ WDG_WREN_WEN_SET

#define WDG_WREN_WEN_SET (   x)    (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK)

◆ WDG_WREN_WEN_SHIFT

#define WDG_WREN_WEN_SHIFT   (0U)