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Data Structures | |
| struct | GPTMR_Type |
| #define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) |
| #define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) |
| #define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) |
| #define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) |
| #define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) |
| #define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) |
| #define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) |
| #define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) |
| #define GPTMR_CHANNEL_CH0 (0UL) |
| #define GPTMR_CHANNEL_CH1 (1UL) |
| #define GPTMR_CHANNEL_CH2 (2UL) |
| #define GPTMR_CHANNEL_CH3 (3UL) |
| #define GPTMR_CHANNEL_CMP_CMP0 (0UL) |
| #define GPTMR_CHANNEL_CMP_CMP1 (1UL) |
| #define GPTMR_CHANNEL_CMP_CMP_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) |
| #define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CMP_CMP_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) |
| #define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) |
| #define GPTMR_CHANNEL_CNT_COUNTER_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) |
| #define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) |
| #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) |
| #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) |
| #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) |
| #define GPTMR_CHANNEL_CR_CAPMODE_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) |
| #define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) |
| #define GPTMR_CHANNEL_CR_CAPMODE_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) |
| #define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) |
| #define GPTMR_CHANNEL_CR_CEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) |
| #define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) |
| #define GPTMR_CHANNEL_CR_CEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) |
| #define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) |
| #define GPTMR_CHANNEL_CR_CMPEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) |
| #define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) |
| #define GPTMR_CHANNEL_CR_CMPEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) |
| #define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) |
| #define GPTMR_CHANNEL_CR_CMPINIT_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) |
| #define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) |
| #define GPTMR_CHANNEL_CR_CMPINIT_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) |
| #define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) |
| #define GPTMR_CHANNEL_CR_CNTRST_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) |
| #define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) |
| #define GPTMR_CHANNEL_CR_CNTRST_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) |
| #define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) |
| #define GPTMR_CHANNEL_CR_CNTUPT_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) |
| #define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) |
| #define GPTMR_CHANNEL_CR_CNTUPT_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) |
| #define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) |
| #define GPTMR_CHANNEL_CR_DBGPAUSE_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) |
| #define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) |
| #define GPTMR_CHANNEL_CR_DBGPAUSE_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) |
| #define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) |
| #define GPTMR_CHANNEL_CR_DMAEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) |
| #define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) |
| #define GPTMR_CHANNEL_CR_DMAEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) |
| #define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) |
| #define GPTMR_CHANNEL_CR_DMASEL_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) |
| #define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) |
| #define GPTMR_CHANNEL_CR_DMASEL_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) |
| #define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) |
| #define GPTMR_CHANNEL_CR_MONITOR_EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) >> GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) |
| #define GPTMR_CHANNEL_CR_MONITOR_EN_MASK (0x8000U) |
| #define GPTMR_CHANNEL_CR_MONITOR_EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) |
| #define GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT (15U) |
| #define GPTMR_CHANNEL_CR_MONITOR_SEL_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) >> GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) |
| #define GPTMR_CHANNEL_CR_MONITOR_SEL_MASK (0x10000UL) |
| #define GPTMR_CHANNEL_CR_MONITOR_SEL_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) |
| #define GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT (16U) |
| #define GPTMR_CHANNEL_CR_OPMODE_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_OPMODE_MASK) >> GPTMR_CHANNEL_CR_OPMODE_SHIFT) |
| #define GPTMR_CHANNEL_CR_OPMODE_MASK (0x20000UL) |
| #define GPTMR_CHANNEL_CR_OPMODE_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_OPMODE_SHIFT) & GPTMR_CHANNEL_CR_OPMODE_MASK) |
| #define GPTMR_CHANNEL_CR_OPMODE_SHIFT (17U) |
| #define GPTMR_CHANNEL_CR_SWSYNCIEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) |
| #define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) |
| #define GPTMR_CHANNEL_CR_SWSYNCIEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) |
| #define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) |
| #define GPTMR_CHANNEL_CR_SYNCFLW_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) |
| #define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) |
| #define GPTMR_CHANNEL_CR_SYNCFLW_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) |
| #define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) |
| #define GPTMR_CHANNEL_CR_SYNCIFEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) |
| #define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) |
| #define GPTMR_CHANNEL_CR_SYNCIFEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) |
| #define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) |
| #define GPTMR_CHANNEL_CR_SYNCIREN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) |
| #define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) |
| #define GPTMR_CHANNEL_CR_SYNCIREN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) |
| #define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) |
| #define GPTMR_CHANNEL_RLD_RLD_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) |
| #define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) |
| #define GPTMR_CHANNEL_RLD_RLD_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) |
| #define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) |
| #define GPTMR_GCR_SWSYNCT_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) |
| #define GPTMR_GCR_SWSYNCT_MASK (0xFU) |
| #define GPTMR_GCR_SWSYNCT_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) |
| #define GPTMR_GCR_SWSYNCT_SHIFT (0U) |
| #define GPTMR_IRQEN_CH0CAPEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) |
| #define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) |
| #define GPTMR_IRQEN_CH0CAPEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) |
| #define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) |
| #define GPTMR_IRQEN_CH0CMP0EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) |
| #define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) |
| #define GPTMR_IRQEN_CH0CMP0EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) |
| #define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) |
| #define GPTMR_IRQEN_CH0CMP1EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) |
| #define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) |
| #define GPTMR_IRQEN_CH0CMP1EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) |
| #define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) |
| #define GPTMR_IRQEN_CH0RLDEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) |
| #define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) |
| #define GPTMR_IRQEN_CH0RLDEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) |
| #define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) |
| #define GPTMR_IRQEN_CH1CAPEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) |
| #define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) |
| #define GPTMR_IRQEN_CH1CAPEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) |
| #define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) |
| #define GPTMR_IRQEN_CH1CMP0EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) |
| #define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) |
| #define GPTMR_IRQEN_CH1CMP0EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) |
| #define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) |
| #define GPTMR_IRQEN_CH1CMP1EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) |
| #define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) |
| #define GPTMR_IRQEN_CH1CMP1EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) |
| #define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) |
| #define GPTMR_IRQEN_CH1RLDEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) |
| #define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) |
| #define GPTMR_IRQEN_CH1RLDEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) |
| #define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) |
| #define GPTMR_IRQEN_CH2CAPEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) |
| #define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) |
| #define GPTMR_IRQEN_CH2CAPEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) |
| #define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) |
| #define GPTMR_IRQEN_CH2CMP0EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) |
| #define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) |
| #define GPTMR_IRQEN_CH2CMP0EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) |
| #define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) |
| #define GPTMR_IRQEN_CH2CMP1EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) |
| #define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) |
| #define GPTMR_IRQEN_CH2CMP1EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) |
| #define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) |
| #define GPTMR_IRQEN_CH2RLDEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) |
| #define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) |
| #define GPTMR_IRQEN_CH2RLDEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) |
| #define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) |
| #define GPTMR_IRQEN_CH3CAPEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) |
| #define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) |
| #define GPTMR_IRQEN_CH3CAPEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) |
| #define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) |
| #define GPTMR_IRQEN_CH3CMP0EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) |
| #define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) |
| #define GPTMR_IRQEN_CH3CMP0EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) |
| #define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) |
| #define GPTMR_IRQEN_CH3CMP1EN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) |
| #define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) |
| #define GPTMR_IRQEN_CH3CMP1EN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) |
| #define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) |
| #define GPTMR_IRQEN_CH3RLDEN_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) |
| #define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) |
| #define GPTMR_IRQEN_CH3RLDEN_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) |
| #define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) |
| #define GPTMR_SR_CH0CAPF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) |
| #define GPTMR_SR_CH0CAPF_MASK (0x2U) |
| #define GPTMR_SR_CH0CAPF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) |
| #define GPTMR_SR_CH0CAPF_SHIFT (1U) |
| #define GPTMR_SR_CH0CMP0F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) |
| #define GPTMR_SR_CH0CMP0F_MASK (0x4U) |
| #define GPTMR_SR_CH0CMP0F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) |
| #define GPTMR_SR_CH0CMP0F_SHIFT (2U) |
| #define GPTMR_SR_CH0CMP1F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) |
| #define GPTMR_SR_CH0CMP1F_MASK (0x8U) |
| #define GPTMR_SR_CH0CMP1F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) |
| #define GPTMR_SR_CH0CMP1F_SHIFT (3U) |
| #define GPTMR_SR_CH0RLDF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) |
| #define GPTMR_SR_CH0RLDF_MASK (0x1U) |
| #define GPTMR_SR_CH0RLDF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) |
| #define GPTMR_SR_CH0RLDF_SHIFT (0U) |
| #define GPTMR_SR_CH1CAPF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) |
| #define GPTMR_SR_CH1CAPF_MASK (0x20U) |
| #define GPTMR_SR_CH1CAPF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) |
| #define GPTMR_SR_CH1CAPF_SHIFT (5U) |
| #define GPTMR_SR_CH1CMP0F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) |
| #define GPTMR_SR_CH1CMP0F_MASK (0x40U) |
| #define GPTMR_SR_CH1CMP0F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) |
| #define GPTMR_SR_CH1CMP0F_SHIFT (6U) |
| #define GPTMR_SR_CH1CMP1F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) |
| #define GPTMR_SR_CH1CMP1F_MASK (0x80U) |
| #define GPTMR_SR_CH1CMP1F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) |
| #define GPTMR_SR_CH1CMP1F_SHIFT (7U) |
| #define GPTMR_SR_CH1RLDF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) |
| #define GPTMR_SR_CH1RLDF_MASK (0x10U) |
| #define GPTMR_SR_CH1RLDF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) |
| #define GPTMR_SR_CH1RLDF_SHIFT (4U) |
| #define GPTMR_SR_CH2CAPF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) |
| #define GPTMR_SR_CH2CAPF_MASK (0x200U) |
| #define GPTMR_SR_CH2CAPF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) |
| #define GPTMR_SR_CH2CAPF_SHIFT (9U) |
| #define GPTMR_SR_CH2CMP0F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) |
| #define GPTMR_SR_CH2CMP0F_MASK (0x400U) |
| #define GPTMR_SR_CH2CMP0F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) |
| #define GPTMR_SR_CH2CMP0F_SHIFT (10U) |
| #define GPTMR_SR_CH2CMP1F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) |
| #define GPTMR_SR_CH2CMP1F_MASK (0x800U) |
| #define GPTMR_SR_CH2CMP1F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) |
| #define GPTMR_SR_CH2CMP1F_SHIFT (11U) |
| #define GPTMR_SR_CH2RLDF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) |
| #define GPTMR_SR_CH2RLDF_MASK (0x100U) |
| #define GPTMR_SR_CH2RLDF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) |
| #define GPTMR_SR_CH2RLDF_SHIFT (8U) |
| #define GPTMR_SR_CH3CAPF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) |
| #define GPTMR_SR_CH3CAPF_MASK (0x2000U) |
| #define GPTMR_SR_CH3CAPF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) |
| #define GPTMR_SR_CH3CAPF_SHIFT (13U) |
| #define GPTMR_SR_CH3CMP0F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) |
| #define GPTMR_SR_CH3CMP0F_MASK (0x4000U) |
| #define GPTMR_SR_CH3CMP0F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) |
| #define GPTMR_SR_CH3CMP0F_SHIFT (14U) |
| #define GPTMR_SR_CH3CMP1F_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) |
| #define GPTMR_SR_CH3CMP1F_MASK (0x8000U) |
| #define GPTMR_SR_CH3CMP1F_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) |
| #define GPTMR_SR_CH3CMP1F_SHIFT (15U) |
| #define GPTMR_SR_CH3RLDF_GET | ( | x | ) | (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) |
| #define GPTMR_SR_CH3RLDF_MASK (0x1000U) |
| #define GPTMR_SR_CH3RLDF_SET | ( | x | ) | (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) |
| #define GPTMR_SR_CH3RLDF_SHIFT (12U) |