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Data Structures | |
| struct | VAD_Type |
| #define VAD_CIC_CFG_POST_SCALE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CIC_CFG_POST_SCALE_MASK) >> VAD_CIC_CFG_POST_SCALE_SHIFT) |
| #define VAD_CIC_CFG_POST_SCALE_MASK (0xFC00U) |
| #define VAD_CIC_CFG_POST_SCALE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CIC_CFG_POST_SCALE_SHIFT) & VAD_CIC_CFG_POST_SCALE_MASK) |
| #define VAD_CIC_CFG_POST_SCALE_SHIFT (10U) |
| #define VAD_COEF_STE_ACT (0UL) |
| #define VAD_COEF_VAL_GET | ( | x | ) | (((uint32_t)(x) & VAD_COEF_VAL_MASK) >> VAD_COEF_VAL_SHIFT) |
| #define VAD_COEF_VAL_MASK (0xFFFFFFFFUL) |
| #define VAD_COEF_VAL_SHIFT (0U) |
| #define VAD_CTRL_CAPT_DLY_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_CAPT_DLY_MASK) >> VAD_CTRL_CAPT_DLY_SHIFT) |
| #define VAD_CTRL_CAPT_DLY_MASK (0xF000000UL) |
| #define VAD_CTRL_CAPT_DLY_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_CAPT_DLY_SHIFT) & VAD_CTRL_CAPT_DLY_MASK) |
| #define VAD_CTRL_CAPT_DLY_SHIFT (24U) |
| #define VAD_CTRL_CH_POL_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_CH_POL_MASK) >> VAD_CTRL_CH_POL_SHIFT) |
| #define VAD_CTRL_CH_POL_MASK (0x6U) |
| #define VAD_CTRL_CH_POL_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_CH_POL_SHIFT) & VAD_CTRL_CH_POL_MASK) |
| #define VAD_CTRL_CH_POL_SHIFT (1U) |
| #define VAD_CTRL_CHNUM_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_CHNUM_MASK) >> VAD_CTRL_CHNUM_SHIFT) |
| #define VAD_CTRL_CHNUM_MASK (0x1U) |
| #define VAD_CTRL_CHNUM_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_CHNUM_SHIFT) & VAD_CTRL_CHNUM_MASK) |
| #define VAD_CTRL_CHNUM_SHIFT (0U) |
| #define VAD_CTRL_CIC_OVLD_ERR_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) >> VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) |
| #define VAD_CTRL_CIC_OVLD_ERR_IE_MASK (0x1000U) |
| #define VAD_CTRL_CIC_OVLD_ERR_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) |
| #define VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT (12U) |
| #define VAD_CTRL_CIC_SAT_ERR_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) >> VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) |
| #define VAD_CTRL_CIC_SAT_ERR_IE_MASK (0x800U) |
| #define VAD_CTRL_CIC_SAT_ERR_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) |
| #define VAD_CTRL_CIC_SAT_ERR_IE_SHIFT (11U) |
| #define VAD_CTRL_FIFO_THRSH_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_FIFO_THRSH_MASK) >> VAD_CTRL_FIFO_THRSH_SHIFT) |
| #define VAD_CTRL_FIFO_THRSH_MASK (0x1E0U) |
| #define VAD_CTRL_FIFO_THRSH_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_FIFO_THRSH_SHIFT) & VAD_CTRL_FIFO_THRSH_MASK) |
| #define VAD_CTRL_FIFO_THRSH_SHIFT (5U) |
| #define VAD_CTRL_IIR_OVFL_ERR_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) >> VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) |
| #define VAD_CTRL_IIR_OVFL_ERR_IE_MASK (0x2000U) |
| #define VAD_CTRL_IIR_OVFL_ERR_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) |
| #define VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT (13U) |
| #define VAD_CTRL_IIR_OVLD_ERR_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) >> VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) |
| #define VAD_CTRL_IIR_OVLD_ERR_IE_MASK (0x4000U) |
| #define VAD_CTRL_IIR_OVLD_ERR_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) |
| #define VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT (14U) |
| #define VAD_CTRL_MEMBUF_DISABLE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_MEMBUF_DISABLE_MASK) >> VAD_CTRL_MEMBUF_DISABLE_SHIFT) |
| #define VAD_CTRL_MEMBUF_DISABLE_MASK (0x200U) |
| #define VAD_CTRL_MEMBUF_DISABLE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_MEMBUF_DISABLE_SHIFT) & VAD_CTRL_MEMBUF_DISABLE_MASK) |
| #define VAD_CTRL_MEMBUF_DISABLE_SHIFT (9U) |
| #define VAD_CTRL_MEMBUF_EMPTY_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) >> VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) |
| #define VAD_CTRL_MEMBUF_EMPTY_IE_MASK (0x10000UL) |
| #define VAD_CTRL_MEMBUF_EMPTY_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) |
| #define VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT (16U) |
| #define VAD_CTRL_OFIFO_AV_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_OFIFO_AV_IE_MASK) >> VAD_CTRL_OFIFO_AV_IE_SHIFT) |
| #define VAD_CTRL_OFIFO_AV_IE_MASK (0x20000UL) |
| #define VAD_CTRL_OFIFO_AV_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_OFIFO_AV_IE_SHIFT) & VAD_CTRL_OFIFO_AV_IE_MASK) |
| #define VAD_CTRL_OFIFO_AV_IE_SHIFT (17U) |
| #define VAD_CTRL_OFIFO_OVFL_ERR_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) |
| #define VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x8000U) |
| #define VAD_CTRL_OFIFO_OVFL_ERR_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) |
| #define VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (15U) |
| #define VAD_CTRL_PDM_CLK_DIV_BYPASS_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) |
| #define VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x10U) |
| #define VAD_CTRL_PDM_CLK_DIV_BYPASS_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) |
| #define VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (4U) |
| #define VAD_CTRL_PDM_CLK_HFDIV_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_PDM_CLK_HFDIV_MASK) >> VAD_CTRL_PDM_CLK_HFDIV_SHIFT) |
| #define VAD_CTRL_PDM_CLK_HFDIV_MASK (0xF00000UL) |
| #define VAD_CTRL_PDM_CLK_HFDIV_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_PDM_CLK_HFDIV_SHIFT) & VAD_CTRL_PDM_CLK_HFDIV_MASK) |
| #define VAD_CTRL_PDM_CLK_HFDIV_SHIFT (20U) |
| #define VAD_CTRL_PDM_CLK_OE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_PDM_CLK_OE_MASK) >> VAD_CTRL_PDM_CLK_OE_SHIFT) |
| #define VAD_CTRL_PDM_CLK_OE_MASK (0x8U) |
| #define VAD_CTRL_PDM_CLK_OE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_PDM_CLK_OE_SHIFT) & VAD_CTRL_PDM_CLK_OE_MASK) |
| #define VAD_CTRL_PDM_CLK_OE_SHIFT (3U) |
| #define VAD_CTRL_VAD_IE_GET | ( | x | ) | (((uint32_t)(x) & VAD_CTRL_VAD_IE_MASK) >> VAD_CTRL_VAD_IE_SHIFT) |
| #define VAD_CTRL_VAD_IE_MASK (0x40000UL) |
| #define VAD_CTRL_VAD_IE_SET | ( | x | ) | (((uint32_t)(x) << VAD_CTRL_VAD_IE_SHIFT) & VAD_CTRL_VAD_IE_MASK) |
| #define VAD_CTRL_VAD_IE_SHIFT (18U) |
| #define VAD_DEC_CTRL0_BLK_CFG_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL0_BLK_CFG_MASK) >> VAD_DEC_CTRL0_BLK_CFG_SHIFT) |
| #define VAD_DEC_CTRL0_BLK_CFG_MASK (0x200U) |
| #define VAD_DEC_CTRL0_BLK_CFG_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL0_BLK_CFG_SHIFT) & VAD_DEC_CTRL0_BLK_CFG_MASK) |
| #define VAD_DEC_CTRL0_BLK_CFG_SHIFT (9U) |
| #define VAD_DEC_CTRL0_NOISE_TOL_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL0_NOISE_TOL_MASK) >> VAD_DEC_CTRL0_NOISE_TOL_SHIFT) |
| #define VAD_DEC_CTRL0_NOISE_TOL_MASK (0xFFFF0000UL) |
| #define VAD_DEC_CTRL0_NOISE_TOL_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL0_NOISE_TOL_SHIFT) & VAD_DEC_CTRL0_NOISE_TOL_MASK) |
| #define VAD_DEC_CTRL0_NOISE_TOL_SHIFT (16U) |
| #define VAD_DEC_CTRL0_SUBBLK_LEN_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) >> VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) |
| #define VAD_DEC_CTRL0_SUBBLK_LEN_MASK (0x1FFU) |
| #define VAD_DEC_CTRL0_SUBBLK_LEN_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) |
| #define VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT (0U) |
| #define VAD_DEC_CTRL1_ZCR_HIGH_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) >> VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) |
| #define VAD_DEC_CTRL1_ZCR_HIGH_MASK (0x3FF800UL) |
| #define VAD_DEC_CTRL1_ZCR_HIGH_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) |
| #define VAD_DEC_CTRL1_ZCR_HIGH_SHIFT (11U) |
| #define VAD_DEC_CTRL1_ZCR_LOW_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_LOW_MASK) >> VAD_DEC_CTRL1_ZCR_LOW_SHIFT) |
| #define VAD_DEC_CTRL1_ZCR_LOW_MASK (0x7FFU) |
| #define VAD_DEC_CTRL1_ZCR_LOW_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_LOW_SHIFT) & VAD_DEC_CTRL1_ZCR_LOW_MASK) |
| #define VAD_DEC_CTRL1_ZCR_LOW_SHIFT (0U) |
| #define VAD_DEC_CTRL2_AMP_HIGH_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_HIGH_MASK) >> VAD_DEC_CTRL2_AMP_HIGH_SHIFT) |
| #define VAD_DEC_CTRL2_AMP_HIGH_MASK (0xFFFF0000UL) |
| #define VAD_DEC_CTRL2_AMP_HIGH_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_HIGH_SHIFT) & VAD_DEC_CTRL2_AMP_HIGH_MASK) |
| #define VAD_DEC_CTRL2_AMP_HIGH_SHIFT (16U) |
| #define VAD_DEC_CTRL2_AMP_LOW_GET | ( | x | ) | (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_LOW_MASK) >> VAD_DEC_CTRL2_AMP_LOW_SHIFT) |
| #define VAD_DEC_CTRL2_AMP_LOW_MASK (0xFFFFU) |
| #define VAD_DEC_CTRL2_AMP_LOW_SET | ( | x | ) | (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_LOW_SHIFT) & VAD_DEC_CTRL2_AMP_LOW_MASK) |
| #define VAD_DEC_CTRL2_AMP_LOW_SHIFT (0U) |
| #define VAD_FILTCTRL_DECRATIO_GET | ( | x | ) | (((uint32_t)(x) & VAD_FILTCTRL_DECRATIO_MASK) >> VAD_FILTCTRL_DECRATIO_SHIFT) |
| #define VAD_FILTCTRL_DECRATIO_MASK (0x700U) |
| #define VAD_FILTCTRL_DECRATIO_SET | ( | x | ) | (((uint32_t)(x) << VAD_FILTCTRL_DECRATIO_SHIFT) & VAD_FILTCTRL_DECRATIO_MASK) |
| #define VAD_FILTCTRL_DECRATIO_SHIFT (8U) |
| #define VAD_FILTCTRL_IIR_SLOT_EN_GET | ( | x | ) | (((uint32_t)(x) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) >> VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) |
| #define VAD_FILTCTRL_IIR_SLOT_EN_MASK (0xFFU) |
| #define VAD_FILTCTRL_IIR_SLOT_EN_SET | ( | x | ) | (((uint32_t)(x) << VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) |
| #define VAD_FILTCTRL_IIR_SLOT_EN_SHIFT (0U) |
| #define VAD_OFIFO_CTRL_EN_GET | ( | x | ) | (((uint32_t)(x) & VAD_OFIFO_CTRL_EN_MASK) >> VAD_OFIFO_CTRL_EN_SHIFT) |
| #define VAD_OFIFO_CTRL_EN_MASK (0x1U) |
| #define VAD_OFIFO_CTRL_EN_SET | ( | x | ) | (((uint32_t)(x) << VAD_OFIFO_CTRL_EN_SHIFT) & VAD_OFIFO_CTRL_EN_MASK) |
| #define VAD_OFIFO_CTRL_EN_SHIFT (0U) |
| #define VAD_OFIFO_D_GET | ( | x | ) | (((uint32_t)(x) & VAD_OFIFO_D_MASK) >> VAD_OFIFO_D_SHIFT) |
| #define VAD_OFIFO_D_MASK (0xFFFFFFFFUL) |
| #define VAD_OFIFO_D_SET | ( | x | ) | (((uint32_t)(x) << VAD_OFIFO_D_SHIFT) & VAD_OFIFO_D_MASK) |
| #define VAD_OFIFO_D_SHIFT (0U) |
| #define VAD_RUN_SFTRST_GET | ( | x | ) | (((uint32_t)(x) & VAD_RUN_SFTRST_MASK) >> VAD_RUN_SFTRST_SHIFT) |
| #define VAD_RUN_SFTRST_MASK (0x2U) |
| #define VAD_RUN_SFTRST_SET | ( | x | ) | (((uint32_t)(x) << VAD_RUN_SFTRST_SHIFT) & VAD_RUN_SFTRST_MASK) |
| #define VAD_RUN_SFTRST_SHIFT (1U) |
| #define VAD_RUN_VAD_EN_GET | ( | x | ) | (((uint32_t)(x) & VAD_RUN_VAD_EN_MASK) >> VAD_RUN_VAD_EN_SHIFT) |
| #define VAD_RUN_VAD_EN_MASK (0x1U) |
| #define VAD_RUN_VAD_EN_SET | ( | x | ) | (((uint32_t)(x) << VAD_RUN_VAD_EN_SHIFT) & VAD_RUN_VAD_EN_MASK) |
| #define VAD_RUN_VAD_EN_SHIFT (0U) |
| #define VAD_ST_CIC_OVLD_ERR_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_CIC_OVLD_ERR_MASK) >> VAD_ST_CIC_OVLD_ERR_SHIFT) |
| #define VAD_ST_CIC_OVLD_ERR_MASK (0x2U) |
| #define VAD_ST_CIC_OVLD_ERR_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_CIC_OVLD_ERR_SHIFT) & VAD_ST_CIC_OVLD_ERR_MASK) |
| #define VAD_ST_CIC_OVLD_ERR_SHIFT (1U) |
| #define VAD_ST_CIC_SAT_ERR_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_CIC_SAT_ERR_MASK) >> VAD_ST_CIC_SAT_ERR_SHIFT) |
| #define VAD_ST_CIC_SAT_ERR_MASK (0x1U) |
| #define VAD_ST_CIC_SAT_ERR_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_CIC_SAT_ERR_SHIFT) & VAD_ST_CIC_SAT_ERR_MASK) |
| #define VAD_ST_CIC_SAT_ERR_SHIFT (0U) |
| #define VAD_ST_IIR_OVFL_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_IIR_OVFL_MASK) >> VAD_ST_IIR_OVFL_SHIFT) |
| #define VAD_ST_IIR_OVFL_MASK (0x4U) |
| #define VAD_ST_IIR_OVFL_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_IIR_OVFL_SHIFT) & VAD_ST_IIR_OVFL_MASK) |
| #define VAD_ST_IIR_OVFL_SHIFT (2U) |
| #define VAD_ST_IIR_OVLD_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_IIR_OVLD_MASK) >> VAD_ST_IIR_OVLD_SHIFT) |
| #define VAD_ST_IIR_OVLD_MASK (0x8U) |
| #define VAD_ST_IIR_OVLD_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_IIR_OVLD_SHIFT) & VAD_ST_IIR_OVLD_MASK) |
| #define VAD_ST_IIR_OVLD_SHIFT (3U) |
| #define VAD_ST_MEMBUF_EMPTY_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_MEMBUF_EMPTY_MASK) >> VAD_ST_MEMBUF_EMPTY_SHIFT) |
| #define VAD_ST_MEMBUF_EMPTY_MASK (0x20U) |
| #define VAD_ST_MEMBUF_EMPTY_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_MEMBUF_EMPTY_SHIFT) & VAD_ST_MEMBUF_EMPTY_MASK) |
| #define VAD_ST_MEMBUF_EMPTY_SHIFT (5U) |
| #define VAD_ST_OFIFO_AV_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_OFIFO_AV_MASK) >> VAD_ST_OFIFO_AV_SHIFT) |
| #define VAD_ST_OFIFO_AV_MASK (0x40U) |
| #define VAD_ST_OFIFO_AV_SHIFT (6U) |
| #define VAD_ST_OFIFO_OVFL_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_OFIFO_OVFL_MASK) >> VAD_ST_OFIFO_OVFL_SHIFT) |
| #define VAD_ST_OFIFO_OVFL_MASK (0x10U) |
| #define VAD_ST_OFIFO_OVFL_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_OFIFO_OVFL_SHIFT) & VAD_ST_OFIFO_OVFL_MASK) |
| #define VAD_ST_OFIFO_OVFL_SHIFT (4U) |
| #define VAD_ST_VAD_GET | ( | x | ) | (((uint32_t)(x) & VAD_ST_VAD_MASK) >> VAD_ST_VAD_SHIFT) |
| #define VAD_ST_VAD_MASK (0x80U) |
| #define VAD_ST_VAD_SET | ( | x | ) | (((uint32_t)(x) << VAD_ST_VAD_SHIFT) & VAD_ST_VAD_MASK) |
| #define VAD_ST_VAD_SHIFT (7U) |