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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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Go to the source code of this file.
Data Structures | |
| struct | RDC_Type |
| #define RDC_ACC_CNT_I_CNT_NEG_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_NEG_MASK) >> RDC_ACC_CNT_I_CNT_NEG_SHIFT) |
| #define RDC_ACC_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) |
| #define RDC_ACC_CNT_I_CNT_NEG_SHIFT (16U) |
| #define RDC_ACC_CNT_I_CNT_POS_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_POS_MASK) >> RDC_ACC_CNT_I_CNT_POS_SHIFT) |
| #define RDC_ACC_CNT_I_CNT_POS_MASK (0xFFFFU) |
| #define RDC_ACC_CNT_I_CNT_POS_SHIFT (0U) |
| #define RDC_ACC_CNT_Q_CNT_NEG_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_NEG_MASK) >> RDC_ACC_CNT_Q_CNT_NEG_SHIFT) |
| #define RDC_ACC_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) |
| #define RDC_ACC_CNT_Q_CNT_NEG_SHIFT (16U) |
| #define RDC_ACC_CNT_Q_CNT_POS_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_POS_MASK) >> RDC_ACC_CNT_Q_CNT_POS_SHIFT) |
| #define RDC_ACC_CNT_Q_CNT_POS_MASK (0xFFFFU) |
| #define RDC_ACC_CNT_Q_CNT_POS_SHIFT (0U) |
| #define RDC_ACC_I_ACC_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_I_ACC_MASK) >> RDC_ACC_I_ACC_SHIFT) |
| #define RDC_ACC_I_ACC_MASK (0xFFFFFFFFUL) |
| #define RDC_ACC_I_ACC_SHIFT (0U) |
| #define RDC_ACC_Q_ACC_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_Q_ACC_MASK) >> RDC_ACC_Q_ACC_SHIFT) |
| #define RDC_ACC_Q_ACC_MASK (0xFFFFFFFFUL) |
| #define RDC_ACC_Q_ACC_SHIFT (0U) |
| #define RDC_ACC_SCALING_ACC_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_SCALING_ACC_SHIFT_MASK) >> RDC_ACC_SCALING_ACC_SHIFT_SHIFT) |
| #define RDC_ACC_SCALING_ACC_SHIFT_MASK (0xFU) |
| #define RDC_ACC_SCALING_ACC_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << RDC_ACC_SCALING_ACC_SHIFT_SHIFT) & RDC_ACC_SCALING_ACC_SHIFT_MASK) |
| #define RDC_ACC_SCALING_ACC_SHIFT_SHIFT (0U) |
| #define RDC_ACC_SCALING_TOXIC_LK_GET | ( | x | ) | (((uint32_t)(x) & RDC_ACC_SCALING_TOXIC_LK_MASK) >> RDC_ACC_SCALING_TOXIC_LK_SHIFT) |
| #define RDC_ACC_SCALING_TOXIC_LK_MASK (0x100U) |
| #define RDC_ACC_SCALING_TOXIC_LK_SET | ( | x | ) | (((uint32_t)(x) << RDC_ACC_SCALING_TOXIC_LK_SHIFT) & RDC_ACC_SCALING_TOXIC_LK_MASK) |
| #define RDC_ACC_SCALING_TOXIC_LK_SHIFT (8U) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK (0x2U) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT (1U) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK (0x1U) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT (0U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK (0x20U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT (5U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK (0x8U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT (3U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK (0x8000U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT (15U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK (0x10U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT (4U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK (0x4U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT (2U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK (0x4000U) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) |
| #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT (14U) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK (0x1000U) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT (12U) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK (0x400U) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) |
| #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT (10U) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK (0x2000U) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT (13U) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK (0x800U) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) |
| #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT (11U) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK (0x100U) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT (8U) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK (0x40U) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) |
| #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT (6U) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK (0x200U) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT (9U) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_GET | ( | x | ) | (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK (0x80U) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SET | ( | x | ) | (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) |
| #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT (7U) |
| #define RDC_AMP_MAX_MAX_GET | ( | x | ) | (((uint32_t)(x) & RDC_AMP_MAX_MAX_MASK) >> RDC_AMP_MAX_MAX_SHIFT) |
| #define RDC_AMP_MAX_MAX_MASK (0xFFFFFFFFUL) |
| #define RDC_AMP_MAX_MAX_SET | ( | x | ) | (((uint32_t)(x) << RDC_AMP_MAX_MAX_SHIFT) & RDC_AMP_MAX_MAX_MASK) |
| #define RDC_AMP_MAX_MAX_SHIFT (0U) |
| #define RDC_AMP_MIN_MIN_GET | ( | x | ) | (((uint32_t)(x) & RDC_AMP_MIN_MIN_MASK) >> RDC_AMP_MIN_MIN_SHIFT) |
| #define RDC_AMP_MIN_MIN_MASK (0xFFFFFFFFUL) |
| #define RDC_AMP_MIN_MIN_SET | ( | x | ) | (((uint32_t)(x) << RDC_AMP_MIN_MIN_SHIFT) & RDC_AMP_MIN_MIN_MASK) |
| #define RDC_AMP_MIN_MIN_SHIFT (0U) |
| #define RDC_EDG_DET_CTL_FILTER_GET | ( | x | ) | (((uint32_t)(x) & RDC_EDG_DET_CTL_FILTER_MASK) >> RDC_EDG_DET_CTL_FILTER_SHIFT) |
| #define RDC_EDG_DET_CTL_FILTER_MASK (0x7U) |
| #define RDC_EDG_DET_CTL_FILTER_SET | ( | x | ) | (((uint32_t)(x) << RDC_EDG_DET_CTL_FILTER_SHIFT) & RDC_EDG_DET_CTL_FILTER_MASK) |
| #define RDC_EDG_DET_CTL_FILTER_SHIFT (0U) |
| #define RDC_EDG_DET_CTL_HOLD_GET | ( | x | ) | (((uint32_t)(x) & RDC_EDG_DET_CTL_HOLD_MASK) >> RDC_EDG_DET_CTL_HOLD_SHIFT) |
| #define RDC_EDG_DET_CTL_HOLD_MASK (0x3F0U) |
| #define RDC_EDG_DET_CTL_HOLD_SET | ( | x | ) | (((uint32_t)(x) << RDC_EDG_DET_CTL_HOLD_SHIFT) & RDC_EDG_DET_CTL_HOLD_MASK) |
| #define RDC_EDG_DET_CTL_HOLD_SHIFT (4U) |
| #define RDC_EXC_OFFSET_AMP_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) >> RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) |
| #define RDC_EXC_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) |
| #define RDC_EXC_OFFSET_AMP_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) |
| #define RDC_EXC_OFFSET_AMP_OFFSET_SHIFT (0U) |
| #define RDC_EXC_PERIOD_EXC_PERIOD_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) >> RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) |
| #define RDC_EXC_PERIOD_EXC_PERIOD_MASK (0xFFFFFFFFUL) |
| #define RDC_EXC_PERIOD_EXC_PERIOD_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) |
| #define RDC_EXC_PERIOD_EXC_PERIOD_SHIFT (0U) |
| #define RDC_EXC_SCALING_AMP_EXP_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_SCALING_AMP_EXP_MASK) >> RDC_EXC_SCALING_AMP_EXP_SHIFT) |
| #define RDC_EXC_SCALING_AMP_EXP_MASK (0xF0U) |
| #define RDC_EXC_SCALING_AMP_EXP_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_SCALING_AMP_EXP_SHIFT) & RDC_EXC_SCALING_AMP_EXP_MASK) |
| #define RDC_EXC_SCALING_AMP_EXP_SHIFT (4U) |
| #define RDC_EXC_SCALING_AMP_MAN_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_SCALING_AMP_MAN_MASK) >> RDC_EXC_SCALING_AMP_MAN_SHIFT) |
| #define RDC_EXC_SCALING_AMP_MAN_MASK (0xFU) |
| #define RDC_EXC_SCALING_AMP_MAN_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_SCALING_AMP_MAN_SHIFT) & RDC_EXC_SCALING_AMP_MAN_MASK) |
| #define RDC_EXC_SCALING_AMP_MAN_SHIFT (0U) |
| #define RDC_EXC_SYNC_DLY_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DELAY_MASK) >> RDC_EXC_SYNC_DLY_DELAY_SHIFT) |
| #define RDC_EXC_SYNC_DLY_DELAY_MASK (0xFFFFFFUL) |
| #define RDC_EXC_SYNC_DLY_DELAY_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DELAY_SHIFT) & RDC_EXC_SYNC_DLY_DELAY_MASK) |
| #define RDC_EXC_SYNC_DLY_DELAY_SHIFT (0U) |
| #define RDC_EXC_SYNC_DLY_DISABLE_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DISABLE_MASK) >> RDC_EXC_SYNC_DLY_DISABLE_SHIFT) |
| #define RDC_EXC_SYNC_DLY_DISABLE_MASK (0x1000000UL) |
| #define RDC_EXC_SYNC_DLY_DISABLE_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DISABLE_SHIFT) & RDC_EXC_SYNC_DLY_DISABLE_MASK) |
| #define RDC_EXC_SYNC_DLY_DISABLE_SHIFT (24U) |
| #define RDC_EXC_TIMMING_PWM_PRD_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_TIMMING_PWM_PRD_MASK) >> RDC_EXC_TIMMING_PWM_PRD_SHIFT) |
| #define RDC_EXC_TIMMING_PWM_PRD_MASK (0xF00000UL) |
| #define RDC_EXC_TIMMING_PWM_PRD_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_TIMMING_PWM_PRD_SHIFT) & RDC_EXC_TIMMING_PWM_PRD_MASK) |
| #define RDC_EXC_TIMMING_PWM_PRD_SHIFT (20U) |
| #define RDC_EXC_TIMMING_SMP_NUM_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_NUM_MASK) >> RDC_EXC_TIMMING_SMP_NUM_SHIFT) |
| #define RDC_EXC_TIMMING_SMP_NUM_MASK (0xF0000UL) |
| #define RDC_EXC_TIMMING_SMP_NUM_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_NUM_SHIFT) & RDC_EXC_TIMMING_SMP_NUM_MASK) |
| #define RDC_EXC_TIMMING_SMP_NUM_SHIFT (16U) |
| #define RDC_EXC_TIMMING_SMP_RATE_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_RATE_MASK) >> RDC_EXC_TIMMING_SMP_RATE_SHIFT) |
| #define RDC_EXC_TIMMING_SMP_RATE_MASK (0xFFFFU) |
| #define RDC_EXC_TIMMING_SMP_RATE_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_RATE_SHIFT) & RDC_EXC_TIMMING_SMP_RATE_MASK) |
| #define RDC_EXC_TIMMING_SMP_RATE_SHIFT (0U) |
| #define RDC_EXC_TIMMING_SWAP_GET | ( | x | ) | (((uint32_t)(x) & RDC_EXC_TIMMING_SWAP_MASK) >> RDC_EXC_TIMMING_SWAP_SHIFT) |
| #define RDC_EXC_TIMMING_SWAP_MASK (0x1000000UL) |
| #define RDC_EXC_TIMMING_SWAP_SET | ( | x | ) | (((uint32_t)(x) << RDC_EXC_TIMMING_SWAP_SHIFT) & RDC_EXC_TIMMING_SWAP_MASK) |
| #define RDC_EXC_TIMMING_SWAP_SHIFT (24U) |
| #define RDC_FALL_DELAY_I_FALL_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_FALL_DELAY_I_FALL_DELAY_MASK) >> RDC_FALL_DELAY_I_FALL_DELAY_SHIFT) |
| #define RDC_FALL_DELAY_I_FALL_DELAY_MASK (0xFFFFFFFFUL) |
| #define RDC_FALL_DELAY_I_FALL_DELAY_SHIFT (0U) |
| #define RDC_FALL_DELAY_Q_FALL_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_FALL_DELAY_Q_FALL_DELAY_MASK) >> RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT) |
| #define RDC_FALL_DELAY_Q_FALL_DELAY_MASK (0xFFFFFFFFUL) |
| #define RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT (0U) |
| #define RDC_IIR_A_IIR_A1_GET | ( | x | ) | (((uint32_t)(x) & RDC_IIR_A_IIR_A1_MASK) >> RDC_IIR_A_IIR_A1_SHIFT) |
| #define RDC_IIR_A_IIR_A1_MASK (0x1FFU) |
| #define RDC_IIR_A_IIR_A1_SET | ( | x | ) | (((uint32_t)(x) << RDC_IIR_A_IIR_A1_SHIFT) & RDC_IIR_A_IIR_A1_MASK) |
| #define RDC_IIR_A_IIR_A1_SHIFT (0U) |
| #define RDC_IIR_A_IIR_A2_GET | ( | x | ) | (((uint32_t)(x) & RDC_IIR_A_IIR_A2_MASK) >> RDC_IIR_A_IIR_A2_SHIFT) |
| #define RDC_IIR_A_IIR_A2_MASK (0xFF0000UL) |
| #define RDC_IIR_A_IIR_A2_SET | ( | x | ) | (((uint32_t)(x) << RDC_IIR_A_IIR_A2_SHIFT) & RDC_IIR_A_IIR_A2_MASK) |
| #define RDC_IIR_A_IIR_A2_SHIFT (16U) |
| #define RDC_IIR_B_IIR_B_GET | ( | x | ) | (((uint32_t)(x) & RDC_IIR_B_IIR_B_MASK) >> RDC_IIR_B_IIR_B_SHIFT) |
| #define RDC_IIR_B_IIR_B_MASK (0x7U) |
| #define RDC_IIR_B_IIR_B_SET | ( | x | ) | (((uint32_t)(x) << RDC_IIR_B_IIR_B_SHIFT) & RDC_IIR_B_IIR_B_MASK) |
| #define RDC_IIR_B_IIR_B_SHIFT (0U) |
| #define RDC_IIR_B_LOWPASS_GET | ( | x | ) | (((uint32_t)(x) & RDC_IIR_B_LOWPASS_MASK) >> RDC_IIR_B_LOWPASS_SHIFT) |
| #define RDC_IIR_B_LOWPASS_MASK (0x1000000UL) |
| #define RDC_IIR_B_LOWPASS_SET | ( | x | ) | (((uint32_t)(x) << RDC_IIR_B_LOWPASS_SHIFT) & RDC_IIR_B_LOWPASS_MASK) |
| #define RDC_IIR_B_LOWPASS_SHIFT (24U) |
| #define RDC_IN_CTL_CH_I_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_IN_CTL_CH_I_SEL_MASK) >> RDC_IN_CTL_CH_I_SEL_SHIFT) |
| #define RDC_IN_CTL_CH_I_SEL_MASK (0x1FU) |
| #define RDC_IN_CTL_CH_I_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_IN_CTL_CH_I_SEL_SHIFT) & RDC_IN_CTL_CH_I_SEL_MASK) |
| #define RDC_IN_CTL_CH_I_SEL_SHIFT (0U) |
| #define RDC_IN_CTL_CH_Q_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_IN_CTL_CH_Q_SEL_MASK) >> RDC_IN_CTL_CH_Q_SEL_SHIFT) |
| #define RDC_IN_CTL_CH_Q_SEL_MASK (0x1F000UL) |
| #define RDC_IN_CTL_CH_Q_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_IN_CTL_CH_Q_SEL_SHIFT) & RDC_IN_CTL_CH_Q_SEL_MASK) |
| #define RDC_IN_CTL_CH_Q_SEL_SHIFT (12U) |
| #define RDC_IN_CTL_PORT_I_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_IN_CTL_PORT_I_SEL_MASK) >> RDC_IN_CTL_PORT_I_SEL_SHIFT) |
| #define RDC_IN_CTL_PORT_I_SEL_MASK (0x100U) |
| #define RDC_IN_CTL_PORT_I_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_IN_CTL_PORT_I_SEL_SHIFT) & RDC_IN_CTL_PORT_I_SEL_MASK) |
| #define RDC_IN_CTL_PORT_I_SEL_SHIFT (8U) |
| #define RDC_IN_CTL_PORT_Q_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_IN_CTL_PORT_Q_SEL_MASK) >> RDC_IN_CTL_PORT_Q_SEL_SHIFT) |
| #define RDC_IN_CTL_PORT_Q_SEL_MASK (0x100000UL) |
| #define RDC_IN_CTL_PORT_Q_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_IN_CTL_PORT_Q_SEL_SHIFT) & RDC_IN_CTL_PORT_Q_SEL_MASK) |
| #define RDC_IN_CTL_PORT_Q_SEL_SHIFT (20U) |
| #define RDC_INT_EN_ACC_AMP_OVH_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) |
| #define RDC_INT_EN_ACC_AMP_OVH_EN_MASK (0x2U) |
| #define RDC_INT_EN_ACC_AMP_OVH_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) |
| #define RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT (1U) |
| #define RDC_INT_EN_ACC_AMP_OVL_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) |
| #define RDC_INT_EN_ACC_AMP_OVL_EN_MASK (0x1U) |
| #define RDC_INT_EN_ACC_AMP_OVL_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) |
| #define RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT (0U) |
| #define RDC_INT_EN_ACC_VLD_I_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_EN_SHIFT) |
| #define RDC_INT_EN_ACC_VLD_I_EN_MASK (0x8000U) |
| #define RDC_INT_EN_ACC_VLD_I_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_EN_MASK) |
| #define RDC_INT_EN_ACC_VLD_I_EN_SHIFT (15U) |
| #define RDC_INT_EN_ACC_VLD_I_OVH_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) |
| #define RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK (0x20U) |
| #define RDC_INT_EN_ACC_VLD_I_OVH_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) |
| #define RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT (5U) |
| #define RDC_INT_EN_ACC_VLD_I_OVL_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) |
| #define RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK (0x8U) |
| #define RDC_INT_EN_ACC_VLD_I_OVL_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) |
| #define RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT (3U) |
| #define RDC_INT_EN_ACC_VLD_Q_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) |
| #define RDC_INT_EN_ACC_VLD_Q_EN_MASK (0x4000U) |
| #define RDC_INT_EN_ACC_VLD_Q_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) |
| #define RDC_INT_EN_ACC_VLD_Q_EN_SHIFT (14U) |
| #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) |
| #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK (0x10U) |
| #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) |
| #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT (4U) |
| #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) |
| #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK (0x4U) |
| #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) |
| #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT (2U) |
| #define RDC_INT_EN_FALLING_DELAY_I_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) |
| #define RDC_INT_EN_FALLING_DELAY_I_EN_MASK (0x1000U) |
| #define RDC_INT_EN_FALLING_DELAY_I_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) |
| #define RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT (12U) |
| #define RDC_INT_EN_FALLING_DELAY_Q_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) |
| #define RDC_INT_EN_FALLING_DELAY_Q_EN_MASK (0x400U) |
| #define RDC_INT_EN_FALLING_DELAY_Q_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) |
| #define RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT (10U) |
| #define RDC_INT_EN_INT_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_INT_EN_MASK) >> RDC_INT_EN_INT_EN_SHIFT) |
| #define RDC_INT_EN_INT_EN_MASK (0x80000000UL) |
| #define RDC_INT_EN_INT_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_INT_EN_SHIFT) & RDC_INT_EN_INT_EN_MASK) |
| #define RDC_INT_EN_INT_EN_SHIFT (31U) |
| #define RDC_INT_EN_RISING_DELAY_I_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) >> RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) |
| #define RDC_INT_EN_RISING_DELAY_I_EN_MASK (0x2000U) |
| #define RDC_INT_EN_RISING_DELAY_I_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) |
| #define RDC_INT_EN_RISING_DELAY_I_EN_SHIFT (13U) |
| #define RDC_INT_EN_RISING_DELAY_Q_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) >> RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) |
| #define RDC_INT_EN_RISING_DELAY_Q_EN_MASK (0x800U) |
| #define RDC_INT_EN_RISING_DELAY_Q_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) |
| #define RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT (11U) |
| #define RDC_INT_EN_SAMPLE_FALLING_I_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) |
| #define RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK (0x100U) |
| #define RDC_INT_EN_SAMPLE_FALLING_I_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) |
| #define RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT (8U) |
| #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) |
| #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK (0x40U) |
| #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) |
| #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT (6U) |
| #define RDC_INT_EN_SAMPLE_RISING_I_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) |
| #define RDC_INT_EN_SAMPLE_RISING_I_EN_MASK (0x200U) |
| #define RDC_INT_EN_SAMPLE_RISING_I_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) |
| #define RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT (9U) |
| #define RDC_INT_EN_SAMPLE_RISING_Q_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) |
| #define RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK (0x80U) |
| #define RDC_INT_EN_SAMPLE_RISING_Q_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) |
| #define RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT (7U) |
| #define RDC_MAX_I_MAX_GET | ( | x | ) | (((uint32_t)(x) & RDC_MAX_I_MAX_MASK) >> RDC_MAX_I_MAX_SHIFT) |
| #define RDC_MAX_I_MAX_MASK (0xFFFFFF00UL) |
| #define RDC_MAX_I_MAX_SET | ( | x | ) | (((uint32_t)(x) << RDC_MAX_I_MAX_SHIFT) & RDC_MAX_I_MAX_MASK) |
| #define RDC_MAX_I_MAX_SHIFT (8U) |
| #define RDC_MAX_I_VALID_GET | ( | x | ) | (((uint32_t)(x) & RDC_MAX_I_VALID_MASK) >> RDC_MAX_I_VALID_SHIFT) |
| #define RDC_MAX_I_VALID_MASK (0x1U) |
| #define RDC_MAX_I_VALID_SET | ( | x | ) | (((uint32_t)(x) << RDC_MAX_I_VALID_SHIFT) & RDC_MAX_I_VALID_MASK) |
| #define RDC_MAX_I_VALID_SHIFT (0U) |
| #define RDC_MAX_MIN_POS_MAX_MIN_POS_GET | ( | x | ) | (((uint32_t)(x) & RDC_MAX_MIN_POS_MAX_MIN_POS_MASK) >> RDC_MAX_MIN_POS_MAX_MIN_POS_SHIFT) |
| #define RDC_MAX_MIN_POS_MAX_MIN_POS_MASK (0x1U) |
| #define RDC_MAX_MIN_POS_MAX_MIN_POS_SET | ( | x | ) | (((uint32_t)(x) << RDC_MAX_MIN_POS_MAX_MIN_POS_SHIFT) & RDC_MAX_MIN_POS_MAX_MIN_POS_MASK) |
| #define RDC_MAX_MIN_POS_MAX_MIN_POS_SHIFT (0U) |
| #define RDC_MAX_Q_MAX_GET | ( | x | ) | (((uint32_t)(x) & RDC_MAX_Q_MAX_MASK) >> RDC_MAX_Q_MAX_SHIFT) |
| #define RDC_MAX_Q_MAX_MASK (0xFFFFFF00UL) |
| #define RDC_MAX_Q_MAX_SET | ( | x | ) | (((uint32_t)(x) << RDC_MAX_Q_MAX_SHIFT) & RDC_MAX_Q_MAX_MASK) |
| #define RDC_MAX_Q_MAX_SHIFT (8U) |
| #define RDC_MAX_Q_VALID_GET | ( | x | ) | (((uint32_t)(x) & RDC_MAX_Q_VALID_MASK) >> RDC_MAX_Q_VALID_SHIFT) |
| #define RDC_MAX_Q_VALID_MASK (0x1U) |
| #define RDC_MAX_Q_VALID_SET | ( | x | ) | (((uint32_t)(x) << RDC_MAX_Q_VALID_SHIFT) & RDC_MAX_Q_VALID_MASK) |
| #define RDC_MAX_Q_VALID_SHIFT (0U) |
| #define RDC_MIN_I_MIN_GET | ( | x | ) | (((uint32_t)(x) & RDC_MIN_I_MIN_MASK) >> RDC_MIN_I_MIN_SHIFT) |
| #define RDC_MIN_I_MIN_MASK (0xFFFFFF00UL) |
| #define RDC_MIN_I_MIN_SET | ( | x | ) | (((uint32_t)(x) << RDC_MIN_I_MIN_SHIFT) & RDC_MIN_I_MIN_MASK) |
| #define RDC_MIN_I_MIN_SHIFT (8U) |
| #define RDC_MIN_I_VALID_GET | ( | x | ) | (((uint32_t)(x) & RDC_MIN_I_VALID_MASK) >> RDC_MIN_I_VALID_SHIFT) |
| #define RDC_MIN_I_VALID_MASK (0x1U) |
| #define RDC_MIN_I_VALID_SET | ( | x | ) | (((uint32_t)(x) << RDC_MIN_I_VALID_SHIFT) & RDC_MIN_I_VALID_MASK) |
| #define RDC_MIN_I_VALID_SHIFT (0U) |
| #define RDC_MIN_Q_MIN_GET | ( | x | ) | (((uint32_t)(x) & RDC_MIN_Q_MIN_MASK) >> RDC_MIN_Q_MIN_SHIFT) |
| #define RDC_MIN_Q_MIN_MASK (0xFFFFFF00UL) |
| #define RDC_MIN_Q_MIN_SET | ( | x | ) | (((uint32_t)(x) << RDC_MIN_Q_MIN_SHIFT) & RDC_MIN_Q_MIN_MASK) |
| #define RDC_MIN_Q_MIN_SHIFT (8U) |
| #define RDC_MIN_Q_VALID_GET | ( | x | ) | (((uint32_t)(x) & RDC_MIN_Q_VALID_MASK) >> RDC_MIN_Q_VALID_SHIFT) |
| #define RDC_MIN_Q_VALID_MASK (0x1U) |
| #define RDC_MIN_Q_VALID_SET | ( | x | ) | (((uint32_t)(x) << RDC_MIN_Q_VALID_SHIFT) & RDC_MIN_Q_VALID_MASK) |
| #define RDC_MIN_Q_VALID_SHIFT (0U) |
| #define RDC_OUT_CTL_CH_I_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_OUT_CTL_CH_I_SEL_MASK) >> RDC_OUT_CTL_CH_I_SEL_SHIFT) |
| #define RDC_OUT_CTL_CH_I_SEL_MASK (0x1FU) |
| #define RDC_OUT_CTL_CH_I_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_OUT_CTL_CH_I_SEL_SHIFT) & RDC_OUT_CTL_CH_I_SEL_MASK) |
| #define RDC_OUT_CTL_CH_I_SEL_SHIFT (0U) |
| #define RDC_OUT_CTL_CH_Q_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_OUT_CTL_CH_Q_SEL_MASK) >> RDC_OUT_CTL_CH_Q_SEL_SHIFT) |
| #define RDC_OUT_CTL_CH_Q_SEL_MASK (0x1F00U) |
| #define RDC_OUT_CTL_CH_Q_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_OUT_CTL_CH_Q_SEL_SHIFT) & RDC_OUT_CTL_CH_Q_SEL_MASK) |
| #define RDC_OUT_CTL_CH_Q_SEL_SHIFT (8U) |
| #define RDC_PWM_DZ_DZ_N_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_DZ_DZ_N_MASK) >> RDC_PWM_DZ_DZ_N_SHIFT) |
| #define RDC_PWM_DZ_DZ_N_MASK (0xFF00U) |
| #define RDC_PWM_DZ_DZ_N_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_DZ_DZ_N_SHIFT) & RDC_PWM_DZ_DZ_N_MASK) |
| #define RDC_PWM_DZ_DZ_N_SHIFT (8U) |
| #define RDC_PWM_DZ_DZ_P_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_DZ_DZ_P_MASK) >> RDC_PWM_DZ_DZ_P_SHIFT) |
| #define RDC_PWM_DZ_DZ_P_MASK (0xFFU) |
| #define RDC_PWM_DZ_DZ_P_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_DZ_DZ_P_SHIFT) & RDC_PWM_DZ_DZ_P_MASK) |
| #define RDC_PWM_DZ_DZ_P_SHIFT (0U) |
| #define RDC_PWM_OFFSET_AMP_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) >> RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) |
| #define RDC_PWM_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) |
| #define RDC_PWM_OFFSET_AMP_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) |
| #define RDC_PWM_OFFSET_AMP_OFFSET_SHIFT (0U) |
| #define RDC_PWM_SCALING_AMP_EXP_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_SCALING_AMP_EXP_MASK) >> RDC_PWM_SCALING_AMP_EXP_SHIFT) |
| #define RDC_PWM_SCALING_AMP_EXP_MASK (0xF0U) |
| #define RDC_PWM_SCALING_AMP_EXP_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_SCALING_AMP_EXP_SHIFT) & RDC_PWM_SCALING_AMP_EXP_MASK) |
| #define RDC_PWM_SCALING_AMP_EXP_SHIFT (4U) |
| #define RDC_PWM_SCALING_AMP_MAN_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_SCALING_AMP_MAN_MASK) >> RDC_PWM_SCALING_AMP_MAN_SHIFT) |
| #define RDC_PWM_SCALING_AMP_MAN_MASK (0xFU) |
| #define RDC_PWM_SCALING_AMP_MAN_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_SCALING_AMP_MAN_SHIFT) & RDC_PWM_SCALING_AMP_MAN_MASK) |
| #define RDC_PWM_SCALING_AMP_MAN_SHIFT (0U) |
| #define RDC_PWM_SCALING_DITHER_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_SCALING_DITHER_MASK) >> RDC_PWM_SCALING_DITHER_SHIFT) |
| #define RDC_PWM_SCALING_DITHER_MASK (0x100U) |
| #define RDC_PWM_SCALING_DITHER_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_SCALING_DITHER_SHIFT) & RDC_PWM_SCALING_DITHER_MASK) |
| #define RDC_PWM_SCALING_DITHER_SHIFT (8U) |
| #define RDC_PWM_SCALING_N_POL_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_SCALING_N_POL_MASK) >> RDC_PWM_SCALING_N_POL_SHIFT) |
| #define RDC_PWM_SCALING_N_POL_MASK (0x2000U) |
| #define RDC_PWM_SCALING_N_POL_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_SCALING_N_POL_SHIFT) & RDC_PWM_SCALING_N_POL_MASK) |
| #define RDC_PWM_SCALING_N_POL_SHIFT (13U) |
| #define RDC_PWM_SCALING_P_POL_GET | ( | x | ) | (((uint32_t)(x) & RDC_PWM_SCALING_P_POL_MASK) >> RDC_PWM_SCALING_P_POL_SHIFT) |
| #define RDC_PWM_SCALING_P_POL_MASK (0x1000U) |
| #define RDC_PWM_SCALING_P_POL_SET | ( | x | ) | (((uint32_t)(x) << RDC_PWM_SCALING_P_POL_SHIFT) & RDC_PWM_SCALING_P_POL_MASK) |
| #define RDC_PWM_SCALING_P_POL_SHIFT (12U) |
| #define RDC_RDC_CTL_ACC_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_ACC_EN_MASK) >> RDC_RDC_CTL_ACC_EN_SHIFT) |
| #define RDC_RDC_CTL_ACC_EN_MASK (0x4U) |
| #define RDC_RDC_CTL_ACC_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_ACC_EN_SHIFT) & RDC_RDC_CTL_ACC_EN_MASK) |
| #define RDC_RDC_CTL_ACC_EN_SHIFT (2U) |
| #define RDC_RDC_CTL_ACC_FAST_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_ACC_FAST_MASK) >> RDC_RDC_CTL_ACC_FAST_SHIFT) |
| #define RDC_RDC_CTL_ACC_FAST_MASK (0x8U) |
| #define RDC_RDC_CTL_ACC_FAST_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_ACC_FAST_SHIFT) & RDC_RDC_CTL_ACC_FAST_MASK) |
| #define RDC_RDC_CTL_ACC_FAST_SHIFT (3U) |
| #define RDC_RDC_CTL_ACC_LEN_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_ACC_LEN_MASK) >> RDC_RDC_CTL_ACC_LEN_SHIFT) |
| #define RDC_RDC_CTL_ACC_LEN_MASK (0xFF000UL) |
| #define RDC_RDC_CTL_ACC_LEN_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_ACC_LEN_SHIFT) & RDC_RDC_CTL_ACC_LEN_MASK) |
| #define RDC_RDC_CTL_ACC_LEN_SHIFT (12U) |
| #define RDC_RDC_CTL_ACC_OUT_MASK_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_ACC_OUT_MASK_MASK) >> RDC_RDC_CTL_ACC_OUT_MASK_SHIFT) |
| #define RDC_RDC_CTL_ACC_OUT_MASK_MASK (0x200U) |
| #define RDC_RDC_CTL_ACC_OUT_MASK_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_ACC_OUT_MASK_SHIFT) & RDC_RDC_CTL_ACC_OUT_MASK_MASK) |
| #define RDC_RDC_CTL_ACC_OUT_MASK_SHIFT (9U) |
| #define RDC_RDC_CTL_EXC_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_EXC_EN_MASK) >> RDC_RDC_CTL_EXC_EN_SHIFT) |
| #define RDC_RDC_CTL_EXC_EN_MASK (0x1U) |
| #define RDC_RDC_CTL_EXC_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_EXC_EN_SHIFT) & RDC_RDC_CTL_EXC_EN_MASK) |
| #define RDC_RDC_CTL_EXC_EN_SHIFT (0U) |
| #define RDC_RDC_CTL_EXC_START_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_EXC_START_MASK) >> RDC_RDC_CTL_EXC_START_SHIFT) |
| #define RDC_RDC_CTL_EXC_START_MASK (0x2U) |
| #define RDC_RDC_CTL_EXC_START_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_EXC_START_SHIFT) & RDC_RDC_CTL_EXC_START_MASK) |
| #define RDC_RDC_CTL_EXC_START_SHIFT (1U) |
| #define RDC_RDC_CTL_IIR_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_IIR_EN_MASK) >> RDC_RDC_CTL_IIR_EN_SHIFT) |
| #define RDC_RDC_CTL_IIR_EN_MASK (0x100U) |
| #define RDC_RDC_CTL_IIR_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_IIR_EN_SHIFT) & RDC_RDC_CTL_IIR_EN_MASK) |
| #define RDC_RDC_CTL_IIR_EN_SHIFT (8U) |
| #define RDC_RDC_CTL_RECTIFY_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_RECTIFY_SEL_MASK) >> RDC_RDC_CTL_RECTIFY_SEL_SHIFT) |
| #define RDC_RDC_CTL_RECTIFY_SEL_MASK (0x70U) |
| #define RDC_RDC_CTL_RECTIFY_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_RECTIFY_SEL_SHIFT) & RDC_RDC_CTL_RECTIFY_SEL_MASK) |
| #define RDC_RDC_CTL_RECTIFY_SEL_SHIFT (4U) |
| #define RDC_RDC_CTL_TS_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_RDC_CTL_TS_SEL_MASK) >> RDC_RDC_CTL_TS_SEL_SHIFT) |
| #define RDC_RDC_CTL_TS_SEL_MASK (0x300000UL) |
| #define RDC_RDC_CTL_TS_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_RDC_CTL_TS_SEL_SHIFT) & RDC_RDC_CTL_TS_SEL_MASK) |
| #define RDC_RDC_CTL_TS_SEL_SHIFT (20U) |
| #define RDC_RISE_DELAY_I_RISE_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_RISE_DELAY_I_RISE_DELAY_MASK) >> RDC_RISE_DELAY_I_RISE_DELAY_SHIFT) |
| #define RDC_RISE_DELAY_I_RISE_DELAY_MASK (0xFFFFFFFFUL) |
| #define RDC_RISE_DELAY_I_RISE_DELAY_SHIFT (0U) |
| #define RDC_RISE_DELAY_Q_RISE_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_RISE_DELAY_Q_RISE_DELAY_MASK) >> RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT) |
| #define RDC_RISE_DELAY_Q_RISE_DELAY_MASK (0xFFFFFFFFUL) |
| #define RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT (0U) |
| #define RDC_SAMPLE_FALL_I_VALUE_GET | ( | x | ) | (((uint32_t)(x) & RDC_SAMPLE_FALL_I_VALUE_MASK) >> RDC_SAMPLE_FALL_I_VALUE_SHIFT) |
| #define RDC_SAMPLE_FALL_I_VALUE_MASK (0xFFFFFF00UL) |
| #define RDC_SAMPLE_FALL_I_VALUE_SHIFT (8U) |
| #define RDC_SAMPLE_FALL_Q_VALUE_GET | ( | x | ) | (((uint32_t)(x) & RDC_SAMPLE_FALL_Q_VALUE_MASK) >> RDC_SAMPLE_FALL_Q_VALUE_SHIFT) |
| #define RDC_SAMPLE_FALL_Q_VALUE_MASK (0xFFFFFF00UL) |
| #define RDC_SAMPLE_FALL_Q_VALUE_SHIFT (8U) |
| #define RDC_SAMPLE_RISE_I_VALUE_GET | ( | x | ) | (((uint32_t)(x) & RDC_SAMPLE_RISE_I_VALUE_MASK) >> RDC_SAMPLE_RISE_I_VALUE_SHIFT) |
| #define RDC_SAMPLE_RISE_I_VALUE_MASK (0xFFFFFF00UL) |
| #define RDC_SAMPLE_RISE_I_VALUE_SHIFT (8U) |
| #define RDC_SAMPLE_RISE_Q_VALUE_GET | ( | x | ) | (((uint32_t)(x) & RDC_SAMPLE_RISE_Q_VALUE_MASK) >> RDC_SAMPLE_RISE_Q_VALUE_SHIFT) |
| #define RDC_SAMPLE_RISE_Q_VALUE_MASK (0xFFFFFF00UL) |
| #define RDC_SAMPLE_RISE_Q_VALUE_SHIFT (8U) |
| #define RDC_SIGN_CNT_I_CNT_NEG_GET | ( | x | ) | (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_NEG_MASK) >> RDC_SIGN_CNT_I_CNT_NEG_SHIFT) |
| #define RDC_SIGN_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) |
| #define RDC_SIGN_CNT_I_CNT_NEG_SHIFT (16U) |
| #define RDC_SIGN_CNT_I_CNT_POS_GET | ( | x | ) | (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_POS_MASK) >> RDC_SIGN_CNT_I_CNT_POS_SHIFT) |
| #define RDC_SIGN_CNT_I_CNT_POS_MASK (0xFFFFU) |
| #define RDC_SIGN_CNT_I_CNT_POS_SHIFT (0U) |
| #define RDC_SIGN_CNT_Q_CNT_NEG_GET | ( | x | ) | (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_NEG_MASK) >> RDC_SIGN_CNT_Q_CNT_NEG_SHIFT) |
| #define RDC_SIGN_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) |
| #define RDC_SIGN_CNT_Q_CNT_NEG_SHIFT (16U) |
| #define RDC_SIGN_CNT_Q_CNT_POS_GET | ( | x | ) | (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_POS_MASK) >> RDC_SIGN_CNT_Q_CNT_POS_SHIFT) |
| #define RDC_SIGN_CNT_Q_CNT_POS_MASK (0xFFFFU) |
| #define RDC_SIGN_CNT_Q_CNT_POS_SHIFT (0U) |
| #define RDC_SYNC_DELAY_I_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_SYNC_DELAY_I_DELAY_MASK) >> RDC_SYNC_DELAY_I_DELAY_SHIFT) |
| #define RDC_SYNC_DELAY_I_DELAY_MASK (0xFFFFFFFFUL) |
| #define RDC_SYNC_DELAY_I_DELAY_SET | ( | x | ) | (((uint32_t)(x) << RDC_SYNC_DELAY_I_DELAY_SHIFT) & RDC_SYNC_DELAY_I_DELAY_MASK) |
| #define RDC_SYNC_DELAY_I_DELAY_SHIFT (0U) |
| #define RDC_SYNC_DELAY_Q_DELAY_GET | ( | x | ) | (((uint32_t)(x) & RDC_SYNC_DELAY_Q_DELAY_MASK) >> RDC_SYNC_DELAY_Q_DELAY_SHIFT) |
| #define RDC_SYNC_DELAY_Q_DELAY_MASK (0xFFFFFFFFUL) |
| #define RDC_SYNC_DELAY_Q_DELAY_SET | ( | x | ) | (((uint32_t)(x) << RDC_SYNC_DELAY_Q_DELAY_SHIFT) & RDC_SYNC_DELAY_Q_DELAY_MASK) |
| #define RDC_SYNC_DELAY_Q_DELAY_SHIFT (0U) |
| #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) |
| #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK (0x10U) |
| #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) |
| #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT (4U) |
| #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_GET | ( | x | ) | (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) |
| #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK (0x20U) |
| #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SET | ( | x | ) | (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) |
| #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT (5U) |
| #define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET | ( | x | ) | (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK) >> RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT) |
| #define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK (0xFFFF0000UL) |
| #define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT (16U) |
| #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_GET | ( | x | ) | (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) >> RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) |
| #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK (0x3U) |
| #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET | ( | x | ) | (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) |
| #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT (0U) |
| #define RDC_THRS_I_THRS4ACC_GET | ( | x | ) | (((uint32_t)(x) & RDC_THRS_I_THRS4ACC_MASK) >> RDC_THRS_I_THRS4ACC_SHIFT) |
| #define RDC_THRS_I_THRS4ACC_MASK (0x1U) |
| #define RDC_THRS_I_THRS4ACC_SET | ( | x | ) | (((uint32_t)(x) << RDC_THRS_I_THRS4ACC_SHIFT) & RDC_THRS_I_THRS4ACC_MASK) |
| #define RDC_THRS_I_THRS4ACC_SHIFT (0U) |
| #define RDC_THRS_I_THRS_GET | ( | x | ) | (((uint32_t)(x) & RDC_THRS_I_THRS_MASK) >> RDC_THRS_I_THRS_SHIFT) |
| #define RDC_THRS_I_THRS_MASK (0xFFFFFF00UL) |
| #define RDC_THRS_I_THRS_SET | ( | x | ) | (((uint32_t)(x) << RDC_THRS_I_THRS_SHIFT) & RDC_THRS_I_THRS_MASK) |
| #define RDC_THRS_I_THRS_SHIFT (8U) |
| #define RDC_THRS_Q_THRS4ACC_GET | ( | x | ) | (((uint32_t)(x) & RDC_THRS_Q_THRS4ACC_MASK) >> RDC_THRS_Q_THRS4ACC_SHIFT) |
| #define RDC_THRS_Q_THRS4ACC_MASK (0x1U) |
| #define RDC_THRS_Q_THRS4ACC_SET | ( | x | ) | (((uint32_t)(x) << RDC_THRS_Q_THRS4ACC_SHIFT) & RDC_THRS_Q_THRS4ACC_MASK) |
| #define RDC_THRS_Q_THRS4ACC_SHIFT (0U) |
| #define RDC_THRS_Q_THRS_GET | ( | x | ) | (((uint32_t)(x) & RDC_THRS_Q_THRS_MASK) >> RDC_THRS_Q_THRS_SHIFT) |
| #define RDC_THRS_Q_THRS_MASK (0xFFFFFF00UL) |
| #define RDC_THRS_Q_THRS_SET | ( | x | ) | (((uint32_t)(x) << RDC_THRS_Q_THRS_SHIFT) & RDC_THRS_Q_THRS_MASK) |
| #define RDC_THRS_Q_THRS_SHIFT (8U) |
| #define RDC_TRIG_OUT0_CFG_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) >> RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) |
| #define RDC_TRIG_OUT0_CFG_ENABLE_MASK (0x100000UL) |
| #define RDC_TRIG_OUT0_CFG_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) |
| #define RDC_TRIG_OUT0_CFG_ENABLE_SHIFT (20U) |
| #define RDC_TRIG_OUT0_CFG_LEAD_TIM_GET | ( | x | ) | (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) |
| #define RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK (0xFFFFFUL) |
| #define RDC_TRIG_OUT0_CFG_LEAD_TIM_SET | ( | x | ) | (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) |
| #define RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT (0U) |
| #define RDC_TRIG_OUT1_CFG_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) >> RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) |
| #define RDC_TRIG_OUT1_CFG_ENABLE_MASK (0x100000UL) |
| #define RDC_TRIG_OUT1_CFG_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) |
| #define RDC_TRIG_OUT1_CFG_ENABLE_SHIFT (20U) |
| #define RDC_TRIG_OUT1_CFG_LEAD_TIM_GET | ( | x | ) | (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) |
| #define RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK (0xFFFFFUL) |
| #define RDC_TRIG_OUT1_CFG_LEAD_TIM_SET | ( | x | ) | (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) |
| #define RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT (0U) |
1.9.1