Data Structures
struct	DDRCTL_Type

Macros
#define	DDRCTL_MSTR_ACTIVE_RANKS_MASK (0xF000000UL)

#define	DDRCTL_MSTR_ACTIVE_RANKS_SHIFT (24U)

#define	DDRCTL_MSTR_ACTIVE_RANKS_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_ACTIVE_RANKS_SHIFT) & DDRCTL_MSTR_ACTIVE_RANKS_MASK)

#define	DDRCTL_MSTR_ACTIVE_RANKS_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_ACTIVE_RANKS_MASK) >> DDRCTL_MSTR_ACTIVE_RANKS_SHIFT)

#define	DDRCTL_MSTR_BURST_RDWR_MASK (0xF0000UL)

#define	DDRCTL_MSTR_BURST_RDWR_SHIFT (16U)

#define	DDRCTL_MSTR_BURST_RDWR_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_BURST_RDWR_SHIFT) & DDRCTL_MSTR_BURST_RDWR_MASK)

#define	DDRCTL_MSTR_BURST_RDWR_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_BURST_RDWR_MASK) >> DDRCTL_MSTR_BURST_RDWR_SHIFT)

#define	DDRCTL_MSTR_DLL_OFF_MODE_MASK (0x8000U)

#define	DDRCTL_MSTR_DLL_OFF_MODE_SHIFT (15U)

#define	DDRCTL_MSTR_DLL_OFF_MODE_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DLL_OFF_MODE_SHIFT) & DDRCTL_MSTR_DLL_OFF_MODE_MASK)

#define	DDRCTL_MSTR_DLL_OFF_MODE_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DLL_OFF_MODE_MASK) >> DDRCTL_MSTR_DLL_OFF_MODE_SHIFT)

#define	DDRCTL_MSTR_DATA_BUS_WIDTH_MASK (0x3000U)

#define	DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT (12U)

#define	DDRCTL_MSTR_DATA_BUS_WIDTH_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK)

#define	DDRCTL_MSTR_DATA_BUS_WIDTH_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK) >> DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT)

#define	DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK (0x400U)

#define	DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT (10U)

#define	DDRCTL_MSTR_EN_2T_TIMING_MODE_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK)

#define	DDRCTL_MSTR_EN_2T_TIMING_MODE_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK) >> DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT)

#define	DDRCTL_MSTR_BURSTCHOP_MASK (0x200U)

#define	DDRCTL_MSTR_BURSTCHOP_SHIFT (9U)

#define	DDRCTL_MSTR_BURSTCHOP_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_BURSTCHOP_SHIFT) & DDRCTL_MSTR_BURSTCHOP_MASK)

#define	DDRCTL_MSTR_BURSTCHOP_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_BURSTCHOP_MASK) >> DDRCTL_MSTR_BURSTCHOP_SHIFT)

#define	DDRCTL_MSTR_DDR3_MASK (0x1U)

#define	DDRCTL_MSTR_DDR3_SHIFT (0U)

#define	DDRCTL_MSTR_DDR3_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DDR3_SHIFT) & DDRCTL_MSTR_DDR3_MASK)

#define	DDRCTL_MSTR_DDR3_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DDR3_MASK) >> DDRCTL_MSTR_DDR3_SHIFT)

#define	DDRCTL_STAT_SELFREF_TYPE_MASK (0x30U)

#define	DDRCTL_STAT_SELFREF_TYPE_SHIFT (4U)

#define	DDRCTL_STAT_SELFREF_TYPE_GET(x) (((uint32_t)(x) & DDRCTL_STAT_SELFREF_TYPE_MASK) >> DDRCTL_STAT_SELFREF_TYPE_SHIFT)

#define	DDRCTL_STAT_OPERATING_MODE_MASK (0x7U)

#define	DDRCTL_STAT_OPERATING_MODE_SHIFT (0U)

#define	DDRCTL_STAT_OPERATING_MODE_GET(x) (((uint32_t)(x) & DDRCTL_STAT_OPERATING_MODE_MASK) >> DDRCTL_STAT_OPERATING_MODE_SHIFT)

#define	DDRCTL_MRCTRL0_MR_WR_MASK (0x80000000UL)

#define	DDRCTL_MRCTRL0_MR_WR_SHIFT (31U)

#define	DDRCTL_MRCTRL0_MR_WR_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_WR_SHIFT) & DDRCTL_MRCTRL0_MR_WR_MASK)

#define	DDRCTL_MRCTRL0_MR_WR_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_WR_MASK) >> DDRCTL_MRCTRL0_MR_WR_SHIFT)

#define	DDRCTL_MRCTRL0_MR_ADDR_MASK (0xF000U)

#define	DDRCTL_MRCTRL0_MR_ADDR_SHIFT (12U)

#define	DDRCTL_MRCTRL0_MR_ADDR_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_ADDR_SHIFT) & DDRCTL_MRCTRL0_MR_ADDR_MASK)

#define	DDRCTL_MRCTRL0_MR_ADDR_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_ADDR_MASK) >> DDRCTL_MRCTRL0_MR_ADDR_SHIFT)

#define	DDRCTL_MRCTRL0_MR_RANK_MASK (0xF0U)

#define	DDRCTL_MRCTRL0_MR_RANK_SHIFT (4U)

#define	DDRCTL_MRCTRL0_MR_RANK_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_RANK_SHIFT) & DDRCTL_MRCTRL0_MR_RANK_MASK)

#define	DDRCTL_MRCTRL0_MR_RANK_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_RANK_MASK) >> DDRCTL_MRCTRL0_MR_RANK_SHIFT)

#define	DDRCTL_MRCTRL1_MR_DATA_MASK (0x3FFFFUL)

#define	DDRCTL_MRCTRL1_MR_DATA_SHIFT (0U)

#define	DDRCTL_MRCTRL1_MR_DATA_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL1_MR_DATA_SHIFT) & DDRCTL_MRCTRL1_MR_DATA_MASK)

#define	DDRCTL_MRCTRL1_MR_DATA_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL1_MR_DATA_MASK) >> DDRCTL_MRCTRL1_MR_DATA_SHIFT)

#define	DDRCTL_MRSTAT_MR_WR_BUSY_MASK (0x1U)

#define	DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT (0U)

#define	DDRCTL_MRSTAT_MR_WR_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_MRSTAT_MR_WR_BUSY_MASK) >> DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT)

#define	DDRCTL_PWRCTL_SELFREF_SW_MASK (0x20U)

#define	DDRCTL_PWRCTL_SELFREF_SW_SHIFT (5U)

#define	DDRCTL_PWRCTL_SELFREF_SW_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_SW_SHIFT) & DDRCTL_PWRCTL_SELFREF_SW_MASK)

#define	DDRCTL_PWRCTL_SELFREF_SW_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_SW_MASK) >> DDRCTL_PWRCTL_SELFREF_SW_SHIFT)

#define	DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK (0x8U)

#define	DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT (3U)

#define	DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK)

#define	DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK) >> DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT)

#define	DDRCTL_PWRCTL_POWERDOWN_EN_MASK (0x2U)

#define	DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT (1U)

#define	DDRCTL_PWRCTL_POWERDOWN_EN_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK)

#define	DDRCTL_PWRCTL_POWERDOWN_EN_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK) >> DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT)

#define	DDRCTL_PWRCTL_SELFREF_EN_MASK (0x1U)

#define	DDRCTL_PWRCTL_SELFREF_EN_SHIFT (0U)

#define	DDRCTL_PWRCTL_SELFREF_EN_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_EN_SHIFT) & DDRCTL_PWRCTL_SELFREF_EN_MASK)

#define	DDRCTL_PWRCTL_SELFREF_EN_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_EN_MASK) >> DDRCTL_PWRCTL_SELFREF_EN_SHIFT)

#define	DDRCTL_PWRTMG_SELFREF_TO_X32_MASK (0xFF0000UL)

#define	DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT (16U)

#define	DDRCTL_PWRTMG_SELFREF_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK)

#define	DDRCTL_PWRTMG_SELFREF_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK) >> DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT)

#define	DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK (0x1FU)

#define	DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT (0U)

#define	DDRCTL_PWRTMG_POWERDOWN_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK)

#define	DDRCTL_PWRTMG_POWERDOWN_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK) >> DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT)

#define	DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK (0xFFF0000UL)

#define	DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT (16U)

#define	DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK)

#define	DDRCTL_HWLPCTL_HW_LP_IDLE_X32_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK) >> DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT)

#define	DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK (0x2U)

#define	DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT (1U)

#define	DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK)

#define	DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT)

#define	DDRCTL_HWLPCTL_HW_LP_EN_MASK (0x1U)

#define	DDRCTL_HWLPCTL_HW_LP_EN_SHIFT (0U)

#define	DDRCTL_HWLPCTL_HW_LP_EN_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EN_MASK)

#define	DDRCTL_HWLPCTL_HW_LP_EN_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EN_SHIFT)

#define	DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK (0xF00000UL)

#define	DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT (20U)

#define	DDRCTL_RFSHCTL0_REFRESH_MARGIN_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK)

#define	DDRCTL_RFSHCTL0_REFRESH_MARGIN_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK) >> DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT)

#define	DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK (0x1F000UL)

#define	DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT (12U)

#define	DDRCTL_RFSHCTL0_REFRESH_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK)

#define	DDRCTL_RFSHCTL0_REFRESH_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK) >> DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT)

#define	DDRCTL_RFSHCTL0_REFRESH_BURST_MASK (0x1F0U)

#define	DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT (4U)

#define	DDRCTL_RFSHCTL0_REFRESH_BURST_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK)

#define	DDRCTL_RFSHCTL0_REFRESH_BURST_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK) >> DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK (0xFFF0000UL)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT (16U)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK (0xFFFU)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT (0U)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK)

#define	DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT)

#define	DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK (0x2U)

#define	DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT (1U)

#define	DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK)

#define	DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK) >> DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT)

#define	DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK (0x1U)

#define	DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT (0U)

#define	DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK)

#define	DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK) >> DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT)

#define	DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK (0xFFF0000UL)

#define	DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT (16U)

#define	DDRCTL_RFSHTMG_T_RFC_NOM_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK)

#define	DDRCTL_RFSHTMG_T_RFC_NOM_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK) >> DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT)

#define	DDRCTL_RFSHTMG_T_RFC_MIN_MASK (0x1FFU)

#define	DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT (0U)

#define	DDRCTL_RFSHTMG_T_RFC_MIN_SET(x) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK)

#define	DDRCTL_RFSHTMG_T_RFC_MIN_GET(x) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK) >> DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT)

#define	DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK (0x3000000UL)

#define	DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT (24U)

#define	DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_GET(x) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT)

#define	DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK (0x3FFFFUL)

#define	DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT (0U)

#define	DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_GET(x) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK (0x4U)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT (2U)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK (0x2U)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT (1U)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK (0x1U)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT (0U)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK)

#define	DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT)

#define	DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK (0x10000UL)

#define	DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT (16U)

#define	DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT)

#define	DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK (0xFFFFU)

#define	DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT (0U)

#define	DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT)

#define	DDRCTL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000UL)

#define	DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT (30U)

#define	DDRCTL_INIT0_SKIP_DRAM_INIT_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK)

#define	DDRCTL_INIT0_SKIP_DRAM_INIT_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK) >> DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT)

#define	DDRCTL_INIT0_POST_CKE_X1024_MASK (0x3FF0000UL)

#define	DDRCTL_INIT0_POST_CKE_X1024_SHIFT (16U)

#define	DDRCTL_INIT0_POST_CKE_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_POST_CKE_X1024_SHIFT) & DDRCTL_INIT0_POST_CKE_X1024_MASK)

#define	DDRCTL_INIT0_POST_CKE_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_POST_CKE_X1024_MASK) >> DDRCTL_INIT0_POST_CKE_X1024_SHIFT)

#define	DDRCTL_INIT0_PRE_CKE_X1024_MASK (0x3FFU)

#define	DDRCTL_INIT0_PRE_CKE_X1024_SHIFT (0U)

#define	DDRCTL_INIT0_PRE_CKE_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_PRE_CKE_X1024_SHIFT) & DDRCTL_INIT0_PRE_CKE_X1024_MASK)

#define	DDRCTL_INIT0_PRE_CKE_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_PRE_CKE_X1024_MASK) >> DDRCTL_INIT0_PRE_CKE_X1024_SHIFT)

#define	DDRCTL_INIT1_DRAM_RSTN_X1024_MASK (0xFF0000UL)

#define	DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT (16U)

#define	DDRCTL_INIT1_DRAM_RSTN_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK)

#define	DDRCTL_INIT1_DRAM_RSTN_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK) >> DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT)

#define	DDRCTL_INIT1_FINAL_WAIT_X32_MASK (0x7F00U)

#define	DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT (8U)

#define	DDRCTL_INIT1_FINAL_WAIT_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK)

#define	DDRCTL_INIT1_FINAL_WAIT_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK) >> DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT)

#define	DDRCTL_INIT1_PRE_OCD_X32_MASK (0xFU)

#define	DDRCTL_INIT1_PRE_OCD_X32_SHIFT (0U)

#define	DDRCTL_INIT1_PRE_OCD_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_PRE_OCD_X32_SHIFT) & DDRCTL_INIT1_PRE_OCD_X32_MASK)

#define	DDRCTL_INIT1_PRE_OCD_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_PRE_OCD_X32_MASK) >> DDRCTL_INIT1_PRE_OCD_X32_SHIFT)

#define	DDRCTL_INIT3_MR_MASK (0xFFFF0000UL)

#define	DDRCTL_INIT3_MR_SHIFT (16U)

#define	DDRCTL_INIT3_MR_SET(x) (((uint32_t)(x) << DDRCTL_INIT3_MR_SHIFT) & DDRCTL_INIT3_MR_MASK)

#define	DDRCTL_INIT3_MR_GET(x) (((uint32_t)(x) & DDRCTL_INIT3_MR_MASK) >> DDRCTL_INIT3_MR_SHIFT)

#define	DDRCTL_INIT3_EMR_MASK (0xFFFFU)

#define	DDRCTL_INIT3_EMR_SHIFT (0U)

#define	DDRCTL_INIT3_EMR_SET(x) (((uint32_t)(x) << DDRCTL_INIT3_EMR_SHIFT) & DDRCTL_INIT3_EMR_MASK)

#define	DDRCTL_INIT3_EMR_GET(x) (((uint32_t)(x) & DDRCTL_INIT3_EMR_MASK) >> DDRCTL_INIT3_EMR_SHIFT)

#define	DDRCTL_INIT4_EMR2_MASK (0xFFFF0000UL)

#define	DDRCTL_INIT4_EMR2_SHIFT (16U)

#define	DDRCTL_INIT4_EMR2_SET(x) (((uint32_t)(x) << DDRCTL_INIT4_EMR2_SHIFT) & DDRCTL_INIT4_EMR2_MASK)

#define	DDRCTL_INIT4_EMR2_GET(x) (((uint32_t)(x) & DDRCTL_INIT4_EMR2_MASK) >> DDRCTL_INIT4_EMR2_SHIFT)

#define	DDRCTL_INIT4_EMR3_MASK (0xFFFFU)

#define	DDRCTL_INIT4_EMR3_SHIFT (0U)

#define	DDRCTL_INIT4_EMR3_SET(x) (((uint32_t)(x) << DDRCTL_INIT4_EMR3_SHIFT) & DDRCTL_INIT4_EMR3_MASK)

#define	DDRCTL_INIT4_EMR3_GET(x) (((uint32_t)(x) & DDRCTL_INIT4_EMR3_MASK) >> DDRCTL_INIT4_EMR3_SHIFT)

#define	DDRCTL_INIT5_DEV_ZQINIT_X32_MASK (0xFF0000UL)

#define	DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT (16U)

#define	DDRCTL_INIT5_DEV_ZQINIT_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK)

#define	DDRCTL_INIT5_DEV_ZQINIT_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK) >> DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT)

#define	DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK (0x2U)

#define	DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT (1U)

#define	DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SET(x) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK)

#define	DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_GET(x) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT)

#define	DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK (0x1U)

#define	DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT (0U)

#define	DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SET(x) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK)

#define	DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_GET(x) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT)

#define	DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK (0xF00U)

#define	DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT (8U)

#define	DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK)

#define	DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT)

#define	DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK (0xF0U)

#define	DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT (4U)

#define	DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK)

#define	DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT)

#define	DDRCTL_RANKCTL_MAX_RANK_RD_MASK (0xFU)

#define	DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT (0U)

#define	DDRCTL_RANKCTL_MAX_RANK_RD_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK)

#define	DDRCTL_RANKCTL_MAX_RANK_RD_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK) >> DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT)

#define	DDRCTL_DRAMTMG0_WR2PRE_MASK (0x7F000000UL)

#define	DDRCTL_DRAMTMG0_WR2PRE_SHIFT (24U)

#define	DDRCTL_DRAMTMG0_WR2PRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_WR2PRE_SHIFT) & DDRCTL_DRAMTMG0_WR2PRE_MASK)

#define	DDRCTL_DRAMTMG0_WR2PRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_WR2PRE_MASK) >> DDRCTL_DRAMTMG0_WR2PRE_SHIFT)

#define	DDRCTL_DRAMTMG0_T_FAW_MASK (0x3F0000UL)

#define	DDRCTL_DRAMTMG0_T_FAW_SHIFT (16U)

#define	DDRCTL_DRAMTMG0_T_FAW_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_FAW_SHIFT) & DDRCTL_DRAMTMG0_T_FAW_MASK)

#define	DDRCTL_DRAMTMG0_T_FAW_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_FAW_MASK) >> DDRCTL_DRAMTMG0_T_FAW_SHIFT)

#define	DDRCTL_DRAMTMG0_T_RAS_MAX_MASK (0x7F00U)

#define	DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT (8U)

#define	DDRCTL_DRAMTMG0_T_RAS_MAX_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK)

#define	DDRCTL_DRAMTMG0_T_RAS_MAX_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT)

#define	DDRCTL_DRAMTMG0_T_RAS_MIN_MASK (0x3FU)

#define	DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT (0U)

#define	DDRCTL_DRAMTMG0_T_RAS_MIN_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK)

#define	DDRCTL_DRAMTMG0_T_RAS_MIN_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT)

#define	DDRCTL_DRAMTMG1_T_XP_MASK (0x1F0000UL)

#define	DDRCTL_DRAMTMG1_T_XP_SHIFT (16U)

#define	DDRCTL_DRAMTMG1_T_XP_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_XP_SHIFT) & DDRCTL_DRAMTMG1_T_XP_MASK)

#define	DDRCTL_DRAMTMG1_T_XP_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_XP_MASK) >> DDRCTL_DRAMTMG1_T_XP_SHIFT)

#define	DDRCTL_DRAMTMG1_RD2PRE_MASK (0x1F00U)

#define	DDRCTL_DRAMTMG1_RD2PRE_SHIFT (8U)

#define	DDRCTL_DRAMTMG1_RD2PRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_RD2PRE_SHIFT) & DDRCTL_DRAMTMG1_RD2PRE_MASK)

#define	DDRCTL_DRAMTMG1_RD2PRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_RD2PRE_MASK) >> DDRCTL_DRAMTMG1_RD2PRE_SHIFT)

#define	DDRCTL_DRAMTMG1_T_RC_MASK (0x7FU)

#define	DDRCTL_DRAMTMG1_T_RC_SHIFT (0U)

#define	DDRCTL_DRAMTMG1_T_RC_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_RC_SHIFT) & DDRCTL_DRAMTMG1_T_RC_MASK)

#define	DDRCTL_DRAMTMG1_T_RC_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_RC_MASK) >> DDRCTL_DRAMTMG1_T_RC_SHIFT)

#define	DDRCTL_DRAMTMG2_RD2WR_MASK (0x1F00U)

#define	DDRCTL_DRAMTMG2_RD2WR_SHIFT (8U)

#define	DDRCTL_DRAMTMG2_RD2WR_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG2_RD2WR_SHIFT) & DDRCTL_DRAMTMG2_RD2WR_MASK)

#define	DDRCTL_DRAMTMG2_RD2WR_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG2_RD2WR_MASK) >> DDRCTL_DRAMTMG2_RD2WR_SHIFT)

#define	DDRCTL_DRAMTMG2_WR2RD_MASK (0x3FU)

#define	DDRCTL_DRAMTMG2_WR2RD_SHIFT (0U)

#define	DDRCTL_DRAMTMG2_WR2RD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG2_WR2RD_SHIFT) & DDRCTL_DRAMTMG2_WR2RD_MASK)

#define	DDRCTL_DRAMTMG2_WR2RD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG2_WR2RD_MASK) >> DDRCTL_DRAMTMG2_WR2RD_SHIFT)

#define	DDRCTL_DRAMTMG3_T_MRD_MASK (0x3F000UL)

#define	DDRCTL_DRAMTMG3_T_MRD_SHIFT (12U)

#define	DDRCTL_DRAMTMG3_T_MRD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MRD_SHIFT) & DDRCTL_DRAMTMG3_T_MRD_MASK)

#define	DDRCTL_DRAMTMG3_T_MRD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MRD_MASK) >> DDRCTL_DRAMTMG3_T_MRD_SHIFT)

#define	DDRCTL_DRAMTMG3_T_MOD_MASK (0x3FFU)

#define	DDRCTL_DRAMTMG3_T_MOD_SHIFT (0U)

#define	DDRCTL_DRAMTMG3_T_MOD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MOD_SHIFT) & DDRCTL_DRAMTMG3_T_MOD_MASK)

#define	DDRCTL_DRAMTMG3_T_MOD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MOD_MASK) >> DDRCTL_DRAMTMG3_T_MOD_SHIFT)

#define	DDRCTL_DRAMTMG4_T_RCD_MASK (0x1F000000UL)

#define	DDRCTL_DRAMTMG4_T_RCD_SHIFT (24U)

#define	DDRCTL_DRAMTMG4_T_RCD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RCD_SHIFT) & DDRCTL_DRAMTMG4_T_RCD_MASK)

#define	DDRCTL_DRAMTMG4_T_RCD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RCD_MASK) >> DDRCTL_DRAMTMG4_T_RCD_SHIFT)

#define	DDRCTL_DRAMTMG4_T_CCD_MASK (0x70000UL)

#define	DDRCTL_DRAMTMG4_T_CCD_SHIFT (16U)

#define	DDRCTL_DRAMTMG4_T_CCD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_CCD_SHIFT) & DDRCTL_DRAMTMG4_T_CCD_MASK)

#define	DDRCTL_DRAMTMG4_T_CCD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_CCD_MASK) >> DDRCTL_DRAMTMG4_T_CCD_SHIFT)

#define	DDRCTL_DRAMTMG4_T_RRD_MASK (0xF00U)

#define	DDRCTL_DRAMTMG4_T_RRD_SHIFT (8U)

#define	DDRCTL_DRAMTMG4_T_RRD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RRD_SHIFT) & DDRCTL_DRAMTMG4_T_RRD_MASK)

#define	DDRCTL_DRAMTMG4_T_RRD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RRD_MASK) >> DDRCTL_DRAMTMG4_T_RRD_SHIFT)

#define	DDRCTL_DRAMTMG4_T_RP_MASK (0x1FU)

#define	DDRCTL_DRAMTMG4_T_RP_SHIFT (0U)

#define	DDRCTL_DRAMTMG4_T_RP_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RP_SHIFT) & DDRCTL_DRAMTMG4_T_RP_MASK)

#define	DDRCTL_DRAMTMG4_T_RP_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RP_MASK) >> DDRCTL_DRAMTMG4_T_RP_SHIFT)

#define	DDRCTL_DRAMTMG5_T_CKSRX_MASK (0xF000000UL)

#define	DDRCTL_DRAMTMG5_T_CKSRX_SHIFT (24U)

#define	DDRCTL_DRAMTMG5_T_CKSRX_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRX_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRX_MASK)

#define	DDRCTL_DRAMTMG5_T_CKSRX_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRX_MASK) >> DDRCTL_DRAMTMG5_T_CKSRX_SHIFT)

#define	DDRCTL_DRAMTMG5_T_CKSRE_MASK (0xF0000UL)

#define	DDRCTL_DRAMTMG5_T_CKSRE_SHIFT (16U)

#define	DDRCTL_DRAMTMG5_T_CKSRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRE_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRE_MASK)

#define	DDRCTL_DRAMTMG5_T_CKSRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRE_MASK) >> DDRCTL_DRAMTMG5_T_CKSRE_SHIFT)

#define	DDRCTL_DRAMTMG5_T_CKESR_MASK (0x3F00U)

#define	DDRCTL_DRAMTMG5_T_CKESR_SHIFT (8U)

#define	DDRCTL_DRAMTMG5_T_CKESR_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKESR_SHIFT) & DDRCTL_DRAMTMG5_T_CKESR_MASK)

#define	DDRCTL_DRAMTMG5_T_CKESR_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKESR_MASK) >> DDRCTL_DRAMTMG5_T_CKESR_SHIFT)

#define	DDRCTL_DRAMTMG5_T_CKE_MASK (0x1FU)

#define	DDRCTL_DRAMTMG5_T_CKE_SHIFT (0U)

#define	DDRCTL_DRAMTMG5_T_CKE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKE_SHIFT) & DDRCTL_DRAMTMG5_T_CKE_MASK)

#define	DDRCTL_DRAMTMG5_T_CKE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKE_MASK) >> DDRCTL_DRAMTMG5_T_CKE_SHIFT)

#define	DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK (0x7F00U)

#define	DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT (8U)

#define	DDRCTL_DRAMTMG8_T_XS_DLL_X32_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK)

#define	DDRCTL_DRAMTMG8_T_XS_DLL_X32_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT)

#define	DDRCTL_DRAMTMG8_T_XS_X32_MASK (0x7FU)

#define	DDRCTL_DRAMTMG8_T_XS_X32_SHIFT (0U)

#define	DDRCTL_DRAMTMG8_T_XS_X32_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_X32_MASK)

#define	DDRCTL_DRAMTMG8_T_XS_X32_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_X32_SHIFT)

#define	DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK (0x80000000UL)

#define	DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT (31U)

#define	DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK)

#define	DDRCTL_ZQCTL0_DIS_AUTO_ZQ_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK) >> DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT)

#define	DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK (0x40000000UL)

#define	DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT (30U)

#define	DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK)

#define	DDRCTL_ZQCTL0_DIS_SRX_ZQCL_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK) >> DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT)

#define	DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK (0x20000000UL)

#define	DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT (29U)

#define	DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK)

#define	DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK) >> DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT)

#define	DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK (0x3FF0000UL)

#define	DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT (16U)

#define	DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK)

#define	DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT)

#define	DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK (0x3FFU)

#define	DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT (0U)

#define	DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK)

#define	DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT)

#define	DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK (0xFFFFFUL)

#define	DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT (0U)

#define	DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK)

#define	DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) >> DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT)

#define	DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK (0x1U)

#define	DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT (0U)

#define	DDRCTL_ZQSTAT_ZQ_RESET_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK) >> DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT)

#define	DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK (0x1F000000UL)

#define	DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT (24U)

#define	DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK)

#define	DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK) >> DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT)

#define	DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK (0x800000UL)

#define	DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT (23U)

#define	DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK)

#define	DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT)

#define	DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK (0x3F0000UL)

#define	DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT (16U)

#define	DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK)

#define	DDRCTL_DFITMG0_DFI_T_RDDATA_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK) >> DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT)

#define	DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK (0x8000U)

#define	DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT (15U)

#define	DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK)

#define	DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK (0x3F00U)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT (8U)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRDATA_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK (0x3FU)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT (0U)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK)

#define	DDRCTL_DFITMG0_DFI_TPHY_WRLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT)

#define	DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK (0x1F0000UL)

#define	DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT (16U)

#define	DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK)

#define	DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK) >> DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK (0xF00U)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK (0xFU)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK)

#define	DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT)

#define	DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK (0xF000000UL)

#define	DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT (24U)

#define	DDRCTL_DFILPCFG0_DFI_TLP_RESP_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK)

#define	DDRCTL_DFILPCFG0_DFI_TLP_RESP_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK) >> DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK (0xF000U)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT (12U)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK (0x100U)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT (8U)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_SR_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK (0xF0U)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT (4U)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK)

#define	DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK (0x1U)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT (0U)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK)

#define	DDRCTL_DFILPCFG0_DFI_LP_EN_PD_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT)

#define	DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK (0x80000000UL)

#define	DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT (31U)

#define	DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK)

#define	DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK) >> DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK (0x3FF0000UL)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT (16U)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK (0x3FFU)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT (0U)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK)

#define	DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK (0xFF0000UL)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT (16U)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK (0xFFU)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT (0U)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK)

#define	DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK (0x80000000UL)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT (31U)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK (0xFFF0000UL)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT (16U)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK (0xFFFU)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT (0U)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK)

#define	DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK (0xFFF0000UL)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT (16U)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK (0xFFFU)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT (0U)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK)

#define	DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT)

#define	DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK (0x1U)

#define	DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT (0U)

#define	DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK)

#define	DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK) >> DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT)

#define	DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK (0x3F00U)

#define	DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT (8U)

#define	DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK)

#define	DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT)

#define	DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK (0x3FU)

#define	DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT (0U)

#define	DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK)

#define	DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT)

#define	DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK (0x1FU)

#define	DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT (0U)

#define	DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK)

#define	DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) >> DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK (0x1F0000UL)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT (16U)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK (0x1F00U)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT (8U)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK (0x1FU)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT (0U)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK)

#define	DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK (0xF000000UL)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT (24U)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK (0xF0000UL)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT (16U)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK (0xF00U)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT (8U)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK (0xFU)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT (0U)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK)

#define	DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK (0xF000000UL)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT (24U)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK (0xF0000UL)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT (16U)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK (0xF00U)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT (8U)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK (0xFU)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT (0U)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK)

#define	DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK (0xF00U)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT (8U)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK (0xFU)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT (0U)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK)

#define	DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK (0xF000000UL)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT (24U)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK (0xF0000UL)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT (16U)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK (0xF00U)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT (8U)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK (0xFU)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT (0U)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK)

#define	DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK (0xF000000UL)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT (24U)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK (0xF0000UL)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT (16U)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK (0xF00U)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT (8U)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK (0xFU)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT (0U)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK)

#define	DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT)

#define	DDRCTL_ODTCFG_WR_ODT_HOLD_MASK (0xF000000UL)

#define	DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT (24U)

#define	DDRCTL_ODTCFG_WR_ODT_HOLD_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK)

#define	DDRCTL_ODTCFG_WR_ODT_HOLD_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT)

#define	DDRCTL_ODTCFG_WR_ODT_DELAY_MASK (0x1F0000UL)

#define	DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT (16U)

#define	DDRCTL_ODTCFG_WR_ODT_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK)

#define	DDRCTL_ODTCFG_WR_ODT_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT)

#define	DDRCTL_ODTCFG_RD_ODT_HOLD_MASK (0xF00U)

#define	DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT (8U)

#define	DDRCTL_ODTCFG_RD_ODT_HOLD_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK)

#define	DDRCTL_ODTCFG_RD_ODT_HOLD_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT)

#define	DDRCTL_ODTCFG_RD_ODT_DELAY_MASK (0x7CU)

#define	DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT (2U)

#define	DDRCTL_ODTCFG_RD_ODT_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK)

#define	DDRCTL_ODTCFG_RD_ODT_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT)

#define	DDRCTL_ODTMAP_RANK1_RD_ODT_MASK (0xF000U)

#define	DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT (12U)

#define	DDRCTL_ODTMAP_RANK1_RD_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK)

#define	DDRCTL_ODTMAP_RANK1_RD_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT)

#define	DDRCTL_ODTMAP_RANK1_WR_ODT_MASK (0xF00U)

#define	DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT (8U)

#define	DDRCTL_ODTMAP_RANK1_WR_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK)

#define	DDRCTL_ODTMAP_RANK1_WR_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT)

#define	DDRCTL_ODTMAP_RANK0_RD_ODT_MASK (0xF0U)

#define	DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT (4U)

#define	DDRCTL_ODTMAP_RANK0_RD_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK)

#define	DDRCTL_ODTMAP_RANK0_RD_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT)

#define	DDRCTL_ODTMAP_RANK0_WR_ODT_MASK (0xFU)

#define	DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT (0U)

#define	DDRCTL_ODTMAP_RANK0_WR_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK)

#define	DDRCTL_ODTMAP_RANK0_WR_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT)

#define	DDRCTL_SCHED_RDWR_IDLE_GAP_MASK (0x7F000000UL)

#define	DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT (24U)

#define	DDRCTL_SCHED_RDWR_IDLE_GAP_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK)

#define	DDRCTL_SCHED_RDWR_IDLE_GAP_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK) >> DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT)

#define	DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK (0xFF0000UL)

#define	DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT (16U)

#define	DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK)

#define	DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK) >> DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT)

#define	DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK (0x3F00U)

#define	DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT (8U)

#define	DDRCTL_SCHED_LPR_NUM_ENTRIES_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK)

#define	DDRCTL_SCHED_LPR_NUM_ENTRIES_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK) >> DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT)

#define	DDRCTL_SCHED_PAGECLOSE_MASK (0x4U)

#define	DDRCTL_SCHED_PAGECLOSE_SHIFT (2U)

#define	DDRCTL_SCHED_PAGECLOSE_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_PAGECLOSE_SHIFT) & DDRCTL_SCHED_PAGECLOSE_MASK)

#define	DDRCTL_SCHED_PAGECLOSE_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_PAGECLOSE_MASK) >> DDRCTL_SCHED_PAGECLOSE_SHIFT)

#define	DDRCTL_SCHED_PREFER_WRITE_MASK (0x2U)

#define	DDRCTL_SCHED_PREFER_WRITE_SHIFT (1U)

#define	DDRCTL_SCHED_PREFER_WRITE_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_PREFER_WRITE_SHIFT) & DDRCTL_SCHED_PREFER_WRITE_MASK)

#define	DDRCTL_SCHED_PREFER_WRITE_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_PREFER_WRITE_MASK) >> DDRCTL_SCHED_PREFER_WRITE_SHIFT)

#define	DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK (0x1U)

#define	DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT (0U)

#define	DDRCTL_SCHED_FORCE_LOW_PRI_N_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK)

#define	DDRCTL_SCHED_FORCE_LOW_PRI_N_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK) >> DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT)

#define	DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK (0xFFU)

#define	DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT (0U)

#define	DDRCTL_SCHED1_PAGECLOSE_TIMER_SET(x) (((uint32_t)(x) << DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK)

#define	DDRCTL_SCHED1_PAGECLOSE_TIMER_GET(x) (((uint32_t)(x) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK) >> DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT)

#define	DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK (0xFF000000UL)

#define	DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT (24U)

#define	DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK)

#define	DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT)

#define	DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK (0xFFFFU)

#define	DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT (0U)

#define	DDRCTL_PERFHPR1_HPR_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK)

#define	DDRCTL_PERFHPR1_HPR_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK) >> DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT)

#define	DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK (0xFF000000UL)

#define	DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT (24U)

#define	DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK)

#define	DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT)

#define	DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK (0xFFFFU)

#define	DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT (0U)

#define	DDRCTL_PERFLPR1_LPR_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK)

#define	DDRCTL_PERFLPR1_LPR_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK) >> DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT)

#define	DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK (0xFF000000UL)

#define	DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT (24U)

#define	DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK)

#define	DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT)

#define	DDRCTL_PERFWR1_W_MAX_STARVE_MASK (0xFFFFU)

#define	DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT (0U)

#define	DDRCTL_PERFWR1_W_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK)

#define	DDRCTL_PERFWR1_W_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK) >> DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT)

#define	DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK (0x7FFU)

#define	DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT (0U)

#define	DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SET(x) (((uint32_t)(x) << DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK)

#define	DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_GET(x) (((uint32_t)(x) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT)

#define	DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK (0x7FFU)

#define	DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT (0U)

#define	DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SET(x) (((uint32_t)(x) << DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK)

#define	DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_GET(x) (((uint32_t)(x) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT)

#define	DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK (0x10U)

#define	DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT (4U)

#define	DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK)

#define	DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK) >> DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT)

#define	DDRCTL_DBG0_DIS_ACT_BYPASS_MASK (0x4U)

#define	DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT (2U)

#define	DDRCTL_DBG0_DIS_ACT_BYPASS_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK)

#define	DDRCTL_DBG0_DIS_ACT_BYPASS_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK) >> DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT)

#define	DDRCTL_DBG0_DIS_RD_BYPASS_MASK (0x2U)

#define	DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT (1U)

#define	DDRCTL_DBG0_DIS_RD_BYPASS_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK)

#define	DDRCTL_DBG0_DIS_RD_BYPASS_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK) >> DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT)

#define	DDRCTL_DBG0_DIS_WC_MASK (0x1U)

#define	DDRCTL_DBG0_DIS_WC_SHIFT (0U)

#define	DDRCTL_DBG0_DIS_WC_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_WC_SHIFT) & DDRCTL_DBG0_DIS_WC_MASK)

#define	DDRCTL_DBG0_DIS_WC_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_WC_MASK) >> DDRCTL_DBG0_DIS_WC_SHIFT)

#define	DDRCTL_DBG1_DIS_HIF_MASK (0x2U)

#define	DDRCTL_DBG1_DIS_HIF_SHIFT (1U)

#define	DDRCTL_DBG1_DIS_HIF_SET(x) (((uint32_t)(x) << DDRCTL_DBG1_DIS_HIF_SHIFT) & DDRCTL_DBG1_DIS_HIF_MASK)

#define	DDRCTL_DBG1_DIS_HIF_GET(x) (((uint32_t)(x) & DDRCTL_DBG1_DIS_HIF_MASK) >> DDRCTL_DBG1_DIS_HIF_SHIFT)

#define	DDRCTL_DBG1_DIS_DQ_MASK (0x1U)

#define	DDRCTL_DBG1_DIS_DQ_SHIFT (0U)

#define	DDRCTL_DBG1_DIS_DQ_SET(x) (((uint32_t)(x) << DDRCTL_DBG1_DIS_DQ_SHIFT) & DDRCTL_DBG1_DIS_DQ_MASK)

#define	DDRCTL_DBG1_DIS_DQ_GET(x) (((uint32_t)(x) & DDRCTL_DBG1_DIS_DQ_MASK) >> DDRCTL_DBG1_DIS_DQ_SHIFT)

#define	DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK (0x20000000UL)

#define	DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT (29U)

#define	DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT)

#define	DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK (0x10000000UL)

#define	DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT (28U)

#define	DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT)

#define	DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK (0x4000000UL)

#define	DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT (26U)

#define	DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT)

#define	DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK (0x2000000UL)

#define	DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT (25U)

#define	DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT)

#define	DDRCTL_DBGCAM_DBG_STALL_MASK (0x1000000UL)

#define	DDRCTL_DBGCAM_DBG_STALL_SHIFT (24U)

#define	DDRCTL_DBGCAM_DBG_STALL_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_STALL_MASK) >> DDRCTL_DBGCAM_DBG_STALL_SHIFT)

#define	DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK (0x7F0000UL)

#define	DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT (16U)

#define	DDRCTL_DBGCAM_DBG_W_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT)

#define	DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK (0x7F00U)

#define	DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT (8U)

#define	DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT)

#define	DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK (0x7FU)

#define	DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT (0U)

#define	DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT)

#define	DDRCTL_DBGCMD_CTRLUPD_MASK (0x20U)

#define	DDRCTL_DBGCMD_CTRLUPD_SHIFT (5U)

#define	DDRCTL_DBGCMD_CTRLUPD_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_CTRLUPD_SHIFT) & DDRCTL_DBGCMD_CTRLUPD_MASK)

#define	DDRCTL_DBGCMD_CTRLUPD_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_CTRLUPD_MASK) >> DDRCTL_DBGCMD_CTRLUPD_SHIFT)

#define	DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK (0x10U)

#define	DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT (4U)

#define	DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK)

#define	DDRCTL_DBGCMD_ZQ_CALIB_SHORT_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK) >> DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT)

#define	DDRCTL_DBGCMD_RANK1_REFRESH_MASK (0x2U)

#define	DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT (1U)

#define	DDRCTL_DBGCMD_RANK1_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK)

#define	DDRCTL_DBGCMD_RANK1_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT)

#define	DDRCTL_DBGCMD_RANK0_REFRESH_MASK (0x1U)

#define	DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT (0U)

#define	DDRCTL_DBGCMD_RANK0_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK)

#define	DDRCTL_DBGCMD_RANK0_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT)

#define	DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK (0x20U)

#define	DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT (5U)

#define	DDRCTL_DBGSTAT_CTRLUPD_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK) >> DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT)

#define	DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK (0x10U)

#define	DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT (4U)

#define	DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK) >> DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT)

#define	DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK (0x2U)

#define	DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT (1U)

#define	DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT)

#define	DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK (0x1U)

#define	DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT (0U)

#define	DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK (0x80000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT (31U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_15_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK (0x40000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT (30U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_14_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK (0x20000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT (29U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_13_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK (0x10000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT (28U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_12_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK (0x8000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT (27U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_11_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK (0x4000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT (26U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_10_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK (0x2000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT (25U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_9_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK (0x1000000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT (24U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_8_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK (0x800000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT (23U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_7_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK (0x400000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT (22U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_6_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK (0x200000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT (21U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_5_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK (0x100000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT (20U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_4_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK (0x80000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT (19U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_3_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK (0x40000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT (18U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_2_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK (0x20000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT (17U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_1_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK (0x10000UL)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT (16U)

#define	DDRCTL_PSTAT_WR_PORT_BUSY_0_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK (0x8000U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT (15U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_15_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK (0x4000U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT (14U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_14_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK (0x2000U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT (13U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_13_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK (0x1000U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT (12U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_12_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK (0x800U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT (11U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_11_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK (0x400U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT (10U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_10_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK (0x200U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT (9U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_9_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK (0x100U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT (8U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_8_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK (0x80U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT (7U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_7_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK (0x40U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT (6U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_6_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK (0x20U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT (5U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_5_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK (0x10U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT (4U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_4_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK (0x8U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT (3U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_3_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK (0x4U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT (2U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_2_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK (0x2U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT (1U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_1_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK (0x1U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT (0U)

#define	DDRCTL_PSTAT_RD_PORT_BUSY_0_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT)

#define	DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK (0x10U)

#define	DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT (4U)

#define	DDRCTL_PCCFG_PAGEMATCH_LIMIT_SET(x) (((uint32_t)(x) << DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK)

#define	DDRCTL_PCCFG_PAGEMATCH_LIMIT_GET(x) (((uint32_t)(x) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK) >> DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT)

#define	DDRCTL_PCCFG_GO2CRITICAL_EN_MASK (0x1U)

#define	DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT (0U)

#define	DDRCTL_PCCFG_GO2CRITICAL_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK)

#define	DDRCTL_PCCFG_GO2CRITICAL_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK) >> DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT)

#define	DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK (0x4000U)

#define	DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT (14U)

#define	DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK)

#define	DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT)

#define	DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK (0x2000U)

#define	DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT (13U)

#define	DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK)

#define	DDRCTL_PCFG_R_RD_PORT_URGENT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT)

#define	DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK (0x1000U)

#define	DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT (12U)

#define	DDRCTL_PCFG_R_RD_PORT_AGING_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK)

#define	DDRCTL_PCFG_R_RD_PORT_AGING_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT)

#define	DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK (0x3FFU)

#define	DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT (0U)

#define	DDRCTL_PCFG_R_RD_PORT_PRIORITY_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK)

#define	DDRCTL_PCFG_R_RD_PORT_PRIORITY_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT)

#define	DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK (0x4000U)

#define	DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT (14U)

#define	DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK)

#define	DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT)

#define	DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK (0x2000U)

#define	DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT (13U)

#define	DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK)

#define	DDRCTL_PCFG_W_WR_PORT_URGENT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT)

#define	DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK (0x1000U)

#define	DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT (12U)

#define	DDRCTL_PCFG_W_WR_PORT_AGING_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK)

#define	DDRCTL_PCFG_W_WR_PORT_AGING_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT)

#define	DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK (0x3FFU)

#define	DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT (0U)

#define	DDRCTL_PCFG_W_WR_PORT_PRIORITY_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK)

#define	DDRCTL_PCFG_W_WR_PORT_PRIORITY_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT)

#define	DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK (0x3U)

#define	DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT (0U)

#define	DDRCTL_PCFG_C_AHB_ENDIANNESS_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK)

#define	DDRCTL_PCFG_C_AHB_ENDIANNESS_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK) >> DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT)

#define	DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK (0xFFFFFFFFUL)

#define	DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT (0U)

#define	DDRCTL_PCFG_ID_MASKCH_ID_MASK_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK)

#define	DDRCTL_PCFG_ID_MASKCH_ID_MASK_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK) >> DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT)

#define	DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK (0xFFFFFFFFUL)

#define	DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT (0U)

#define	DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK)

#define	DDRCTL_PCFG_ID_VALUECH_ID_VALUE_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK) >> DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT)

#define	DDRCTL_PCFG_CTRL_PORT_EN_MASK (0x1U)

#define	DDRCTL_PCFG_CTRL_PORT_EN_SHIFT (0U)

#define	DDRCTL_PCFG_CTRL_PORT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_CTRL_PORT_EN_SHIFT) & DDRCTL_PCFG_CTRL_PORT_EN_MASK)

#define	DDRCTL_PCFG_CTRL_PORT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_CTRL_PORT_EN_MASK) >> DDRCTL_PCFG_CTRL_PORT_EN_SHIFT)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK (0x300000UL)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT (20U)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK (0x30000UL)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT (16U)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK (0xFU)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT (0U)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK)

#define	DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK (0x7FF0000UL)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT (16U)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK (0x7FFU)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT (0U)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK)

#define	DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK (0x300000UL)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT (20U)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK (0x30000UL)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT (16U)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK (0xFU)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT (0U)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK)

#define	DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT)

#define	DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK (0x7FFU)

#define	DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT (0U)

#define	DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK)

#define	DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK) >> DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT)

#define	DDRCTL_SAR_BASE_BASE_ADDR_MASK (0xFFFFFFFFUL)

#define	DDRCTL_SAR_BASE_BASE_ADDR_SHIFT (0U)

#define	DDRCTL_SAR_BASE_BASE_ADDR_SET(x) (((uint32_t)(x) << DDRCTL_SAR_BASE_BASE_ADDR_SHIFT) & DDRCTL_SAR_BASE_BASE_ADDR_MASK)

#define	DDRCTL_SAR_BASE_BASE_ADDR_GET(x) (((uint32_t)(x) & DDRCTL_SAR_BASE_BASE_ADDR_MASK) >> DDRCTL_SAR_BASE_BASE_ADDR_SHIFT)

#define	DDRCTL_SAR_SIZE_NBLOCKS_MASK (0xFFU)

#define	DDRCTL_SAR_SIZE_NBLOCKS_SHIFT (0U)

#define	DDRCTL_SAR_SIZE_NBLOCKS_SET(x) (((uint32_t)(x) << DDRCTL_SAR_SIZE_NBLOCKS_SHIFT) & DDRCTL_SAR_SIZE_NBLOCKS_MASK)

#define	DDRCTL_SAR_SIZE_NBLOCKS_GET(x) (((uint32_t)(x) & DDRCTL_SAR_SIZE_NBLOCKS_MASK) >> DDRCTL_SAR_SIZE_NBLOCKS_SHIFT)

#define	DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK (0x1FFF00UL)

#define	DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT (8U)

#define	DDRCTL_SBRCTL_SCRUB_INTERVAL_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK)

#define	DDRCTL_SBRCTL_SCRUB_INTERVAL_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK) >> DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT)

#define	DDRCTL_SBRCTL_SCRUB_BURST_MASK (0x70U)

#define	DDRCTL_SBRCTL_SCRUB_BURST_SHIFT (4U)

#define	DDRCTL_SBRCTL_SCRUB_BURST_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_BURST_SHIFT) & DDRCTL_SBRCTL_SCRUB_BURST_MASK)

#define	DDRCTL_SBRCTL_SCRUB_BURST_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_BURST_MASK) >> DDRCTL_SBRCTL_SCRUB_BURST_SHIFT)

#define	DDRCTL_SBRCTL_SCRUB_MODE_MASK (0x4U)

#define	DDRCTL_SBRCTL_SCRUB_MODE_SHIFT (2U)

#define	DDRCTL_SBRCTL_SCRUB_MODE_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_MODE_SHIFT) & DDRCTL_SBRCTL_SCRUB_MODE_MASK)

#define	DDRCTL_SBRCTL_SCRUB_MODE_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_MODE_MASK) >> DDRCTL_SBRCTL_SCRUB_MODE_SHIFT)

#define	DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK (0x2U)

#define	DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT (1U)

#define	DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK)

#define	DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK) >> DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT)

#define	DDRCTL_SBRCTL_SCRUB_EN_MASK (0x1U)

#define	DDRCTL_SBRCTL_SCRUB_EN_SHIFT (0U)

#define	DDRCTL_SBRCTL_SCRUB_EN_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_EN_SHIFT) & DDRCTL_SBRCTL_SCRUB_EN_MASK)

#define	DDRCTL_SBRCTL_SCRUB_EN_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_EN_MASK) >> DDRCTL_SBRCTL_SCRUB_EN_SHIFT)

#define	DDRCTL_SBRSTAT_SCRUB_DONE_MASK (0x2U)

#define	DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT (1U)

#define	DDRCTL_SBRSTAT_SCRUB_DONE_GET(x) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_DONE_MASK) >> DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT)

#define	DDRCTL_SBRSTAT_SCRUB_BUSY_MASK (0x1U)

#define	DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT (0U)

#define	DDRCTL_SBRSTAT_SCRUB_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_BUSY_MASK) >> DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT)

#define	DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK (0xFFFFFFFFUL)

#define	DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT (0U)

#define	DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SET(x) (((uint32_t)(x) << DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK)

#define	DDRCTL_SBRWDATA0_SCRUB_PATTERN0_GET(x) (((uint32_t)(x) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK) >> DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT)

#define	DDRCTL_ID_0 (0UL)

#define	DDRCTL_ID_1 (1UL)

#define	DDRCTL_ID_2 (2UL)

#define	DDRCTL_ID_3 (3UL)

#define	DDRCTL_ID_4 (4UL)

#define	DDRCTL_ID_5 (5UL)

#define	DDRCTL_ID_6 (6UL)

#define	DDRCTL_ID_7 (7UL)

#define	DDRCTL_ID_8 (8UL)

#define	DDRCTL_ID_9 (9UL)

#define	DDRCTL_ID_10 (10UL)

#define	DDRCTL_ID_11 (11UL)

#define	DDRCTL_ID_12 (12UL)

#define	DDRCTL_ID_13 (13UL)

#define	DDRCTL_ID_14 (14UL)

#define	DDRCTL_ID_15 (15UL)

#define	DDRCTL_PCFG_0 (0UL)

#define	DDRCTL_PCFG_1 (1UL)

#define	DDRCTL_PCFG_2 (2UL)

#define	DDRCTL_PCFG_3 (3UL)

#define	DDRCTL_PCFG_4 (4UL)

#define	DDRCTL_PCFG_5 (5UL)

#define	DDRCTL_PCFG_6 (6UL)

#define	DDRCTL_PCFG_7 (7UL)

#define	DDRCTL_PCFG_8 (8UL)

#define	DDRCTL_PCFG_9 (9UL)

#define	DDRCTL_PCFG_10 (10UL)

#define	DDRCTL_PCFG_11 (11UL)

#define	DDRCTL_PCFG_12 (12UL)

#define	DDRCTL_PCFG_13 (13UL)

#define	DDRCTL_PCFG_14 (14UL)

#define	DDRCTL_PCFG_15 (15UL)

#define	DDRCTL_SAR_0 (0UL)

#define	DDRCTL_SAR_1 (1UL)

#define	DDRCTL_SAR_2 (2UL)

#define	DDRCTL_SAR_3 (3UL)

Macro Definition Documentation

◆ DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_GET

#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) >> DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT)

◆ DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK

#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK (0x1FU)

◆ DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SET

#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK)

◆ DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT

#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT (0U)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_GET

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK (0x1FU)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SET

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT (0U)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_GET

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK (0x1F00U)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SET

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT (8U)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_GET

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK (0x1F0000UL)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SET

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK)

◆ DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT

#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT (16U)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_GET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK (0xFU)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT (0U)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_GET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK (0xF00U)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT (8U)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_GET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK (0xF0000UL)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT (16U)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_GET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK (0xF000000UL)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SET

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK)

◆ DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT

#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT (24U)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_GET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK (0xFU)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT (0U)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_GET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK (0xF00U)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT (8U)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_GET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK (0xF0000UL)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT (16U)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_GET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK (0xF000000UL)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SET

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK)

◆ DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT

#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT (24U)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_GET

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK (0xFU)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SET

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT (0U)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_GET

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK (0xF00U)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SET

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK)

◆ DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT

#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT (8U)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_GET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK (0xFU)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT (0U)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_GET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK (0xF000000UL)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT (24U)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_GET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK (0xF00U)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT (8U)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_GET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK (0xF0000UL)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SET

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK)

◆ DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT

#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT (16U)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_GET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK (0xFU)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT (0U)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_GET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK (0xF00U)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT (8U)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_GET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK (0xF0000UL)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT (16U)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_GET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_GET ( x ) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK (0xF000000UL)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SET

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SET ( x ) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK)

◆ DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT

#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT (24U)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_GET

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_GET ( x ) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK (0x4U)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SET

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SET ( x ) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT (2U)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_GET

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_GET ( x ) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK (0x2U)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SET

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SET ( x ) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT (1U)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_GET

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK (0x1U)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SET

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK)

◆ DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT

#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT (0U)

◆ DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_GET

#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_GET ( x ) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT)

◆ DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK

#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK (0xFFFFU)

◆ DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT

#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT (0U)

◆ DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_GET

#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_GET ( x ) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT)

◆ DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK

#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK (0x10000UL)

◆ DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT

#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT (16U)

◆ DDRCTL_DBG0_DIS_ACT_BYPASS_GET

#define DDRCTL_DBG0_DIS_ACT_BYPASS_GET ( x ) (((uint32_t)(x) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK) >> DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT)

◆ DDRCTL_DBG0_DIS_ACT_BYPASS_MASK

#define DDRCTL_DBG0_DIS_ACT_BYPASS_MASK (0x4U)

◆ DDRCTL_DBG0_DIS_ACT_BYPASS_SET

#define DDRCTL_DBG0_DIS_ACT_BYPASS_SET ( x ) (((uint32_t)(x) << DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK)

◆ DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT

#define DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT (2U)

◆ DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_GET

#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_GET ( x ) (((uint32_t)(x) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK) >> DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT)

◆ DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK

#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK (0x10U)

◆ DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SET

#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SET ( x ) (((uint32_t)(x) << DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK)

◆ DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT

#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT (4U)

◆ DDRCTL_DBG0_DIS_RD_BYPASS_GET

#define DDRCTL_DBG0_DIS_RD_BYPASS_GET ( x ) (((uint32_t)(x) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK) >> DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT)

◆ DDRCTL_DBG0_DIS_RD_BYPASS_MASK

#define DDRCTL_DBG0_DIS_RD_BYPASS_MASK (0x2U)

◆ DDRCTL_DBG0_DIS_RD_BYPASS_SET

#define DDRCTL_DBG0_DIS_RD_BYPASS_SET ( x ) (((uint32_t)(x) << DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK)

◆ DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT

#define DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT (1U)

◆ DDRCTL_DBG0_DIS_WC_GET

#define DDRCTL_DBG0_DIS_WC_GET ( x ) (((uint32_t)(x) & DDRCTL_DBG0_DIS_WC_MASK) >> DDRCTL_DBG0_DIS_WC_SHIFT)

◆ DDRCTL_DBG0_DIS_WC_MASK

#define DDRCTL_DBG0_DIS_WC_MASK (0x1U)

◆ DDRCTL_DBG0_DIS_WC_SET

#define DDRCTL_DBG0_DIS_WC_SET ( x ) (((uint32_t)(x) << DDRCTL_DBG0_DIS_WC_SHIFT) & DDRCTL_DBG0_DIS_WC_MASK)

◆ DDRCTL_DBG0_DIS_WC_SHIFT

#define DDRCTL_DBG0_DIS_WC_SHIFT (0U)

◆ DDRCTL_DBG1_DIS_DQ_GET

#define DDRCTL_DBG1_DIS_DQ_GET ( x ) (((uint32_t)(x) & DDRCTL_DBG1_DIS_DQ_MASK) >> DDRCTL_DBG1_DIS_DQ_SHIFT)

◆ DDRCTL_DBG1_DIS_DQ_MASK

#define DDRCTL_DBG1_DIS_DQ_MASK (0x1U)

◆ DDRCTL_DBG1_DIS_DQ_SET

#define DDRCTL_DBG1_DIS_DQ_SET ( x ) (((uint32_t)(x) << DDRCTL_DBG1_DIS_DQ_SHIFT) & DDRCTL_DBG1_DIS_DQ_MASK)

◆ DDRCTL_DBG1_DIS_DQ_SHIFT

#define DDRCTL_DBG1_DIS_DQ_SHIFT (0U)

◆ DDRCTL_DBG1_DIS_HIF_GET

#define DDRCTL_DBG1_DIS_HIF_GET ( x ) (((uint32_t)(x) & DDRCTL_DBG1_DIS_HIF_MASK) >> DDRCTL_DBG1_DIS_HIF_SHIFT)

◆ DDRCTL_DBG1_DIS_HIF_MASK

#define DDRCTL_DBG1_DIS_HIF_MASK (0x2U)

◆ DDRCTL_DBG1_DIS_HIF_SET

#define DDRCTL_DBG1_DIS_HIF_SET ( x ) (((uint32_t)(x) << DDRCTL_DBG1_DIS_HIF_SHIFT) & DDRCTL_DBG1_DIS_HIF_MASK)

◆ DDRCTL_DBG1_DIS_HIF_SHIFT

#define DDRCTL_DBG1_DIS_HIF_SHIFT (1U)

◆ DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_GET

#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT)

◆ DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK

#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK (0x7FU)

◆ DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT

#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT (0U)

◆ DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_GET

#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT)

◆ DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK

#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK (0x7F00U)

◆ DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT

#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT (8U)

◆ DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_GET

#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT)

◆ DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK

#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK (0x2000000UL)

◆ DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT

#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT (25U)

◆ DDRCTL_DBGCAM_DBG_STALL_GET

#define DDRCTL_DBGCAM_DBG_STALL_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_STALL_MASK) >> DDRCTL_DBGCAM_DBG_STALL_SHIFT)

◆ DDRCTL_DBGCAM_DBG_STALL_MASK

#define DDRCTL_DBGCAM_DBG_STALL_MASK (0x1000000UL)

◆ DDRCTL_DBGCAM_DBG_STALL_SHIFT

#define DDRCTL_DBGCAM_DBG_STALL_SHIFT (24U)

◆ DDRCTL_DBGCAM_DBG_W_Q_DEPTH_GET

#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT)

◆ DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK

#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK (0x7F0000UL)

◆ DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT

#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT (16U)

◆ DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_GET

#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT)

◆ DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK

#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK (0x4000000UL)

◆ DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT

#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT (26U)

◆ DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_GET

#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT)

◆ DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK

#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK (0x10000000UL)

◆ DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT

#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT (28U)

◆ DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_GET

#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT)

◆ DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK

#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK (0x20000000UL)

◆ DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT

#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT (29U)

◆ DDRCTL_DBGCMD_CTRLUPD_GET

#define DDRCTL_DBGCMD_CTRLUPD_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCMD_CTRLUPD_MASK) >> DDRCTL_DBGCMD_CTRLUPD_SHIFT)

◆ DDRCTL_DBGCMD_CTRLUPD_MASK

#define DDRCTL_DBGCMD_CTRLUPD_MASK (0x20U)

◆ DDRCTL_DBGCMD_CTRLUPD_SET

#define DDRCTL_DBGCMD_CTRLUPD_SET ( x ) (((uint32_t)(x) << DDRCTL_DBGCMD_CTRLUPD_SHIFT) & DDRCTL_DBGCMD_CTRLUPD_MASK)

◆ DDRCTL_DBGCMD_CTRLUPD_SHIFT

#define DDRCTL_DBGCMD_CTRLUPD_SHIFT (5U)

◆ DDRCTL_DBGCMD_RANK0_REFRESH_GET

#define DDRCTL_DBGCMD_RANK0_REFRESH_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT)

◆ DDRCTL_DBGCMD_RANK0_REFRESH_MASK

#define DDRCTL_DBGCMD_RANK0_REFRESH_MASK (0x1U)

◆ DDRCTL_DBGCMD_RANK0_REFRESH_SET

#define DDRCTL_DBGCMD_RANK0_REFRESH_SET ( x ) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK)

◆ DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT

#define DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT (0U)

◆ DDRCTL_DBGCMD_RANK1_REFRESH_GET

#define DDRCTL_DBGCMD_RANK1_REFRESH_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT)

◆ DDRCTL_DBGCMD_RANK1_REFRESH_MASK

#define DDRCTL_DBGCMD_RANK1_REFRESH_MASK (0x2U)

◆ DDRCTL_DBGCMD_RANK1_REFRESH_SET

#define DDRCTL_DBGCMD_RANK1_REFRESH_SET ( x ) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK)

◆ DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT

#define DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT (1U)

◆ DDRCTL_DBGCMD_ZQ_CALIB_SHORT_GET

#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK) >> DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT)

◆ DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK

#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK (0x10U)

◆ DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SET

#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SET ( x ) (((uint32_t)(x) << DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK)

◆ DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT

#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT (4U)

◆ DDRCTL_DBGSTAT_CTRLUPD_BUSY_GET

#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK) >> DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT)

◆ DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK

#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK (0x20U)

◆ DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT

#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT (5U)

◆ DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_GET

#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT)

◆ DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK

#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK (0x1U)

◆ DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT

#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT (0U)

◆ DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_GET

#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT)

◆ DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK

#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK (0x2U)

◆ DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT

#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT (1U)

◆ DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_GET

#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK) >> DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT)

◆ DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK

#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK (0x10U)

◆ DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT

#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT (4U)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_PD_GET

#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_GET ( x ) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK

#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK (0x1U)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SET

#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SET ( x ) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT

#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT (0U)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_SR_GET

#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_GET ( x ) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK

#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK (0x100U)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SET

#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SET ( x ) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK)

◆ DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT

#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT (8U)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_GET

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_GET ( x ) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK (0xF0U)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SET

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SET ( x ) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT (4U)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_GET

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_GET ( x ) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK (0xF000U)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SET

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SET ( x ) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK)

◆ DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT

#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT (12U)

◆ DDRCTL_DFILPCFG0_DFI_TLP_RESP_GET

#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_GET ( x ) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK) >> DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT)

◆ DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK

#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK (0xF000000UL)

◆ DDRCTL_DFILPCFG0_DFI_TLP_RESP_SET

#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_SET ( x ) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK)

◆ DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT

#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT (24U)

◆ DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_GET

#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK) >> DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT)

◆ DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK

#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK (0x1U)

◆ DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SET

#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK)

◆ DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT

#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT (0U)

◆ DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_GET

#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT)

◆ DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK

#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK (0x800000UL)

◆ DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SET

#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK)

◆ DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT

#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT (23U)

◆ DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_GET

#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK) >> DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT)

◆ DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK

#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK (0x1F000000UL)

◆ DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SET

#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK)

◆ DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT

#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT (24U)

◆ DDRCTL_DFITMG0_DFI_T_RDDATA_EN_GET

#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK) >> DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT)

◆ DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK

#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK (0x3F0000UL)

◆ DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SET

#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK)

◆ DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT

#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT (16U)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRDATA_GET

#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK

#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK (0x3F00U)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SET

#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT

#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT (8U)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRLAT_GET

#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK

#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK (0x3FU)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SET

#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK)

◆ DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT

#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT (0U)

◆ DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_GET

#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT)

◆ DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK

#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK (0x8000U)

◆ DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SET

#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK)

◆ DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT

#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT (15U)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_GET

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK (0xF00U)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SET

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_GET

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK (0xFU)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SET

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK)

◆ DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT

#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U)

◆ DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_GET

#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK) >> DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT)

◆ DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK

#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK (0x1F0000UL)

◆ DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SET

#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK)

◆ DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT

#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT (16U)

◆ DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_GET

#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT)

◆ DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK

#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK (0x3F00U)

◆ DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SET

#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK)

◆ DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT

#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT (8U)

◆ DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_GET

#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_GET ( x ) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT)

◆ DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK

#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK (0x3FU)

◆ DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SET

#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SET ( x ) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK)

◆ DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT

#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT (0U)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_GET

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK (0x3FF0000UL)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SET

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT (16U)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_GET

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK (0x3FFU)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SET

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK)

◆ DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT

#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT (0U)

◆ DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_GET

#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK) >> DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT)

◆ DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK

#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK (0x80000000UL)

◆ DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SET

#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK)

◆ DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT

#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT (31U)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_GET

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK (0xFFU)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SET

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT (0U)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_GET

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK (0xFF0000UL)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SET

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK)

◆ DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT

#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT (16U)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_EN_GET

#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK

#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK (0x80000000UL)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SET

#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT

#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT (31U)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_GET

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK (0xFFFU)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SET

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT (0U)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_GET

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK (0xFFF0000UL)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SET

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK)

◆ DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT

#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT (16U)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_GET

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK (0xFFFU)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SET

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT (0U)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_GET

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_GET ( x ) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK (0xFFF0000UL)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SET

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SET ( x ) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK)

◆ DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT

#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT (16U)

◆ DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_GET

#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT)

◆ DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK

#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK (0x2U)

◆ DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SET

#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK)

◆ DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT

#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT (1U)

◆ DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_GET

#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT)

◆ DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK

#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK (0x1U)

◆ DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SET

#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK)

◆ DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT

#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT (0U)

◆ DDRCTL_DRAMTMG0_T_FAW_GET

#define DDRCTL_DRAMTMG0_T_FAW_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_FAW_MASK) >> DDRCTL_DRAMTMG0_T_FAW_SHIFT)

◆ DDRCTL_DRAMTMG0_T_FAW_MASK

#define DDRCTL_DRAMTMG0_T_FAW_MASK (0x3F0000UL)

◆ DDRCTL_DRAMTMG0_T_FAW_SET

#define DDRCTL_DRAMTMG0_T_FAW_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_FAW_SHIFT) & DDRCTL_DRAMTMG0_T_FAW_MASK)

◆ DDRCTL_DRAMTMG0_T_FAW_SHIFT

#define DDRCTL_DRAMTMG0_T_FAW_SHIFT (16U)

◆ DDRCTL_DRAMTMG0_T_RAS_MAX_GET

#define DDRCTL_DRAMTMG0_T_RAS_MAX_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT)

◆ DDRCTL_DRAMTMG0_T_RAS_MAX_MASK

#define DDRCTL_DRAMTMG0_T_RAS_MAX_MASK (0x7F00U)

◆ DDRCTL_DRAMTMG0_T_RAS_MAX_SET

#define DDRCTL_DRAMTMG0_T_RAS_MAX_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK)

◆ DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT

#define DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT (8U)

◆ DDRCTL_DRAMTMG0_T_RAS_MIN_GET

#define DDRCTL_DRAMTMG0_T_RAS_MIN_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT)

◆ DDRCTL_DRAMTMG0_T_RAS_MIN_MASK

#define DDRCTL_DRAMTMG0_T_RAS_MIN_MASK (0x3FU)

◆ DDRCTL_DRAMTMG0_T_RAS_MIN_SET

#define DDRCTL_DRAMTMG0_T_RAS_MIN_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK)

◆ DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT

#define DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT (0U)

◆ DDRCTL_DRAMTMG0_WR2PRE_GET

#define DDRCTL_DRAMTMG0_WR2PRE_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG0_WR2PRE_MASK) >> DDRCTL_DRAMTMG0_WR2PRE_SHIFT)

◆ DDRCTL_DRAMTMG0_WR2PRE_MASK

#define DDRCTL_DRAMTMG0_WR2PRE_MASK (0x7F000000UL)

◆ DDRCTL_DRAMTMG0_WR2PRE_SET

#define DDRCTL_DRAMTMG0_WR2PRE_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG0_WR2PRE_SHIFT) & DDRCTL_DRAMTMG0_WR2PRE_MASK)

◆ DDRCTL_DRAMTMG0_WR2PRE_SHIFT

#define DDRCTL_DRAMTMG0_WR2PRE_SHIFT (24U)

◆ DDRCTL_DRAMTMG1_RD2PRE_GET

#define DDRCTL_DRAMTMG1_RD2PRE_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG1_RD2PRE_MASK) >> DDRCTL_DRAMTMG1_RD2PRE_SHIFT)

◆ DDRCTL_DRAMTMG1_RD2PRE_MASK

#define DDRCTL_DRAMTMG1_RD2PRE_MASK (0x1F00U)

◆ DDRCTL_DRAMTMG1_RD2PRE_SET

#define DDRCTL_DRAMTMG1_RD2PRE_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG1_RD2PRE_SHIFT) & DDRCTL_DRAMTMG1_RD2PRE_MASK)

◆ DDRCTL_DRAMTMG1_RD2PRE_SHIFT

#define DDRCTL_DRAMTMG1_RD2PRE_SHIFT (8U)

◆ DDRCTL_DRAMTMG1_T_RC_GET

#define DDRCTL_DRAMTMG1_T_RC_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_RC_MASK) >> DDRCTL_DRAMTMG1_T_RC_SHIFT)

◆ DDRCTL_DRAMTMG1_T_RC_MASK

#define DDRCTL_DRAMTMG1_T_RC_MASK (0x7FU)

◆ DDRCTL_DRAMTMG1_T_RC_SET

#define DDRCTL_DRAMTMG1_T_RC_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_RC_SHIFT) & DDRCTL_DRAMTMG1_T_RC_MASK)

◆ DDRCTL_DRAMTMG1_T_RC_SHIFT

#define DDRCTL_DRAMTMG1_T_RC_SHIFT (0U)

◆ DDRCTL_DRAMTMG1_T_XP_GET

#define DDRCTL_DRAMTMG1_T_XP_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_XP_MASK) >> DDRCTL_DRAMTMG1_T_XP_SHIFT)

◆ DDRCTL_DRAMTMG1_T_XP_MASK

#define DDRCTL_DRAMTMG1_T_XP_MASK (0x1F0000UL)

◆ DDRCTL_DRAMTMG1_T_XP_SET

#define DDRCTL_DRAMTMG1_T_XP_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_XP_SHIFT) & DDRCTL_DRAMTMG1_T_XP_MASK)

◆ DDRCTL_DRAMTMG1_T_XP_SHIFT

#define DDRCTL_DRAMTMG1_T_XP_SHIFT (16U)

◆ DDRCTL_DRAMTMG2_RD2WR_GET

#define DDRCTL_DRAMTMG2_RD2WR_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG2_RD2WR_MASK) >> DDRCTL_DRAMTMG2_RD2WR_SHIFT)

◆ DDRCTL_DRAMTMG2_RD2WR_MASK

#define DDRCTL_DRAMTMG2_RD2WR_MASK (0x1F00U)

◆ DDRCTL_DRAMTMG2_RD2WR_SET

#define DDRCTL_DRAMTMG2_RD2WR_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG2_RD2WR_SHIFT) & DDRCTL_DRAMTMG2_RD2WR_MASK)

◆ DDRCTL_DRAMTMG2_RD2WR_SHIFT

#define DDRCTL_DRAMTMG2_RD2WR_SHIFT (8U)

◆ DDRCTL_DRAMTMG2_WR2RD_GET

#define DDRCTL_DRAMTMG2_WR2RD_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG2_WR2RD_MASK) >> DDRCTL_DRAMTMG2_WR2RD_SHIFT)

◆ DDRCTL_DRAMTMG2_WR2RD_MASK

#define DDRCTL_DRAMTMG2_WR2RD_MASK (0x3FU)

◆ DDRCTL_DRAMTMG2_WR2RD_SET

#define DDRCTL_DRAMTMG2_WR2RD_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG2_WR2RD_SHIFT) & DDRCTL_DRAMTMG2_WR2RD_MASK)

◆ DDRCTL_DRAMTMG2_WR2RD_SHIFT

#define DDRCTL_DRAMTMG2_WR2RD_SHIFT (0U)

◆ DDRCTL_DRAMTMG3_T_MOD_GET

#define DDRCTL_DRAMTMG3_T_MOD_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MOD_MASK) >> DDRCTL_DRAMTMG3_T_MOD_SHIFT)

◆ DDRCTL_DRAMTMG3_T_MOD_MASK

#define DDRCTL_DRAMTMG3_T_MOD_MASK (0x3FFU)

◆ DDRCTL_DRAMTMG3_T_MOD_SET

#define DDRCTL_DRAMTMG3_T_MOD_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MOD_SHIFT) & DDRCTL_DRAMTMG3_T_MOD_MASK)

◆ DDRCTL_DRAMTMG3_T_MOD_SHIFT

#define DDRCTL_DRAMTMG3_T_MOD_SHIFT (0U)

◆ DDRCTL_DRAMTMG3_T_MRD_GET

#define DDRCTL_DRAMTMG3_T_MRD_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MRD_MASK) >> DDRCTL_DRAMTMG3_T_MRD_SHIFT)

◆ DDRCTL_DRAMTMG3_T_MRD_MASK

#define DDRCTL_DRAMTMG3_T_MRD_MASK (0x3F000UL)

◆ DDRCTL_DRAMTMG3_T_MRD_SET

#define DDRCTL_DRAMTMG3_T_MRD_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MRD_SHIFT) & DDRCTL_DRAMTMG3_T_MRD_MASK)

◆ DDRCTL_DRAMTMG3_T_MRD_SHIFT

#define DDRCTL_DRAMTMG3_T_MRD_SHIFT (12U)

◆ DDRCTL_DRAMTMG4_T_CCD_GET

#define DDRCTL_DRAMTMG4_T_CCD_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_CCD_MASK) >> DDRCTL_DRAMTMG4_T_CCD_SHIFT)

◆ DDRCTL_DRAMTMG4_T_CCD_MASK

#define DDRCTL_DRAMTMG4_T_CCD_MASK (0x70000UL)

◆ DDRCTL_DRAMTMG4_T_CCD_SET

#define DDRCTL_DRAMTMG4_T_CCD_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_CCD_SHIFT) & DDRCTL_DRAMTMG4_T_CCD_MASK)

◆ DDRCTL_DRAMTMG4_T_CCD_SHIFT

#define DDRCTL_DRAMTMG4_T_CCD_SHIFT (16U)

◆ DDRCTL_DRAMTMG4_T_RCD_GET

#define DDRCTL_DRAMTMG4_T_RCD_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RCD_MASK) >> DDRCTL_DRAMTMG4_T_RCD_SHIFT)

◆ DDRCTL_DRAMTMG4_T_RCD_MASK

#define DDRCTL_DRAMTMG4_T_RCD_MASK (0x1F000000UL)

◆ DDRCTL_DRAMTMG4_T_RCD_SET

#define DDRCTL_DRAMTMG4_T_RCD_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RCD_SHIFT) & DDRCTL_DRAMTMG4_T_RCD_MASK)

◆ DDRCTL_DRAMTMG4_T_RCD_SHIFT

#define DDRCTL_DRAMTMG4_T_RCD_SHIFT (24U)

◆ DDRCTL_DRAMTMG4_T_RP_GET

#define DDRCTL_DRAMTMG4_T_RP_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RP_MASK) >> DDRCTL_DRAMTMG4_T_RP_SHIFT)

◆ DDRCTL_DRAMTMG4_T_RP_MASK

#define DDRCTL_DRAMTMG4_T_RP_MASK (0x1FU)

◆ DDRCTL_DRAMTMG4_T_RP_SET

#define DDRCTL_DRAMTMG4_T_RP_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RP_SHIFT) & DDRCTL_DRAMTMG4_T_RP_MASK)

◆ DDRCTL_DRAMTMG4_T_RP_SHIFT

#define DDRCTL_DRAMTMG4_T_RP_SHIFT (0U)

◆ DDRCTL_DRAMTMG4_T_RRD_GET

#define DDRCTL_DRAMTMG4_T_RRD_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RRD_MASK) >> DDRCTL_DRAMTMG4_T_RRD_SHIFT)

◆ DDRCTL_DRAMTMG4_T_RRD_MASK

#define DDRCTL_DRAMTMG4_T_RRD_MASK (0xF00U)

◆ DDRCTL_DRAMTMG4_T_RRD_SET

#define DDRCTL_DRAMTMG4_T_RRD_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RRD_SHIFT) & DDRCTL_DRAMTMG4_T_RRD_MASK)

◆ DDRCTL_DRAMTMG4_T_RRD_SHIFT

#define DDRCTL_DRAMTMG4_T_RRD_SHIFT (8U)

◆ DDRCTL_DRAMTMG5_T_CKE_GET

#define DDRCTL_DRAMTMG5_T_CKE_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKE_MASK) >> DDRCTL_DRAMTMG5_T_CKE_SHIFT)

◆ DDRCTL_DRAMTMG5_T_CKE_MASK

#define DDRCTL_DRAMTMG5_T_CKE_MASK (0x1FU)

◆ DDRCTL_DRAMTMG5_T_CKE_SET

#define DDRCTL_DRAMTMG5_T_CKE_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKE_SHIFT) & DDRCTL_DRAMTMG5_T_CKE_MASK)

◆ DDRCTL_DRAMTMG5_T_CKE_SHIFT

#define DDRCTL_DRAMTMG5_T_CKE_SHIFT (0U)

◆ DDRCTL_DRAMTMG5_T_CKESR_GET

#define DDRCTL_DRAMTMG5_T_CKESR_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKESR_MASK) >> DDRCTL_DRAMTMG5_T_CKESR_SHIFT)

◆ DDRCTL_DRAMTMG5_T_CKESR_MASK

#define DDRCTL_DRAMTMG5_T_CKESR_MASK (0x3F00U)

◆ DDRCTL_DRAMTMG5_T_CKESR_SET

#define DDRCTL_DRAMTMG5_T_CKESR_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKESR_SHIFT) & DDRCTL_DRAMTMG5_T_CKESR_MASK)

◆ DDRCTL_DRAMTMG5_T_CKESR_SHIFT

#define DDRCTL_DRAMTMG5_T_CKESR_SHIFT (8U)

◆ DDRCTL_DRAMTMG5_T_CKSRE_GET

#define DDRCTL_DRAMTMG5_T_CKSRE_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRE_MASK) >> DDRCTL_DRAMTMG5_T_CKSRE_SHIFT)

◆ DDRCTL_DRAMTMG5_T_CKSRE_MASK

#define DDRCTL_DRAMTMG5_T_CKSRE_MASK (0xF0000UL)

◆ DDRCTL_DRAMTMG5_T_CKSRE_SET

#define DDRCTL_DRAMTMG5_T_CKSRE_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRE_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRE_MASK)

◆ DDRCTL_DRAMTMG5_T_CKSRE_SHIFT

#define DDRCTL_DRAMTMG5_T_CKSRE_SHIFT (16U)

◆ DDRCTL_DRAMTMG5_T_CKSRX_GET

#define DDRCTL_DRAMTMG5_T_CKSRX_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRX_MASK) >> DDRCTL_DRAMTMG5_T_CKSRX_SHIFT)

◆ DDRCTL_DRAMTMG5_T_CKSRX_MASK

#define DDRCTL_DRAMTMG5_T_CKSRX_MASK (0xF000000UL)

◆ DDRCTL_DRAMTMG5_T_CKSRX_SET

#define DDRCTL_DRAMTMG5_T_CKSRX_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRX_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRX_MASK)

◆ DDRCTL_DRAMTMG5_T_CKSRX_SHIFT

#define DDRCTL_DRAMTMG5_T_CKSRX_SHIFT (24U)

◆ DDRCTL_DRAMTMG8_T_XS_DLL_X32_GET

#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT)

◆ DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK

#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK (0x7F00U)

◆ DDRCTL_DRAMTMG8_T_XS_DLL_X32_SET

#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK)

◆ DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT

#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT (8U)

◆ DDRCTL_DRAMTMG8_T_XS_X32_GET

#define DDRCTL_DRAMTMG8_T_XS_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_X32_SHIFT)

◆ DDRCTL_DRAMTMG8_T_XS_X32_MASK

#define DDRCTL_DRAMTMG8_T_XS_X32_MASK (0x7FU)

◆ DDRCTL_DRAMTMG8_T_XS_X32_SET

#define DDRCTL_DRAMTMG8_T_XS_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_X32_MASK)

◆ DDRCTL_DRAMTMG8_T_XS_X32_SHIFT

#define DDRCTL_DRAMTMG8_T_XS_X32_SHIFT (0U)

◆ DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_GET

#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_GET ( x ) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT)

◆ DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK

#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK (0x3000000UL)

◆ DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT

#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT (24U)

◆ DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_GET

#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_GET ( x ) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT)

◆ DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK

#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK (0x3FFFFUL)

◆ DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT

#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT (0U)

◆ DDRCTL_HWLPCTL_HW_LP_EN_GET

#define DDRCTL_HWLPCTL_HW_LP_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EN_SHIFT)

◆ DDRCTL_HWLPCTL_HW_LP_EN_MASK

#define DDRCTL_HWLPCTL_HW_LP_EN_MASK (0x1U)

◆ DDRCTL_HWLPCTL_HW_LP_EN_SET

#define DDRCTL_HWLPCTL_HW_LP_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EN_MASK)

◆ DDRCTL_HWLPCTL_HW_LP_EN_SHIFT

#define DDRCTL_HWLPCTL_HW_LP_EN_SHIFT (0U)

◆ DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_GET

#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT)

◆ DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK

#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK (0x2U)

◆ DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SET

#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK)

◆ DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT

#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT (1U)

◆ DDRCTL_HWLPCTL_HW_LP_IDLE_X32_GET

#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK) >> DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT)

◆ DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK

#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK (0xFFF0000UL)

◆ DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SET

#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK)

◆ DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT

#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT (16U)

◆ DDRCTL_ID_0

#define DDRCTL_ID_0 (0UL)

◆ DDRCTL_ID_1

#define DDRCTL_ID_1 (1UL)

◆ DDRCTL_ID_10

#define DDRCTL_ID_10 (10UL)

◆ DDRCTL_ID_11

#define DDRCTL_ID_11 (11UL)

◆ DDRCTL_ID_12

#define DDRCTL_ID_12 (12UL)

◆ DDRCTL_ID_13

#define DDRCTL_ID_13 (13UL)

◆ DDRCTL_ID_14

#define DDRCTL_ID_14 (14UL)

◆ DDRCTL_ID_15

#define DDRCTL_ID_15 (15UL)

◆ DDRCTL_ID_2

#define DDRCTL_ID_2 (2UL)

◆ DDRCTL_ID_3

#define DDRCTL_ID_3 (3UL)

◆ DDRCTL_ID_4

#define DDRCTL_ID_4 (4UL)

◆ DDRCTL_ID_5

#define DDRCTL_ID_5 (5UL)

◆ DDRCTL_ID_6

#define DDRCTL_ID_6 (6UL)

◆ DDRCTL_ID_7

#define DDRCTL_ID_7 (7UL)

◆ DDRCTL_ID_8

#define DDRCTL_ID_8 (8UL)

◆ DDRCTL_ID_9

#define DDRCTL_ID_9 (9UL)

◆ DDRCTL_INIT0_POST_CKE_X1024_GET

#define DDRCTL_INIT0_POST_CKE_X1024_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT0_POST_CKE_X1024_MASK) >> DDRCTL_INIT0_POST_CKE_X1024_SHIFT)

◆ DDRCTL_INIT0_POST_CKE_X1024_MASK

#define DDRCTL_INIT0_POST_CKE_X1024_MASK (0x3FF0000UL)

◆ DDRCTL_INIT0_POST_CKE_X1024_SET

#define DDRCTL_INIT0_POST_CKE_X1024_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT0_POST_CKE_X1024_SHIFT) & DDRCTL_INIT0_POST_CKE_X1024_MASK)

◆ DDRCTL_INIT0_POST_CKE_X1024_SHIFT

#define DDRCTL_INIT0_POST_CKE_X1024_SHIFT (16U)

◆ DDRCTL_INIT0_PRE_CKE_X1024_GET

#define DDRCTL_INIT0_PRE_CKE_X1024_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT0_PRE_CKE_X1024_MASK) >> DDRCTL_INIT0_PRE_CKE_X1024_SHIFT)

◆ DDRCTL_INIT0_PRE_CKE_X1024_MASK

#define DDRCTL_INIT0_PRE_CKE_X1024_MASK (0x3FFU)

◆ DDRCTL_INIT0_PRE_CKE_X1024_SET

#define DDRCTL_INIT0_PRE_CKE_X1024_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT0_PRE_CKE_X1024_SHIFT) & DDRCTL_INIT0_PRE_CKE_X1024_MASK)

◆ DDRCTL_INIT0_PRE_CKE_X1024_SHIFT

#define DDRCTL_INIT0_PRE_CKE_X1024_SHIFT (0U)

◆ DDRCTL_INIT0_SKIP_DRAM_INIT_GET

#define DDRCTL_INIT0_SKIP_DRAM_INIT_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK) >> DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT)

◆ DDRCTL_INIT0_SKIP_DRAM_INIT_MASK

#define DDRCTL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000UL)

◆ DDRCTL_INIT0_SKIP_DRAM_INIT_SET

#define DDRCTL_INIT0_SKIP_DRAM_INIT_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK)

◆ DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT

#define DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT (30U)

◆ DDRCTL_INIT1_DRAM_RSTN_X1024_GET

#define DDRCTL_INIT1_DRAM_RSTN_X1024_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK) >> DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT)

◆ DDRCTL_INIT1_DRAM_RSTN_X1024_MASK

#define DDRCTL_INIT1_DRAM_RSTN_X1024_MASK (0xFF0000UL)

◆ DDRCTL_INIT1_DRAM_RSTN_X1024_SET

#define DDRCTL_INIT1_DRAM_RSTN_X1024_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK)

◆ DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT

#define DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT (16U)

◆ DDRCTL_INIT1_FINAL_WAIT_X32_GET

#define DDRCTL_INIT1_FINAL_WAIT_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK) >> DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT)

◆ DDRCTL_INIT1_FINAL_WAIT_X32_MASK

#define DDRCTL_INIT1_FINAL_WAIT_X32_MASK (0x7F00U)

◆ DDRCTL_INIT1_FINAL_WAIT_X32_SET

#define DDRCTL_INIT1_FINAL_WAIT_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK)

◆ DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT

#define DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT (8U)

◆ DDRCTL_INIT1_PRE_OCD_X32_GET

#define DDRCTL_INIT1_PRE_OCD_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT1_PRE_OCD_X32_MASK) >> DDRCTL_INIT1_PRE_OCD_X32_SHIFT)

◆ DDRCTL_INIT1_PRE_OCD_X32_MASK

#define DDRCTL_INIT1_PRE_OCD_X32_MASK (0xFU)

◆ DDRCTL_INIT1_PRE_OCD_X32_SET

#define DDRCTL_INIT1_PRE_OCD_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT1_PRE_OCD_X32_SHIFT) & DDRCTL_INIT1_PRE_OCD_X32_MASK)

◆ DDRCTL_INIT1_PRE_OCD_X32_SHIFT

#define DDRCTL_INIT1_PRE_OCD_X32_SHIFT (0U)

◆ DDRCTL_INIT3_EMR_GET

#define DDRCTL_INIT3_EMR_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT3_EMR_MASK) >> DDRCTL_INIT3_EMR_SHIFT)

◆ DDRCTL_INIT3_EMR_MASK

#define DDRCTL_INIT3_EMR_MASK (0xFFFFU)

◆ DDRCTL_INIT3_EMR_SET

#define DDRCTL_INIT3_EMR_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT3_EMR_SHIFT) & DDRCTL_INIT3_EMR_MASK)

◆ DDRCTL_INIT3_EMR_SHIFT

#define DDRCTL_INIT3_EMR_SHIFT (0U)

◆ DDRCTL_INIT3_MR_GET

#define DDRCTL_INIT3_MR_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT3_MR_MASK) >> DDRCTL_INIT3_MR_SHIFT)

◆ DDRCTL_INIT3_MR_MASK

#define DDRCTL_INIT3_MR_MASK (0xFFFF0000UL)

◆ DDRCTL_INIT3_MR_SET

#define DDRCTL_INIT3_MR_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT3_MR_SHIFT) & DDRCTL_INIT3_MR_MASK)

◆ DDRCTL_INIT3_MR_SHIFT

#define DDRCTL_INIT3_MR_SHIFT (16U)

◆ DDRCTL_INIT4_EMR2_GET

#define DDRCTL_INIT4_EMR2_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT4_EMR2_MASK) >> DDRCTL_INIT4_EMR2_SHIFT)

◆ DDRCTL_INIT4_EMR2_MASK

#define DDRCTL_INIT4_EMR2_MASK (0xFFFF0000UL)

◆ DDRCTL_INIT4_EMR2_SET

#define DDRCTL_INIT4_EMR2_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT4_EMR2_SHIFT) & DDRCTL_INIT4_EMR2_MASK)

◆ DDRCTL_INIT4_EMR2_SHIFT

#define DDRCTL_INIT4_EMR2_SHIFT (16U)

◆ DDRCTL_INIT4_EMR3_GET

#define DDRCTL_INIT4_EMR3_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT4_EMR3_MASK) >> DDRCTL_INIT4_EMR3_SHIFT)

◆ DDRCTL_INIT4_EMR3_MASK

#define DDRCTL_INIT4_EMR3_MASK (0xFFFFU)

◆ DDRCTL_INIT4_EMR3_SET

#define DDRCTL_INIT4_EMR3_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT4_EMR3_SHIFT) & DDRCTL_INIT4_EMR3_MASK)

◆ DDRCTL_INIT4_EMR3_SHIFT

#define DDRCTL_INIT4_EMR3_SHIFT (0U)

◆ DDRCTL_INIT5_DEV_ZQINIT_X32_GET

#define DDRCTL_INIT5_DEV_ZQINIT_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK) >> DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT)

◆ DDRCTL_INIT5_DEV_ZQINIT_X32_MASK

#define DDRCTL_INIT5_DEV_ZQINIT_X32_MASK (0xFF0000UL)

◆ DDRCTL_INIT5_DEV_ZQINIT_X32_SET

#define DDRCTL_INIT5_DEV_ZQINIT_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK)

◆ DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT

#define DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT (16U)

◆ DDRCTL_MRCTRL0_MR_ADDR_GET

#define DDRCTL_MRCTRL0_MR_ADDR_GET ( x ) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_ADDR_MASK) >> DDRCTL_MRCTRL0_MR_ADDR_SHIFT)

◆ DDRCTL_MRCTRL0_MR_ADDR_MASK

#define DDRCTL_MRCTRL0_MR_ADDR_MASK (0xF000U)

◆ DDRCTL_MRCTRL0_MR_ADDR_SET

#define DDRCTL_MRCTRL0_MR_ADDR_SET ( x ) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_ADDR_SHIFT) & DDRCTL_MRCTRL0_MR_ADDR_MASK)

◆ DDRCTL_MRCTRL0_MR_ADDR_SHIFT

#define DDRCTL_MRCTRL0_MR_ADDR_SHIFT (12U)

◆ DDRCTL_MRCTRL0_MR_RANK_GET

#define DDRCTL_MRCTRL0_MR_RANK_GET ( x ) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_RANK_MASK) >> DDRCTL_MRCTRL0_MR_RANK_SHIFT)

◆ DDRCTL_MRCTRL0_MR_RANK_MASK

#define DDRCTL_MRCTRL0_MR_RANK_MASK (0xF0U)

◆ DDRCTL_MRCTRL0_MR_RANK_SET

#define DDRCTL_MRCTRL0_MR_RANK_SET ( x ) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_RANK_SHIFT) & DDRCTL_MRCTRL0_MR_RANK_MASK)

◆ DDRCTL_MRCTRL0_MR_RANK_SHIFT

#define DDRCTL_MRCTRL0_MR_RANK_SHIFT (4U)

◆ DDRCTL_MRCTRL0_MR_WR_GET

#define DDRCTL_MRCTRL0_MR_WR_GET ( x ) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_WR_MASK) >> DDRCTL_MRCTRL0_MR_WR_SHIFT)

◆ DDRCTL_MRCTRL0_MR_WR_MASK

#define DDRCTL_MRCTRL0_MR_WR_MASK (0x80000000UL)

◆ DDRCTL_MRCTRL0_MR_WR_SET

#define DDRCTL_MRCTRL0_MR_WR_SET ( x ) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_WR_SHIFT) & DDRCTL_MRCTRL0_MR_WR_MASK)

◆ DDRCTL_MRCTRL0_MR_WR_SHIFT

#define DDRCTL_MRCTRL0_MR_WR_SHIFT (31U)

◆ DDRCTL_MRCTRL1_MR_DATA_GET

#define DDRCTL_MRCTRL1_MR_DATA_GET ( x ) (((uint32_t)(x) & DDRCTL_MRCTRL1_MR_DATA_MASK) >> DDRCTL_MRCTRL1_MR_DATA_SHIFT)

◆ DDRCTL_MRCTRL1_MR_DATA_MASK

#define DDRCTL_MRCTRL1_MR_DATA_MASK (0x3FFFFUL)

◆ DDRCTL_MRCTRL1_MR_DATA_SET

#define DDRCTL_MRCTRL1_MR_DATA_SET ( x ) (((uint32_t)(x) << DDRCTL_MRCTRL1_MR_DATA_SHIFT) & DDRCTL_MRCTRL1_MR_DATA_MASK)

◆ DDRCTL_MRCTRL1_MR_DATA_SHIFT

#define DDRCTL_MRCTRL1_MR_DATA_SHIFT (0U)

◆ DDRCTL_MRSTAT_MR_WR_BUSY_GET

#define DDRCTL_MRSTAT_MR_WR_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_MRSTAT_MR_WR_BUSY_MASK) >> DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT)

◆ DDRCTL_MRSTAT_MR_WR_BUSY_MASK

#define DDRCTL_MRSTAT_MR_WR_BUSY_MASK (0x1U)

◆ DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT

#define DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT (0U)

◆ DDRCTL_MSTR_ACTIVE_RANKS_GET

#define DDRCTL_MSTR_ACTIVE_RANKS_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_ACTIVE_RANKS_MASK) >> DDRCTL_MSTR_ACTIVE_RANKS_SHIFT)

◆ DDRCTL_MSTR_ACTIVE_RANKS_MASK

#define DDRCTL_MSTR_ACTIVE_RANKS_MASK (0xF000000UL)

◆ DDRCTL_MSTR_ACTIVE_RANKS_SET

#define DDRCTL_MSTR_ACTIVE_RANKS_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_ACTIVE_RANKS_SHIFT) & DDRCTL_MSTR_ACTIVE_RANKS_MASK)

◆ DDRCTL_MSTR_ACTIVE_RANKS_SHIFT

#define DDRCTL_MSTR_ACTIVE_RANKS_SHIFT (24U)

◆ DDRCTL_MSTR_BURST_RDWR_GET

#define DDRCTL_MSTR_BURST_RDWR_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_BURST_RDWR_MASK) >> DDRCTL_MSTR_BURST_RDWR_SHIFT)

◆ DDRCTL_MSTR_BURST_RDWR_MASK

#define DDRCTL_MSTR_BURST_RDWR_MASK (0xF0000UL)

◆ DDRCTL_MSTR_BURST_RDWR_SET

#define DDRCTL_MSTR_BURST_RDWR_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_BURST_RDWR_SHIFT) & DDRCTL_MSTR_BURST_RDWR_MASK)

◆ DDRCTL_MSTR_BURST_RDWR_SHIFT

#define DDRCTL_MSTR_BURST_RDWR_SHIFT (16U)

◆ DDRCTL_MSTR_BURSTCHOP_GET

#define DDRCTL_MSTR_BURSTCHOP_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_BURSTCHOP_MASK) >> DDRCTL_MSTR_BURSTCHOP_SHIFT)

◆ DDRCTL_MSTR_BURSTCHOP_MASK

#define DDRCTL_MSTR_BURSTCHOP_MASK (0x200U)

◆ DDRCTL_MSTR_BURSTCHOP_SET

#define DDRCTL_MSTR_BURSTCHOP_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_BURSTCHOP_SHIFT) & DDRCTL_MSTR_BURSTCHOP_MASK)

◆ DDRCTL_MSTR_BURSTCHOP_SHIFT

#define DDRCTL_MSTR_BURSTCHOP_SHIFT (9U)

◆ DDRCTL_MSTR_DATA_BUS_WIDTH_GET

#define DDRCTL_MSTR_DATA_BUS_WIDTH_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK) >> DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT)

◆ DDRCTL_MSTR_DATA_BUS_WIDTH_MASK

#define DDRCTL_MSTR_DATA_BUS_WIDTH_MASK (0x3000U)

◆ DDRCTL_MSTR_DATA_BUS_WIDTH_SET

#define DDRCTL_MSTR_DATA_BUS_WIDTH_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK)

◆ DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT

#define DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT (12U)

◆ DDRCTL_MSTR_DDR3_GET

#define DDRCTL_MSTR_DDR3_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_DDR3_MASK) >> DDRCTL_MSTR_DDR3_SHIFT)

◆ DDRCTL_MSTR_DDR3_MASK

#define DDRCTL_MSTR_DDR3_MASK (0x1U)

◆ DDRCTL_MSTR_DDR3_SET

#define DDRCTL_MSTR_DDR3_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_DDR3_SHIFT) & DDRCTL_MSTR_DDR3_MASK)

◆ DDRCTL_MSTR_DDR3_SHIFT

#define DDRCTL_MSTR_DDR3_SHIFT (0U)

◆ DDRCTL_MSTR_DLL_OFF_MODE_GET

#define DDRCTL_MSTR_DLL_OFF_MODE_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_DLL_OFF_MODE_MASK) >> DDRCTL_MSTR_DLL_OFF_MODE_SHIFT)

◆ DDRCTL_MSTR_DLL_OFF_MODE_MASK

#define DDRCTL_MSTR_DLL_OFF_MODE_MASK (0x8000U)

◆ DDRCTL_MSTR_DLL_OFF_MODE_SET

#define DDRCTL_MSTR_DLL_OFF_MODE_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_DLL_OFF_MODE_SHIFT) & DDRCTL_MSTR_DLL_OFF_MODE_MASK)

◆ DDRCTL_MSTR_DLL_OFF_MODE_SHIFT

#define DDRCTL_MSTR_DLL_OFF_MODE_SHIFT (15U)

◆ DDRCTL_MSTR_EN_2T_TIMING_MODE_GET

#define DDRCTL_MSTR_EN_2T_TIMING_MODE_GET ( x ) (((uint32_t)(x) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK) >> DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT)

◆ DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK

#define DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK (0x400U)

◆ DDRCTL_MSTR_EN_2T_TIMING_MODE_SET

#define DDRCTL_MSTR_EN_2T_TIMING_MODE_SET ( x ) (((uint32_t)(x) << DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK)

◆ DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT

#define DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT (10U)

◆ DDRCTL_ODTCFG_RD_ODT_DELAY_GET

#define DDRCTL_ODTCFG_RD_ODT_DELAY_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT)

◆ DDRCTL_ODTCFG_RD_ODT_DELAY_MASK

#define DDRCTL_ODTCFG_RD_ODT_DELAY_MASK (0x7CU)

◆ DDRCTL_ODTCFG_RD_ODT_DELAY_SET

#define DDRCTL_ODTCFG_RD_ODT_DELAY_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK)

◆ DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT

#define DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT (2U)

◆ DDRCTL_ODTCFG_RD_ODT_HOLD_GET

#define DDRCTL_ODTCFG_RD_ODT_HOLD_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT)

◆ DDRCTL_ODTCFG_RD_ODT_HOLD_MASK

#define DDRCTL_ODTCFG_RD_ODT_HOLD_MASK (0xF00U)

◆ DDRCTL_ODTCFG_RD_ODT_HOLD_SET

#define DDRCTL_ODTCFG_RD_ODT_HOLD_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK)

◆ DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT

#define DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT (8U)

◆ DDRCTL_ODTCFG_WR_ODT_DELAY_GET

#define DDRCTL_ODTCFG_WR_ODT_DELAY_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT)

◆ DDRCTL_ODTCFG_WR_ODT_DELAY_MASK

#define DDRCTL_ODTCFG_WR_ODT_DELAY_MASK (0x1F0000UL)

◆ DDRCTL_ODTCFG_WR_ODT_DELAY_SET

#define DDRCTL_ODTCFG_WR_ODT_DELAY_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK)

◆ DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT

#define DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT (16U)

◆ DDRCTL_ODTCFG_WR_ODT_HOLD_GET

#define DDRCTL_ODTCFG_WR_ODT_HOLD_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT)

◆ DDRCTL_ODTCFG_WR_ODT_HOLD_MASK

#define DDRCTL_ODTCFG_WR_ODT_HOLD_MASK (0xF000000UL)

◆ DDRCTL_ODTCFG_WR_ODT_HOLD_SET

#define DDRCTL_ODTCFG_WR_ODT_HOLD_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK)

◆ DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT

#define DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT (24U)

◆ DDRCTL_ODTMAP_RANK0_RD_ODT_GET

#define DDRCTL_ODTMAP_RANK0_RD_ODT_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT)

◆ DDRCTL_ODTMAP_RANK0_RD_ODT_MASK

#define DDRCTL_ODTMAP_RANK0_RD_ODT_MASK (0xF0U)

◆ DDRCTL_ODTMAP_RANK0_RD_ODT_SET

#define DDRCTL_ODTMAP_RANK0_RD_ODT_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK)

◆ DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT

#define DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT (4U)

◆ DDRCTL_ODTMAP_RANK0_WR_ODT_GET

#define DDRCTL_ODTMAP_RANK0_WR_ODT_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT)

◆ DDRCTL_ODTMAP_RANK0_WR_ODT_MASK

#define DDRCTL_ODTMAP_RANK0_WR_ODT_MASK (0xFU)

◆ DDRCTL_ODTMAP_RANK0_WR_ODT_SET

#define DDRCTL_ODTMAP_RANK0_WR_ODT_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK)

◆ DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT

#define DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT (0U)

◆ DDRCTL_ODTMAP_RANK1_RD_ODT_GET

#define DDRCTL_ODTMAP_RANK1_RD_ODT_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT)

◆ DDRCTL_ODTMAP_RANK1_RD_ODT_MASK

#define DDRCTL_ODTMAP_RANK1_RD_ODT_MASK (0xF000U)

◆ DDRCTL_ODTMAP_RANK1_RD_ODT_SET

#define DDRCTL_ODTMAP_RANK1_RD_ODT_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK)

◆ DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT

#define DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT (12U)

◆ DDRCTL_ODTMAP_RANK1_WR_ODT_GET

#define DDRCTL_ODTMAP_RANK1_WR_ODT_GET ( x ) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT)

◆ DDRCTL_ODTMAP_RANK1_WR_ODT_MASK

#define DDRCTL_ODTMAP_RANK1_WR_ODT_MASK (0xF00U)

◆ DDRCTL_ODTMAP_RANK1_WR_ODT_SET

#define DDRCTL_ODTMAP_RANK1_WR_ODT_SET ( x ) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK)

◆ DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT

#define DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT (8U)

◆ DDRCTL_PCCFG_GO2CRITICAL_EN_GET

#define DDRCTL_PCCFG_GO2CRITICAL_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK) >> DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT)

◆ DDRCTL_PCCFG_GO2CRITICAL_EN_MASK

#define DDRCTL_PCCFG_GO2CRITICAL_EN_MASK (0x1U)

◆ DDRCTL_PCCFG_GO2CRITICAL_EN_SET

#define DDRCTL_PCCFG_GO2CRITICAL_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK)

◆ DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT

#define DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT (0U)

◆ DDRCTL_PCCFG_PAGEMATCH_LIMIT_GET

#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_GET ( x ) (((uint32_t)(x) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK) >> DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT)

◆ DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK

#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK (0x10U)

◆ DDRCTL_PCCFG_PAGEMATCH_LIMIT_SET

#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_SET ( x ) (((uint32_t)(x) << DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK)

◆ DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT

#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT (4U)

◆ DDRCTL_PCFG_0

#define DDRCTL_PCFG_0 (0UL)

◆ DDRCTL_PCFG_1

#define DDRCTL_PCFG_1 (1UL)

◆ DDRCTL_PCFG_10

#define DDRCTL_PCFG_10 (10UL)

◆ DDRCTL_PCFG_11

#define DDRCTL_PCFG_11 (11UL)

◆ DDRCTL_PCFG_12

#define DDRCTL_PCFG_12 (12UL)

◆ DDRCTL_PCFG_13

#define DDRCTL_PCFG_13 (13UL)

◆ DDRCTL_PCFG_14

#define DDRCTL_PCFG_14 (14UL)

◆ DDRCTL_PCFG_15

#define DDRCTL_PCFG_15 (15UL)

◆ DDRCTL_PCFG_2

#define DDRCTL_PCFG_2 (2UL)

◆ DDRCTL_PCFG_3

#define DDRCTL_PCFG_3 (3UL)

◆ DDRCTL_PCFG_4

#define DDRCTL_PCFG_4 (4UL)

◆ DDRCTL_PCFG_5

#define DDRCTL_PCFG_5 (5UL)

◆ DDRCTL_PCFG_6

#define DDRCTL_PCFG_6 (6UL)

◆ DDRCTL_PCFG_7

#define DDRCTL_PCFG_7 (7UL)

◆ DDRCTL_PCFG_8

#define DDRCTL_PCFG_8 (8UL)

◆ DDRCTL_PCFG_9

#define DDRCTL_PCFG_9 (9UL)

◆ DDRCTL_PCFG_C_AHB_ENDIANNESS_GET

#define DDRCTL_PCFG_C_AHB_ENDIANNESS_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK) >> DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT)

◆ DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK

#define DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK (0x3U)

◆ DDRCTL_PCFG_C_AHB_ENDIANNESS_SET

#define DDRCTL_PCFG_C_AHB_ENDIANNESS_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK)

◆ DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT

#define DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT (0U)

◆ DDRCTL_PCFG_CTRL_PORT_EN_GET

#define DDRCTL_PCFG_CTRL_PORT_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_CTRL_PORT_EN_MASK) >> DDRCTL_PCFG_CTRL_PORT_EN_SHIFT)

◆ DDRCTL_PCFG_CTRL_PORT_EN_MASK

#define DDRCTL_PCFG_CTRL_PORT_EN_MASK (0x1U)

◆ DDRCTL_PCFG_CTRL_PORT_EN_SET

#define DDRCTL_PCFG_CTRL_PORT_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_CTRL_PORT_EN_SHIFT) & DDRCTL_PCFG_CTRL_PORT_EN_MASK)

◆ DDRCTL_PCFG_CTRL_PORT_EN_SHIFT

#define DDRCTL_PCFG_CTRL_PORT_EN_SHIFT (0U)

◆ DDRCTL_PCFG_ID_MASKCH_ID_MASK_GET

#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK) >> DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT)

◆ DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK

#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK (0xFFFFFFFFUL)

◆ DDRCTL_PCFG_ID_MASKCH_ID_MASK_SET

#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK)

◆ DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT

#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT (0U)

◆ DDRCTL_PCFG_ID_VALUECH_ID_VALUE_GET

#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK) >> DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT)

◆ DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK

#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK (0xFFFFFFFFUL)

◆ DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SET

#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK)

◆ DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT

#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT (0U)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_GET

#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK

#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK (0xFU)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SET

#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT

#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT (0U)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_GET

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK (0x30000UL)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SET

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT (16U)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_GET

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK (0x300000UL)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SET

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK)

◆ DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT

#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT (20U)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_GET

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK (0x7FFU)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SET

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT (0U)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_GET

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK (0x7FF0000UL)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SET

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK)

◆ DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT

#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT (16U)

◆ DDRCTL_PCFG_R_RD_PORT_AGING_EN_GET

#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT)

◆ DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK

#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK (0x1000U)

◆ DDRCTL_PCFG_R_RD_PORT_AGING_EN_SET

#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK)

◆ DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT

#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT (12U)

◆ DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_GET

#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT)

◆ DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK

#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK (0x4000U)

◆ DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SET

#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK)

◆ DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT

#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT (14U)

◆ DDRCTL_PCFG_R_RD_PORT_PRIORITY_GET

#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT)

◆ DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK

#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK (0x3FFU)

◆ DDRCTL_PCFG_R_RD_PORT_PRIORITY_SET

#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK)

◆ DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT

#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT (0U)

◆ DDRCTL_PCFG_R_RD_PORT_URGENT_EN_GET

#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT)

◆ DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK

#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK (0x2000U)

◆ DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SET

#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK)

◆ DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT

#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT (13U)

◆ DDRCTL_PCFG_W_WR_PORT_AGING_EN_GET

#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT)

◆ DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK

#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK (0x1000U)

◆ DDRCTL_PCFG_W_WR_PORT_AGING_EN_SET

#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK)

◆ DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT

#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT (12U)

◆ DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_GET

#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT)

◆ DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK

#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK (0x4000U)

◆ DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SET

#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK)

◆ DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT

#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT (14U)

◆ DDRCTL_PCFG_W_WR_PORT_PRIORITY_GET

#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT)

◆ DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK

#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK (0x3FFU)

◆ DDRCTL_PCFG_W_WR_PORT_PRIORITY_SET

#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK)

◆ DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT

#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT (0U)

◆ DDRCTL_PCFG_W_WR_PORT_URGENT_EN_GET

#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT)

◆ DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK

#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK (0x2000U)

◆ DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SET

#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK)

◆ DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT

#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT (13U)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_GET

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK (0xFU)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SET

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT (0U)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_GET

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK (0x30000UL)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SET

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT (16U)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_GET

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK (0x300000UL)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SET

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK)

◆ DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT

#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT (20U)

◆ DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_GET

#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_GET ( x ) (((uint32_t)(x) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK) >> DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT)

◆ DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK

#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK (0x7FFU)

◆ DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SET

#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SET ( x ) (((uint32_t)(x) << DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK)

◆ DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT

#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT (0U)

◆ DDRCTL_PERFHPR1_HPR_MAX_STARVE_GET

#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK) >> DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT)

◆ DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK

#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK (0xFFFFU)

◆ DDRCTL_PERFHPR1_HPR_MAX_STARVE_SET

#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK)

◆ DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT

#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT (0U)

◆ DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_GET

#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT)

◆ DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK

#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK (0xFF000000UL)

◆ DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SET

#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK)

◆ DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT

#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT (24U)

◆ DDRCTL_PERFLPR1_LPR_MAX_STARVE_GET

#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK) >> DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT)

◆ DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK

#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK (0xFFFFU)

◆ DDRCTL_PERFLPR1_LPR_MAX_STARVE_SET

#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK)

◆ DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT

#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT (0U)

◆ DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_GET

#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT)

◆ DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK

#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK (0xFF000000UL)

◆ DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SET

#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK)

◆ DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT

#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT (24U)

◆ DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_GET

#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT)

◆ DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK

#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK (0x7FFU)

◆ DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SET

#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK)

◆ DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT

#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT (0U)

◆ DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_GET

#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT)

◆ DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK

#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK (0x7FFU)

◆ DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SET

#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK)

◆ DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT

#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT (0U)

◆ DDRCTL_PERFWR1_W_MAX_STARVE_GET

#define DDRCTL_PERFWR1_W_MAX_STARVE_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK) >> DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT)

◆ DDRCTL_PERFWR1_W_MAX_STARVE_MASK

#define DDRCTL_PERFWR1_W_MAX_STARVE_MASK (0xFFFFU)

◆ DDRCTL_PERFWR1_W_MAX_STARVE_SET

#define DDRCTL_PERFWR1_W_MAX_STARVE_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK)

◆ DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT

#define DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT (0U)

◆ DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_GET

#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_GET ( x ) (((uint32_t)(x) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT)

◆ DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK

#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK (0xFF000000UL)

◆ DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SET

#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SET ( x ) (((uint32_t)(x) << DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK)

◆ DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT

#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT (24U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_0_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_0_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK (0x1U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT (0U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_10_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_10_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK (0x400U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT (10U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_11_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_11_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK (0x800U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT (11U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_12_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_12_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK (0x1000U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT (12U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_13_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_13_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK (0x2000U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT (13U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_14_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_14_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK (0x4000U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT (14U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_15_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_15_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK (0x8000U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT (15U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_1_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_1_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK (0x2U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT (1U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_2_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_2_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK (0x4U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT (2U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_3_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_3_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK (0x8U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT (3U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_4_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_4_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK (0x10U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT (4U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_5_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_5_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK (0x20U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT (5U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_6_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_6_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK (0x40U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT (6U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_7_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_7_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK (0x80U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT (7U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_8_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_8_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK (0x100U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT (8U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_9_GET

#define DDRCTL_PSTAT_RD_PORT_BUSY_9_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK

#define DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK (0x200U)

◆ DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT

#define DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT (9U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_0_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_0_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK (0x10000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT (16U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_10_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_10_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK (0x4000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT (26U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_11_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_11_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK (0x8000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT (27U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_12_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_12_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK (0x10000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT (28U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_13_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_13_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK (0x20000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT (29U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_14_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_14_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK (0x40000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT (30U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_15_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_15_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK (0x80000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT (31U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_1_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_1_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK (0x20000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT (17U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_2_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_2_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK (0x40000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT (18U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_3_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_3_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK (0x80000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT (19U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_4_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_4_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK (0x100000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT (20U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_5_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_5_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK (0x200000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT (21U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_6_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_6_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK (0x400000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT (22U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_7_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_7_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK (0x800000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT (23U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_8_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_8_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK (0x1000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT (24U)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_9_GET

#define DDRCTL_PSTAT_WR_PORT_BUSY_9_GET ( x ) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK

#define DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK (0x2000000UL)

◆ DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT

#define DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT (25U)

◆ DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_GET

#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_GET ( x ) (((uint32_t)(x) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK) >> DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT)

◆ DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK

#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK (0x8U)

◆ DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SET

#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SET ( x ) (((uint32_t)(x) << DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK)

◆ DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT

#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT (3U)

◆ DDRCTL_PWRCTL_POWERDOWN_EN_GET

#define DDRCTL_PWRCTL_POWERDOWN_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK) >> DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT)

◆ DDRCTL_PWRCTL_POWERDOWN_EN_MASK

#define DDRCTL_PWRCTL_POWERDOWN_EN_MASK (0x2U)

◆ DDRCTL_PWRCTL_POWERDOWN_EN_SET

#define DDRCTL_PWRCTL_POWERDOWN_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK)

◆ DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT

#define DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT (1U)

◆ DDRCTL_PWRCTL_SELFREF_EN_GET

#define DDRCTL_PWRCTL_SELFREF_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_EN_MASK) >> DDRCTL_PWRCTL_SELFREF_EN_SHIFT)

◆ DDRCTL_PWRCTL_SELFREF_EN_MASK

#define DDRCTL_PWRCTL_SELFREF_EN_MASK (0x1U)

◆ DDRCTL_PWRCTL_SELFREF_EN_SET

#define DDRCTL_PWRCTL_SELFREF_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_EN_SHIFT) & DDRCTL_PWRCTL_SELFREF_EN_MASK)

◆ DDRCTL_PWRCTL_SELFREF_EN_SHIFT

#define DDRCTL_PWRCTL_SELFREF_EN_SHIFT (0U)

◆ DDRCTL_PWRCTL_SELFREF_SW_GET

#define DDRCTL_PWRCTL_SELFREF_SW_GET ( x ) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_SW_MASK) >> DDRCTL_PWRCTL_SELFREF_SW_SHIFT)

◆ DDRCTL_PWRCTL_SELFREF_SW_MASK

#define DDRCTL_PWRCTL_SELFREF_SW_MASK (0x20U)

◆ DDRCTL_PWRCTL_SELFREF_SW_SET

#define DDRCTL_PWRCTL_SELFREF_SW_SET ( x ) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_SW_SHIFT) & DDRCTL_PWRCTL_SELFREF_SW_MASK)

◆ DDRCTL_PWRCTL_SELFREF_SW_SHIFT

#define DDRCTL_PWRCTL_SELFREF_SW_SHIFT (5U)

◆ DDRCTL_PWRTMG_POWERDOWN_TO_X32_GET

#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK) >> DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT)

◆ DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK

#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK (0x1FU)

◆ DDRCTL_PWRTMG_POWERDOWN_TO_X32_SET

#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK)

◆ DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT

#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT (0U)

◆ DDRCTL_PWRTMG_SELFREF_TO_X32_GET

#define DDRCTL_PWRTMG_SELFREF_TO_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK) >> DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT)

◆ DDRCTL_PWRTMG_SELFREF_TO_X32_MASK

#define DDRCTL_PWRTMG_SELFREF_TO_X32_MASK (0xFF0000UL)

◆ DDRCTL_PWRTMG_SELFREF_TO_X32_SET

#define DDRCTL_PWRTMG_SELFREF_TO_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK)

◆ DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT

#define DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT (16U)

◆ DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_GET

#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_GET ( x ) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT)

◆ DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK

#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK (0xF0U)

◆ DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SET

#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SET ( x ) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK)

◆ DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT

#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT (4U)

◆ DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_GET

#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_GET ( x ) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT)

◆ DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK

#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK (0xF00U)

◆ DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SET

#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SET ( x ) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK)

◆ DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT

#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT (8U)

◆ DDRCTL_RANKCTL_MAX_RANK_RD_GET

#define DDRCTL_RANKCTL_MAX_RANK_RD_GET ( x ) (((uint32_t)(x) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK) >> DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT)

◆ DDRCTL_RANKCTL_MAX_RANK_RD_MASK

#define DDRCTL_RANKCTL_MAX_RANK_RD_MASK (0xFU)

◆ DDRCTL_RANKCTL_MAX_RANK_RD_SET

#define DDRCTL_RANKCTL_MAX_RANK_RD_SET ( x ) (((uint32_t)(x) << DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK)

◆ DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT

#define DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT (0U)

◆ DDRCTL_RFSHCTL0_REFRESH_BURST_GET

#define DDRCTL_RFSHCTL0_REFRESH_BURST_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK) >> DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT)

◆ DDRCTL_RFSHCTL0_REFRESH_BURST_MASK

#define DDRCTL_RFSHCTL0_REFRESH_BURST_MASK (0x1F0U)

◆ DDRCTL_RFSHCTL0_REFRESH_BURST_SET

#define DDRCTL_RFSHCTL0_REFRESH_BURST_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK)

◆ DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT

#define DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT (4U)

◆ DDRCTL_RFSHCTL0_REFRESH_MARGIN_GET

#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK) >> DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT)

◆ DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK

#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK (0xF00000UL)

◆ DDRCTL_RFSHCTL0_REFRESH_MARGIN_SET

#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK)

◆ DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT

#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT (20U)

◆ DDRCTL_RFSHCTL0_REFRESH_TO_X32_GET

#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK) >> DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT)

◆ DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK

#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK (0x1F000UL)

◆ DDRCTL_RFSHCTL0_REFRESH_TO_X32_SET

#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK)

◆ DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT

#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT (12U)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_GET

#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK

#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK (0xFFFU)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SET

#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT

#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT (0U)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_GET

#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK

#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK (0xFFF0000UL)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SET

#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK)

◆ DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT

#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT (16U)

◆ DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_GET

#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK) >> DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT)

◆ DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK

#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK (0x1U)

◆ DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SET

#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK)

◆ DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT

#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT (0U)

◆ DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_GET

#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK) >> DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT)

◆ DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK

#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK (0x2U)

◆ DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SET

#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK)

◆ DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT

#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT (1U)

◆ DDRCTL_RFSHTMG_T_RFC_MIN_GET

#define DDRCTL_RFSHTMG_T_RFC_MIN_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK) >> DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT)

◆ DDRCTL_RFSHTMG_T_RFC_MIN_MASK

#define DDRCTL_RFSHTMG_T_RFC_MIN_MASK (0x1FFU)

◆ DDRCTL_RFSHTMG_T_RFC_MIN_SET

#define DDRCTL_RFSHTMG_T_RFC_MIN_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK)

◆ DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT

#define DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT (0U)

◆ DDRCTL_RFSHTMG_T_RFC_NOM_X32_GET

#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_GET ( x ) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK) >> DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT)

◆ DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK

#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK (0xFFF0000UL)

◆ DDRCTL_RFSHTMG_T_RFC_NOM_X32_SET

#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_SET ( x ) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK)

◆ DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT

#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT (16U)

◆ DDRCTL_SAR_0

#define DDRCTL_SAR_0 (0UL)

◆ DDRCTL_SAR_1

#define DDRCTL_SAR_1 (1UL)

◆ DDRCTL_SAR_2

#define DDRCTL_SAR_2 (2UL)

◆ DDRCTL_SAR_3

#define DDRCTL_SAR_3 (3UL)

◆ DDRCTL_SAR_BASE_BASE_ADDR_GET

#define DDRCTL_SAR_BASE_BASE_ADDR_GET ( x ) (((uint32_t)(x) & DDRCTL_SAR_BASE_BASE_ADDR_MASK) >> DDRCTL_SAR_BASE_BASE_ADDR_SHIFT)

◆ DDRCTL_SAR_BASE_BASE_ADDR_MASK

#define DDRCTL_SAR_BASE_BASE_ADDR_MASK (0xFFFFFFFFUL)

◆ DDRCTL_SAR_BASE_BASE_ADDR_SET

#define DDRCTL_SAR_BASE_BASE_ADDR_SET ( x ) (((uint32_t)(x) << DDRCTL_SAR_BASE_BASE_ADDR_SHIFT) & DDRCTL_SAR_BASE_BASE_ADDR_MASK)

◆ DDRCTL_SAR_BASE_BASE_ADDR_SHIFT

#define DDRCTL_SAR_BASE_BASE_ADDR_SHIFT (0U)

◆ DDRCTL_SAR_SIZE_NBLOCKS_GET

#define DDRCTL_SAR_SIZE_NBLOCKS_GET ( x ) (((uint32_t)(x) & DDRCTL_SAR_SIZE_NBLOCKS_MASK) >> DDRCTL_SAR_SIZE_NBLOCKS_SHIFT)

◆ DDRCTL_SAR_SIZE_NBLOCKS_MASK

#define DDRCTL_SAR_SIZE_NBLOCKS_MASK (0xFFU)

◆ DDRCTL_SAR_SIZE_NBLOCKS_SET

#define DDRCTL_SAR_SIZE_NBLOCKS_SET ( x ) (((uint32_t)(x) << DDRCTL_SAR_SIZE_NBLOCKS_SHIFT) & DDRCTL_SAR_SIZE_NBLOCKS_MASK)

◆ DDRCTL_SAR_SIZE_NBLOCKS_SHIFT

#define DDRCTL_SAR_SIZE_NBLOCKS_SHIFT (0U)

◆ DDRCTL_SBRCTL_SCRUB_BURST_GET

#define DDRCTL_SBRCTL_SCRUB_BURST_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_BURST_MASK) >> DDRCTL_SBRCTL_SCRUB_BURST_SHIFT)

◆ DDRCTL_SBRCTL_SCRUB_BURST_MASK

#define DDRCTL_SBRCTL_SCRUB_BURST_MASK (0x70U)

◆ DDRCTL_SBRCTL_SCRUB_BURST_SET

#define DDRCTL_SBRCTL_SCRUB_BURST_SET ( x ) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_BURST_SHIFT) & DDRCTL_SBRCTL_SCRUB_BURST_MASK)

◆ DDRCTL_SBRCTL_SCRUB_BURST_SHIFT

#define DDRCTL_SBRCTL_SCRUB_BURST_SHIFT (4U)

◆ DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_GET

#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK) >> DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT)

◆ DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK

#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK (0x2U)

◆ DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SET

#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SET ( x ) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK)

◆ DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT

#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT (1U)

◆ DDRCTL_SBRCTL_SCRUB_EN_GET

#define DDRCTL_SBRCTL_SCRUB_EN_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_EN_MASK) >> DDRCTL_SBRCTL_SCRUB_EN_SHIFT)

◆ DDRCTL_SBRCTL_SCRUB_EN_MASK

#define DDRCTL_SBRCTL_SCRUB_EN_MASK (0x1U)

◆ DDRCTL_SBRCTL_SCRUB_EN_SET

#define DDRCTL_SBRCTL_SCRUB_EN_SET ( x ) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_EN_SHIFT) & DDRCTL_SBRCTL_SCRUB_EN_MASK)

◆ DDRCTL_SBRCTL_SCRUB_EN_SHIFT

#define DDRCTL_SBRCTL_SCRUB_EN_SHIFT (0U)

◆ DDRCTL_SBRCTL_SCRUB_INTERVAL_GET

#define DDRCTL_SBRCTL_SCRUB_INTERVAL_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK) >> DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT)

◆ DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK

#define DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK (0x1FFF00UL)

◆ DDRCTL_SBRCTL_SCRUB_INTERVAL_SET

#define DDRCTL_SBRCTL_SCRUB_INTERVAL_SET ( x ) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK)

◆ DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT

#define DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT (8U)

◆ DDRCTL_SBRCTL_SCRUB_MODE_GET

#define DDRCTL_SBRCTL_SCRUB_MODE_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_MODE_MASK) >> DDRCTL_SBRCTL_SCRUB_MODE_SHIFT)

◆ DDRCTL_SBRCTL_SCRUB_MODE_MASK

#define DDRCTL_SBRCTL_SCRUB_MODE_MASK (0x4U)

◆ DDRCTL_SBRCTL_SCRUB_MODE_SET

#define DDRCTL_SBRCTL_SCRUB_MODE_SET ( x ) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_MODE_SHIFT) & DDRCTL_SBRCTL_SCRUB_MODE_MASK)

◆ DDRCTL_SBRCTL_SCRUB_MODE_SHIFT

#define DDRCTL_SBRCTL_SCRUB_MODE_SHIFT (2U)

◆ DDRCTL_SBRSTAT_SCRUB_BUSY_GET

#define DDRCTL_SBRSTAT_SCRUB_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_BUSY_MASK) >> DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT)

◆ DDRCTL_SBRSTAT_SCRUB_BUSY_MASK

#define DDRCTL_SBRSTAT_SCRUB_BUSY_MASK (0x1U)

◆ DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT

#define DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT (0U)

◆ DDRCTL_SBRSTAT_SCRUB_DONE_GET

#define DDRCTL_SBRSTAT_SCRUB_DONE_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_DONE_MASK) >> DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT)

◆ DDRCTL_SBRSTAT_SCRUB_DONE_MASK

#define DDRCTL_SBRSTAT_SCRUB_DONE_MASK (0x2U)

◆ DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT

#define DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT (1U)

◆ DDRCTL_SBRWDATA0_SCRUB_PATTERN0_GET

#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_GET ( x ) (((uint32_t)(x) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK) >> DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT)

◆ DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK

#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK (0xFFFFFFFFUL)

◆ DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SET

#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SET ( x ) (((uint32_t)(x) << DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK)

◆ DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT

#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT (0U)

◆ DDRCTL_SCHED1_PAGECLOSE_TIMER_GET

#define DDRCTL_SCHED1_PAGECLOSE_TIMER_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK) >> DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT)

◆ DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK

#define DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK (0xFFU)

◆ DDRCTL_SCHED1_PAGECLOSE_TIMER_SET

#define DDRCTL_SCHED1_PAGECLOSE_TIMER_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK)

◆ DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT

#define DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT (0U)

◆ DDRCTL_SCHED_FORCE_LOW_PRI_N_GET

#define DDRCTL_SCHED_FORCE_LOW_PRI_N_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK) >> DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT)

◆ DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK

#define DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK (0x1U)

◆ DDRCTL_SCHED_FORCE_LOW_PRI_N_SET

#define DDRCTL_SCHED_FORCE_LOW_PRI_N_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK)

◆ DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT

#define DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT (0U)

◆ DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_GET

#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK) >> DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT)

◆ DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK

#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK (0xFF0000UL)

◆ DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SET

#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK)

◆ DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT

#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT (16U)

◆ DDRCTL_SCHED_LPR_NUM_ENTRIES_GET

#define DDRCTL_SCHED_LPR_NUM_ENTRIES_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK) >> DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT)

◆ DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK

#define DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK (0x3F00U)

◆ DDRCTL_SCHED_LPR_NUM_ENTRIES_SET

#define DDRCTL_SCHED_LPR_NUM_ENTRIES_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK)

◆ DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT

#define DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT (8U)

◆ DDRCTL_SCHED_PAGECLOSE_GET

#define DDRCTL_SCHED_PAGECLOSE_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED_PAGECLOSE_MASK) >> DDRCTL_SCHED_PAGECLOSE_SHIFT)

◆ DDRCTL_SCHED_PAGECLOSE_MASK

#define DDRCTL_SCHED_PAGECLOSE_MASK (0x4U)

◆ DDRCTL_SCHED_PAGECLOSE_SET

#define DDRCTL_SCHED_PAGECLOSE_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED_PAGECLOSE_SHIFT) & DDRCTL_SCHED_PAGECLOSE_MASK)

◆ DDRCTL_SCHED_PAGECLOSE_SHIFT

#define DDRCTL_SCHED_PAGECLOSE_SHIFT (2U)

◆ DDRCTL_SCHED_PREFER_WRITE_GET

#define DDRCTL_SCHED_PREFER_WRITE_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED_PREFER_WRITE_MASK) >> DDRCTL_SCHED_PREFER_WRITE_SHIFT)

◆ DDRCTL_SCHED_PREFER_WRITE_MASK

#define DDRCTL_SCHED_PREFER_WRITE_MASK (0x2U)

◆ DDRCTL_SCHED_PREFER_WRITE_SET

#define DDRCTL_SCHED_PREFER_WRITE_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED_PREFER_WRITE_SHIFT) & DDRCTL_SCHED_PREFER_WRITE_MASK)

◆ DDRCTL_SCHED_PREFER_WRITE_SHIFT

#define DDRCTL_SCHED_PREFER_WRITE_SHIFT (1U)

◆ DDRCTL_SCHED_RDWR_IDLE_GAP_GET

#define DDRCTL_SCHED_RDWR_IDLE_GAP_GET ( x ) (((uint32_t)(x) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK) >> DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT)

◆ DDRCTL_SCHED_RDWR_IDLE_GAP_MASK

#define DDRCTL_SCHED_RDWR_IDLE_GAP_MASK (0x7F000000UL)

◆ DDRCTL_SCHED_RDWR_IDLE_GAP_SET

#define DDRCTL_SCHED_RDWR_IDLE_GAP_SET ( x ) (((uint32_t)(x) << DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK)

◆ DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT

#define DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT (24U)

◆ DDRCTL_STAT_OPERATING_MODE_GET

#define DDRCTL_STAT_OPERATING_MODE_GET ( x ) (((uint32_t)(x) & DDRCTL_STAT_OPERATING_MODE_MASK) >> DDRCTL_STAT_OPERATING_MODE_SHIFT)

◆ DDRCTL_STAT_OPERATING_MODE_MASK

#define DDRCTL_STAT_OPERATING_MODE_MASK (0x7U)

◆ DDRCTL_STAT_OPERATING_MODE_SHIFT

#define DDRCTL_STAT_OPERATING_MODE_SHIFT (0U)

◆ DDRCTL_STAT_SELFREF_TYPE_GET

#define DDRCTL_STAT_SELFREF_TYPE_GET ( x ) (((uint32_t)(x) & DDRCTL_STAT_SELFREF_TYPE_MASK) >> DDRCTL_STAT_SELFREF_TYPE_SHIFT)

◆ DDRCTL_STAT_SELFREF_TYPE_MASK

#define DDRCTL_STAT_SELFREF_TYPE_MASK (0x30U)

◆ DDRCTL_STAT_SELFREF_TYPE_SHIFT

#define DDRCTL_STAT_SELFREF_TYPE_SHIFT (4U)

◆ DDRCTL_ZQCTL0_DIS_AUTO_ZQ_GET

#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK) >> DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT)

◆ DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK

#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK (0x80000000UL)

◆ DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SET

#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SET ( x ) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK)

◆ DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT

#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT (31U)

◆ DDRCTL_ZQCTL0_DIS_SRX_ZQCL_GET

#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK) >> DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT)

◆ DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK

#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK (0x40000000UL)

◆ DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SET

#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SET ( x ) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK)

◆ DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT

#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT (30U)

◆ DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_GET

#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT)

◆ DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK

#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK (0x3FF0000UL)

◆ DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SET

#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SET ( x ) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK)

◆ DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT

#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT (16U)

◆ DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_GET

#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT)

◆ DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK

#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK (0x3FFU)

◆ DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SET

#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SET ( x ) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK)

◆ DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT

#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT (0U)

◆ DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_GET

#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK) >> DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT)

◆ DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK

#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK (0x20000000UL)

◆ DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SET

#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SET ( x ) (((uint32_t)(x) << DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK)

◆ DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT

#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT (29U)

◆ DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_GET

#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) >> DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT)

◆ DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK

#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK (0xFFFFFUL)

◆ DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SET

#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SET ( x ) (((uint32_t)(x) << DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK)

◆ DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT

#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT (0U)

◆ DDRCTL_ZQSTAT_ZQ_RESET_BUSY_GET

#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_GET ( x ) (((uint32_t)(x) & DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK) >> DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT)

◆ DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK

#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK (0x1U)

◆ DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT

#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT (0U)

Data Structures

Macros