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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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Go to the source code of this file.
Enumerations | |
| enum | DP83867_REG_Type { DP83867_BMCR = 0 , DP83867_BMSR = 1 , DP83867_PHYIDR1 = 2 , DP83867_PHYIDR2 = 3 , DP83867_ANAR = 4 , DP83867_ANLPAR = 5 , DP83867_ANER = 6 , DP83867_ANNPTR = 7 , DP83867_ANNPRR = 8 , DP83867_CFG1 = 9 , DP83867_STS1 = 10 , DP83867_REGCR = 13 , DP83867_ADDAR = 14 , DP83867_1KSCR = 15 , DP83867_PHYCR = 16 , DP83867_PHYSTS = 17 , DP83867_MICR = 18 , DP83867_ISR = 19 , DP83867_CRG2 = 20 , DP83867_RECR = 21 , DP83867_STS2 = 23 , DP83867_LEDCR1 = 24 , DP83867_LEDCR2 = 25 , DP83867_LEDCR3 = 26 , DP83867_CFG3 = 30 , DP83867_CTRL = 31 , DP83867_RGMIIDCTL = 134 } |
| #define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT) |
| #define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK (0x2000U) |
| #define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT (13U) |
| #define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT) |
| #define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK (0x1000U) |
| #define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT (12U) |
| #define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT) |
| #define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK (0x8000U) |
| #define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT (15U) |
| #define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT) |
| #define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK (0x4000U) |
| #define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT (14U) |
| #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) >> DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) |
| #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK (0xFFFFU) |
| #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) |
| #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT (0U) |
| #define DP83867_ANAR_10_FD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_10_FD_MASK) >> DP83867_ANAR_10_FD_SHIFT) |
| #define DP83867_ANAR_10_FD_MASK (0x40U) |
| #define DP83867_ANAR_10_FD_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_10_FD_SHIFT) & DP83867_ANAR_10_FD_MASK) |
| #define DP83867_ANAR_10_FD_SHIFT (6U) |
| #define DP83867_ANAR_10BASETE_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_10BASETE_EN_MASK) >> DP83867_ANAR_10BASETE_EN_SHIFT) |
| #define DP83867_ANAR_10BASETE_EN_MASK (0x20U) |
| #define DP83867_ANAR_10BASETE_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_10BASETE_EN_SHIFT) & DP83867_ANAR_10BASETE_EN_MASK) |
| #define DP83867_ANAR_10BASETE_EN_SHIFT (5U) |
| #define DP83867_ANAR_ASM_DIR_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_ASM_DIR_MASK) >> DP83867_ANAR_ASM_DIR_SHIFT) |
| #define DP83867_ANAR_ASM_DIR_MASK (0x800U) |
| #define DP83867_ANAR_ASM_DIR_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_ASM_DIR_SHIFT) & DP83867_ANAR_ASM_DIR_MASK) |
| #define DP83867_ANAR_ASM_DIR_SHIFT (11U) |
| #define DP83867_ANAR_NP_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_NP_MASK) >> DP83867_ANAR_NP_SHIFT) |
| #define DP83867_ANAR_NP_MASK (0x8000U) |
| #define DP83867_ANAR_NP_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_NP_SHIFT) & DP83867_ANAR_NP_MASK) |
| #define DP83867_ANAR_NP_SHIFT (15U) |
| #define DP83867_ANAR_PAUSE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_PAUSE_MASK) >> DP83867_ANAR_PAUSE_SHIFT) |
| #define DP83867_ANAR_PAUSE_MASK (0x400U) |
| #define DP83867_ANAR_PAUSE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_PAUSE_SHIFT) & DP83867_ANAR_PAUSE_MASK) |
| #define DP83867_ANAR_PAUSE_SHIFT (10U) |
| #define DP83867_ANAR_RF_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_RF_MASK) >> DP83867_ANAR_RF_SHIFT) |
| #define DP83867_ANAR_RF_MASK (0x2000U) |
| #define DP83867_ANAR_RF_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_RF_SHIFT) & DP83867_ANAR_RF_MASK) |
| #define DP83867_ANAR_RF_SHIFT (13U) |
| #define DP83867_ANAR_SELECTOR_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_SELECTOR_MASK) >> DP83867_ANAR_SELECTOR_SHIFT) |
| #define DP83867_ANAR_SELECTOR_MASK (0x1FU) |
| #define DP83867_ANAR_SELECTOR_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_SELECTOR_SHIFT) & DP83867_ANAR_SELECTOR_MASK) |
| #define DP83867_ANAR_SELECTOR_SHIFT (0U) |
| #define DP83867_ANAR_T4_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_T4_MASK) >> DP83867_ANAR_T4_SHIFT) |
| #define DP83867_ANAR_T4_MASK (0x200U) |
| #define DP83867_ANAR_T4_SHIFT (9U) |
| #define DP83867_ANAR_TX_FD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_TX_FD_MASK) >> DP83867_ANAR_TX_FD_SHIFT) |
| #define DP83867_ANAR_TX_FD_MASK (0x100U) |
| #define DP83867_ANAR_TX_FD_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_TX_FD_SHIFT) & DP83867_ANAR_TX_FD_MASK) |
| #define DP83867_ANAR_TX_FD_SHIFT (8U) |
| #define DP83867_ANAR_TX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANAR_TX_MASK) >> DP83867_ANAR_TX_SHIFT) |
| #define DP83867_ANAR_TX_MASK (0x80U) |
| #define DP83867_ANAR_TX_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANAR_TX_SHIFT) & DP83867_ANAR_TX_MASK) |
| #define DP83867_ANAR_TX_SHIFT (7U) |
| #define DP83867_ANER_LP_AN_ABLE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_LP_AN_ABLE_MASK) >> DP83867_ANER_LP_AN_ABLE_SHIFT) |
| #define DP83867_ANER_LP_AN_ABLE_MASK (0x1U) |
| #define DP83867_ANER_LP_AN_ABLE_SHIFT (0U) |
| #define DP83867_ANER_LP_NP_ABLE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_LP_NP_ABLE_MASK) >> DP83867_ANER_LP_NP_ABLE_SHIFT) |
| #define DP83867_ANER_LP_NP_ABLE_MASK (0x8U) |
| #define DP83867_ANER_LP_NP_ABLE_SHIFT (3U) |
| #define DP83867_ANER_NP_ABLE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_NP_ABLE_MASK) >> DP83867_ANER_NP_ABLE_SHIFT) |
| #define DP83867_ANER_NP_ABLE_MASK (0x4U) |
| #define DP83867_ANER_NP_ABLE_SHIFT (2U) |
| #define DP83867_ANER_PAGE_RX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_PAGE_RX_MASK) >> DP83867_ANER_PAGE_RX_SHIFT) |
| #define DP83867_ANER_PAGE_RX_MASK (0x2U) |
| #define DP83867_ANER_PAGE_RX_SHIFT (1U) |
| #define DP83867_ANER_PDF_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_PDF_MASK) >> DP83867_ANER_PDF_SHIFT) |
| #define DP83867_ANER_PDF_MASK (0x10U) |
| #define DP83867_ANER_PDF_SHIFT (4U) |
| #define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK) >> DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT) |
| #define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK (0x40U) |
| #define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT (6U) |
| #define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK) >> DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT) |
| #define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK (0x20U) |
| #define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT (5U) |
| #define DP83867_ANLPAR_10_FD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_10_FD_MASK) >> DP83867_ANLPAR_10_FD_SHIFT) |
| #define DP83867_ANLPAR_10_FD_MASK (0x40U) |
| #define DP83867_ANLPAR_10_FD_SHIFT (6U) |
| #define DP83867_ANLPAR_10_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_10_MASK) >> DP83867_ANLPAR_10_SHIFT) |
| #define DP83867_ANLPAR_10_MASK (0x20U) |
| #define DP83867_ANLPAR_10_SHIFT (5U) |
| #define DP83867_ANLPAR_ACK_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_ACK_MASK) >> DP83867_ANLPAR_ACK_SHIFT) |
| #define DP83867_ANLPAR_ACK_MASK (0x4000U) |
| #define DP83867_ANLPAR_ACK_SHIFT (14U) |
| #define DP83867_ANLPAR_ASM_DIR_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_ASM_DIR_MASK) >> DP83867_ANLPAR_ASM_DIR_SHIFT) |
| #define DP83867_ANLPAR_ASM_DIR_MASK (0x800U) |
| #define DP83867_ANLPAR_ASM_DIR_SHIFT (11U) |
| #define DP83867_ANLPAR_NP_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_NP_MASK) >> DP83867_ANLPAR_NP_SHIFT) |
| #define DP83867_ANLPAR_NP_MASK (0x8000U) |
| #define DP83867_ANLPAR_NP_SHIFT (15U) |
| #define DP83867_ANLPAR_PAUSE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_PAUSE_MASK) >> DP83867_ANLPAR_PAUSE_SHIFT) |
| #define DP83867_ANLPAR_PAUSE_MASK (0x400U) |
| #define DP83867_ANLPAR_PAUSE_SHIFT (10U) |
| #define DP83867_ANLPAR_RF_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_RF_MASK) >> DP83867_ANLPAR_RF_SHIFT) |
| #define DP83867_ANLPAR_RF_MASK (0x2000U) |
| #define DP83867_ANLPAR_RF_SHIFT (13U) |
| #define DP83867_ANLPAR_SELECTOR_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_SELECTOR_MASK) >> DP83867_ANLPAR_SELECTOR_SHIFT) |
| #define DP83867_ANLPAR_SELECTOR_MASK (0x1FU) |
| #define DP83867_ANLPAR_SELECTOR_SHIFT (0U) |
| #define DP83867_ANLPAR_T4_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_T4_MASK) >> DP83867_ANLPAR_T4_SHIFT) |
| #define DP83867_ANLPAR_T4_MASK (0x200U) |
| #define DP83867_ANLPAR_T4_SHIFT (9U) |
| #define DP83867_ANLPAR_TX_FD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_TX_FD_MASK) >> DP83867_ANLPAR_TX_FD_SHIFT) |
| #define DP83867_ANLPAR_TX_FD_MASK (0x100U) |
| #define DP83867_ANLPAR_TX_FD_SHIFT (8U) |
| #define DP83867_ANLPAR_TX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANLPAR_TX_MASK) >> DP83867_ANLPAR_TX_SHIFT) |
| #define DP83867_ANLPAR_TX_MASK (0x80U) |
| #define DP83867_ANLPAR_TX_SHIFT (7U) |
| #define DP83867_ANNPRR_ACK2_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPRR_ACK2_MASK) >> DP83867_ANNPRR_ACK2_SHIFT) |
| #define DP83867_ANNPRR_ACK2_MASK (0x1000U) |
| #define DP83867_ANNPRR_ACK2_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPRR_ACK2_SHIFT) & DP83867_ANNPRR_ACK2_MASK) |
| #define DP83867_ANNPRR_ACK2_SHIFT (12U) |
| #define DP83867_ANNPRR_ACK_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPRR_ACK_MASK) >> DP83867_ANNPRR_ACK_SHIFT) |
| #define DP83867_ANNPRR_ACK_MASK (0x4000U) |
| #define DP83867_ANNPRR_ACK_SHIFT (14U) |
| #define DP83867_ANNPRR_CODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPRR_CODE_MASK) >> DP83867_ANNPRR_CODE_SHIFT) |
| #define DP83867_ANNPRR_CODE_MASK (0x7FFU) |
| #define DP83867_ANNPRR_CODE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPRR_CODE_SHIFT) & DP83867_ANNPRR_CODE_MASK) |
| #define DP83867_ANNPRR_CODE_SHIFT (0U) |
| #define DP83867_ANNPRR_MP_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPRR_MP_MASK) >> DP83867_ANNPRR_MP_SHIFT) |
| #define DP83867_ANNPRR_MP_MASK (0x2000U) |
| #define DP83867_ANNPRR_MP_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPRR_MP_SHIFT) & DP83867_ANNPRR_MP_MASK) |
| #define DP83867_ANNPRR_MP_SHIFT (13U) |
| #define DP83867_ANNPRR_NP_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPRR_NP_MASK) >> DP83867_ANNPRR_NP_SHIFT) |
| #define DP83867_ANNPRR_NP_MASK (0x8000U) |
| #define DP83867_ANNPRR_NP_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPRR_NP_SHIFT) & DP83867_ANNPRR_NP_MASK) |
| #define DP83867_ANNPRR_NP_SHIFT (15U) |
| #define DP83867_ANNPRR_TOG_TX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPRR_TOG_TX_MASK) >> DP83867_ANNPRR_TOG_TX_SHIFT) |
| #define DP83867_ANNPRR_TOG_TX_MASK (0x800U) |
| #define DP83867_ANNPRR_TOG_TX_SHIFT (11U) |
| #define DP83867_ANNPTR_ACK2_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPTR_ACK2_MASK) >> DP83867_ANNPTR_ACK2_SHIFT) |
| #define DP83867_ANNPTR_ACK2_MASK (0x1000U) |
| #define DP83867_ANNPTR_ACK2_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPTR_ACK2_SHIFT) & DP83867_ANNPTR_ACK2_MASK) |
| #define DP83867_ANNPTR_ACK2_SHIFT (12U) |
| #define DP83867_ANNPTR_ACK_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPTR_ACK_MASK) >> DP83867_ANNPTR_ACK_SHIFT) |
| #define DP83867_ANNPTR_ACK_MASK (0x4000U) |
| #define DP83867_ANNPTR_ACK_SHIFT (14U) |
| #define DP83867_ANNPTR_CODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPTR_CODE_MASK) >> DP83867_ANNPTR_CODE_SHIFT) |
| #define DP83867_ANNPTR_CODE_MASK (0x7FFU) |
| #define DP83867_ANNPTR_CODE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPTR_CODE_SHIFT) & DP83867_ANNPTR_CODE_MASK) |
| #define DP83867_ANNPTR_CODE_SHIFT (0U) |
| #define DP83867_ANNPTR_MP_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPTR_MP_MASK) >> DP83867_ANNPTR_MP_SHIFT) |
| #define DP83867_ANNPTR_MP_MASK (0x2000U) |
| #define DP83867_ANNPTR_MP_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPTR_MP_SHIFT) & DP83867_ANNPTR_MP_MASK) |
| #define DP83867_ANNPTR_MP_SHIFT (13U) |
| #define DP83867_ANNPTR_NP_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPTR_NP_MASK) >> DP83867_ANNPTR_NP_SHIFT) |
| #define DP83867_ANNPTR_NP_MASK (0x8000U) |
| #define DP83867_ANNPTR_NP_SET | ( | x | ) | (((uint16_t)(x) << DP83867_ANNPTR_NP_SHIFT) & DP83867_ANNPTR_NP_MASK) |
| #define DP83867_ANNPTR_NP_SHIFT (15U) |
| #define DP83867_ANNPTR_TOG_TX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ANNPTR_TOG_TX_MASK) >> DP83867_ANNPTR_TOG_TX_SHIFT) |
| #define DP83867_ANNPTR_TOG_TX_MASK (0x800U) |
| #define DP83867_ANNPTR_TOG_TX_SHIFT (11U) |
| #define DP83867_BMCR_ANE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) |
| #define DP83867_BMCR_ANE_MASK (0x1000U) |
| #define DP83867_BMCR_ANE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) |
| #define DP83867_BMCR_ANE_SHIFT (12U) |
| #define DP83867_BMCR_COLLISION_TEST_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) |
| #define DP83867_BMCR_COLLISION_TEST_MASK (0x80U) |
| #define DP83867_BMCR_COLLISION_TEST_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) |
| #define DP83867_BMCR_COLLISION_TEST_SHIFT (7U) |
| #define DP83867_BMCR_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) |
| #define DP83867_BMCR_DUPLEX_MASK (0x100U) |
| #define DP83867_BMCR_DUPLEX_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) |
| #define DP83867_BMCR_DUPLEX_SHIFT (8U) |
| #define DP83867_BMCR_ISOLATE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) |
| #define DP83867_BMCR_ISOLATE_MASK (0x400U) |
| #define DP83867_BMCR_ISOLATE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) |
| #define DP83867_BMCR_ISOLATE_SHIFT (10U) |
| #define DP83867_BMCR_LOOPBACK_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) |
| #define DP83867_BMCR_LOOPBACK_MASK (0x4000U) |
| #define DP83867_BMCR_LOOPBACK_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) |
| #define DP83867_BMCR_LOOPBACK_SHIFT (14U) |
| #define DP83867_BMCR_PWD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) |
| #define DP83867_BMCR_PWD_MASK (0x800U) |
| #define DP83867_BMCR_PWD_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) |
| #define DP83867_BMCR_PWD_SHIFT (11U) |
| #define DP83867_BMCR_RESET_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) |
| #define DP83867_BMCR_RESET_MASK (0x8000U) |
| #define DP83867_BMCR_RESET_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) |
| #define DP83867_BMCR_RESET_SHIFT (15U) |
| #define DP83867_BMCR_RESTART_AN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) |
| #define DP83867_BMCR_RESTART_AN_MASK (0x200U) |
| #define DP83867_BMCR_RESTART_AN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) |
| #define DP83867_BMCR_RESTART_AN_SHIFT (9U) |
| #define DP83867_BMCR_SPEED0_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) |
| #define DP83867_BMCR_SPEED0_MASK (0x2000U) |
| #define DP83867_BMCR_SPEED0_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) |
| #define DP83867_BMCR_SPEED0_SHIFT (13U) |
| #define DP83867_BMCR_SPEED1_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) |
| #define DP83867_BMCR_SPEED1_MASK (0x40U) |
| #define DP83867_BMCR_SPEED1_SET | ( | x | ) | (((uint16_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) |
| #define DP83867_BMCR_SPEED1_SHIFT (6U) |
| #define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT) |
| #define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK (0x400U) |
| #define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT (10U) |
| #define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT) |
| #define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK (0x200U) |
| #define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT (9U) |
| #define DP83867_BMSR_100BASE_T4_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_100BASE_T4_MASK) >> DP83867_BMSR_100BASE_T4_SHIFT) |
| #define DP83867_BMSR_100BASE_T4_MASK (0x8000U) |
| #define DP83867_BMSR_100BASE_T4_SHIFT (15U) |
| #define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) |
| #define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) |
| #define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) |
| #define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT) |
| #define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK (0x2000U) |
| #define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT (13U) |
| #define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT) |
| #define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK (0x1000U) |
| #define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT (12U) |
| #define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT) |
| #define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK (0x800U) |
| #define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT (11U) |
| #define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) |
| #define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) |
| #define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) |
| #define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) |
| #define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) |
| #define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) |
| #define DP83867_BMSR_EXTENDED_CAPABILITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT) |
| #define DP83867_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) |
| #define DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) |
| #define DP83867_BMSR_EXTENDED_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_EXTENDED_STATUS_MASK) >> DP83867_BMSR_EXTENDED_STATUS_SHIFT) |
| #define DP83867_BMSR_EXTENDED_STATUS_MASK (0x100U) |
| #define DP83867_BMSR_EXTENDED_STATUS_SHIFT (8U) |
| #define DP83867_BMSR_JABBER_DETECT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_JABBER_DETECT_MASK) >> DP83867_BMSR_JABBER_DETECT_SHIFT) |
| #define DP83867_BMSR_JABBER_DETECT_MASK (0x2U) |
| #define DP83867_BMSR_JABBER_DETECT_SHIFT (1U) |
| #define DP83867_BMSR_LINK_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) |
| #define DP83867_BMSR_LINK_STATUS_MASK (0x4U) |
| #define DP83867_BMSR_LINK_STATUS_SHIFT (2U) |
| #define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) |
| #define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) |
| #define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) |
| #define DP83867_BMSR_REMOTE_FAULT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_BMSR_REMOTE_FAULT_MASK) >> DP83867_BMSR_REMOTE_FAULT_SHIFT) |
| #define DP83867_BMSR_REMOTE_FAULT_MASK (0x10U) |
| #define DP83867_BMSR_REMOTE_FAULT_SHIFT (4U) |
| #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) |
| #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK (0x200U) |
| #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) |
| #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT (9U) |
| #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) |
| #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK (0x100U) |
| #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) |
| #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT (8U) |
| #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) >> DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) |
| #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK (0x800U) |
| #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) |
| #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT (11U) |
| #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) >> DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) |
| #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK (0x1000U) |
| #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) |
| #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT (12U) |
| #define DP83867_CFG1_PORT_TYPE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_PORT_TYPE_MASK) >> DP83867_CFG1_PORT_TYPE_SHIFT) |
| #define DP83867_CFG1_PORT_TYPE_MASK (0x400U) |
| #define DP83867_CFG1_PORT_TYPE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_PORT_TYPE_SHIFT) & DP83867_CFG1_PORT_TYPE_MASK) |
| #define DP83867_CFG1_PORT_TYPE_SHIFT (10U) |
| #define DP83867_CFG1_TDR_AUTO_RUN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_TDR_AUTO_RUN_MASK) >> DP83867_CFG1_TDR_AUTO_RUN_SHIFT) |
| #define DP83867_CFG1_TDR_AUTO_RUN_MASK (0x80U) |
| #define DP83867_CFG1_TDR_AUTO_RUN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_TDR_AUTO_RUN_SHIFT) & DP83867_CFG1_TDR_AUTO_RUN_MASK) |
| #define DP83867_CFG1_TDR_AUTO_RUN_SHIFT (7U) |
| #define DP83867_CFG1_TEST_MODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG1_TEST_MODE_MASK) >> DP83867_CFG1_TEST_MODE_SHIFT) |
| #define DP83867_CFG1_TEST_MODE_MASK (0xE000U) |
| #define DP83867_CFG1_TEST_MODE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG1_TEST_MODE_SHIFT) & DP83867_CFG1_TEST_MODE_MASK) |
| #define DP83867_CFG1_TEST_MODE_SHIFT (13U) |
| #define DP83867_CFG3_EXTENDED_FD_ABILITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) >> DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) |
| #define DP83867_CFG3_EXTENDED_FD_ABILITY_MASK (0x800U) |
| #define DP83867_CFG3_EXTENDED_FD_ABILITY_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) |
| #define DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT (11U) |
| #define DP83867_CFG3_FAST_AN_ENABLE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_FAST_AN_ENABLE_MASK) >> DP83867_CFG3_FAST_AN_ENABLE_SHIFT) |
| #define DP83867_CFG3_FAST_AN_ENABLE_MASK (0x4000U) |
| #define DP83867_CFG3_FAST_AN_ENABLE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_FAST_AN_ENABLE_SHIFT) & DP83867_CFG3_FAST_AN_ENABLE_MASK) |
| #define DP83867_CFG3_FAST_AN_ENABLE_SHIFT (14U) |
| #define DP83867_CFG3_FAST_AN_SEL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_FAST_AN_SEL_MASK) >> DP83867_CFG3_FAST_AN_SEL_SHIFT) |
| #define DP83867_CFG3_FAST_AN_SEL_MASK (0x3000U) |
| #define DP83867_CFG3_FAST_AN_SEL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_FAST_AN_SEL_SHIFT) & DP83867_CFG3_FAST_AN_SEL_MASK) |
| #define DP83867_CFG3_FAST_AN_SEL_SHIFT (12U) |
| #define DP83867_CFG3_FAST_AUTO_MDIX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) >> DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) |
| #define DP83867_CFG3_FAST_AUTO_MDIX_MASK (0x100U) |
| #define DP83867_CFG3_FAST_AUTO_MDIX_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) |
| #define DP83867_CFG3_FAST_AUTO_MDIX_SHIFT (8U) |
| #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) >> DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) |
| #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK (0x8000U) |
| #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) |
| #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT (15U) |
| #define DP83867_CFG3_FORCE_INTERRUPT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_FORCE_INTERRUPT_MASK) >> DP83867_CFG3_FORCE_INTERRUPT_SHIFT) |
| #define DP83867_CFG3_FORCE_INTERRUPT_MASK (0x40U) |
| #define DP83867_CFG3_FORCE_INTERRUPT_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_FORCE_INTERRUPT_SHIFT) & DP83867_CFG3_FORCE_INTERRUPT_MASK) |
| #define DP83867_CFG3_FORCE_INTERRUPT_SHIFT (6U) |
| #define DP83867_CFG3_INT_OE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_INT_OE_MASK) >> DP83867_CFG3_INT_OE_SHIFT) |
| #define DP83867_CFG3_INT_OE_MASK (0x80U) |
| #define DP83867_CFG3_INT_OE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_INT_OE_SHIFT) & DP83867_CFG3_INT_OE_MASK) |
| #define DP83867_CFG3_INT_OE_SHIFT (7U) |
| #define DP83867_CFG3_ROBUST_AUTO_MDIX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) >> DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) |
| #define DP83867_CFG3_ROBUST_AUTO_MDIX_MASK (0x200U) |
| #define DP83867_CFG3_ROBUST_AUTO_MDIX_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) |
| #define DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT (9U) |
| #define DP83867_CFG3_TDR_DONE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_TDR_DONE_MASK) >> DP83867_CFG3_TDR_DONE_SHIFT) |
| #define DP83867_CFG3_TDR_DONE_MASK (0x2U) |
| #define DP83867_CFG3_TDR_DONE_SHIFT (1U) |
| #define DP83867_CFG3_TDR_FAIL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_TDR_FAIL_MASK) >> DP83867_CFG3_TDR_FAIL_SHIFT) |
| #define DP83867_CFG3_TDR_FAIL_MASK (0x4U) |
| #define DP83867_CFG3_TDR_FAIL_SHIFT (2U) |
| #define DP83867_CFG3_TDR_START_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CFG3_TDR_START_MASK) >> DP83867_CFG3_TDR_START_SHIFT) |
| #define DP83867_CFG3_TDR_START_MASK (0x1U) |
| #define DP83867_CFG3_TDR_START_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CFG3_TDR_START_SHIFT) & DP83867_CFG3_TDR_START_MASK) |
| #define DP83867_CFG3_TDR_START_SHIFT (0U) |
| #define DP83867_CRG2_INTERRUPT_POLARITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) >> DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) |
| #define DP83867_CRG2_INTERRUPT_POLARITY_MASK (0x2000U) |
| #define DP83867_CRG2_INTERRUPT_POLARITY_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) |
| #define DP83867_CRG2_INTERRUPT_POLARITY_SHIFT (13U) |
| #define DP83867_CRG2_SGMII_AUTONEG_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) >> DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) |
| #define DP83867_CRG2_SGMII_AUTONEG_EN_MASK (0x80U) |
| #define DP83867_CRG2_SGMII_AUTONEG_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) |
| #define DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT (7U) |
| #define DP83867_CRG2_SPEED_OPT_10M_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) >> DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) |
| #define DP83867_CRG2_SPEED_OPT_10M_EN_MASK (0x40U) |
| #define DP83867_CRG2_SPEED_OPT_10M_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) |
| #define DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT (6U) |
| #define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK) >> DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT) |
| #define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK (0xC00U) |
| #define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT (10U) |
| #define DP83867_CRG2_SPEED_OPT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_EN_MASK) >> DP83867_CRG2_SPEED_OPT_EN_SHIFT) |
| #define DP83867_CRG2_SPEED_OPT_EN_MASK (0x200U) |
| #define DP83867_CRG2_SPEED_OPT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_EN_MASK) |
| #define DP83867_CRG2_SPEED_OPT_EN_SHIFT (9U) |
| #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) >> DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) |
| #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK (0x100U) |
| #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) |
| #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT (8U) |
| #define DP83867_CTRL_SW_RESET_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CTRL_SW_RESET_MASK) >> DP83867_CTRL_SW_RESET_SHIFT) |
| #define DP83867_CTRL_SW_RESET_MASK (0x8000U) |
| #define DP83867_CTRL_SW_RESET_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CTRL_SW_RESET_SHIFT) & DP83867_CTRL_SW_RESET_MASK) |
| #define DP83867_CTRL_SW_RESET_SHIFT (15U) |
| #define DP83867_CTRL_SW_RESTART_GET | ( | x | ) | (((uint16_t)(x) & DP83867_CTRL_SW_RESTART_MASK) >> DP83867_CTRL_SW_RESTART_SHIFT) |
| #define DP83867_CTRL_SW_RESTART_MASK (0x4000U) |
| #define DP83867_CTRL_SW_RESTART_SET | ( | x | ) | (((uint16_t)(x) << DP83867_CTRL_SW_RESTART_SHIFT) & DP83867_CTRL_SW_RESTART_MASK) |
| #define DP83867_CTRL_SW_RESTART_SHIFT (14U) |
| #define DP83867_ISR_AUTONEG_COMP_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_AUTONEG_COMP_INT_MASK) >> DP83867_ISR_AUTONEG_COMP_INT_SHIFT) |
| #define DP83867_ISR_AUTONEG_COMP_INT_MASK (0x800U) |
| #define DP83867_ISR_AUTONEG_COMP_INT_SHIFT (11U) |
| #define DP83867_ISR_AUTONEG_ERR_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_AUTONEG_ERR_INT_MASK) >> DP83867_ISR_AUTONEG_ERR_INT_SHIFT) |
| #define DP83867_ISR_AUTONEG_ERR_INT_MASK (0x8000U) |
| #define DP83867_ISR_AUTONEG_ERR_INT_SHIFT (15U) |
| #define DP83867_ISR_DUPLEX_MODE_CHNG_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK) >> DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT) |
| #define DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK (0x2000U) |
| #define DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT (13U) |
| #define DP83867_ISR_FALSE_CARRIER_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_FALSE_CARRIER_INT_MASK) >> DP83867_ISR_FALSE_CARRIER_INT_SHIFT) |
| #define DP83867_ISR_FALSE_CARRIER_INT_MASK (0x100U) |
| #define DP83867_ISR_FALSE_CARRIER_INT_SHIFT (8U) |
| #define DP83867_ISR_JABBER_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_JABBER_INT_MASK) >> DP83867_ISR_JABBER_INT_SHIFT) |
| #define DP83867_ISR_JABBER_INT_MASK (0x1U) |
| #define DP83867_ISR_JABBER_INT_SHIFT (0U) |
| #define DP83867_ISR_LINK_STATUS_CHNG_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_LINK_STATUS_CHNG_INT_MASK) >> DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT) |
| #define DP83867_ISR_LINK_STATUS_CHNG_INT_MASK (0x400U) |
| #define DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT (10U) |
| #define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK) >> DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT) |
| #define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK (0x40U) |
| #define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT (6U) |
| #define DP83867_ISR_PAGE_RECEIVED_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_PAGE_RECEIVED_INT_MASK) >> DP83867_ISR_PAGE_RECEIVED_INT_SHIFT) |
| #define DP83867_ISR_PAGE_RECEIVED_INT_MASK (0x1000U) |
| #define DP83867_ISR_PAGE_RECEIVED_INT_SHIFT (12U) |
| #define DP83867_ISR_POLARITY_CHNG_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_POLARITY_CHNG_INT_MASK) >> DP83867_ISR_POLARITY_CHNG_INT_SHIFT) |
| #define DP83867_ISR_POLARITY_CHNG_INT_MASK (0x2U) |
| #define DP83867_ISR_POLARITY_CHNG_INT_SHIFT (1U) |
| #define DP83867_ISR_SLEEP_MODE_CHNG_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK) >> DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT) |
| #define DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK (0x10U) |
| #define DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT (4U) |
| #define DP83867_ISR_SPEED_CHNG_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_SPEED_CHNG_INT_MASK) >> DP83867_ISR_SPEED_CHNG_INT_SHIFT) |
| #define DP83867_ISR_SPEED_CHNG_INT_MASK (0x4000U) |
| #define DP83867_ISR_SPEED_CHNG_INT_SHIFT (14U) |
| #define DP83867_ISR_SPEED_OPT_EVENT_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_SPEED_OPT_EVENT_INT_MASK) >> DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT) |
| #define DP83867_ISR_SPEED_OPT_EVENT_INT_MASK (0x20U) |
| #define DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT (5U) |
| #define DP83867_ISR_WOL_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_WOL_INT_MASK) >> DP83867_ISR_WOL_INT_SHIFT) |
| #define DP83867_ISR_WOL_INT_MASK (0x8U) |
| #define DP83867_ISR_WOL_INT_SHIFT (3U) |
| #define DP83867_ISR_XGMII_ERR_INT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_ISR_XGMII_ERR_INT_MASK) >> DP83867_ISR_XGMII_ERR_INT_SHIFT) |
| #define DP83867_ISR_XGMII_ERR_INT_MASK (0x4U) |
| #define DP83867_ISR_XGMII_ERR_INT_SHIFT (2U) |
| #define DP83867_LEDCR1_LED_0_SEL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR1_LED_0_SEL_MASK) >> DP83867_LEDCR1_LED_0_SEL_SHIFT) |
| #define DP83867_LEDCR1_LED_0_SEL_MASK (0xFU) |
| #define DP83867_LEDCR1_LED_0_SEL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR1_LED_0_SEL_SHIFT) & DP83867_LEDCR1_LED_0_SEL_MASK) |
| #define DP83867_LEDCR1_LED_0_SEL_SHIFT (0U) |
| #define DP83867_LEDCR1_LED_1_SEL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR1_LED_1_SEL_MASK) >> DP83867_LEDCR1_LED_1_SEL_SHIFT) |
| #define DP83867_LEDCR1_LED_1_SEL_MASK (0xF0U) |
| #define DP83867_LEDCR1_LED_1_SEL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR1_LED_1_SEL_SHIFT) & DP83867_LEDCR1_LED_1_SEL_MASK) |
| #define DP83867_LEDCR1_LED_1_SEL_SHIFT (4U) |
| #define DP83867_LEDCR1_LED_2_SEL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR1_LED_2_SEL_MASK) >> DP83867_LEDCR1_LED_2_SEL_SHIFT) |
| #define DP83867_LEDCR1_LED_2_SEL_MASK (0xF00U) |
| #define DP83867_LEDCR1_LED_2_SEL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR1_LED_2_SEL_SHIFT) & DP83867_LEDCR1_LED_2_SEL_MASK) |
| #define DP83867_LEDCR1_LED_2_SEL_SHIFT (8U) |
| #define DP83867_LEDCR1_LED_GPIO_SEL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) >> DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) |
| #define DP83867_LEDCR1_LED_GPIO_SEL_MASK (0xF000U) |
| #define DP83867_LEDCR1_LED_GPIO_SEL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) |
| #define DP83867_LEDCR1_LED_GPIO_SEL_SHIFT (12U) |
| #define DP83867_LEDCR2_LED_0_DRV_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) >> DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) |
| #define DP83867_LEDCR2_LED_0_DRV_EN_MASK (0x1U) |
| #define DP83867_LEDCR2_LED_0_DRV_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) |
| #define DP83867_LEDCR2_LED_0_DRV_EN_SHIFT (0U) |
| #define DP83867_LEDCR2_LED_0_DRV_VAL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) |
| #define DP83867_LEDCR2_LED_0_DRV_VAL_MASK (0x2U) |
| #define DP83867_LEDCR2_LED_0_DRV_VAL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) |
| #define DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT (1U) |
| #define DP83867_LEDCR2_LED_0_POLARITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_0_POLARITY_MASK) >> DP83867_LEDCR2_LED_0_POLARITY_SHIFT) |
| #define DP83867_LEDCR2_LED_0_POLARITY_MASK (0x4U) |
| #define DP83867_LEDCR2_LED_0_POLARITY_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_0_POLARITY_SHIFT) & DP83867_LEDCR2_LED_0_POLARITY_MASK) |
| #define DP83867_LEDCR2_LED_0_POLARITY_SHIFT (2U) |
| #define DP83867_LEDCR2_LED_1_DRV_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) >> DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) |
| #define DP83867_LEDCR2_LED_1_DRV_EN_MASK (0x10U) |
| #define DP83867_LEDCR2_LED_1_DRV_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) |
| #define DP83867_LEDCR2_LED_1_DRV_EN_SHIFT (4U) |
| #define DP83867_LEDCR2_LED_1_DRV_VAL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) |
| #define DP83867_LEDCR2_LED_1_DRV_VAL_MASK (0x20U) |
| #define DP83867_LEDCR2_LED_1_DRV_VAL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) |
| #define DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT (5U) |
| #define DP83867_LEDCR2_LED_1_POLARITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_1_POLARITY_MASK) >> DP83867_LEDCR2_LED_1_POLARITY_SHIFT) |
| #define DP83867_LEDCR2_LED_1_POLARITY_MASK (0x40U) |
| #define DP83867_LEDCR2_LED_1_POLARITY_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_1_POLARITY_SHIFT) & DP83867_LEDCR2_LED_1_POLARITY_MASK) |
| #define DP83867_LEDCR2_LED_1_POLARITY_SHIFT (6U) |
| #define DP83867_LEDCR2_LED_2_DRV_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) >> DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) |
| #define DP83867_LEDCR2_LED_2_DRV_EN_MASK (0x100U) |
| #define DP83867_LEDCR2_LED_2_DRV_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) |
| #define DP83867_LEDCR2_LED_2_DRV_EN_SHIFT (8U) |
| #define DP83867_LEDCR2_LED_2_DRV_VAL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) |
| #define DP83867_LEDCR2_LED_2_DRV_VAL_MASK (0x200U) |
| #define DP83867_LEDCR2_LED_2_DRV_VAL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) |
| #define DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT (9U) |
| #define DP83867_LEDCR2_LED_2_POLARITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_2_POLARITY_MASK) >> DP83867_LEDCR2_LED_2_POLARITY_SHIFT) |
| #define DP83867_LEDCR2_LED_2_POLARITY_MASK (0x400U) |
| #define DP83867_LEDCR2_LED_2_POLARITY_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_2_POLARITY_SHIFT) & DP83867_LEDCR2_LED_2_POLARITY_MASK) |
| #define DP83867_LEDCR2_LED_2_POLARITY_SHIFT (10U) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK (0x1000U) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT (12U) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK (0x2000U) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) |
| #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT (13U) |
| #define DP83867_LEDCR2_LED_GPIO_POLARITY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) >> DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) |
| #define DP83867_LEDCR2_LED_GPIO_POLARITY_MASK (0x4000U) |
| #define DP83867_LEDCR2_LED_GPIO_POLARITY_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) |
| #define DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT (14U) |
| #define DP83867_LEDCR3_LEDS_BLINK_RATE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) >> DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) |
| #define DP83867_LEDCR3_LEDS_BLINK_RATE_MASK (0x3U) |
| #define DP83867_LEDCR3_LEDS_BLINK_RATE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) |
| #define DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT (0U) |
| #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_GET | ( | x | ) | (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) >> DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) |
| #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK (0x4U) |
| #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SET | ( | x | ) | (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) |
| #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT (2U) |
| #define DP83867_MICR_AUTONEG_COMP_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) >> DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) |
| #define DP83867_MICR_AUTONEG_COMP_INT_EN_MASK (0x800U) |
| #define DP83867_MICR_AUTONEG_COMP_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) |
| #define DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT (11U) |
| #define DP83867_MICR_AUTONEG_ERR_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) >> DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) |
| #define DP83867_MICR_AUTONEG_ERR_INT_EN_MASK (0x8000U) |
| #define DP83867_MICR_AUTONEG_ERR_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) |
| #define DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT (15U) |
| #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) |
| #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK (0x2000U) |
| #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) |
| #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT (13U) |
| #define DP83867_MICR_FALSE_CARRIER_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) >> DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) |
| #define DP83867_MICR_FALSE_CARRIER_INT_EN_MASK (0x100U) |
| #define DP83867_MICR_FALSE_CARRIER_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) |
| #define DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT (8U) |
| #define DP83867_MICR_JABBER_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_JABBER_INT_EN_MASK) >> DP83867_MICR_JABBER_INT_EN_SHIFT) |
| #define DP83867_MICR_JABBER_INT_EN_MASK (0x1U) |
| #define DP83867_MICR_JABBER_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_JABBER_INT_EN_SHIFT) & DP83867_MICR_JABBER_INT_EN_MASK) |
| #define DP83867_MICR_JABBER_INT_EN_SHIFT (0U) |
| #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) >> DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) |
| #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK (0x400U) |
| #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) |
| #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT (10U) |
| #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) >> DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) |
| #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK (0x40U) |
| #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) |
| #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT (6U) |
| #define DP83867_MICR_PAGE_RECEIVED_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) >> DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) |
| #define DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK (0x1000U) |
| #define DP83867_MICR_PAGE_RECEIVED_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) |
| #define DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT (12U) |
| #define DP83867_MICR_POLARITY_CHNG_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) >> DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) |
| #define DP83867_MICR_POLARITY_CHNG_INT_EN_MASK (0x2U) |
| #define DP83867_MICR_POLARITY_CHNG_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) |
| #define DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT (1U) |
| #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) |
| #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK (0x10U) |
| #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) |
| #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT (4U) |
| #define DP83867_MICR_SPEED_CHNG_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) >> DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) |
| #define DP83867_MICR_SPEED_CHNG_INT_EN_MASK (0x4000U) |
| #define DP83867_MICR_SPEED_CHNG_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) |
| #define DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT (14U) |
| #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) >> DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) |
| #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK (0x20U) |
| #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) |
| #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT (5U) |
| #define DP83867_MICR_WOL_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_WOL_INT_EN_MASK) >> DP83867_MICR_WOL_INT_EN_SHIFT) |
| #define DP83867_MICR_WOL_INT_EN_MASK (0x8U) |
| #define DP83867_MICR_WOL_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_WOL_INT_EN_SHIFT) & DP83867_MICR_WOL_INT_EN_MASK) |
| #define DP83867_MICR_WOL_INT_EN_SHIFT (3U) |
| #define DP83867_MICR_XGMII_ERR_INT_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) >> DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) |
| #define DP83867_MICR_XGMII_ERR_INT_EN_MASK (0x4U) |
| #define DP83867_MICR_XGMII_ERR_INT_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) |
| #define DP83867_MICR_XGMII_ERR_INT_EN_SHIFT (2U) |
| #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) >> DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) |
| #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK (0x80U) |
| #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) |
| #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT (7U) |
| #define DP83867_PHYCR_DISABLE_CLK_125_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_DISABLE_CLK_125_MASK) >> DP83867_PHYCR_DISABLE_CLK_125_SHIFT) |
| #define DP83867_PHYCR_DISABLE_CLK_125_MASK (0x10U) |
| #define DP83867_PHYCR_DISABLE_CLK_125_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_DISABLE_CLK_125_SHIFT) & DP83867_PHYCR_DISABLE_CLK_125_MASK) |
| #define DP83867_PHYCR_DISABLE_CLK_125_SHIFT (4U) |
| #define DP83867_PHYCR_DISABLE_JABBER_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_DISABLE_JABBER_MASK) >> DP83867_PHYCR_DISABLE_JABBER_SHIFT) |
| #define DP83867_PHYCR_DISABLE_JABBER_MASK (0x1U) |
| #define DP83867_PHYCR_DISABLE_JABBER_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_DISABLE_JABBER_SHIFT) & DP83867_PHYCR_DISABLE_JABBER_MASK) |
| #define DP83867_PHYCR_DISABLE_JABBER_SHIFT (0U) |
| #define DP83867_PHYCR_FORCE_LINK_GOOD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) >> DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) |
| #define DP83867_PHYCR_FORCE_LINK_GOOD_MASK (0x400U) |
| #define DP83867_PHYCR_FORCE_LINK_GOOD_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) |
| #define DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT (10U) |
| #define DP83867_PHYCR_LINE_DRIVER_INV_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) >> DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) |
| #define DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK (0x2U) |
| #define DP83867_PHYCR_LINE_DRIVER_INV_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) |
| #define DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT (1U) |
| #define DP83867_PHYCR_MDI_CROSSOVER_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_MDI_CROSSOVER_MASK) >> DP83867_PHYCR_MDI_CROSSOVER_SHIFT) |
| #define DP83867_PHYCR_MDI_CROSSOVER_MASK (0x60U) |
| #define DP83867_PHYCR_MDI_CROSSOVER_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_MDI_CROSSOVER_SHIFT) & DP83867_PHYCR_MDI_CROSSOVER_MASK) |
| #define DP83867_PHYCR_MDI_CROSSOVER_SHIFT (5U) |
| #define DP83867_PHYCR_POWER_SAVE_MODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) >> DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) |
| #define DP83867_PHYCR_POWER_SAVE_MODE_MASK (0x300U) |
| #define DP83867_PHYCR_POWER_SAVE_MODE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) |
| #define DP83867_PHYCR_POWER_SAVE_MODE_SHIFT (8U) |
| #define DP83867_PHYCR_RX_FIFO_DEPTH_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) |
| #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK (0x3000U) |
| #define DP83867_PHYCR_RX_FIFO_DEPTH_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) |
| #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT (12U) |
| #define DP83867_PHYCR_SGMII_EN_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_SGMII_EN_MASK) >> DP83867_PHYCR_SGMII_EN_SHIFT) |
| #define DP83867_PHYCR_SGMII_EN_MASK (0x800U) |
| #define DP83867_PHYCR_SGMII_EN_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_SGMII_EN_SHIFT) & DP83867_PHYCR_SGMII_EN_MASK) |
| #define DP83867_PHYCR_SGMII_EN_SHIFT (11U) |
| #define DP83867_PHYCR_STANDBY_MODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_STANDBY_MODE_MASK) >> DP83867_PHYCR_STANDBY_MODE_SHIFT) |
| #define DP83867_PHYCR_STANDBY_MODE_MASK (0x4U) |
| #define DP83867_PHYCR_STANDBY_MODE_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_STANDBY_MODE_SHIFT) & DP83867_PHYCR_STANDBY_MODE_MASK) |
| #define DP83867_PHYCR_STANDBY_MODE_SHIFT (2U) |
| #define DP83867_PHYCR_TX_FIFO_DEPTH_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) |
| #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK (0xC000U) |
| #define DP83867_PHYCR_TX_FIFO_DEPTH_SET | ( | x | ) | (((uint16_t)(x) << DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) |
| #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT (14U) |
| #define DP83867_PHYIDR1_OUI_MSB_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYIDR1_OUI_MSB_MASK) >> DP83867_PHYIDR1_OUI_MSB_SHIFT) |
| #define DP83867_PHYIDR1_OUI_MSB_MASK (0xFFFFU) |
| #define DP83867_PHYIDR1_OUI_MSB_SHIFT (0U) |
| #define DP83867_PHYIDR2_MDL_REV_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYIDR2_MDL_REV_MASK) >> DP83867_PHYIDR2_MDL_REV_SHIFT) |
| #define DP83867_PHYIDR2_MDL_REV_MASK (0xFU) |
| #define DP83867_PHYIDR2_MDL_REV_SHIFT (0U) |
| #define DP83867_PHYIDR2_OUI_LSB_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYIDR2_OUI_LSB_MASK) >> DP83867_PHYIDR2_OUI_LSB_SHIFT) |
| #define DP83867_PHYIDR2_OUI_LSB_MASK (0xFC00U) |
| #define DP83867_PHYIDR2_OUI_LSB_SHIFT (10U) |
| #define DP83867_PHYIDR2_VNDR_MDL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYIDR2_VNDR_MDL_MASK) >> DP83867_PHYIDR2_VNDR_MDL_SHIFT) |
| #define DP83867_PHYIDR2_VNDR_MDL_MASK (0x3F0U) |
| #define DP83867_PHYIDR2_VNDR_MDL_SHIFT (4U) |
| #define DP83867_PHYSTS_DUPLEX_MODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_DUPLEX_MODE_MASK) >> DP83867_PHYSTS_DUPLEX_MODE_SHIFT) |
| #define DP83867_PHYSTS_DUPLEX_MODE_MASK (0x2000U) |
| #define DP83867_PHYSTS_DUPLEX_MODE_SHIFT (13U) |
| #define DP83867_PHYSTS_JABBER_DETECT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_JABBER_DETECT_MASK) >> DP83867_PHYSTS_JABBER_DETECT_SHIFT) |
| #define DP83867_PHYSTS_JABBER_DETECT_MASK (0x1U) |
| #define DP83867_PHYSTS_JABBER_DETECT_SHIFT (0U) |
| #define DP83867_PHYSTS_LINK_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_LINK_STATUS_MASK) >> DP83867_PHYSTS_LINK_STATUS_SHIFT) |
| #define DP83867_PHYSTS_LINK_STATUS_MASK (0x400U) |
| #define DP83867_PHYSTS_LINK_STATUS_SHIFT (10U) |
| #define DP83867_PHYSTS_MDI_X_MODE_AB_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_AB_MASK) >> DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT) |
| #define DP83867_PHYSTS_MDI_X_MODE_AB_MASK (0x100U) |
| #define DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT (8U) |
| #define DP83867_PHYSTS_MDI_X_MODE_CD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_CD_MASK) >> DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT) |
| #define DP83867_PHYSTS_MDI_X_MODE_CD_MASK (0x200U) |
| #define DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT (9U) |
| #define DP83867_PHYSTS_PAGE_RECEIVED_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_PAGE_RECEIVED_MASK) >> DP83867_PHYSTS_PAGE_RECEIVED_SHIFT) |
| #define DP83867_PHYSTS_PAGE_RECEIVED_MASK (0x1000U) |
| #define DP83867_PHYSTS_PAGE_RECEIVED_SHIFT (12U) |
| #define DP83867_PHYSTS_POLARITY_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_POLARITY_STATUS_MASK) >> DP83867_PHYSTS_POLARITY_STATUS_SHIFT) |
| #define DP83867_PHYSTS_POLARITY_STATUS_MASK (0x2U) |
| #define DP83867_PHYSTS_POLARITY_STATUS_SHIFT (1U) |
| #define DP83867_PHYSTS_SLEEP_MODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_SLEEP_MODE_MASK) >> DP83867_PHYSTS_SLEEP_MODE_SHIFT) |
| #define DP83867_PHYSTS_SLEEP_MODE_MASK (0x40U) |
| #define DP83867_PHYSTS_SLEEP_MODE_SHIFT (6U) |
| #define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK) >> DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT) |
| #define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK (0x800U) |
| #define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT (11U) |
| #define DP83867_PHYSTS_SPEED_OPT_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_SPEED_OPT_STATUS_MASK) >> DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT) |
| #define DP83867_PHYSTS_SPEED_OPT_STATUS_MASK (0x80U) |
| #define DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT (7U) |
| #define DP83867_PHYSTS_SPEED_SELECTION_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_SPEED_SELECTION_MASK) >> DP83867_PHYSTS_SPEED_SELECTION_SHIFT) |
| #define DP83867_PHYSTS_SPEED_SELECTION_MASK (0xC000U) |
| #define DP83867_PHYSTS_SPEED_SELECTION_SHIFT (14U) |
| #define DP83867_PHYSTS_WIRE_CROSS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_PHYSTS_WIRE_CROSS_MASK) >> DP83867_PHYSTS_WIRE_CROSS_SHIFT) |
| #define DP83867_PHYSTS_WIRE_CROSS_MASK (0x3CU) |
| #define DP83867_PHYSTS_WIRE_CROSS_SHIFT (2U) |
| #define DP83867_RECR_RXERCNT_15_0_GET | ( | x | ) | (((uint16_t)(x) & DP83867_RECR_RXERCNT_15_0_MASK) >> DP83867_RECR_RXERCNT_15_0_SHIFT) |
| #define DP83867_RECR_RXERCNT_15_0_MASK (0xFFFFU) |
| #define DP83867_RECR_RXERCNT_15_0_SET | ( | x | ) | (((uint16_t)(x) << DP83867_RECR_RXERCNT_15_0_SHIFT) & DP83867_RECR_RXERCNT_15_0_MASK) |
| #define DP83867_RECR_RXERCNT_15_0_SHIFT (0U) |
| #define DP83867_REGCR_DEVAD_GET | ( | x | ) | (((uint16_t)(x) & DP83867_REGCR_DEVAD_MASK) >> DP83867_REGCR_DEVAD_SHIFT) |
| #define DP83867_REGCR_DEVAD_MASK (0x1FU) |
| #define DP83867_REGCR_DEVAD_SET | ( | x | ) | (((uint16_t)(x) << DP83867_REGCR_DEVAD_SHIFT) & DP83867_REGCR_DEVAD_MASK) |
| #define DP83867_REGCR_DEVAD_SHIFT (0U) |
| #define DP83867_REGCR_FUNCTION_GET | ( | x | ) | (((uint16_t)(x) & DP83867_REGCR_FUNCTION_MASK) >> DP83867_REGCR_FUNCTION_SHIFT) |
| #define DP83867_REGCR_FUNCTION_MASK (0xC000U) |
| #define DP83867_REGCR_FUNCTION_SET | ( | x | ) | (((uint16_t)(x) << DP83867_REGCR_FUNCTION_SHIFT) & DP83867_REGCR_FUNCTION_MASK) |
| #define DP83867_REGCR_FUNCTION_SHIFT (14U) |
| #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) |
| #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK (0xFU) |
| #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) |
| #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT (0U) |
| #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_GET | ( | x | ) | (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) |
| #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK (0xF0U) |
| #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SET | ( | x | ) | (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) |
| #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT (4U) |
| #define DP83867_STS1_1000BASE_T_FULL_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT) |
| #define DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK (0x800U) |
| #define DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT (11U) |
| #define DP83867_STS1_1000BASE_T_HALF_DUPLEX_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT) |
| #define DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK (0x400U) |
| #define DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT (10U) |
| #define DP83867_STS1_IDLE_ERROR_COUNTER_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_IDLE_ERROR_COUNTER_MASK) >> DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT) |
| #define DP83867_STS1_IDLE_ERROR_COUNTER_MASK (0xFFU) |
| #define DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT (0U) |
| #define DP83867_STS1_LOCAL_RECEIVER_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK) >> DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT) |
| #define DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK (0x2000U) |
| #define DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT (13U) |
| #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT) |
| #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK (0x8000U) |
| #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT (15U) |
| #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT) |
| #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK (0x4000U) |
| #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT (14U) |
| #define DP83867_STS1_REMOTE_RECEIVER_STATUS_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK) >> DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT) |
| #define DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK (0x1000U) |
| #define DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT (12U) |
| #define DP83867_STS2_CORE_PWR_MODE_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS2_CORE_PWR_MODE_MASK) >> DP83867_STS2_CORE_PWR_MODE_SHIFT) |
| #define DP83867_STS2_CORE_PWR_MODE_MASK (0x40U) |
| #define DP83867_STS2_CORE_PWR_MODE_SHIFT (6U) |
| #define DP83867_STS2_PKT_GEN_BUSY_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS2_PKT_GEN_BUSY_MASK) >> DP83867_STS2_PKT_GEN_BUSY_SHIFT) |
| #define DP83867_STS2_PKT_GEN_BUSY_MASK (0x200U) |
| #define DP83867_STS2_PKT_GEN_BUSY_SHIFT (9U) |
| #define DP83867_STS2_PRBS_LOCK_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_MASK) >> DP83867_STS2_PRBS_LOCK_SHIFT) |
| #define DP83867_STS2_PRBS_LOCK_LOST_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_LOST_MASK) >> DP83867_STS2_PRBS_LOCK_LOST_SHIFT) |
| #define DP83867_STS2_PRBS_LOCK_LOST_MASK (0x400U) |
| #define DP83867_STS2_PRBS_LOCK_LOST_SHIFT (10U) |
| #define DP83867_STS2_PRBS_LOCK_MASK (0x800U) |
| #define DP83867_STS2_PRBS_LOCK_SHIFT (11U) |
| #define DP83867_STS2_SCR_MODE_MASTER_1G_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS2_SCR_MODE_MASTER_1G_MASK) >> DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT) |
| #define DP83867_STS2_SCR_MODE_MASTER_1G_MASK (0x100U) |
| #define DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT (8U) |
| #define DP83867_STS2_SCR_MODE_SLAVE_1G_GET | ( | x | ) | (((uint16_t)(x) & DP83867_STS2_SCR_MODE_SLAVE_1G_MASK) >> DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT) |
| #define DP83867_STS2_SCR_MODE_SLAVE_1G_MASK (0x80U) |
| #define DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT (7U) |
| enum DP83867_REG_Type |
1.9.1